3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
11 * Wu Fengguang <wfg@linux.intel.com>
14 * Wu Fengguang <wfg@linux.intel.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <sound/core.h>
35 #include "hda_codec.h"
36 #include "hda_local.h"
39 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
40 * could support two independent pipes, each of them can be connected to one or
41 * more ports (DVI, HDMI or DisplayPort).
43 * The HDA correspondence of pipes/ports are converter/pin nodes.
45 #define MAX_HDMI_CVTS 3
46 #define MAX_HDMI_PINS 3
51 hda_nid_t cvt
[MAX_HDMI_CVTS
+1]; /* audio sources */
52 hda_nid_t pin
[MAX_HDMI_PINS
+1]; /* audio sinks */
55 * source connection for each pin
57 hda_nid_t pin_cvt
[MAX_HDMI_PINS
+1];
60 * HDMI sink attached to each pin
62 struct hdmi_eld sink_eld
[MAX_HDMI_PINS
];
65 * export one pcm per pipe
67 struct hda_pcm pcm_rec
[MAX_HDMI_CVTS
];
68 struct hda_pcm_stream codec_pcm_pars
[MAX_HDMI_CVTS
];
73 struct hda_multi_out multiout
;
74 struct hda_pcm_stream
*pcm_playback
;
77 /* PD bit indicates only the update, not the current state */
78 unsigned int old_pin_detect
:1;
82 struct hdmi_audio_infoframe
{
89 u8 CC02_CT47
; /* CC in bits 0:2, CT in 4:7 */
93 u8 LFEPBL01_LSV36_DM_INH7
;
96 struct dp_audio_infoframe
{
99 u8 ver
; /* 0x11 << 2 */
101 u8 CC02_CT47
; /* match with HDMI infoframe from this on */
105 u8 LFEPBL01_LSV36_DM_INH7
;
109 * CEA speaker placement:
112 * FLW FL FLC FC FRC FR FRW
119 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
120 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
122 enum cea_speaker_placement
{
123 FL
= (1 << 0), /* Front Left */
124 FC
= (1 << 1), /* Front Center */
125 FR
= (1 << 2), /* Front Right */
126 FLC
= (1 << 3), /* Front Left Center */
127 FRC
= (1 << 4), /* Front Right Center */
128 RL
= (1 << 5), /* Rear Left */
129 RC
= (1 << 6), /* Rear Center */
130 RR
= (1 << 7), /* Rear Right */
131 RLC
= (1 << 8), /* Rear Left Center */
132 RRC
= (1 << 9), /* Rear Right Center */
133 LFE
= (1 << 10), /* Low Frequency Effect */
134 FLW
= (1 << 11), /* Front Left Wide */
135 FRW
= (1 << 12), /* Front Right Wide */
136 FLH
= (1 << 13), /* Front Left High */
137 FCH
= (1 << 14), /* Front Center High */
138 FRH
= (1 << 15), /* Front Right High */
139 TC
= (1 << 16), /* Top Center */
143 * ELD SA bits in the CEA Speaker Allocation data block
145 static int eld_speaker_allocation_bits
[] = {
153 /* the following are not defined in ELD yet */
160 struct cea_channel_speaker_allocation
{
164 /* derived values, just for convenience */
172 * surround40 surround41 surround50 surround51 surround71
173 * ch0 front left = = = =
174 * ch1 front right = = = =
175 * ch2 rear left = = = =
176 * ch3 rear right = = = =
177 * ch4 LFE center center center
182 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
184 static int hdmi_channel_mapping
[0x32][8] = {
186 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
188 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
190 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
192 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
194 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
196 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
198 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
200 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
202 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
206 * This is an ordered list!
208 * The preceding ones have better chances to be selected by
209 * hdmi_channel_allocation().
211 static struct cea_channel_speaker_allocation channel_allocations
[] = {
212 /* channel: 7 6 5 4 3 2 1 0 */
213 { .ca_index
= 0x00, .speakers
= { 0, 0, 0, 0, 0, 0, FR
, FL
} },
215 { .ca_index
= 0x01, .speakers
= { 0, 0, 0, 0, 0, LFE
, FR
, FL
} },
217 { .ca_index
= 0x02, .speakers
= { 0, 0, 0, 0, FC
, 0, FR
, FL
} },
219 { .ca_index
= 0x08, .speakers
= { 0, 0, RR
, RL
, 0, 0, FR
, FL
} },
221 { .ca_index
= 0x09, .speakers
= { 0, 0, RR
, RL
, 0, LFE
, FR
, FL
} },
223 { .ca_index
= 0x0a, .speakers
= { 0, 0, RR
, RL
, FC
, 0, FR
, FL
} },
225 { .ca_index
= 0x0b, .speakers
= { 0, 0, RR
, RL
, FC
, LFE
, FR
, FL
} },
227 { .ca_index
= 0x0f, .speakers
= { 0, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
229 { .ca_index
= 0x13, .speakers
= { RRC
, RLC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
231 { .ca_index
= 0x03, .speakers
= { 0, 0, 0, 0, FC
, LFE
, FR
, FL
} },
232 { .ca_index
= 0x04, .speakers
= { 0, 0, 0, RC
, 0, 0, FR
, FL
} },
233 { .ca_index
= 0x05, .speakers
= { 0, 0, 0, RC
, 0, LFE
, FR
, FL
} },
234 { .ca_index
= 0x06, .speakers
= { 0, 0, 0, RC
, FC
, 0, FR
, FL
} },
235 { .ca_index
= 0x07, .speakers
= { 0, 0, 0, RC
, FC
, LFE
, FR
, FL
} },
236 { .ca_index
= 0x0c, .speakers
= { 0, RC
, RR
, RL
, 0, 0, FR
, FL
} },
237 { .ca_index
= 0x0d, .speakers
= { 0, RC
, RR
, RL
, 0, LFE
, FR
, FL
} },
238 { .ca_index
= 0x0e, .speakers
= { 0, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
239 { .ca_index
= 0x10, .speakers
= { RRC
, RLC
, RR
, RL
, 0, 0, FR
, FL
} },
240 { .ca_index
= 0x11, .speakers
= { RRC
, RLC
, RR
, RL
, 0, LFE
, FR
, FL
} },
241 { .ca_index
= 0x12, .speakers
= { RRC
, RLC
, RR
, RL
, FC
, 0, FR
, FL
} },
242 { .ca_index
= 0x14, .speakers
= { FRC
, FLC
, 0, 0, 0, 0, FR
, FL
} },
243 { .ca_index
= 0x15, .speakers
= { FRC
, FLC
, 0, 0, 0, LFE
, FR
, FL
} },
244 { .ca_index
= 0x16, .speakers
= { FRC
, FLC
, 0, 0, FC
, 0, FR
, FL
} },
245 { .ca_index
= 0x17, .speakers
= { FRC
, FLC
, 0, 0, FC
, LFE
, FR
, FL
} },
246 { .ca_index
= 0x18, .speakers
= { FRC
, FLC
, 0, RC
, 0, 0, FR
, FL
} },
247 { .ca_index
= 0x19, .speakers
= { FRC
, FLC
, 0, RC
, 0, LFE
, FR
, FL
} },
248 { .ca_index
= 0x1a, .speakers
= { FRC
, FLC
, 0, RC
, FC
, 0, FR
, FL
} },
249 { .ca_index
= 0x1b, .speakers
= { FRC
, FLC
, 0, RC
, FC
, LFE
, FR
, FL
} },
250 { .ca_index
= 0x1c, .speakers
= { FRC
, FLC
, RR
, RL
, 0, 0, FR
, FL
} },
251 { .ca_index
= 0x1d, .speakers
= { FRC
, FLC
, RR
, RL
, 0, LFE
, FR
, FL
} },
252 { .ca_index
= 0x1e, .speakers
= { FRC
, FLC
, RR
, RL
, FC
, 0, FR
, FL
} },
253 { .ca_index
= 0x1f, .speakers
= { FRC
, FLC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
254 { .ca_index
= 0x20, .speakers
= { 0, FCH
, RR
, RL
, FC
, 0, FR
, FL
} },
255 { .ca_index
= 0x21, .speakers
= { 0, FCH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
256 { .ca_index
= 0x22, .speakers
= { TC
, 0, RR
, RL
, FC
, 0, FR
, FL
} },
257 { .ca_index
= 0x23, .speakers
= { TC
, 0, RR
, RL
, FC
, LFE
, FR
, FL
} },
258 { .ca_index
= 0x24, .speakers
= { FRH
, FLH
, RR
, RL
, 0, 0, FR
, FL
} },
259 { .ca_index
= 0x25, .speakers
= { FRH
, FLH
, RR
, RL
, 0, LFE
, FR
, FL
} },
260 { .ca_index
= 0x26, .speakers
= { FRW
, FLW
, RR
, RL
, 0, 0, FR
, FL
} },
261 { .ca_index
= 0x27, .speakers
= { FRW
, FLW
, RR
, RL
, 0, LFE
, FR
, FL
} },
262 { .ca_index
= 0x28, .speakers
= { TC
, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
263 { .ca_index
= 0x29, .speakers
= { TC
, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
264 { .ca_index
= 0x2a, .speakers
= { FCH
, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
265 { .ca_index
= 0x2b, .speakers
= { FCH
, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
266 { .ca_index
= 0x2c, .speakers
= { TC
, FCH
, RR
, RL
, FC
, 0, FR
, FL
} },
267 { .ca_index
= 0x2d, .speakers
= { TC
, FCH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
268 { .ca_index
= 0x2e, .speakers
= { FRH
, FLH
, RR
, RL
, FC
, 0, FR
, FL
} },
269 { .ca_index
= 0x2f, .speakers
= { FRH
, FLH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
270 { .ca_index
= 0x30, .speakers
= { FRW
, FLW
, RR
, RL
, FC
, 0, FR
, FL
} },
271 { .ca_index
= 0x31, .speakers
= { FRW
, FLW
, RR
, RL
, FC
, LFE
, FR
, FL
} },
279 static int hda_node_index(hda_nid_t
*nids
, hda_nid_t nid
)
283 for (i
= 0; nids
[i
]; i
++)
287 snd_printk(KERN_WARNING
"HDMI: nid %d not registered\n", nid
);
291 static void hdmi_get_show_eld(struct hda_codec
*codec
, hda_nid_t pin_nid
,
292 struct hdmi_eld
*eld
)
294 if (!snd_hdmi_get_eld(eld
, codec
, pin_nid
))
295 snd_hdmi_show_eld(eld
);
299 static void hdmi_get_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
300 int *packet_index
, int *byte_index
)
304 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
305 AC_VERB_GET_HDMI_DIP_INDEX
, 0);
307 *packet_index
= val
>> 5;
308 *byte_index
= val
& 0x1f;
312 static void hdmi_set_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
313 int packet_index
, int byte_index
)
317 val
= (packet_index
<< 5) | (byte_index
& 0x1f);
319 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_INDEX
, val
);
322 static void hdmi_write_dip_byte(struct hda_codec
*codec
, hda_nid_t pin_nid
,
325 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_DATA
, val
);
328 static void hdmi_enable_output(struct hda_codec
*codec
, hda_nid_t pin_nid
)
331 if (get_wcaps(codec
, pin_nid
) & AC_WCAP_OUT_AMP
)
332 snd_hda_codec_write(codec
, pin_nid
, 0,
333 AC_VERB_SET_AMP_GAIN_MUTE
, AMP_OUT_UNMUTE
);
335 snd_hda_codec_write(codec
, pin_nid
, 0,
336 AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
);
339 static int hdmi_get_channel_count(struct hda_codec
*codec
, hda_nid_t nid
)
341 return 1 + snd_hda_codec_read(codec
, nid
, 0,
342 AC_VERB_GET_CVT_CHAN_COUNT
, 0);
345 static void hdmi_set_channel_count(struct hda_codec
*codec
,
346 hda_nid_t nid
, int chs
)
348 if (chs
!= hdmi_get_channel_count(codec
, nid
))
349 snd_hda_codec_write(codec
, nid
, 0,
350 AC_VERB_SET_CVT_CHAN_COUNT
, chs
- 1);
355 * Channel mapping routines
359 * Compute derived values in channel_allocations[].
361 static void init_channel_allocations(void)
364 struct cea_channel_speaker_allocation
*p
;
366 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
367 p
= channel_allocations
+ i
;
370 for (j
= 0; j
< ARRAY_SIZE(p
->speakers
); j
++)
371 if (p
->speakers
[j
]) {
373 p
->spk_mask
|= p
->speakers
[j
];
379 * The transformation takes two steps:
381 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
382 * spk_mask => (channel_allocations[]) => ai->CA
384 * TODO: it could select the wrong CA from multiple candidates.
386 static int hdmi_channel_allocation(struct hda_codec
*codec
, hda_nid_t nid
,
389 struct hdmi_spec
*spec
= codec
->spec
;
390 struct hdmi_eld
*eld
;
394 char buf
[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE
];
397 * CA defaults to 0 for basic stereo audio
402 i
= hda_node_index(spec
->pin_cvt
, nid
);
405 eld
= &spec
->sink_eld
[i
];
408 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
409 * in console or for audio devices. Assume the highest speakers
410 * configuration, to _not_ prohibit multi-channel audio playback.
413 eld
->spk_alloc
= 0xffff;
416 * expand ELD's speaker allocation mask
418 * ELD tells the speaker mask in a compact(paired) form,
419 * expand ELD's notions to match the ones used by Audio InfoFrame.
421 for (i
= 0; i
< ARRAY_SIZE(eld_speaker_allocation_bits
); i
++) {
422 if (eld
->spk_alloc
& (1 << i
))
423 spk_mask
|= eld_speaker_allocation_bits
[i
];
426 /* search for the first working match in the CA table */
427 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
428 if (channels
== channel_allocations
[i
].channels
&&
429 (spk_mask
& channel_allocations
[i
].spk_mask
) ==
430 channel_allocations
[i
].spk_mask
) {
431 ca
= channel_allocations
[i
].ca_index
;
436 snd_print_channel_allocation(eld
->spk_alloc
, buf
, sizeof(buf
));
437 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
443 static void hdmi_debug_channel_mapping(struct hda_codec
*codec
,
446 #ifdef CONFIG_SND_DEBUG_VERBOSE
450 for (i
= 0; i
< 8; i
++) {
451 slot
= snd_hda_codec_read(codec
, pin_nid
, 0,
452 AC_VERB_GET_HDMI_CHAN_SLOT
, i
);
453 printk(KERN_DEBUG
"HDMI: ASP channel %d => slot %d\n",
454 slot
>> 4, slot
& 0xf);
460 static void hdmi_setup_channel_mapping(struct hda_codec
*codec
,
467 if (hdmi_channel_mapping
[ca
][1] == 0) {
468 for (i
= 0; i
< channel_allocations
[ca
].channels
; i
++)
469 hdmi_channel_mapping
[ca
][i
] = i
| (i
<< 4);
471 hdmi_channel_mapping
[ca
][i
] = 0xf | (i
<< 4);
474 for (i
= 0; i
< 8; i
++) {
475 err
= snd_hda_codec_write(codec
, pin_nid
, 0,
476 AC_VERB_SET_HDMI_CHAN_SLOT
,
477 hdmi_channel_mapping
[ca
][i
]);
479 snd_printdd(KERN_NOTICE
480 "HDMI: channel mapping failed\n");
485 hdmi_debug_channel_mapping(codec
, pin_nid
);
490 * Audio InfoFrame routines
494 * Enable Audio InfoFrame Transmission
496 static void hdmi_start_infoframe_trans(struct hda_codec
*codec
,
499 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
500 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
505 * Disable Audio InfoFrame Transmission
507 static void hdmi_stop_infoframe_trans(struct hda_codec
*codec
,
510 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
511 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
515 static void hdmi_debug_dip_size(struct hda_codec
*codec
, hda_nid_t pin_nid
)
517 #ifdef CONFIG_SND_DEBUG_VERBOSE
521 size
= snd_hdmi_get_eld_size(codec
, pin_nid
);
522 printk(KERN_DEBUG
"HDMI: ELD buf size is %d\n", size
);
524 for (i
= 0; i
< 8; i
++) {
525 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
526 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
527 printk(KERN_DEBUG
"HDMI: DIP GP[%d] buf size is %d\n", i
, size
);
532 static void hdmi_clear_dip_buffers(struct hda_codec
*codec
, hda_nid_t pin_nid
)
538 for (i
= 0; i
< 8; i
++) {
539 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
540 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
544 hdmi_set_dip_index(codec
, pin_nid
, i
, 0x0);
545 for (j
= 1; j
< 1000; j
++) {
546 hdmi_write_dip_byte(codec
, pin_nid
, 0x0);
547 hdmi_get_dip_index(codec
, pin_nid
, &pi
, &bi
);
549 snd_printd(KERN_INFO
"dip index %d: %d != %d\n",
551 if (bi
== 0) /* byte index wrapped around */
555 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
561 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe
*hdmi_ai
)
563 u8
*bytes
= (u8
*)hdmi_ai
;
567 hdmi_ai
->checksum
= 0;
569 for (i
= 0; i
< sizeof(*hdmi_ai
); i
++)
572 hdmi_ai
->checksum
= -sum
;
575 static void hdmi_fill_audio_infoframe(struct hda_codec
*codec
,
581 hdmi_debug_dip_size(codec
, pin_nid
);
582 hdmi_clear_dip_buffers(codec
, pin_nid
); /* be paranoid */
584 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
585 for (i
= 0; i
< size
; i
++)
586 hdmi_write_dip_byte(codec
, pin_nid
, dip
[i
]);
589 static bool hdmi_infoframe_uptodate(struct hda_codec
*codec
, hda_nid_t pin_nid
,
595 if (snd_hda_codec_read(codec
, pin_nid
, 0, AC_VERB_GET_HDMI_DIP_XMIT
, 0)
599 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
600 for (i
= 0; i
< size
; i
++) {
601 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
602 AC_VERB_GET_HDMI_DIP_DATA
, 0);
610 static void hdmi_setup_audio_infoframe(struct hda_codec
*codec
, hda_nid_t nid
,
611 struct snd_pcm_substream
*substream
)
613 struct hdmi_spec
*spec
= codec
->spec
;
615 int channels
= substream
->runtime
->channels
;
618 u8 ai
[max(sizeof(struct hdmi_audio_infoframe
),
619 sizeof(struct dp_audio_infoframe
))];
621 ca
= hdmi_channel_allocation(codec
, nid
, channels
);
623 for (i
= 0; i
< spec
->num_pins
; i
++) {
624 if (spec
->pin_cvt
[i
] != nid
)
626 if (!spec
->sink_eld
[i
].monitor_present
)
629 pin_nid
= spec
->pin
[i
];
631 memset(ai
, 0, sizeof(ai
));
632 if (spec
->sink_eld
[i
].conn_type
== 0) { /* HDMI */
633 struct hdmi_audio_infoframe
*hdmi_ai
;
635 hdmi_ai
= (struct hdmi_audio_infoframe
*)ai
;
636 hdmi_ai
->type
= 0x84;
639 hdmi_ai
->CC02_CT47
= channels
- 1;
640 hdmi_checksum_audio_infoframe(hdmi_ai
);
641 } else if (spec
->sink_eld
[i
].conn_type
== 1) { /* DisplayPort */
642 struct dp_audio_infoframe
*dp_ai
;
644 dp_ai
= (struct dp_audio_infoframe
*)ai
;
647 dp_ai
->ver
= 0x11 << 2;
648 dp_ai
->CC02_CT47
= channels
- 1;
650 snd_printd("HDMI: unknown connection type at pin %d\n",
656 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
657 * sizeof(*dp_ai) to avoid partial match/update problems when
658 * the user switches between HDMI/DP monitors.
660 if (!hdmi_infoframe_uptodate(codec
, pin_nid
, ai
, sizeof(ai
))) {
661 snd_printdd("hdmi_setup_audio_infoframe: "
662 "cvt=%d pin=%d channels=%d\n",
665 hdmi_setup_channel_mapping(codec
, pin_nid
, ca
);
666 hdmi_stop_infoframe_trans(codec
, pin_nid
);
667 hdmi_fill_audio_infoframe(codec
, pin_nid
,
669 hdmi_start_infoframe_trans(codec
, pin_nid
);
679 static void hdmi_present_sense(struct hda_codec
*codec
, hda_nid_t pin_nid
,
680 struct hdmi_eld
*eld
);
682 static void hdmi_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
684 struct hdmi_spec
*spec
= codec
->spec
;
685 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
686 int pind
= !!(res
& AC_UNSOL_RES_PD
);
687 int eldv
= !!(res
& AC_UNSOL_RES_ELDV
);
691 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
694 index
= hda_node_index(spec
->pin
, tag
);
698 if (spec
->old_pin_detect
) {
700 hdmi_present_sense(codec
, tag
, &spec
->sink_eld
[index
]);
701 pind
= spec
->sink_eld
[index
].monitor_present
;
704 spec
->sink_eld
[index
].monitor_present
= pind
;
705 spec
->sink_eld
[index
].eld_valid
= eldv
;
708 hdmi_get_show_eld(codec
, spec
->pin
[index
],
709 &spec
->sink_eld
[index
]);
710 /* TODO: do real things about ELD */
714 static void hdmi_non_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
716 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
717 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
718 int cp_state
= !!(res
& AC_UNSOL_RES_CP_STATE
);
719 int cp_ready
= !!(res
& AC_UNSOL_RES_CP_READY
);
722 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
736 static void hdmi_unsol_event(struct hda_codec
*codec
, unsigned int res
)
738 struct hdmi_spec
*spec
= codec
->spec
;
739 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
740 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
742 if (hda_node_index(spec
->pin
, tag
) < 0) {
743 snd_printd(KERN_INFO
"Unexpected HDMI event tag 0x%x\n", tag
);
748 hdmi_intrinsic_event(codec
, res
);
750 hdmi_non_intrinsic_event(codec
, res
);
757 /* HBR should be Non-PCM, 8 channels */
758 #define is_hbr_format(format) \
759 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
761 static int hdmi_setup_stream(struct hda_codec
*codec
, hda_nid_t nid
,
762 u32 stream_tag
, int format
)
764 struct hdmi_spec
*spec
= codec
->spec
;
769 for (i
= 0; i
< spec
->num_pins
; i
++) {
770 if (spec
->pin_cvt
[i
] != nid
)
772 if (!(snd_hda_query_pin_caps(codec
, spec
->pin
[i
]) & AC_PINCAP_HBR
))
775 pinctl
= snd_hda_codec_read(codec
, spec
->pin
[i
], 0,
776 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
778 new_pinctl
= pinctl
& ~AC_PINCTL_EPT
;
779 if (is_hbr_format(format
))
780 new_pinctl
|= AC_PINCTL_EPT_HBR
;
782 new_pinctl
|= AC_PINCTL_EPT_NATIVE
;
784 snd_printdd("hdmi_setup_stream: "
785 "NID=0x%x, %spinctl=0x%x\n",
787 pinctl
== new_pinctl
? "" : "new-",
790 if (pinctl
!= new_pinctl
)
791 snd_hda_codec_write(codec
, spec
->pin
[i
], 0,
792 AC_VERB_SET_PIN_WIDGET_CONTROL
,
796 if (is_hbr_format(format
) && !new_pinctl
) {
797 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
801 snd_hda_codec_setup_stream(codec
, nid
, stream_tag
, 0, format
);
808 static int hdmi_pcm_open(struct hda_pcm_stream
*hinfo
,
809 struct hda_codec
*codec
,
810 struct snd_pcm_substream
*substream
)
812 struct hdmi_spec
*spec
= codec
->spec
;
813 struct hdmi_eld
*eld
;
814 struct hda_pcm_stream
*codec_pars
;
817 for (idx
= 0; idx
< spec
->num_cvts
; idx
++)
818 if (hinfo
->nid
== spec
->cvt
[idx
])
820 if (snd_BUG_ON(idx
>= spec
->num_cvts
) ||
821 snd_BUG_ON(idx
>= spec
->num_pins
))
824 /* save the PCM info the codec provides */
825 codec_pars
= &spec
->codec_pcm_pars
[idx
];
826 if (!codec_pars
->rates
)
827 *codec_pars
= *hinfo
;
829 eld
= &spec
->sink_eld
[idx
];
830 if (eld
->sad_count
> 0) {
831 hdmi_eld_update_pcm_info(eld
, hinfo
, codec_pars
);
832 if (hinfo
->channels_min
> hinfo
->channels_max
||
833 !hinfo
->rates
|| !hinfo
->formats
)
836 /* fallback to the codec default */
837 hinfo
->channels_min
= codec_pars
->channels_min
;
838 hinfo
->channels_max
= codec_pars
->channels_max
;
839 hinfo
->rates
= codec_pars
->rates
;
840 hinfo
->formats
= codec_pars
->formats
;
841 hinfo
->maxbps
= codec_pars
->maxbps
;
847 * HDA/HDMI auto parsing
849 static int hdmi_read_pin_conn(struct hda_codec
*codec
, hda_nid_t pin_nid
)
851 struct hdmi_spec
*spec
= codec
->spec
;
852 hda_nid_t conn_list
[HDA_MAX_CONNECTIONS
];
856 if (!(get_wcaps(codec
, pin_nid
) & AC_WCAP_CONN_LIST
)) {
857 snd_printk(KERN_WARNING
858 "HDMI: pin %d wcaps %#x "
859 "does not support connection list\n",
860 pin_nid
, get_wcaps(codec
, pin_nid
));
864 conn_len
= snd_hda_get_connections(codec
, pin_nid
, conn_list
,
865 HDA_MAX_CONNECTIONS
);
867 curr
= snd_hda_codec_read(codec
, pin_nid
, 0,
868 AC_VERB_GET_CONNECT_SEL
, 0);
872 index
= hda_node_index(spec
->pin
, pin_nid
);
876 spec
->pin_cvt
[index
] = conn_list
[curr
];
881 static void hdmi_present_sense(struct hda_codec
*codec
, hda_nid_t pin_nid
,
882 struct hdmi_eld
*eld
)
884 int present
= snd_hda_pin_sense(codec
, pin_nid
);
886 eld
->monitor_present
= !!(present
& AC_PINSENSE_PRESENCE
);
887 eld
->eld_valid
= !!(present
& AC_PINSENSE_ELDV
);
889 if (present
& AC_PINSENSE_ELDV
)
890 hdmi_get_show_eld(codec
, pin_nid
, eld
);
893 static int hdmi_add_pin(struct hda_codec
*codec
, hda_nid_t pin_nid
)
895 struct hdmi_spec
*spec
= codec
->spec
;
897 if (spec
->num_pins
>= MAX_HDMI_PINS
) {
898 snd_printk(KERN_WARNING
899 "HDMI: no space for pin %d\n", pin_nid
);
903 hdmi_present_sense(codec
, pin_nid
, &spec
->sink_eld
[spec
->num_pins
]);
905 spec
->pin
[spec
->num_pins
] = pin_nid
;
909 * It is assumed that converter nodes come first in the node list and
910 * hence have been registered and usable now.
912 return hdmi_read_pin_conn(codec
, pin_nid
);
915 static int hdmi_add_cvt(struct hda_codec
*codec
, hda_nid_t nid
)
917 struct hdmi_spec
*spec
= codec
->spec
;
919 if (spec
->num_cvts
>= MAX_HDMI_CVTS
) {
920 snd_printk(KERN_WARNING
921 "HDMI: no space for converter %d\n", nid
);
925 spec
->cvt
[spec
->num_cvts
] = nid
;
931 static int hdmi_parse_codec(struct hda_codec
*codec
)
936 nodes
= snd_hda_get_sub_nodes(codec
, codec
->afg
, &nid
);
937 if (!nid
|| nodes
< 0) {
938 snd_printk(KERN_WARNING
"HDMI: failed to get afg sub nodes\n");
942 for (i
= 0; i
< nodes
; i
++, nid
++) {
946 caps
= snd_hda_param_read(codec
, nid
, AC_PAR_AUDIO_WIDGET_CAP
);
947 type
= get_wcaps_type(caps
);
949 if (!(caps
& AC_WCAP_DIGITAL
))
954 hdmi_add_cvt(codec
, nid
);
957 caps
= snd_hda_param_read(codec
, nid
, AC_PAR_PIN_CAP
);
958 if (!(caps
& (AC_PINCAP_HDMI
| AC_PINCAP_DP
)))
960 hdmi_add_pin(codec
, nid
);
966 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
967 * can be lost and presence sense verb will become inaccurate if the
968 * HDA link is powered off at hot plug or hw initialization time.
970 #ifdef CONFIG_SND_HDA_POWER_SAVE
971 if (!(snd_hda_param_read(codec
, codec
->afg
, AC_PAR_POWER_STATE
) &
973 codec
->bus
->power_keep_link_on
= 1;
981 static char *generic_hdmi_pcm_names
[MAX_HDMI_CVTS
] = {
991 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
992 struct hda_codec
*codec
,
993 unsigned int stream_tag
,
995 struct snd_pcm_substream
*substream
)
997 hdmi_set_channel_count(codec
, hinfo
->nid
,
998 substream
->runtime
->channels
);
1000 hdmi_setup_audio_infoframe(codec
, hinfo
->nid
, substream
);
1002 return hdmi_setup_stream(codec
, hinfo
->nid
, stream_tag
, format
);
1005 static struct hda_pcm_stream generic_hdmi_pcm_playback
= {
1009 .open
= hdmi_pcm_open
,
1010 .prepare
= generic_hdmi_playback_pcm_prepare
,
1014 static int generic_hdmi_build_pcms(struct hda_codec
*codec
)
1016 struct hdmi_spec
*spec
= codec
->spec
;
1017 struct hda_pcm
*info
= spec
->pcm_rec
;
1020 codec
->num_pcms
= spec
->num_cvts
;
1021 codec
->pcm_info
= info
;
1023 for (i
= 0; i
< codec
->num_pcms
; i
++, info
++) {
1025 struct hda_pcm_stream
*pstr
;
1027 chans
= get_wcaps(codec
, spec
->cvt
[i
]);
1028 chans
= get_wcaps_channels(chans
);
1030 info
->name
= generic_hdmi_pcm_names
[i
];
1031 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
1032 pstr
= &info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
1033 if (spec
->pcm_playback
)
1034 *pstr
= *spec
->pcm_playback
;
1036 *pstr
= generic_hdmi_pcm_playback
;
1037 pstr
->nid
= spec
->cvt
[i
];
1038 if (pstr
->channels_max
<= 2 && chans
&& chans
<= 16)
1039 pstr
->channels_max
= chans
;
1045 static int generic_hdmi_build_controls(struct hda_codec
*codec
)
1047 struct hdmi_spec
*spec
= codec
->spec
;
1051 for (i
= 0; i
< codec
->num_pcms
; i
++) {
1052 err
= snd_hda_create_spdif_out_ctls(codec
, spec
->cvt
[i
]);
1060 static int generic_hdmi_init(struct hda_codec
*codec
)
1062 struct hdmi_spec
*spec
= codec
->spec
;
1065 for (i
= 0; spec
->pin
[i
]; i
++) {
1066 hdmi_enable_output(codec
, spec
->pin
[i
]);
1067 snd_hda_codec_write(codec
, spec
->pin
[i
], 0,
1068 AC_VERB_SET_UNSOLICITED_ENABLE
,
1069 AC_USRSP_EN
| spec
->pin
[i
]);
1074 static void generic_hdmi_free(struct hda_codec
*codec
)
1076 struct hdmi_spec
*spec
= codec
->spec
;
1079 for (i
= 0; i
< spec
->num_pins
; i
++)
1080 snd_hda_eld_proc_free(codec
, &spec
->sink_eld
[i
]);
1085 static struct hda_codec_ops generic_hdmi_patch_ops
= {
1086 .init
= generic_hdmi_init
,
1087 .free
= generic_hdmi_free
,
1088 .build_pcms
= generic_hdmi_build_pcms
,
1089 .build_controls
= generic_hdmi_build_controls
,
1090 .unsol_event
= hdmi_unsol_event
,
1093 static int patch_generic_hdmi(struct hda_codec
*codec
)
1095 struct hdmi_spec
*spec
;
1098 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
1103 if (hdmi_parse_codec(codec
) < 0) {
1108 codec
->patch_ops
= generic_hdmi_patch_ops
;
1110 for (i
= 0; i
< spec
->num_pins
; i
++)
1111 snd_hda_eld_proc_new(codec
, &spec
->sink_eld
[i
], i
);
1113 init_channel_allocations();
1119 * Nvidia specific implementations
1122 #define Nv_VERB_SET_Channel_Allocation 0xF79
1123 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1124 #define Nv_VERB_SET_Audio_Protection_On 0xF98
1125 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
1127 #define nvhdmi_master_con_nid_7x 0x04
1128 #define nvhdmi_master_pin_nid_7x 0x05
1130 static hda_nid_t nvhdmi_con_nids_7x
[4] = {
1131 /*front, rear, clfe, rear_surr */
1135 static struct hda_verb nvhdmi_basic_init_7x
[] = {
1136 /* set audio protect on */
1137 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
1138 /* enable digital output on pin widget */
1139 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1140 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1141 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1142 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1143 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1147 #ifdef LIMITED_RATE_FMT_SUPPORT
1148 /* support only the safe format and rate */
1149 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1150 #define SUPPORTED_MAXBPS 16
1151 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1153 /* support all rates and formats */
1154 #define SUPPORTED_RATES \
1155 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1156 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1157 SNDRV_PCM_RATE_192000)
1158 #define SUPPORTED_MAXBPS 24
1159 #define SUPPORTED_FORMATS \
1160 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1163 static int nvhdmi_7x_init(struct hda_codec
*codec
)
1165 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x
);
1169 static int simple_playback_pcm_open(struct hda_pcm_stream
*hinfo
,
1170 struct hda_codec
*codec
,
1171 struct snd_pcm_substream
*substream
)
1173 struct hdmi_spec
*spec
= codec
->spec
;
1174 return snd_hda_multi_out_dig_open(codec
, &spec
->multiout
);
1177 static int simple_playback_pcm_close(struct hda_pcm_stream
*hinfo
,
1178 struct hda_codec
*codec
,
1179 struct snd_pcm_substream
*substream
)
1181 struct hdmi_spec
*spec
= codec
->spec
;
1182 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
1185 static int simple_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1186 struct hda_codec
*codec
,
1187 unsigned int stream_tag
,
1188 unsigned int format
,
1189 struct snd_pcm_substream
*substream
)
1191 struct hdmi_spec
*spec
= codec
->spec
;
1192 return snd_hda_multi_out_dig_prepare(codec
, &spec
->multiout
,
1193 stream_tag
, format
, substream
);
1196 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream
*hinfo
,
1197 struct hda_codec
*codec
,
1198 struct snd_pcm_substream
*substream
)
1200 struct hdmi_spec
*spec
= codec
->spec
;
1203 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
,
1204 0, AC_VERB_SET_CHANNEL_STREAMID
, 0);
1205 for (i
= 0; i
< 4; i
++) {
1206 /* set the stream id */
1207 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
1208 AC_VERB_SET_CHANNEL_STREAMID
, 0);
1209 /* set the stream format */
1210 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
1211 AC_VERB_SET_STREAM_FORMAT
, 0);
1214 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
1217 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1218 struct hda_codec
*codec
,
1219 unsigned int stream_tag
,
1220 unsigned int format
,
1221 struct snd_pcm_substream
*substream
)
1224 unsigned int dataDCC1
, dataDCC2
, chan
, chanmask
, channel_id
;
1227 mutex_lock(&codec
->spdif_mutex
);
1229 chs
= substream
->runtime
->channels
;
1230 chan
= chs
? (chs
- 1) : 1;
1248 dataDCC1
= AC_DIG1_ENABLE
| AC_DIG1_COPYRIGHT
;
1251 /* set the Audio InforFrame Channel Allocation */
1252 snd_hda_codec_write(codec
, 0x1, 0,
1253 Nv_VERB_SET_Channel_Allocation
, chanmask
);
1255 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1256 if (codec
->spdif_status_reset
&& (codec
->spdif_ctls
& AC_DIG1_ENABLE
))
1257 snd_hda_codec_write(codec
,
1258 nvhdmi_master_con_nid_7x
,
1260 AC_VERB_SET_DIGI_CONVERT_1
,
1261 codec
->spdif_ctls
& ~AC_DIG1_ENABLE
& 0xff);
1263 /* set the stream id */
1264 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
1265 AC_VERB_SET_CHANNEL_STREAMID
, (stream_tag
<< 4) | 0x0);
1267 /* set the stream format */
1268 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
1269 AC_VERB_SET_STREAM_FORMAT
, format
);
1271 /* turn on again (if needed) */
1272 /* enable and set the channel status audio/data flag */
1273 if (codec
->spdif_status_reset
&& (codec
->spdif_ctls
& AC_DIG1_ENABLE
)) {
1274 snd_hda_codec_write(codec
,
1275 nvhdmi_master_con_nid_7x
,
1277 AC_VERB_SET_DIGI_CONVERT_1
,
1278 codec
->spdif_ctls
& 0xff);
1279 snd_hda_codec_write(codec
,
1280 nvhdmi_master_con_nid_7x
,
1282 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
1285 for (i
= 0; i
< 4; i
++) {
1291 /* turn off SPDIF once;
1292 *otherwise the IEC958 bits won't be updated
1294 if (codec
->spdif_status_reset
&&
1295 (codec
->spdif_ctls
& AC_DIG1_ENABLE
))
1296 snd_hda_codec_write(codec
,
1297 nvhdmi_con_nids_7x
[i
],
1299 AC_VERB_SET_DIGI_CONVERT_1
,
1300 codec
->spdif_ctls
& ~AC_DIG1_ENABLE
& 0xff);
1301 /* set the stream id */
1302 snd_hda_codec_write(codec
,
1303 nvhdmi_con_nids_7x
[i
],
1305 AC_VERB_SET_CHANNEL_STREAMID
,
1306 (stream_tag
<< 4) | channel_id
);
1307 /* set the stream format */
1308 snd_hda_codec_write(codec
,
1309 nvhdmi_con_nids_7x
[i
],
1311 AC_VERB_SET_STREAM_FORMAT
,
1313 /* turn on again (if needed) */
1314 /* enable and set the channel status audio/data flag */
1315 if (codec
->spdif_status_reset
&&
1316 (codec
->spdif_ctls
& AC_DIG1_ENABLE
)) {
1317 snd_hda_codec_write(codec
,
1318 nvhdmi_con_nids_7x
[i
],
1320 AC_VERB_SET_DIGI_CONVERT_1
,
1321 codec
->spdif_ctls
& 0xff);
1322 snd_hda_codec_write(codec
,
1323 nvhdmi_con_nids_7x
[i
],
1325 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
1329 /* set the Audio Info Frame Checksum */
1330 snd_hda_codec_write(codec
, 0x1, 0,
1331 Nv_VERB_SET_Info_Frame_Checksum
,
1332 (0x71 - chan
- chanmask
));
1334 mutex_unlock(&codec
->spdif_mutex
);
1338 static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x
= {
1342 .nid
= nvhdmi_master_con_nid_7x
,
1343 .rates
= SUPPORTED_RATES
,
1344 .maxbps
= SUPPORTED_MAXBPS
,
1345 .formats
= SUPPORTED_FORMATS
,
1347 .open
= simple_playback_pcm_open
,
1348 .close
= nvhdmi_8ch_7x_pcm_close
,
1349 .prepare
= nvhdmi_8ch_7x_pcm_prepare
1353 static struct hda_pcm_stream nvhdmi_pcm_playback_2ch
= {
1357 .nid
= nvhdmi_master_con_nid_7x
,
1358 .rates
= SUPPORTED_RATES
,
1359 .maxbps
= SUPPORTED_MAXBPS
,
1360 .formats
= SUPPORTED_FORMATS
,
1362 .open
= simple_playback_pcm_open
,
1363 .close
= simple_playback_pcm_close
,
1364 .prepare
= simple_playback_pcm_prepare
1368 static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x
= {
1369 .build_controls
= generic_hdmi_build_controls
,
1370 .build_pcms
= generic_hdmi_build_pcms
,
1371 .init
= nvhdmi_7x_init
,
1372 .free
= generic_hdmi_free
,
1375 static struct hda_codec_ops nvhdmi_patch_ops_2ch
= {
1376 .build_controls
= generic_hdmi_build_controls
,
1377 .build_pcms
= generic_hdmi_build_pcms
,
1378 .init
= nvhdmi_7x_init
,
1379 .free
= generic_hdmi_free
,
1382 static int patch_nvhdmi_8ch_89(struct hda_codec
*codec
)
1384 struct hdmi_spec
*spec
;
1385 int err
= patch_generic_hdmi(codec
);
1390 spec
->old_pin_detect
= 1;
1394 static int patch_nvhdmi_2ch(struct hda_codec
*codec
)
1396 struct hdmi_spec
*spec
;
1398 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
1404 spec
->multiout
.num_dacs
= 0; /* no analog */
1405 spec
->multiout
.max_channels
= 2;
1406 spec
->multiout
.dig_out_nid
= nvhdmi_master_con_nid_7x
;
1407 spec
->old_pin_detect
= 1;
1409 spec
->cvt
[0] = nvhdmi_master_con_nid_7x
;
1410 spec
->pcm_playback
= &nvhdmi_pcm_playback_2ch
;
1412 codec
->patch_ops
= nvhdmi_patch_ops_2ch
;
1417 static int patch_nvhdmi_8ch_7x(struct hda_codec
*codec
)
1419 struct hdmi_spec
*spec
;
1420 int err
= patch_nvhdmi_2ch(codec
);
1425 spec
->multiout
.max_channels
= 8;
1426 spec
->pcm_playback
= &nvhdmi_pcm_playback_8ch_7x
;
1427 codec
->patch_ops
= nvhdmi_patch_ops_8ch_7x
;
1432 * ATI-specific implementations
1434 * FIXME: we may omit the whole this and use the generic code once after
1435 * it's confirmed to work.
1438 #define ATIHDMI_CVT_NID 0x02 /* audio converter */
1439 #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1441 static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1442 struct hda_codec
*codec
,
1443 unsigned int stream_tag
,
1444 unsigned int format
,
1445 struct snd_pcm_substream
*substream
)
1447 struct hdmi_spec
*spec
= codec
->spec
;
1448 int chans
= substream
->runtime
->channels
;
1451 err
= simple_playback_pcm_prepare(hinfo
, codec
, stream_tag
, format
,
1455 snd_hda_codec_write(codec
, spec
->cvt
[0], 0, AC_VERB_SET_CVT_CHAN_COUNT
,
1458 for (i
= 0; i
< chans
; i
++) {
1459 snd_hda_codec_write(codec
, spec
->cvt
[0], 0,
1460 AC_VERB_SET_HDMI_CHAN_SLOT
,
1466 static struct hda_pcm_stream atihdmi_pcm_digital_playback
= {
1470 .nid
= ATIHDMI_CVT_NID
,
1472 .open
= simple_playback_pcm_open
,
1473 .close
= simple_playback_pcm_close
,
1474 .prepare
= atihdmi_playback_pcm_prepare
1478 static struct hda_verb atihdmi_basic_init
[] = {
1479 /* enable digital output on pin widget */
1480 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
},
1484 static int atihdmi_init(struct hda_codec
*codec
)
1486 struct hdmi_spec
*spec
= codec
->spec
;
1488 snd_hda_sequence_write(codec
, atihdmi_basic_init
);
1489 /* SI codec requires to unmute the pin */
1490 if (get_wcaps(codec
, spec
->pin
[0]) & AC_WCAP_OUT_AMP
)
1491 snd_hda_codec_write(codec
, spec
->pin
[0], 0,
1492 AC_VERB_SET_AMP_GAIN_MUTE
,
1497 static struct hda_codec_ops atihdmi_patch_ops
= {
1498 .build_controls
= generic_hdmi_build_controls
,
1499 .build_pcms
= generic_hdmi_build_pcms
,
1500 .init
= atihdmi_init
,
1501 .free
= generic_hdmi_free
,
1505 static int patch_atihdmi(struct hda_codec
*codec
)
1507 struct hdmi_spec
*spec
;
1509 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
1515 spec
->multiout
.num_dacs
= 0; /* no analog */
1516 spec
->multiout
.max_channels
= 2;
1517 spec
->multiout
.dig_out_nid
= ATIHDMI_CVT_NID
;
1519 spec
->cvt
[0] = ATIHDMI_CVT_NID
;
1520 spec
->pin
[0] = ATIHDMI_PIN_NID
;
1521 spec
->pcm_playback
= &atihdmi_pcm_digital_playback
;
1523 codec
->patch_ops
= atihdmi_patch_ops
;
1532 static struct hda_codec_preset snd_hda_preset_hdmi
[] = {
1533 { .id
= 0x1002793c, .name
= "RS600 HDMI", .patch
= patch_atihdmi
},
1534 { .id
= 0x10027919, .name
= "RS600 HDMI", .patch
= patch_atihdmi
},
1535 { .id
= 0x1002791a, .name
= "RS690/780 HDMI", .patch
= patch_atihdmi
},
1536 { .id
= 0x1002aa01, .name
= "R6xx HDMI", .patch
= patch_atihdmi
},
1537 { .id
= 0x10951390, .name
= "SiI1390 HDMI", .patch
= patch_generic_hdmi
},
1538 { .id
= 0x10951392, .name
= "SiI1392 HDMI", .patch
= patch_generic_hdmi
},
1539 { .id
= 0x17e80047, .name
= "Chrontel HDMI", .patch
= patch_generic_hdmi
},
1540 { .id
= 0x10de0002, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1541 { .id
= 0x10de0003, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1542 { .id
= 0x10de0005, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1543 { .id
= 0x10de0006, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1544 { .id
= 0x10de0007, .name
= "MCP79/7A HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1545 { .id
= 0x10de000a, .name
= "GPU 0a HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1546 { .id
= 0x10de000b, .name
= "GPU 0b HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1547 { .id
= 0x10de000c, .name
= "MCP89 HDMI", .patch
= patch_nvhdmi_8ch_89
},
1548 { .id
= 0x10de000d, .name
= "GPU 0d HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1549 { .id
= 0x10de0010, .name
= "GPU 10 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1550 { .id
= 0x10de0011, .name
= "GPU 11 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1551 { .id
= 0x10de0012, .name
= "GPU 12 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1552 { .id
= 0x10de0013, .name
= "GPU 13 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1553 { .id
= 0x10de0014, .name
= "GPU 14 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1554 { .id
= 0x10de0018, .name
= "GPU 18 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1555 { .id
= 0x10de0019, .name
= "GPU 19 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1556 { .id
= 0x10de001a, .name
= "GPU 1a HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1557 { .id
= 0x10de001b, .name
= "GPU 1b HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1558 { .id
= 0x10de001c, .name
= "GPU 1c HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1559 { .id
= 0x10de0040, .name
= "GPU 40 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1560 { .id
= 0x10de0041, .name
= "GPU 41 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1561 { .id
= 0x10de0042, .name
= "GPU 42 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1562 { .id
= 0x10de0043, .name
= "GPU 43 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1563 { .id
= 0x10de0044, .name
= "GPU 44 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1564 { .id
= 0x10de0067, .name
= "MCP67 HDMI", .patch
= patch_nvhdmi_2ch
},
1565 { .id
= 0x10de8001, .name
= "MCP73 HDMI", .patch
= patch_nvhdmi_2ch
},
1566 { .id
= 0x80860054, .name
= "IbexPeak HDMI", .patch
= patch_generic_hdmi
},
1567 { .id
= 0x80862801, .name
= "Bearlake HDMI", .patch
= patch_generic_hdmi
},
1568 { .id
= 0x80862802, .name
= "Cantiga HDMI", .patch
= patch_generic_hdmi
},
1569 { .id
= 0x80862803, .name
= "Eaglelake HDMI", .patch
= patch_generic_hdmi
},
1570 { .id
= 0x80862804, .name
= "IbexPeak HDMI", .patch
= patch_generic_hdmi
},
1571 { .id
= 0x80862805, .name
= "CougarPoint HDMI", .patch
= patch_generic_hdmi
},
1572 { .id
= 0x808629fb, .name
= "Crestline HDMI", .patch
= patch_generic_hdmi
},
1576 MODULE_ALIAS("snd-hda-codec-id:1002793c");
1577 MODULE_ALIAS("snd-hda-codec-id:10027919");
1578 MODULE_ALIAS("snd-hda-codec-id:1002791a");
1579 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1580 MODULE_ALIAS("snd-hda-codec-id:10951390");
1581 MODULE_ALIAS("snd-hda-codec-id:10951392");
1582 MODULE_ALIAS("snd-hda-codec-id:10de0002");
1583 MODULE_ALIAS("snd-hda-codec-id:10de0003");
1584 MODULE_ALIAS("snd-hda-codec-id:10de0005");
1585 MODULE_ALIAS("snd-hda-codec-id:10de0006");
1586 MODULE_ALIAS("snd-hda-codec-id:10de0007");
1587 MODULE_ALIAS("snd-hda-codec-id:10de000a");
1588 MODULE_ALIAS("snd-hda-codec-id:10de000b");
1589 MODULE_ALIAS("snd-hda-codec-id:10de000c");
1590 MODULE_ALIAS("snd-hda-codec-id:10de000d");
1591 MODULE_ALIAS("snd-hda-codec-id:10de0010");
1592 MODULE_ALIAS("snd-hda-codec-id:10de0011");
1593 MODULE_ALIAS("snd-hda-codec-id:10de0012");
1594 MODULE_ALIAS("snd-hda-codec-id:10de0013");
1595 MODULE_ALIAS("snd-hda-codec-id:10de0014");
1596 MODULE_ALIAS("snd-hda-codec-id:10de0018");
1597 MODULE_ALIAS("snd-hda-codec-id:10de0019");
1598 MODULE_ALIAS("snd-hda-codec-id:10de001a");
1599 MODULE_ALIAS("snd-hda-codec-id:10de001b");
1600 MODULE_ALIAS("snd-hda-codec-id:10de001c");
1601 MODULE_ALIAS("snd-hda-codec-id:10de0040");
1602 MODULE_ALIAS("snd-hda-codec-id:10de0041");
1603 MODULE_ALIAS("snd-hda-codec-id:10de0042");
1604 MODULE_ALIAS("snd-hda-codec-id:10de0043");
1605 MODULE_ALIAS("snd-hda-codec-id:10de0044");
1606 MODULE_ALIAS("snd-hda-codec-id:10de0067");
1607 MODULE_ALIAS("snd-hda-codec-id:10de8001");
1608 MODULE_ALIAS("snd-hda-codec-id:17e80047");
1609 MODULE_ALIAS("snd-hda-codec-id:80860054");
1610 MODULE_ALIAS("snd-hda-codec-id:80862801");
1611 MODULE_ALIAS("snd-hda-codec-id:80862802");
1612 MODULE_ALIAS("snd-hda-codec-id:80862803");
1613 MODULE_ALIAS("snd-hda-codec-id:80862804");
1614 MODULE_ALIAS("snd-hda-codec-id:80862805");
1615 MODULE_ALIAS("snd-hda-codec-id:808629fb");
1617 MODULE_LICENSE("GPL");
1618 MODULE_DESCRIPTION("HDMI HD-audio codec");
1619 MODULE_ALIAS("snd-hda-codec-intelhdmi");
1620 MODULE_ALIAS("snd-hda-codec-nvhdmi");
1621 MODULE_ALIAS("snd-hda-codec-atihdmi");
1623 static struct hda_codec_preset_list intel_list
= {
1624 .preset
= snd_hda_preset_hdmi
,
1625 .owner
= THIS_MODULE
,
1628 static int __init
patch_hdmi_init(void)
1630 return snd_hda_add_codec_preset(&intel_list
);
1633 static void __exit
patch_hdmi_exit(void)
1635 snd_hda_delete_codec_preset(&intel_list
);
1638 module_init(patch_hdmi_init
)
1639 module_exit(patch_hdmi_exit
)