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Merge branch 'firewire-kernel-streaming' of git://git.alsa-project.org/alsa-kprivate
[firewire-audio.git] / sound / pci / hda / patch_hdmi.c
blobec0fa2dd0a2792a3fb7e1a18334fd3eb28225b29
1 /*
2 *
3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
4 *
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9 *
10 * Authors:
11 * Wu Fengguang <wfg@linux.intel.com>
12 *
13 * Maintained by:
14 * Wu Fengguang <wfg@linux.intel.com>
15 *
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <linux/moduleparam.h>
35 #include <sound/core.h>
36 #include "hda_codec.h"
37 #include "hda_local.h"
38
39 static bool static_hdmi_pcm;
40 module_param(static_hdmi_pcm, bool, 0644);
41 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
42
43 /*
44 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
45 * could support two independent pipes, each of them can be connected to one or
46 * more ports (DVI, HDMI or DisplayPort).
47 *
48 * The HDA correspondence of pipes/ports are converter/pin nodes.
49 */
50 #define MAX_HDMI_CVTS 3
51 #define MAX_HDMI_PINS 3
52
53 struct hdmi_spec {
54 int num_cvts;
55 int num_pins;
56 hda_nid_t cvt[MAX_HDMI_CVTS+1]; /* audio sources */
57 hda_nid_t pin[MAX_HDMI_PINS+1]; /* audio sinks */
58
59 /*
60 * source connection for each pin
61 */
62 hda_nid_t pin_cvt[MAX_HDMI_PINS+1];
63
64 /*
65 * HDMI sink attached to each pin
66 */
67 struct hdmi_eld sink_eld[MAX_HDMI_PINS];
68
69 /*
70 * export one pcm per pipe
71 */
72 struct hda_pcm pcm_rec[MAX_HDMI_CVTS];
73 struct hda_pcm_stream codec_pcm_pars[MAX_HDMI_CVTS];
74
75 /*
76 * ati/nvhdmi specific
77 */
78 struct hda_multi_out multiout;
79 struct hda_pcm_stream *pcm_playback;
80
81 /* misc flags */
82 /* PD bit indicates only the update, not the current state */
83 unsigned int old_pin_detect:1;
84 };
85
86
87 struct hdmi_audio_infoframe {
88 u8 type; /* 0x84 */
89 u8 ver; /* 0x01 */
90 u8 len; /* 0x0a */
91
92 u8 checksum;
93
94 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
95 u8 SS01_SF24;
96 u8 CXT04;
97 u8 CA;
98 u8 LFEPBL01_LSV36_DM_INH7;
99 };
100
101 struct dp_audio_infoframe {
102 u8 type; /* 0x84 */
103 u8 len; /* 0x1b */
104 u8 ver; /* 0x11 << 2 */
105
106 u8 CC02_CT47; /* match with HDMI infoframe from this on */
107 u8 SS01_SF24;
108 u8 CXT04;
109 u8 CA;
110 u8 LFEPBL01_LSV36_DM_INH7;
111 };
112
113 /*
114 * CEA speaker placement:
115 *
116 * FLH FCH FRH
117 * FLW FL FLC FC FRC FR FRW
118 *
119 * LFE
120 * TC
121 *
122 * RL RLC RC RRC RR
123 *
124 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
125 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
126 */
127 enum cea_speaker_placement {
128 FL = (1 << 0), /* Front Left */
129 FC = (1 << 1), /* Front Center */
130 FR = (1 << 2), /* Front Right */
131 FLC = (1 << 3), /* Front Left Center */
132 FRC = (1 << 4), /* Front Right Center */
133 RL = (1 << 5), /* Rear Left */
134 RC = (1 << 6), /* Rear Center */
135 RR = (1 << 7), /* Rear Right */
136 RLC = (1 << 8), /* Rear Left Center */
137 RRC = (1 << 9), /* Rear Right Center */
138 LFE = (1 << 10), /* Low Frequency Effect */
139 FLW = (1 << 11), /* Front Left Wide */
140 FRW = (1 << 12), /* Front Right Wide */
141 FLH = (1 << 13), /* Front Left High */
142 FCH = (1 << 14), /* Front Center High */
143 FRH = (1 << 15), /* Front Right High */
144 TC = (1 << 16), /* Top Center */
145 };
146
147 /*
148 * ELD SA bits in the CEA Speaker Allocation data block
149 */
150 static int eld_speaker_allocation_bits[] = {
151 [0] = FL | FR,
152 [1] = LFE,
153 [2] = FC,
154 [3] = RL | RR,
155 [4] = RC,
156 [5] = FLC | FRC,
157 [6] = RLC | RRC,
158 /* the following are not defined in ELD yet */
159 [7] = FLW | FRW,
160 [8] = FLH | FRH,
161 [9] = TC,
162 [10] = FCH,
163 };
164
165 struct cea_channel_speaker_allocation {
166 int ca_index;
167 int speakers[8];
168
169 /* derived values, just for convenience */
170 int channels;
171 int spk_mask;
172 };
173
174 /*
175 * ALSA sequence is:
176 *
177 * surround40 surround41 surround50 surround51 surround71
178 * ch0 front left = = = =
179 * ch1 front right = = = =
180 * ch2 rear left = = = =
181 * ch3 rear right = = = =
182 * ch4 LFE center center center
183 * ch5 LFE LFE
184 * ch6 side left
185 * ch7 side right
186 *
187 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
188 */
189 static int hdmi_channel_mapping[0x32][8] = {
190 /* stereo */
191 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
192 /* 2.1 */
193 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
194 /* Dolby Surround */
195 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
196 /* surround40 */
197 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
198 /* 4ch */
199 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
200 /* surround41 */
201 [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
202 /* surround50 */
203 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
204 /* surround51 */
205 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
206 /* 7.1 */
207 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
208 };
209
210 /*
211 * This is an ordered list!
212 *
213 * The preceding ones have better chances to be selected by
214 * hdmi_channel_allocation().
215 */
216 static struct cea_channel_speaker_allocation channel_allocations[] = {
217 /* channel: 7 6 5 4 3 2 1 0 */
218 { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
219 /* 2.1 */
220 { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
221 /* Dolby Surround */
222 { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
223 /* surround40 */
224 { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
225 /* surround41 */
226 { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
227 /* surround50 */
228 { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
229 /* surround51 */
230 { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
231 /* 6.1 */
232 { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
233 /* surround71 */
234 { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
235
236 { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
237 { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
238 { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
239 { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
240 { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
241 { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
242 { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
243 { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
244 { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
245 { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
246 { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
247 { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
248 { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
249 { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
250 { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
251 { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
252 { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
253 { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
254 { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
255 { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
256 { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
257 { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
258 { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
259 { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
260 { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
261 { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
262 { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
263 { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
264 { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
265 { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
266 { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
267 { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
268 { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
269 { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
270 { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
271 { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
272 { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
273 { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
274 { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
275 { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
276 { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
277 };
278
279
280 /*
281 * HDMI routines
282 */
283
284 static int hda_node_index(hda_nid_t *nids, hda_nid_t nid)
285 {
286 int i;
287
288 for (i = 0; nids[i]; i++)
289 if (nids[i] == nid)
290 return i;
291
292 snd_printk(KERN_WARNING "HDMI: nid %d not registered\n", nid);
293 return -EINVAL;
294 }
295
296 static void hdmi_get_show_eld(struct hda_codec *codec, hda_nid_t pin_nid,
297 struct hdmi_eld *eld)
298 {
299 if (!snd_hdmi_get_eld(eld, codec, pin_nid))
300 snd_hdmi_show_eld(eld);
301 }
302
303 #ifdef BE_PARANOID
304 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
305 int *packet_index, int *byte_index)
306 {
307 int val;
308
309 val = snd_hda_codec_read(codec, pin_nid, 0,
310 AC_VERB_GET_HDMI_DIP_INDEX, 0);
311
312 *packet_index = val >> 5;
313 *byte_index = val & 0x1f;
314 }
315 #endif
316
317 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
318 int packet_index, int byte_index)
319 {
320 int val;
321
322 val = (packet_index << 5) | (byte_index & 0x1f);
323
324 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
325 }
326
327 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
328 unsigned char val)
329 {
330 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
331 }
332
333 static void hdmi_enable_output(struct hda_codec *codec, hda_nid_t pin_nid)
334 {
335 /* Unmute */
336 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
337 snd_hda_codec_write(codec, pin_nid, 0,
338 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
339 /* Enable pin out */
340 snd_hda_codec_write(codec, pin_nid, 0,
341 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
342 }
343
344 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t nid)
345 {
346 return 1 + snd_hda_codec_read(codec, nid, 0,
347 AC_VERB_GET_CVT_CHAN_COUNT, 0);
348 }
349
350 static void hdmi_set_channel_count(struct hda_codec *codec,
351 hda_nid_t nid, int chs)
352 {
353 if (chs != hdmi_get_channel_count(codec, nid))
354 snd_hda_codec_write(codec, nid, 0,
355 AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
356 }
357
358
359 /*
360 * Channel mapping routines
361 */
362
363 /*
364 * Compute derived values in channel_allocations[].
365 */
366 static void init_channel_allocations(void)
367 {
368 int i, j;
369 struct cea_channel_speaker_allocation *p;
370
371 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
372 p = channel_allocations + i;
373 p->channels = 0;
374 p->spk_mask = 0;
375 for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
376 if (p->speakers[j]) {
377 p->channels++;
378 p->spk_mask |= p->speakers[j];
379 }
380 }
381 }
382
383 /*
384 * The transformation takes two steps:
385 *
386 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
387 * spk_mask => (channel_allocations[]) => ai->CA
388 *
389 * TODO: it could select the wrong CA from multiple candidates.
390 */
391 static int hdmi_channel_allocation(struct hda_codec *codec, hda_nid_t nid,
392 int channels)
393 {
394 struct hdmi_spec *spec = codec->spec;
395 struct hdmi_eld *eld;
396 int i;
397 int ca = 0;
398 int spk_mask = 0;
399 char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
400
401 /*
402 * CA defaults to 0 for basic stereo audio
403 */
404 if (channels <= 2)
405 return 0;
406
407 i = hda_node_index(spec->pin_cvt, nid);
408 if (i < 0)
409 return 0;
410 eld = &spec->sink_eld[i];
411
412 /*
413 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
414 * in console or for audio devices. Assume the highest speakers
415 * configuration, to _not_ prohibit multi-channel audio playback.
416 */
417 if (!eld->spk_alloc)
418 eld->spk_alloc = 0xffff;
419
420 /*
421 * expand ELD's speaker allocation mask
422 *
423 * ELD tells the speaker mask in a compact(paired) form,
424 * expand ELD's notions to match the ones used by Audio InfoFrame.
425 */
426 for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
427 if (eld->spk_alloc & (1 << i))
428 spk_mask |= eld_speaker_allocation_bits[i];
429 }
430
431 /* search for the first working match in the CA table */
432 for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
433 if (channels == channel_allocations[i].channels &&
434 (spk_mask & channel_allocations[i].spk_mask) ==
435 channel_allocations[i].spk_mask) {
436 ca = channel_allocations[i].ca_index;
437 break;
438 }
439 }
440
441 snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
442 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
443 ca, channels, buf);
444
445 return ca;
446 }
447
448 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
449 hda_nid_t pin_nid)
450 {
451 #ifdef CONFIG_SND_DEBUG_VERBOSE
452 int i;
453 int slot;
454
455 for (i = 0; i < 8; i++) {
456 slot = snd_hda_codec_read(codec, pin_nid, 0,
457 AC_VERB_GET_HDMI_CHAN_SLOT, i);
458 printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
459 slot >> 4, slot & 0xf);
460 }
461 #endif
462 }
463
464
465 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
466 hda_nid_t pin_nid,
467 int ca)
468 {
469 int i;
470 int err;
471
472 if (hdmi_channel_mapping[ca][1] == 0) {
473 for (i = 0; i < channel_allocations[ca].channels; i++)
474 hdmi_channel_mapping[ca][i] = i | (i << 4);
475 for (; i < 8; i++)
476 hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
477 }
478
479 for (i = 0; i < 8; i++) {
480 err = snd_hda_codec_write(codec, pin_nid, 0,
481 AC_VERB_SET_HDMI_CHAN_SLOT,
482 hdmi_channel_mapping[ca][i]);
483 if (err) {
484 snd_printdd(KERN_NOTICE
485 "HDMI: channel mapping failed\n");
486 break;
487 }
488 }
489
490 hdmi_debug_channel_mapping(codec, pin_nid);
491 }
492
493
494 /*
495 * Audio InfoFrame routines
496 */
497
498 /*
499 * Enable Audio InfoFrame Transmission
500 */
501 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
502 hda_nid_t pin_nid)
503 {
504 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
505 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
506 AC_DIPXMIT_BEST);
507 }
508
509 /*
510 * Disable Audio InfoFrame Transmission
511 */
512 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
513 hda_nid_t pin_nid)
514 {
515 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
516 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
517 AC_DIPXMIT_DISABLE);
518 }
519
520 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
521 {
522 #ifdef CONFIG_SND_DEBUG_VERBOSE
523 int i;
524 int size;
525
526 size = snd_hdmi_get_eld_size(codec, pin_nid);
527 printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
528
529 for (i = 0; i < 8; i++) {
530 size = snd_hda_codec_read(codec, pin_nid, 0,
531 AC_VERB_GET_HDMI_DIP_SIZE, i);
532 printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
533 }
534 #endif
535 }
536
537 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
538 {
539 #ifdef BE_PARANOID
540 int i, j;
541 int size;
542 int pi, bi;
543 for (i = 0; i < 8; i++) {
544 size = snd_hda_codec_read(codec, pin_nid, 0,
545 AC_VERB_GET_HDMI_DIP_SIZE, i);
546 if (size == 0)
547 continue;
548
549 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
550 for (j = 1; j < 1000; j++) {
551 hdmi_write_dip_byte(codec, pin_nid, 0x0);
552 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
553 if (pi != i)
554 snd_printd(KERN_INFO "dip index %d: %d != %d\n",
555 bi, pi, i);
556 if (bi == 0) /* byte index wrapped around */
557 break;
558 }
559 snd_printd(KERN_INFO
560 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
561 i, size, j);
562 }
563 #endif
564 }
565
566 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
567 {
568 u8 *bytes = (u8 *)hdmi_ai;
569 u8 sum = 0;
570 int i;
571
572 hdmi_ai->checksum = 0;
573
574 for (i = 0; i < sizeof(*hdmi_ai); i++)
575 sum += bytes[i];
576
577 hdmi_ai->checksum = -sum;
578 }
579
580 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
581 hda_nid_t pin_nid,
582 u8 *dip, int size)
583 {
584 int i;
585
586 hdmi_debug_dip_size(codec, pin_nid);
587 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
588
589 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
590 for (i = 0; i < size; i++)
591 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
592 }
593
594 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
595 u8 *dip, int size)
596 {
597 u8 val;
598 int i;
599
600 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
601 != AC_DIPXMIT_BEST)
602 return false;
603
604 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
605 for (i = 0; i < size; i++) {
606 val = snd_hda_codec_read(codec, pin_nid, 0,
607 AC_VERB_GET_HDMI_DIP_DATA, 0);
608 if (val != dip[i])
609 return false;
610 }
611
612 return true;
613 }
614
615 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, hda_nid_t nid,
616 struct snd_pcm_substream *substream)
617 {
618 struct hdmi_spec *spec = codec->spec;
619 hda_nid_t pin_nid;
620 int channels = substream->runtime->channels;
621 int ca;
622 int i;
623 u8 ai[max(sizeof(struct hdmi_audio_infoframe),
624 sizeof(struct dp_audio_infoframe))];
625
626 ca = hdmi_channel_allocation(codec, nid, channels);
627
628 for (i = 0; i < spec->num_pins; i++) {
629 if (spec->pin_cvt[i] != nid)
630 continue;
631 if (!spec->sink_eld[i].monitor_present)
632 continue;
633
634 pin_nid = spec->pin[i];
635
636 memset(ai, 0, sizeof(ai));
637 if (spec->sink_eld[i].conn_type == 0) { /* HDMI */
638 struct hdmi_audio_infoframe *hdmi_ai;
639
640 hdmi_ai = (struct hdmi_audio_infoframe *)ai;
641 hdmi_ai->type = 0x84;
642 hdmi_ai->ver = 0x01;
643 hdmi_ai->len = 0x0a;
644 hdmi_ai->CC02_CT47 = channels - 1;
645 hdmi_ai->CA = ca;
646 hdmi_checksum_audio_infoframe(hdmi_ai);
647 } else if (spec->sink_eld[i].conn_type == 1) { /* DisplayPort */
648 struct dp_audio_infoframe *dp_ai;
649
650 dp_ai = (struct dp_audio_infoframe *)ai;
651 dp_ai->type = 0x84;
652 dp_ai->len = 0x1b;
653 dp_ai->ver = 0x11 << 2;
654 dp_ai->CC02_CT47 = channels - 1;
655 dp_ai->CA = ca;
656 } else {
657 snd_printd("HDMI: unknown connection type at pin %d\n",
658 pin_nid);
659 continue;
660 }
661
662 /*
663 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
664 * sizeof(*dp_ai) to avoid partial match/update problems when
665 * the user switches between HDMI/DP monitors.
666 */
667 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai, sizeof(ai))) {
668 snd_printdd("hdmi_setup_audio_infoframe: "
669 "cvt=%d pin=%d channels=%d\n",
670 nid, pin_nid,
671 channels);
672 hdmi_setup_channel_mapping(codec, pin_nid, ca);
673 hdmi_stop_infoframe_trans(codec, pin_nid);
674 hdmi_fill_audio_infoframe(codec, pin_nid,
675 ai, sizeof(ai));
676 hdmi_start_infoframe_trans(codec, pin_nid);
677 }
678 }
679 }
680
681
682 /*
683 * Unsolicited events
684 */
685
686 static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
687 struct hdmi_eld *eld);
688
689 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
690 {
691 struct hdmi_spec *spec = codec->spec;
692 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
693 int pind = !!(res & AC_UNSOL_RES_PD);
694 int eldv = !!(res & AC_UNSOL_RES_ELDV);
695 int index;
696
697 printk(KERN_INFO
698 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
699 tag, pind, eldv);
700
701 index = hda_node_index(spec->pin, tag);
702 if (index < 0)
703 return;
704
705 if (spec->old_pin_detect) {
706 if (pind)
707 hdmi_present_sense(codec, tag, &spec->sink_eld[index]);
708 pind = spec->sink_eld[index].monitor_present;
709 }
710
711 spec->sink_eld[index].monitor_present = pind;
712 spec->sink_eld[index].eld_valid = eldv;
713
714 if (pind && eldv) {
715 hdmi_get_show_eld(codec, spec->pin[index],
716 &spec->sink_eld[index]);
717 /* TODO: do real things about ELD */
718 }
719 }
720
721 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
722 {
723 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
724 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
725 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
726 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
727
728 printk(KERN_INFO
729 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
730 tag,
731 subtag,
732 cp_state,
733 cp_ready);
734
735 /* TODO */
736 if (cp_state)
737 ;
738 if (cp_ready)
739 ;
740 }
741
742
743 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
744 {
745 struct hdmi_spec *spec = codec->spec;
746 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
747 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
748
749 if (hda_node_index(spec->pin, tag) < 0) {
750 snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
751 return;
752 }
753
754 if (subtag == 0)
755 hdmi_intrinsic_event(codec, res);
756 else
757 hdmi_non_intrinsic_event(codec, res);
758 }
759
760 /*
761 * Callbacks
762 */
763
764 /* HBR should be Non-PCM, 8 channels */
765 #define is_hbr_format(format) \
766 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
767
768 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t nid,
769 u32 stream_tag, int format)
770 {
771 struct hdmi_spec *spec = codec->spec;
772 int pinctl;
773 int new_pinctl = 0;
774 int i;
775
776 for (i = 0; i < spec->num_pins; i++) {
777 if (spec->pin_cvt[i] != nid)
778 continue;
779 if (!(snd_hda_query_pin_caps(codec, spec->pin[i]) & AC_PINCAP_HBR))
780 continue;
781
782 pinctl = snd_hda_codec_read(codec, spec->pin[i], 0,
783 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
784
785 new_pinctl = pinctl & ~AC_PINCTL_EPT;
786 if (is_hbr_format(format))
787 new_pinctl |= AC_PINCTL_EPT_HBR;
788 else
789 new_pinctl |= AC_PINCTL_EPT_NATIVE;
790
791 snd_printdd("hdmi_setup_stream: "
792 "NID=0x%x, %spinctl=0x%x\n",
793 spec->pin[i],
794 pinctl == new_pinctl ? "" : "new-",
795 new_pinctl);
796
797 if (pinctl != new_pinctl)
798 snd_hda_codec_write(codec, spec->pin[i], 0,
799 AC_VERB_SET_PIN_WIDGET_CONTROL,
800 new_pinctl);
801 }
802
803 if (is_hbr_format(format) && !new_pinctl) {
804 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
805 return -EINVAL;
806 }
807
808 snd_hda_codec_setup_stream(codec, nid, stream_tag, 0, format);
809 return 0;
810 }
811
812 /*
813 * HDA PCM callbacks
814 */
815 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
816 struct hda_codec *codec,
817 struct snd_pcm_substream *substream)
818 {
819 struct hdmi_spec *spec = codec->spec;
820 struct hdmi_eld *eld;
821 struct hda_pcm_stream *codec_pars;
822 struct snd_pcm_runtime *runtime = substream->runtime;
823 unsigned int idx;
824
825 for (idx = 0; idx < spec->num_cvts; idx++)
826 if (hinfo->nid == spec->cvt[idx])
827 break;
828 if (snd_BUG_ON(idx >= spec->num_cvts) ||
829 snd_BUG_ON(idx >= spec->num_pins))
830 return -EINVAL;
831
832 /* save the PCM info the codec provides */
833 codec_pars = &spec->codec_pcm_pars[idx];
834 if (!codec_pars->rates)
835 *codec_pars = *hinfo;
836
837 eld = &spec->sink_eld[idx];
838 if (!static_hdmi_pcm && eld->eld_valid && eld->sad_count > 0) {
839 hdmi_eld_update_pcm_info(eld, hinfo, codec_pars);
840 if (hinfo->channels_min > hinfo->channels_max ||
841 !hinfo->rates || !hinfo->formats)
842 return -ENODEV;
843 } else {
844 /* fallback to the codec default */
845 hinfo->channels_max = codec_pars->channels_max;
846 hinfo->rates = codec_pars->rates;
847 hinfo->formats = codec_pars->formats;
848 hinfo->maxbps = codec_pars->maxbps;
849 }
850 /* store the updated parameters */
851 runtime->hw.channels_min = hinfo->channels_min;
852 runtime->hw.channels_max = hinfo->channels_max;
853 runtime->hw.formats = hinfo->formats;
854 runtime->hw.rates = hinfo->rates;
855
856 snd_pcm_hw_constraint_step(substream->runtime, 0,
857 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
858 return 0;
859 }
860
861 /*
862 * HDA/HDMI auto parsing
863 */
864 static int hdmi_read_pin_conn(struct hda_codec *codec, hda_nid_t pin_nid)
865 {
866 struct hdmi_spec *spec = codec->spec;
867 hda_nid_t conn_list[HDA_MAX_CONNECTIONS];
868 int conn_len, curr;
869 int index;
870
871 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
872 snd_printk(KERN_WARNING
873 "HDMI: pin %d wcaps %#x "
874 "does not support connection list\n",
875 pin_nid, get_wcaps(codec, pin_nid));
876 return -EINVAL;
877 }
878
879 conn_len = snd_hda_get_connections(codec, pin_nid, conn_list,
880 HDA_MAX_CONNECTIONS);
881 if (conn_len > 1)
882 curr = snd_hda_codec_read(codec, pin_nid, 0,
883 AC_VERB_GET_CONNECT_SEL, 0);
884 else
885 curr = 0;
886
887 index = hda_node_index(spec->pin, pin_nid);
888 if (index < 0)
889 return -EINVAL;
890
891 spec->pin_cvt[index] = conn_list[curr];
892
893 return 0;
894 }
895
896 static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
897 struct hdmi_eld *eld)
898 {
899 int present = snd_hda_pin_sense(codec, pin_nid);
900
901 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
902 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
903
904 if (present & AC_PINSENSE_ELDV)
905 hdmi_get_show_eld(codec, pin_nid, eld);
906 }
907
908 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
909 {
910 struct hdmi_spec *spec = codec->spec;
911
912 if (spec->num_pins >= MAX_HDMI_PINS) {
913 snd_printk(KERN_WARNING
914 "HDMI: no space for pin %d\n", pin_nid);
915 return -E2BIG;
916 }
917
918 hdmi_present_sense(codec, pin_nid, &spec->sink_eld[spec->num_pins]);
919
920 spec->pin[spec->num_pins] = pin_nid;
921 spec->num_pins++;
922
923 return hdmi_read_pin_conn(codec, pin_nid);
924 }
925
926 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t nid)
927 {
928 int i, found_pin = 0;
929 struct hdmi_spec *spec = codec->spec;
930
931 for (i = 0; i < spec->num_pins; i++)
932 if (nid == spec->pin_cvt[i]) {
933 found_pin = 1;
934 break;
935 }
936
937 if (!found_pin) {
938 snd_printdd("HDMI: Skipping node %d (no connection)\n", nid);
939 return -EINVAL;
940 }
941
942 if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
943 return -E2BIG;
944
945 spec->cvt[spec->num_cvts] = nid;
946 spec->num_cvts++;
947
948 return 0;
949 }
950
951 static int hdmi_parse_codec(struct hda_codec *codec)
952 {
953 hda_nid_t nid;
954 int i, nodes;
955 int num_tmp_cvts = 0;
956 hda_nid_t tmp_cvt[MAX_HDMI_CVTS];
957
958 nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
959 if (!nid || nodes < 0) {
960 snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
961 return -EINVAL;
962 }
963
964 for (i = 0; i < nodes; i++, nid++) {
965 unsigned int caps;
966 unsigned int type;
967 unsigned int config;
968
969 caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
970 type = get_wcaps_type(caps);
971
972 if (!(caps & AC_WCAP_DIGITAL))
973 continue;
974
975 switch (type) {
976 case AC_WID_AUD_OUT:
977 if (num_tmp_cvts >= MAX_HDMI_CVTS) {
978 snd_printk(KERN_WARNING
979 "HDMI: no space for converter %d\n", nid);
980 continue;
981 }
982 tmp_cvt[num_tmp_cvts] = nid;
983 num_tmp_cvts++;
984 break;
985 case AC_WID_PIN:
986 caps = snd_hda_param_read(codec, nid, AC_PAR_PIN_CAP);
987 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
988 continue;
989
990 config = snd_hda_codec_read(codec, nid, 0,
991 AC_VERB_GET_CONFIG_DEFAULT, 0);
992 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
993 continue;
994
995 hdmi_add_pin(codec, nid);
996 break;
997 }
998 }
999
1000 for (i = 0; i < num_tmp_cvts; i++)
1001 hdmi_add_cvt(codec, tmp_cvt[i]);
1002
1003 /*
1004 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
1005 * can be lost and presence sense verb will become inaccurate if the
1006 * HDA link is powered off at hot plug or hw initialization time.
1007 */
1008 #ifdef CONFIG_SND_HDA_POWER_SAVE
1009 if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
1010 AC_PWRST_EPSS))
1011 codec->bus->power_keep_link_on = 1;
1012 #endif
1013
1014 return 0;
1015 }
1016
1017 /*
1018 */
1019 static char *generic_hdmi_pcm_names[MAX_HDMI_CVTS] = {
1020 "HDMI 0",
1021 "HDMI 1",
1022 "HDMI 2",
1023 };
1024
1025 /*
1026 * HDMI callbacks
1027 */
1028
1029 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1030 struct hda_codec *codec,
1031 unsigned int stream_tag,
1032 unsigned int format,
1033 struct snd_pcm_substream *substream)
1034 {
1035 hdmi_set_channel_count(codec, hinfo->nid,
1036 substream->runtime->channels);
1037
1038 hdmi_setup_audio_infoframe(codec, hinfo->nid, substream);
1039
1040 return hdmi_setup_stream(codec, hinfo->nid, stream_tag, format);
1041 }
1042
1043 static struct hda_pcm_stream generic_hdmi_pcm_playback = {
1044 .substreams = 1,
1045 .channels_min = 2,
1046 .ops = {
1047 .open = hdmi_pcm_open,
1048 .prepare = generic_hdmi_playback_pcm_prepare,
1049 },
1050 };
1051
1052 static int generic_hdmi_build_pcms(struct hda_codec *codec)
1053 {
1054 struct hdmi_spec *spec = codec->spec;
1055 struct hda_pcm *info = spec->pcm_rec;
1056 int i;
1057
1058 codec->num_pcms = spec->num_cvts;
1059 codec->pcm_info = info;
1060
1061 for (i = 0; i < codec->num_pcms; i++, info++) {
1062 unsigned int chans;
1063 struct hda_pcm_stream *pstr;
1064
1065 chans = get_wcaps(codec, spec->cvt[i]);
1066 chans = get_wcaps_channels(chans);
1067
1068 info->name = generic_hdmi_pcm_names[i];
1069 info->pcm_type = HDA_PCM_TYPE_HDMI;
1070 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
1071 if (spec->pcm_playback)
1072 *pstr = *spec->pcm_playback;
1073 else
1074 *pstr = generic_hdmi_pcm_playback;
1075 pstr->nid = spec->cvt[i];
1076 if (pstr->channels_max <= 2 && chans && chans <= 16)
1077 pstr->channels_max = chans;
1078 }
1079
1080 return 0;
1081 }
1082
1083 static int generic_hdmi_build_controls(struct hda_codec *codec)
1084 {
1085 struct hdmi_spec *spec = codec->spec;
1086 int err;
1087 int i;
1088
1089 for (i = 0; i < codec->num_pcms; i++) {
1090 err = snd_hda_create_spdif_out_ctls(codec, spec->cvt[i]);
1091 if (err < 0)
1092 return err;
1093 }
1094
1095 return 0;
1096 }
1097
1098 static int generic_hdmi_init(struct hda_codec *codec)
1099 {
1100 struct hdmi_spec *spec = codec->spec;
1101 int i;
1102
1103 for (i = 0; spec->pin[i]; i++) {
1104 hdmi_enable_output(codec, spec->pin[i]);
1105 snd_hda_codec_write(codec, spec->pin[i], 0,
1106 AC_VERB_SET_UNSOLICITED_ENABLE,
1107 AC_USRSP_EN | spec->pin[i]);
1108 }
1109 return 0;
1110 }
1111
1112 static void generic_hdmi_free(struct hda_codec *codec)
1113 {
1114 struct hdmi_spec *spec = codec->spec;
1115 int i;
1116
1117 for (i = 0; i < spec->num_pins; i++)
1118 snd_hda_eld_proc_free(codec, &spec->sink_eld[i]);
1119
1120 kfree(spec);
1121 }
1122
1123 static struct hda_codec_ops generic_hdmi_patch_ops = {
1124 .init = generic_hdmi_init,
1125 .free = generic_hdmi_free,
1126 .build_pcms = generic_hdmi_build_pcms,
1127 .build_controls = generic_hdmi_build_controls,
1128 .unsol_event = hdmi_unsol_event,
1129 };
1130
1131 static int patch_generic_hdmi(struct hda_codec *codec)
1132 {
1133 struct hdmi_spec *spec;
1134 int i;
1135
1136 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1137 if (spec == NULL)
1138 return -ENOMEM;
1139
1140 codec->spec = spec;
1141 if (hdmi_parse_codec(codec) < 0) {
1142 codec->spec = NULL;
1143 kfree(spec);
1144 return -EINVAL;
1145 }
1146 codec->patch_ops = generic_hdmi_patch_ops;
1147
1148 for (i = 0; i < spec->num_pins; i++)
1149 snd_hda_eld_proc_new(codec, &spec->sink_eld[i], i);
1150
1151 init_channel_allocations();
1152
1153 return 0;
1154 }
1155
1156 /*
1157 * Nvidia specific implementations
1158 */
1159
1160 #define Nv_VERB_SET_Channel_Allocation 0xF79
1161 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1162 #define Nv_VERB_SET_Audio_Protection_On 0xF98
1163 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
1164
1165 #define nvhdmi_master_con_nid_7x 0x04
1166 #define nvhdmi_master_pin_nid_7x 0x05
1167
1168 static hda_nid_t nvhdmi_con_nids_7x[4] = {
1169 /*front, rear, clfe, rear_surr */
1170 0x6, 0x8, 0xa, 0xc,
1171 };
1172
1173 static struct hda_verb nvhdmi_basic_init_7x[] = {
1174 /* set audio protect on */
1175 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
1176 /* enable digital output on pin widget */
1177 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1178 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1179 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1180 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1181 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
1182 {} /* terminator */
1183 };
1184
1185 #ifdef LIMITED_RATE_FMT_SUPPORT
1186 /* support only the safe format and rate */
1187 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1188 #define SUPPORTED_MAXBPS 16
1189 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1190 #else
1191 /* support all rates and formats */
1192 #define SUPPORTED_RATES \
1193 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1194 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1195 SNDRV_PCM_RATE_192000)
1196 #define SUPPORTED_MAXBPS 24
1197 #define SUPPORTED_FORMATS \
1198 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1199 #endif
1200
1201 static int nvhdmi_7x_init(struct hda_codec *codec)
1202 {
1203 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
1204 return 0;
1205 }
1206
1207 static unsigned int channels_2_6_8[] = {
1208 2, 6, 8
1209 };
1210
1211 static unsigned int channels_2_8[] = {
1212 2, 8
1213 };
1214
1215 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
1216 .count = ARRAY_SIZE(channels_2_6_8),
1217 .list = channels_2_6_8,
1218 .mask = 0,
1219 };
1220
1221 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
1222 .count = ARRAY_SIZE(channels_2_8),
1223 .list = channels_2_8,
1224 .mask = 0,
1225 };
1226
1227 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
1228 struct hda_codec *codec,
1229 struct snd_pcm_substream *substream)
1230 {
1231 struct hdmi_spec *spec = codec->spec;
1232 struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
1233
1234 switch (codec->preset->id) {
1235 case 0x10de0002:
1236 case 0x10de0003:
1237 case 0x10de0005:
1238 case 0x10de0006:
1239 hw_constraints_channels = &hw_constraints_2_8_channels;
1240 break;
1241 case 0x10de0007:
1242 hw_constraints_channels = &hw_constraints_2_6_8_channels;
1243 break;
1244 default:
1245 break;
1246 }
1247
1248 if (hw_constraints_channels != NULL) {
1249 snd_pcm_hw_constraint_list(substream->runtime, 0,
1250 SNDRV_PCM_HW_PARAM_CHANNELS,
1251 hw_constraints_channels);
1252 } else {
1253 snd_pcm_hw_constraint_step(substream->runtime, 0,
1254 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1255 }
1256
1257 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
1258 }
1259
1260 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
1261 struct hda_codec *codec,
1262 struct snd_pcm_substream *substream)
1263 {
1264 struct hdmi_spec *spec = codec->spec;
1265 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1266 }
1267
1268 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1269 struct hda_codec *codec,
1270 unsigned int stream_tag,
1271 unsigned int format,
1272 struct snd_pcm_substream *substream)
1273 {
1274 struct hdmi_spec *spec = codec->spec;
1275 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
1276 stream_tag, format, substream);
1277 }
1278
1279 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
1280 struct hda_codec *codec,
1281 struct snd_pcm_substream *substream)
1282 {
1283 struct hdmi_spec *spec = codec->spec;
1284 int i;
1285
1286 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
1287 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
1288 for (i = 0; i < 4; i++) {
1289 /* set the stream id */
1290 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1291 AC_VERB_SET_CHANNEL_STREAMID, 0);
1292 /* set the stream format */
1293 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
1294 AC_VERB_SET_STREAM_FORMAT, 0);
1295 }
1296
1297 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
1298 }
1299
1300 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
1301 struct hda_codec *codec,
1302 unsigned int stream_tag,
1303 unsigned int format,
1304 struct snd_pcm_substream *substream)
1305 {
1306 int chs;
1307 unsigned int dataDCC1, dataDCC2, chan, chanmask, channel_id;
1308 int i;
1309
1310 mutex_lock(&codec->spdif_mutex);
1311
1312 chs = substream->runtime->channels;
1313 chan = chs ? (chs - 1) : 1;
1314
1315 switch (chs) {
1316 default:
1317 case 0:
1318 case 2:
1319 chanmask = 0x00;
1320 break;
1321 case 4:
1322 chanmask = 0x08;
1323 break;
1324 case 6:
1325 chanmask = 0x0b;
1326 break;
1327 case 8:
1328 chanmask = 0x13;
1329 break;
1330 }
1331 dataDCC1 = AC_DIG1_ENABLE | AC_DIG1_COPYRIGHT;
1332 dataDCC2 = 0x2;
1333
1334 /* set the Audio InforFrame Channel Allocation */
1335 snd_hda_codec_write(codec, 0x1, 0,
1336 Nv_VERB_SET_Channel_Allocation, chanmask);
1337
1338 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1339 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE))
1340 snd_hda_codec_write(codec,
1341 nvhdmi_master_con_nid_7x,
1342 0,
1343 AC_VERB_SET_DIGI_CONVERT_1,
1344 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
1345
1346 /* set the stream id */
1347 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1348 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
1349
1350 /* set the stream format */
1351 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
1352 AC_VERB_SET_STREAM_FORMAT, format);
1353
1354 /* turn on again (if needed) */
1355 /* enable and set the channel status audio/data flag */
1356 if (codec->spdif_status_reset && (codec->spdif_ctls & AC_DIG1_ENABLE)) {
1357 snd_hda_codec_write(codec,
1358 nvhdmi_master_con_nid_7x,
1359 0,
1360 AC_VERB_SET_DIGI_CONVERT_1,
1361 codec->spdif_ctls & 0xff);
1362 snd_hda_codec_write(codec,
1363 nvhdmi_master_con_nid_7x,
1364 0,
1365 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1366 }
1367
1368 for (i = 0; i < 4; i++) {
1369 if (chs == 2)
1370 channel_id = 0;
1371 else
1372 channel_id = i * 2;
1373
1374 /* turn off SPDIF once;
1375 *otherwise the IEC958 bits won't be updated
1376 */
1377 if (codec->spdif_status_reset &&
1378 (codec->spdif_ctls & AC_DIG1_ENABLE))
1379 snd_hda_codec_write(codec,
1380 nvhdmi_con_nids_7x[i],
1381 0,
1382 AC_VERB_SET_DIGI_CONVERT_1,
1383 codec->spdif_ctls & ~AC_DIG1_ENABLE & 0xff);
1384 /* set the stream id */
1385 snd_hda_codec_write(codec,
1386 nvhdmi_con_nids_7x[i],
1387 0,
1388 AC_VERB_SET_CHANNEL_STREAMID,
1389 (stream_tag << 4) | channel_id);
1390 /* set the stream format */
1391 snd_hda_codec_write(codec,
1392 nvhdmi_con_nids_7x[i],
1393 0,
1394 AC_VERB_SET_STREAM_FORMAT,
1395 format);
1396 /* turn on again (if needed) */
1397 /* enable and set the channel status audio/data flag */
1398 if (codec->spdif_status_reset &&
1399 (codec->spdif_ctls & AC_DIG1_ENABLE)) {
1400 snd_hda_codec_write(codec,
1401 nvhdmi_con_nids_7x[i],
1402 0,
1403 AC_VERB_SET_DIGI_CONVERT_1,
1404 codec->spdif_ctls & 0xff);
1405 snd_hda_codec_write(codec,
1406 nvhdmi_con_nids_7x[i],
1407 0,
1408 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
1409 }
1410 }
1411
1412 /* set the Audio Info Frame Checksum */
1413 snd_hda_codec_write(codec, 0x1, 0,
1414 Nv_VERB_SET_Info_Frame_Checksum,
1415 (0x71 - chan - chanmask));
1416
1417 mutex_unlock(&codec->spdif_mutex);
1418 return 0;
1419 }
1420
1421 static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
1422 .substreams = 1,
1423 .channels_min = 2,
1424 .channels_max = 8,
1425 .nid = nvhdmi_master_con_nid_7x,
1426 .rates = SUPPORTED_RATES,
1427 .maxbps = SUPPORTED_MAXBPS,
1428 .formats = SUPPORTED_FORMATS,
1429 .ops = {
1430 .open = simple_playback_pcm_open,
1431 .close = nvhdmi_8ch_7x_pcm_close,
1432 .prepare = nvhdmi_8ch_7x_pcm_prepare
1433 },
1434 };
1435
1436 static struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
1437 .substreams = 1,
1438 .channels_min = 2,
1439 .channels_max = 2,
1440 .nid = nvhdmi_master_con_nid_7x,
1441 .rates = SUPPORTED_RATES,
1442 .maxbps = SUPPORTED_MAXBPS,
1443 .formats = SUPPORTED_FORMATS,
1444 .ops = {
1445 .open = simple_playback_pcm_open,
1446 .close = simple_playback_pcm_close,
1447 .prepare = simple_playback_pcm_prepare
1448 },
1449 };
1450
1451 static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
1452 .build_controls = generic_hdmi_build_controls,
1453 .build_pcms = generic_hdmi_build_pcms,
1454 .init = nvhdmi_7x_init,
1455 .free = generic_hdmi_free,
1456 };
1457
1458 static struct hda_codec_ops nvhdmi_patch_ops_2ch = {
1459 .build_controls = generic_hdmi_build_controls,
1460 .build_pcms = generic_hdmi_build_pcms,
1461 .init = nvhdmi_7x_init,
1462 .free = generic_hdmi_free,
1463 };
1464
1465 static int patch_nvhdmi_8ch_89(struct hda_codec *codec)
1466 {
1467 struct hdmi_spec *spec;
1468 int err = patch_generic_hdmi(codec);
1469
1470 if (err < 0)
1471 return err;
1472 spec = codec->spec;
1473 spec->old_pin_detect = 1;
1474 return 0;
1475 }
1476
1477 static int patch_nvhdmi_2ch(struct hda_codec *codec)
1478 {
1479 struct hdmi_spec *spec;
1480
1481 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1482 if (spec == NULL)
1483 return -ENOMEM;
1484
1485 codec->spec = spec;
1486
1487 spec->multiout.num_dacs = 0; /* no analog */
1488 spec->multiout.max_channels = 2;
1489 spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
1490 spec->old_pin_detect = 1;
1491 spec->num_cvts = 1;
1492 spec->cvt[0] = nvhdmi_master_con_nid_7x;
1493 spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
1494
1495 codec->patch_ops = nvhdmi_patch_ops_2ch;
1496
1497 return 0;
1498 }
1499
1500 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
1501 {
1502 struct hdmi_spec *spec;
1503 int err = patch_nvhdmi_2ch(codec);
1504
1505 if (err < 0)
1506 return err;
1507 spec = codec->spec;
1508 spec->multiout.max_channels = 8;
1509 spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
1510 codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
1511 return 0;
1512 }
1513
1514 /*
1515 * ATI-specific implementations
1516 *
1517 * FIXME: we may omit the whole this and use the generic code once after
1518 * it's confirmed to work.
1519 */
1520
1521 #define ATIHDMI_CVT_NID 0x02 /* audio converter */
1522 #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1523
1524 static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1525 struct hda_codec *codec,
1526 unsigned int stream_tag,
1527 unsigned int format,
1528 struct snd_pcm_substream *substream)
1529 {
1530 struct hdmi_spec *spec = codec->spec;
1531 int chans = substream->runtime->channels;
1532 int i, err;
1533
1534 err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
1535 substream);
1536 if (err < 0)
1537 return err;
1538 snd_hda_codec_write(codec, spec->cvt[0], 0, AC_VERB_SET_CVT_CHAN_COUNT,
1539 chans - 1);
1540 /* FIXME: XXX */
1541 for (i = 0; i < chans; i++) {
1542 snd_hda_codec_write(codec, spec->cvt[0], 0,
1543 AC_VERB_SET_HDMI_CHAN_SLOT,
1544 (i << 4) | i);
1545 }
1546 return 0;
1547 }
1548
1549 static struct hda_pcm_stream atihdmi_pcm_digital_playback = {
1550 .substreams = 1,
1551 .channels_min = 2,
1552 .channels_max = 2,
1553 .nid = ATIHDMI_CVT_NID,
1554 .ops = {
1555 .open = simple_playback_pcm_open,
1556 .close = simple_playback_pcm_close,
1557 .prepare = atihdmi_playback_pcm_prepare
1558 },
1559 };
1560
1561 static struct hda_verb atihdmi_basic_init[] = {
1562 /* enable digital output on pin widget */
1563 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
1564 {} /* terminator */
1565 };
1566
1567 static int atihdmi_init(struct hda_codec *codec)
1568 {
1569 struct hdmi_spec *spec = codec->spec;
1570
1571 snd_hda_sequence_write(codec, atihdmi_basic_init);
1572 /* SI codec requires to unmute the pin */
1573 if (get_wcaps(codec, spec->pin[0]) & AC_WCAP_OUT_AMP)
1574 snd_hda_codec_write(codec, spec->pin[0], 0,
1575 AC_VERB_SET_AMP_GAIN_MUTE,
1576 AMP_OUT_UNMUTE);
1577 return 0;
1578 }
1579
1580 static struct hda_codec_ops atihdmi_patch_ops = {
1581 .build_controls = generic_hdmi_build_controls,
1582 .build_pcms = generic_hdmi_build_pcms,
1583 .init = atihdmi_init,
1584 .free = generic_hdmi_free,
1585 };
1586
1587
1588 static int patch_atihdmi(struct hda_codec *codec)
1589 {
1590 struct hdmi_spec *spec;
1591
1592 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
1593 if (spec == NULL)
1594 return -ENOMEM;
1595
1596 codec->spec = spec;
1597
1598 spec->multiout.num_dacs = 0; /* no analog */
1599 spec->multiout.max_channels = 2;
1600 spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
1601 spec->num_cvts = 1;
1602 spec->cvt[0] = ATIHDMI_CVT_NID;
1603 spec->pin[0] = ATIHDMI_PIN_NID;
1604 spec->pcm_playback = &atihdmi_pcm_digital_playback;
1605
1606 codec->patch_ops = atihdmi_patch_ops;
1607
1608 return 0;
1609 }
1610
1611
1612 /*
1613 * patch entries
1614 */
1615 static struct hda_codec_preset snd_hda_preset_hdmi[] = {
1616 { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
1617 { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
1618 { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
1619 { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
1620 { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
1621 { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
1622 { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
1623 { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1624 { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1625 { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1626 { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
1627 { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
1628 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1629 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1630 { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_nvhdmi_8ch_89 },
1631 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1632 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1633 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1634 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1635 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1636 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1637 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1638 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1639 /* 17 is known to be absent */
1640 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1641 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1642 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1643 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1644 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1645 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1646 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1647 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1648 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1649 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_nvhdmi_8ch_89 },
1650 { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
1651 { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
1652 { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1653 { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
1654 { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
1655 { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
1656 { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
1657 { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
1658 { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
1659 {} /* terminator */
1660 };
1661
1662 MODULE_ALIAS("snd-hda-codec-id:1002793c");
1663 MODULE_ALIAS("snd-hda-codec-id:10027919");
1664 MODULE_ALIAS("snd-hda-codec-id:1002791a");
1665 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1666 MODULE_ALIAS("snd-hda-codec-id:10951390");
1667 MODULE_ALIAS("snd-hda-codec-id:10951392");
1668 MODULE_ALIAS("snd-hda-codec-id:10de0002");
1669 MODULE_ALIAS("snd-hda-codec-id:10de0003");
1670 MODULE_ALIAS("snd-hda-codec-id:10de0005");
1671 MODULE_ALIAS("snd-hda-codec-id:10de0006");
1672 MODULE_ALIAS("snd-hda-codec-id:10de0007");
1673 MODULE_ALIAS("snd-hda-codec-id:10de000a");
1674 MODULE_ALIAS("snd-hda-codec-id:10de000b");
1675 MODULE_ALIAS("snd-hda-codec-id:10de000c");
1676 MODULE_ALIAS("snd-hda-codec-id:10de000d");
1677 MODULE_ALIAS("snd-hda-codec-id:10de0010");
1678 MODULE_ALIAS("snd-hda-codec-id:10de0011");
1679 MODULE_ALIAS("snd-hda-codec-id:10de0012");
1680 MODULE_ALIAS("snd-hda-codec-id:10de0013");
1681 MODULE_ALIAS("snd-hda-codec-id:10de0014");
1682 MODULE_ALIAS("snd-hda-codec-id:10de0015");
1683 MODULE_ALIAS("snd-hda-codec-id:10de0016");
1684 MODULE_ALIAS("snd-hda-codec-id:10de0018");
1685 MODULE_ALIAS("snd-hda-codec-id:10de0019");
1686 MODULE_ALIAS("snd-hda-codec-id:10de001a");
1687 MODULE_ALIAS("snd-hda-codec-id:10de001b");
1688 MODULE_ALIAS("snd-hda-codec-id:10de001c");
1689 MODULE_ALIAS("snd-hda-codec-id:10de0040");
1690 MODULE_ALIAS("snd-hda-codec-id:10de0041");
1691 MODULE_ALIAS("snd-hda-codec-id:10de0042");
1692 MODULE_ALIAS("snd-hda-codec-id:10de0043");
1693 MODULE_ALIAS("snd-hda-codec-id:10de0044");
1694 MODULE_ALIAS("snd-hda-codec-id:10de0067");
1695 MODULE_ALIAS("snd-hda-codec-id:10de8001");
1696 MODULE_ALIAS("snd-hda-codec-id:17e80047");
1697 MODULE_ALIAS("snd-hda-codec-id:80860054");
1698 MODULE_ALIAS("snd-hda-codec-id:80862801");
1699 MODULE_ALIAS("snd-hda-codec-id:80862802");
1700 MODULE_ALIAS("snd-hda-codec-id:80862803");
1701 MODULE_ALIAS("snd-hda-codec-id:80862804");
1702 MODULE_ALIAS("snd-hda-codec-id:80862805");
1703 MODULE_ALIAS("snd-hda-codec-id:808629fb");
1704
1705 MODULE_LICENSE("GPL");
1706 MODULE_DESCRIPTION("HDMI HD-audio codec");
1707 MODULE_ALIAS("snd-hda-codec-intelhdmi");
1708 MODULE_ALIAS("snd-hda-codec-nvhdmi");
1709 MODULE_ALIAS("snd-hda-codec-atihdmi");
1710
1711 static struct hda_codec_preset_list intel_list = {
1712 .preset = snd_hda_preset_hdmi,
1713 .owner = THIS_MODULE,
1714 };
1715
1716 static int __init patch_hdmi_init(void)
1717 {
1718 return snd_hda_add_codec_preset(&intel_list);
1719 }
1720
1721 static void __exit patch_hdmi_exit(void)
1722 {
1723 snd_hda_delete_codec_preset(&intel_list);
1724 }
1725
1726 module_init(patch_hdmi_init)
1727 module_exit(patch_hdmi_exit)
AMDTP streaming driver for the Linux FireWire stack (Juju)