3 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6 * Copyright (c) 2006 ATI Technologies Inc.
7 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
8 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
11 * Wu Fengguang <wfg@linux.intel.com>
14 * Wu Fengguang <wfg@linux.intel.com>
16 * This program is free software; you can redistribute it and/or modify it
17 * under the terms of the GNU General Public License as published by the Free
18 * Software Foundation; either version 2 of the License, or (at your option)
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software Foundation,
28 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/slab.h>
34 #include <sound/core.h>
35 #include "hda_codec.h"
36 #include "hda_local.h"
39 * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
40 * could support two independent pipes, each of them can be connected to one or
41 * more ports (DVI, HDMI or DisplayPort).
43 * The HDA correspondence of pipes/ports are converter/pin nodes.
45 #define MAX_HDMI_CVTS 3
46 #define MAX_HDMI_PINS 3
51 hda_nid_t cvt
[MAX_HDMI_CVTS
+1]; /* audio sources */
52 hda_nid_t pin
[MAX_HDMI_PINS
+1]; /* audio sinks */
55 * source connection for each pin
57 hda_nid_t pin_cvt
[MAX_HDMI_PINS
+1];
60 * HDMI sink attached to each pin
62 struct hdmi_eld sink_eld
[MAX_HDMI_PINS
];
65 * export one pcm per pipe
67 struct hda_pcm pcm_rec
[MAX_HDMI_CVTS
];
68 struct hda_pcm_stream codec_pcm_pars
[MAX_HDMI_CVTS
];
73 struct hda_multi_out multiout
;
74 struct hda_pcm_stream
*pcm_playback
;
77 /* PD bit indicates only the update, not the current state */
78 unsigned int old_pin_detect
:1;
82 struct hdmi_audio_infoframe
{
87 u8 checksum
; /* PB0 */
88 u8 CC02_CT47
; /* CC in bits 0:2, CT in 4:7 */
92 u8 LFEPBL01_LSV36_DM_INH7
;
93 u8 reserved
[5]; /* PB6 - PB10 */
97 * CEA speaker placement:
100 * FLW FL FLC FC FRC FR FRW
107 * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
108 * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
110 enum cea_speaker_placement
{
111 FL
= (1 << 0), /* Front Left */
112 FC
= (1 << 1), /* Front Center */
113 FR
= (1 << 2), /* Front Right */
114 FLC
= (1 << 3), /* Front Left Center */
115 FRC
= (1 << 4), /* Front Right Center */
116 RL
= (1 << 5), /* Rear Left */
117 RC
= (1 << 6), /* Rear Center */
118 RR
= (1 << 7), /* Rear Right */
119 RLC
= (1 << 8), /* Rear Left Center */
120 RRC
= (1 << 9), /* Rear Right Center */
121 LFE
= (1 << 10), /* Low Frequency Effect */
122 FLW
= (1 << 11), /* Front Left Wide */
123 FRW
= (1 << 12), /* Front Right Wide */
124 FLH
= (1 << 13), /* Front Left High */
125 FCH
= (1 << 14), /* Front Center High */
126 FRH
= (1 << 15), /* Front Right High */
127 TC
= (1 << 16), /* Top Center */
131 * ELD SA bits in the CEA Speaker Allocation data block
133 static int eld_speaker_allocation_bits
[] = {
141 /* the following are not defined in ELD yet */
148 struct cea_channel_speaker_allocation
{
152 /* derived values, just for convenience */
160 * surround40 surround41 surround50 surround51 surround71
161 * ch0 front left = = = =
162 * ch1 front right = = = =
163 * ch2 rear left = = = =
164 * ch3 rear right = = = =
165 * ch4 LFE center center center
170 * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
172 static int hdmi_channel_mapping
[0x32][8] = {
174 [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
176 [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
178 [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
180 [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
182 [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
184 [0x09] = { 0x00, 0x11, 0x24, 0x34, 0x43, 0xf2, 0xf6, 0xf7 },
186 [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
188 [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
190 [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
194 * This is an ordered list!
196 * The preceding ones have better chances to be selected by
197 * hdmi_setup_channel_allocation().
199 static struct cea_channel_speaker_allocation channel_allocations
[] = {
200 /* channel: 7 6 5 4 3 2 1 0 */
201 { .ca_index
= 0x00, .speakers
= { 0, 0, 0, 0, 0, 0, FR
, FL
} },
203 { .ca_index
= 0x01, .speakers
= { 0, 0, 0, 0, 0, LFE
, FR
, FL
} },
205 { .ca_index
= 0x02, .speakers
= { 0, 0, 0, 0, FC
, 0, FR
, FL
} },
207 { .ca_index
= 0x08, .speakers
= { 0, 0, RR
, RL
, 0, 0, FR
, FL
} },
209 { .ca_index
= 0x09, .speakers
= { 0, 0, RR
, RL
, 0, LFE
, FR
, FL
} },
211 { .ca_index
= 0x0a, .speakers
= { 0, 0, RR
, RL
, FC
, 0, FR
, FL
} },
213 { .ca_index
= 0x0b, .speakers
= { 0, 0, RR
, RL
, FC
, LFE
, FR
, FL
} },
215 { .ca_index
= 0x0f, .speakers
= { 0, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
217 { .ca_index
= 0x13, .speakers
= { RRC
, RLC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
219 { .ca_index
= 0x03, .speakers
= { 0, 0, 0, 0, FC
, LFE
, FR
, FL
} },
220 { .ca_index
= 0x04, .speakers
= { 0, 0, 0, RC
, 0, 0, FR
, FL
} },
221 { .ca_index
= 0x05, .speakers
= { 0, 0, 0, RC
, 0, LFE
, FR
, FL
} },
222 { .ca_index
= 0x06, .speakers
= { 0, 0, 0, RC
, FC
, 0, FR
, FL
} },
223 { .ca_index
= 0x07, .speakers
= { 0, 0, 0, RC
, FC
, LFE
, FR
, FL
} },
224 { .ca_index
= 0x0c, .speakers
= { 0, RC
, RR
, RL
, 0, 0, FR
, FL
} },
225 { .ca_index
= 0x0d, .speakers
= { 0, RC
, RR
, RL
, 0, LFE
, FR
, FL
} },
226 { .ca_index
= 0x0e, .speakers
= { 0, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
227 { .ca_index
= 0x10, .speakers
= { RRC
, RLC
, RR
, RL
, 0, 0, FR
, FL
} },
228 { .ca_index
= 0x11, .speakers
= { RRC
, RLC
, RR
, RL
, 0, LFE
, FR
, FL
} },
229 { .ca_index
= 0x12, .speakers
= { RRC
, RLC
, RR
, RL
, FC
, 0, FR
, FL
} },
230 { .ca_index
= 0x14, .speakers
= { FRC
, FLC
, 0, 0, 0, 0, FR
, FL
} },
231 { .ca_index
= 0x15, .speakers
= { FRC
, FLC
, 0, 0, 0, LFE
, FR
, FL
} },
232 { .ca_index
= 0x16, .speakers
= { FRC
, FLC
, 0, 0, FC
, 0, FR
, FL
} },
233 { .ca_index
= 0x17, .speakers
= { FRC
, FLC
, 0, 0, FC
, LFE
, FR
, FL
} },
234 { .ca_index
= 0x18, .speakers
= { FRC
, FLC
, 0, RC
, 0, 0, FR
, FL
} },
235 { .ca_index
= 0x19, .speakers
= { FRC
, FLC
, 0, RC
, 0, LFE
, FR
, FL
} },
236 { .ca_index
= 0x1a, .speakers
= { FRC
, FLC
, 0, RC
, FC
, 0, FR
, FL
} },
237 { .ca_index
= 0x1b, .speakers
= { FRC
, FLC
, 0, RC
, FC
, LFE
, FR
, FL
} },
238 { .ca_index
= 0x1c, .speakers
= { FRC
, FLC
, RR
, RL
, 0, 0, FR
, FL
} },
239 { .ca_index
= 0x1d, .speakers
= { FRC
, FLC
, RR
, RL
, 0, LFE
, FR
, FL
} },
240 { .ca_index
= 0x1e, .speakers
= { FRC
, FLC
, RR
, RL
, FC
, 0, FR
, FL
} },
241 { .ca_index
= 0x1f, .speakers
= { FRC
, FLC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
242 { .ca_index
= 0x20, .speakers
= { 0, FCH
, RR
, RL
, FC
, 0, FR
, FL
} },
243 { .ca_index
= 0x21, .speakers
= { 0, FCH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
244 { .ca_index
= 0x22, .speakers
= { TC
, 0, RR
, RL
, FC
, 0, FR
, FL
} },
245 { .ca_index
= 0x23, .speakers
= { TC
, 0, RR
, RL
, FC
, LFE
, FR
, FL
} },
246 { .ca_index
= 0x24, .speakers
= { FRH
, FLH
, RR
, RL
, 0, 0, FR
, FL
} },
247 { .ca_index
= 0x25, .speakers
= { FRH
, FLH
, RR
, RL
, 0, LFE
, FR
, FL
} },
248 { .ca_index
= 0x26, .speakers
= { FRW
, FLW
, RR
, RL
, 0, 0, FR
, FL
} },
249 { .ca_index
= 0x27, .speakers
= { FRW
, FLW
, RR
, RL
, 0, LFE
, FR
, FL
} },
250 { .ca_index
= 0x28, .speakers
= { TC
, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
251 { .ca_index
= 0x29, .speakers
= { TC
, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
252 { .ca_index
= 0x2a, .speakers
= { FCH
, RC
, RR
, RL
, FC
, 0, FR
, FL
} },
253 { .ca_index
= 0x2b, .speakers
= { FCH
, RC
, RR
, RL
, FC
, LFE
, FR
, FL
} },
254 { .ca_index
= 0x2c, .speakers
= { TC
, FCH
, RR
, RL
, FC
, 0, FR
, FL
} },
255 { .ca_index
= 0x2d, .speakers
= { TC
, FCH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
256 { .ca_index
= 0x2e, .speakers
= { FRH
, FLH
, RR
, RL
, FC
, 0, FR
, FL
} },
257 { .ca_index
= 0x2f, .speakers
= { FRH
, FLH
, RR
, RL
, FC
, LFE
, FR
, FL
} },
258 { .ca_index
= 0x30, .speakers
= { FRW
, FLW
, RR
, RL
, FC
, 0, FR
, FL
} },
259 { .ca_index
= 0x31, .speakers
= { FRW
, FLW
, RR
, RL
, FC
, LFE
, FR
, FL
} },
267 static int hda_node_index(hda_nid_t
*nids
, hda_nid_t nid
)
271 for (i
= 0; nids
[i
]; i
++)
275 snd_printk(KERN_WARNING
"HDMI: nid %d not registered\n", nid
);
279 static void hdmi_get_show_eld(struct hda_codec
*codec
, hda_nid_t pin_nid
,
280 struct hdmi_eld
*eld
)
282 if (!snd_hdmi_get_eld(eld
, codec
, pin_nid
))
283 snd_hdmi_show_eld(eld
);
287 static void hdmi_get_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
288 int *packet_index
, int *byte_index
)
292 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
293 AC_VERB_GET_HDMI_DIP_INDEX
, 0);
295 *packet_index
= val
>> 5;
296 *byte_index
= val
& 0x1f;
300 static void hdmi_set_dip_index(struct hda_codec
*codec
, hda_nid_t pin_nid
,
301 int packet_index
, int byte_index
)
305 val
= (packet_index
<< 5) | (byte_index
& 0x1f);
307 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_INDEX
, val
);
310 static void hdmi_write_dip_byte(struct hda_codec
*codec
, hda_nid_t pin_nid
,
313 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_DATA
, val
);
316 static void hdmi_enable_output(struct hda_codec
*codec
, hda_nid_t pin_nid
)
319 if (get_wcaps(codec
, pin_nid
) & AC_WCAP_OUT_AMP
)
320 snd_hda_codec_write(codec
, pin_nid
, 0,
321 AC_VERB_SET_AMP_GAIN_MUTE
, AMP_OUT_UNMUTE
);
323 snd_hda_codec_write(codec
, pin_nid
, 0,
324 AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
);
327 static int hdmi_get_channel_count(struct hda_codec
*codec
, hda_nid_t nid
)
329 return 1 + snd_hda_codec_read(codec
, nid
, 0,
330 AC_VERB_GET_CVT_CHAN_COUNT
, 0);
333 static void hdmi_set_channel_count(struct hda_codec
*codec
,
334 hda_nid_t nid
, int chs
)
336 if (chs
!= hdmi_get_channel_count(codec
, nid
))
337 snd_hda_codec_write(codec
, nid
, 0,
338 AC_VERB_SET_CVT_CHAN_COUNT
, chs
- 1);
343 * Channel mapping routines
347 * Compute derived values in channel_allocations[].
349 static void init_channel_allocations(void)
352 struct cea_channel_speaker_allocation
*p
;
354 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
355 p
= channel_allocations
+ i
;
358 for (j
= 0; j
< ARRAY_SIZE(p
->speakers
); j
++)
359 if (p
->speakers
[j
]) {
361 p
->spk_mask
|= p
->speakers
[j
];
367 * The transformation takes two steps:
369 * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
370 * spk_mask => (channel_allocations[]) => ai->CA
372 * TODO: it could select the wrong CA from multiple candidates.
374 static int hdmi_setup_channel_allocation(struct hda_codec
*codec
, hda_nid_t nid
,
375 struct hdmi_audio_infoframe
*ai
)
377 struct hdmi_spec
*spec
= codec
->spec
;
378 struct hdmi_eld
*eld
;
381 int channels
= 1 + (ai
->CC02_CT47
& 0x7);
382 char buf
[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE
];
385 * CA defaults to 0 for basic stereo audio
390 i
= hda_node_index(spec
->pin_cvt
, nid
);
393 eld
= &spec
->sink_eld
[i
];
396 * HDMI sink's ELD info cannot always be retrieved for now, e.g.
397 * in console or for audio devices. Assume the highest speakers
398 * configuration, to _not_ prohibit multi-channel audio playback.
401 eld
->spk_alloc
= 0xffff;
404 * expand ELD's speaker allocation mask
406 * ELD tells the speaker mask in a compact(paired) form,
407 * expand ELD's notions to match the ones used by Audio InfoFrame.
409 for (i
= 0; i
< ARRAY_SIZE(eld_speaker_allocation_bits
); i
++) {
410 if (eld
->spk_alloc
& (1 << i
))
411 spk_mask
|= eld_speaker_allocation_bits
[i
];
414 /* search for the first working match in the CA table */
415 for (i
= 0; i
< ARRAY_SIZE(channel_allocations
); i
++) {
416 if (channels
== channel_allocations
[i
].channels
&&
417 (spk_mask
& channel_allocations
[i
].spk_mask
) ==
418 channel_allocations
[i
].spk_mask
) {
419 ai
->CA
= channel_allocations
[i
].ca_index
;
424 snd_print_channel_allocation(eld
->spk_alloc
, buf
, sizeof(buf
));
425 snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
426 ai
->CA
, channels
, buf
);
431 static void hdmi_debug_channel_mapping(struct hda_codec
*codec
,
434 #ifdef CONFIG_SND_DEBUG_VERBOSE
438 for (i
= 0; i
< 8; i
++) {
439 slot
= snd_hda_codec_read(codec
, pin_nid
, 0,
440 AC_VERB_GET_HDMI_CHAN_SLOT
, i
);
441 printk(KERN_DEBUG
"HDMI: ASP channel %d => slot %d\n",
442 slot
>> 4, slot
& 0xf);
448 static void hdmi_setup_channel_mapping(struct hda_codec
*codec
,
450 struct hdmi_audio_infoframe
*ai
)
456 if (hdmi_channel_mapping
[ca
][1] == 0) {
457 for (i
= 0; i
< channel_allocations
[ca
].channels
; i
++)
458 hdmi_channel_mapping
[ca
][i
] = i
| (i
<< 4);
460 hdmi_channel_mapping
[ca
][i
] = 0xf | (i
<< 4);
463 for (i
= 0; i
< 8; i
++) {
464 err
= snd_hda_codec_write(codec
, pin_nid
, 0,
465 AC_VERB_SET_HDMI_CHAN_SLOT
,
466 hdmi_channel_mapping
[ca
][i
]);
468 snd_printdd(KERN_NOTICE
469 "HDMI: channel mapping failed\n");
474 hdmi_debug_channel_mapping(codec
, pin_nid
);
479 * Audio InfoFrame routines
483 * Enable Audio InfoFrame Transmission
485 static void hdmi_start_infoframe_trans(struct hda_codec
*codec
,
488 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
489 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
494 * Disable Audio InfoFrame Transmission
496 static void hdmi_stop_infoframe_trans(struct hda_codec
*codec
,
499 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
500 snd_hda_codec_write(codec
, pin_nid
, 0, AC_VERB_SET_HDMI_DIP_XMIT
,
504 static void hdmi_debug_dip_size(struct hda_codec
*codec
, hda_nid_t pin_nid
)
506 #ifdef CONFIG_SND_DEBUG_VERBOSE
510 size
= snd_hdmi_get_eld_size(codec
, pin_nid
);
511 printk(KERN_DEBUG
"HDMI: ELD buf size is %d\n", size
);
513 for (i
= 0; i
< 8; i
++) {
514 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
515 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
516 printk(KERN_DEBUG
"HDMI: DIP GP[%d] buf size is %d\n", i
, size
);
521 static void hdmi_clear_dip_buffers(struct hda_codec
*codec
, hda_nid_t pin_nid
)
527 for (i
= 0; i
< 8; i
++) {
528 size
= snd_hda_codec_read(codec
, pin_nid
, 0,
529 AC_VERB_GET_HDMI_DIP_SIZE
, i
);
533 hdmi_set_dip_index(codec
, pin_nid
, i
, 0x0);
534 for (j
= 1; j
< 1000; j
++) {
535 hdmi_write_dip_byte(codec
, pin_nid
, 0x0);
536 hdmi_get_dip_index(codec
, pin_nid
, &pi
, &bi
);
538 snd_printd(KERN_INFO
"dip index %d: %d != %d\n",
540 if (bi
== 0) /* byte index wrapped around */
544 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
550 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe
*ai
)
552 u8
*bytes
= (u8
*)ai
;
558 for (i
= 0; i
< sizeof(*ai
); i
++)
564 static void hdmi_fill_audio_infoframe(struct hda_codec
*codec
,
566 struct hdmi_audio_infoframe
*ai
)
568 u8
*bytes
= (u8
*)ai
;
571 hdmi_debug_dip_size(codec
, pin_nid
);
572 hdmi_clear_dip_buffers(codec
, pin_nid
); /* be paranoid */
574 hdmi_checksum_audio_infoframe(ai
);
576 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
577 for (i
= 0; i
< sizeof(*ai
); i
++)
578 hdmi_write_dip_byte(codec
, pin_nid
, bytes
[i
]);
581 static bool hdmi_infoframe_uptodate(struct hda_codec
*codec
, hda_nid_t pin_nid
,
582 struct hdmi_audio_infoframe
*ai
)
584 u8
*bytes
= (u8
*)ai
;
588 if (snd_hda_codec_read(codec
, pin_nid
, 0, AC_VERB_GET_HDMI_DIP_XMIT
, 0)
592 hdmi_set_dip_index(codec
, pin_nid
, 0x0, 0x0);
593 for (i
= 0; i
< sizeof(*ai
); i
++) {
594 val
= snd_hda_codec_read(codec
, pin_nid
, 0,
595 AC_VERB_GET_HDMI_DIP_DATA
, 0);
603 static void hdmi_setup_audio_infoframe(struct hda_codec
*codec
, hda_nid_t nid
,
604 struct snd_pcm_substream
*substream
)
606 struct hdmi_spec
*spec
= codec
->spec
;
609 struct hdmi_audio_infoframe ai
= {
613 .CC02_CT47
= substream
->runtime
->channels
- 1,
616 hdmi_setup_channel_allocation(codec
, nid
, &ai
);
618 for (i
= 0; i
< spec
->num_pins
; i
++) {
619 if (spec
->pin_cvt
[i
] != nid
)
621 if (!spec
->sink_eld
[i
].monitor_present
)
624 pin_nid
= spec
->pin
[i
];
625 if (!hdmi_infoframe_uptodate(codec
, pin_nid
, &ai
)) {
626 snd_printdd("hdmi_setup_audio_infoframe: "
627 "cvt=%d pin=%d channels=%d\n",
629 substream
->runtime
->channels
);
630 hdmi_setup_channel_mapping(codec
, pin_nid
, &ai
);
631 hdmi_stop_infoframe_trans(codec
, pin_nid
);
632 hdmi_fill_audio_infoframe(codec
, pin_nid
, &ai
);
633 hdmi_start_infoframe_trans(codec
, pin_nid
);
643 static void hdmi_present_sense(struct hda_codec
*codec
, hda_nid_t pin_nid
,
644 struct hdmi_eld
*eld
);
646 static void hdmi_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
648 struct hdmi_spec
*spec
= codec
->spec
;
649 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
650 int pind
= !!(res
& AC_UNSOL_RES_PD
);
651 int eldv
= !!(res
& AC_UNSOL_RES_ELDV
);
655 "HDMI hot plug event: Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
658 index
= hda_node_index(spec
->pin
, tag
);
662 if (spec
->old_pin_detect
) {
664 hdmi_present_sense(codec
, tag
, &spec
->sink_eld
[index
]);
665 pind
= spec
->sink_eld
[index
].monitor_present
;
668 spec
->sink_eld
[index
].monitor_present
= pind
;
669 spec
->sink_eld
[index
].eld_valid
= eldv
;
672 hdmi_get_show_eld(codec
, spec
->pin
[index
],
673 &spec
->sink_eld
[index
]);
674 /* TODO: do real things about ELD */
678 static void hdmi_non_intrinsic_event(struct hda_codec
*codec
, unsigned int res
)
680 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
681 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
682 int cp_state
= !!(res
& AC_UNSOL_RES_CP_STATE
);
683 int cp_ready
= !!(res
& AC_UNSOL_RES_CP_READY
);
686 "HDMI CP event: PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
700 static void hdmi_unsol_event(struct hda_codec
*codec
, unsigned int res
)
702 struct hdmi_spec
*spec
= codec
->spec
;
703 int tag
= res
>> AC_UNSOL_RES_TAG_SHIFT
;
704 int subtag
= (res
& AC_UNSOL_RES_SUBTAG
) >> AC_UNSOL_RES_SUBTAG_SHIFT
;
706 if (hda_node_index(spec
->pin
, tag
) < 0) {
707 snd_printd(KERN_INFO
"Unexpected HDMI event tag 0x%x\n", tag
);
712 hdmi_intrinsic_event(codec
, res
);
714 hdmi_non_intrinsic_event(codec
, res
);
721 /* HBR should be Non-PCM, 8 channels */
722 #define is_hbr_format(format) \
723 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
725 static int hdmi_setup_stream(struct hda_codec
*codec
, hda_nid_t nid
,
726 u32 stream_tag
, int format
)
728 struct hdmi_spec
*spec
= codec
->spec
;
733 for (i
= 0; i
< spec
->num_pins
; i
++) {
734 if (spec
->pin_cvt
[i
] != nid
)
736 if (!(snd_hda_query_pin_caps(codec
, spec
->pin
[i
]) & AC_PINCAP_HBR
))
739 pinctl
= snd_hda_codec_read(codec
, spec
->pin
[i
], 0,
740 AC_VERB_GET_PIN_WIDGET_CONTROL
, 0);
742 new_pinctl
= pinctl
& ~AC_PINCTL_EPT
;
743 if (is_hbr_format(format
))
744 new_pinctl
|= AC_PINCTL_EPT_HBR
;
746 new_pinctl
|= AC_PINCTL_EPT_NATIVE
;
748 snd_printdd("hdmi_setup_stream: "
749 "NID=0x%x, %spinctl=0x%x\n",
751 pinctl
== new_pinctl
? "" : "new-",
754 if (pinctl
!= new_pinctl
)
755 snd_hda_codec_write(codec
, spec
->pin
[i
], 0,
756 AC_VERB_SET_PIN_WIDGET_CONTROL
,
760 if (is_hbr_format(format
) && !new_pinctl
) {
761 snd_printdd("hdmi_setup_stream: HBR is not supported\n");
765 snd_hda_codec_setup_stream(codec
, nid
, stream_tag
, 0, format
);
772 static int hdmi_pcm_open(struct hda_pcm_stream
*hinfo
,
773 struct hda_codec
*codec
,
774 struct snd_pcm_substream
*substream
)
776 struct hdmi_spec
*spec
= codec
->spec
;
777 struct hdmi_eld
*eld
;
778 struct hda_pcm_stream
*codec_pars
;
781 for (idx
= 0; idx
< spec
->num_cvts
; idx
++)
782 if (hinfo
->nid
== spec
->cvt
[idx
])
784 if (snd_BUG_ON(idx
>= spec
->num_cvts
) ||
785 snd_BUG_ON(idx
>= spec
->num_pins
))
788 /* save the PCM info the codec provides */
789 codec_pars
= &spec
->codec_pcm_pars
[idx
];
790 if (!codec_pars
->rates
)
791 *codec_pars
= *hinfo
;
793 eld
= &spec
->sink_eld
[idx
];
794 if (eld
->sad_count
> 0) {
795 hdmi_eld_update_pcm_info(eld
, hinfo
, codec_pars
);
796 if (hinfo
->channels_min
> hinfo
->channels_max
||
797 !hinfo
->rates
|| !hinfo
->formats
)
800 /* fallback to the codec default */
801 hinfo
->channels_min
= codec_pars
->channels_min
;
802 hinfo
->channels_max
= codec_pars
->channels_max
;
803 hinfo
->rates
= codec_pars
->rates
;
804 hinfo
->formats
= codec_pars
->formats
;
805 hinfo
->maxbps
= codec_pars
->maxbps
;
811 * HDA/HDMI auto parsing
813 static int hdmi_read_pin_conn(struct hda_codec
*codec
, hda_nid_t pin_nid
)
815 struct hdmi_spec
*spec
= codec
->spec
;
816 hda_nid_t conn_list
[HDA_MAX_CONNECTIONS
];
820 if (!(get_wcaps(codec
, pin_nid
) & AC_WCAP_CONN_LIST
)) {
821 snd_printk(KERN_WARNING
822 "HDMI: pin %d wcaps %#x "
823 "does not support connection list\n",
824 pin_nid
, get_wcaps(codec
, pin_nid
));
828 conn_len
= snd_hda_get_connections(codec
, pin_nid
, conn_list
,
829 HDA_MAX_CONNECTIONS
);
831 curr
= snd_hda_codec_read(codec
, pin_nid
, 0,
832 AC_VERB_GET_CONNECT_SEL
, 0);
836 index
= hda_node_index(spec
->pin
, pin_nid
);
840 spec
->pin_cvt
[index
] = conn_list
[curr
];
845 static void hdmi_present_sense(struct hda_codec
*codec
, hda_nid_t pin_nid
,
846 struct hdmi_eld
*eld
)
848 int present
= snd_hda_pin_sense(codec
, pin_nid
);
850 eld
->monitor_present
= !!(present
& AC_PINSENSE_PRESENCE
);
851 eld
->eld_valid
= !!(present
& AC_PINSENSE_ELDV
);
853 if (present
& AC_PINSENSE_ELDV
)
854 hdmi_get_show_eld(codec
, pin_nid
, eld
);
857 static int hdmi_add_pin(struct hda_codec
*codec
, hda_nid_t pin_nid
)
859 struct hdmi_spec
*spec
= codec
->spec
;
861 if (spec
->num_pins
>= MAX_HDMI_PINS
) {
862 snd_printk(KERN_WARNING
863 "HDMI: no space for pin %d\n", pin_nid
);
867 hdmi_present_sense(codec
, pin_nid
, &spec
->sink_eld
[spec
->num_pins
]);
869 spec
->pin
[spec
->num_pins
] = pin_nid
;
873 * It is assumed that converter nodes come first in the node list and
874 * hence have been registered and usable now.
876 return hdmi_read_pin_conn(codec
, pin_nid
);
879 static int hdmi_add_cvt(struct hda_codec
*codec
, hda_nid_t nid
)
881 struct hdmi_spec
*spec
= codec
->spec
;
883 if (spec
->num_cvts
>= MAX_HDMI_CVTS
) {
884 snd_printk(KERN_WARNING
885 "HDMI: no space for converter %d\n", nid
);
889 spec
->cvt
[spec
->num_cvts
] = nid
;
895 static int hdmi_parse_codec(struct hda_codec
*codec
)
900 nodes
= snd_hda_get_sub_nodes(codec
, codec
->afg
, &nid
);
901 if (!nid
|| nodes
< 0) {
902 snd_printk(KERN_WARNING
"HDMI: failed to get afg sub nodes\n");
906 for (i
= 0; i
< nodes
; i
++, nid
++) {
910 caps
= snd_hda_param_read(codec
, nid
, AC_PAR_AUDIO_WIDGET_CAP
);
911 type
= get_wcaps_type(caps
);
913 if (!(caps
& AC_WCAP_DIGITAL
))
918 hdmi_add_cvt(codec
, nid
);
921 caps
= snd_hda_param_read(codec
, nid
, AC_PAR_PIN_CAP
);
922 if (!(caps
& (AC_PINCAP_HDMI
| AC_PINCAP_DP
)))
924 hdmi_add_pin(codec
, nid
);
930 * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
931 * can be lost and presence sense verb will become inaccurate if the
932 * HDA link is powered off at hot plug or hw initialization time.
934 #ifdef CONFIG_SND_HDA_POWER_SAVE
935 if (!(snd_hda_param_read(codec
, codec
->afg
, AC_PAR_POWER_STATE
) &
937 codec
->bus
->power_keep_link_on
= 1;
945 static char *generic_hdmi_pcm_names
[MAX_HDMI_CVTS
] = {
955 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
956 struct hda_codec
*codec
,
957 unsigned int stream_tag
,
959 struct snd_pcm_substream
*substream
)
961 hdmi_set_channel_count(codec
, hinfo
->nid
,
962 substream
->runtime
->channels
);
964 hdmi_setup_audio_infoframe(codec
, hinfo
->nid
, substream
);
966 return hdmi_setup_stream(codec
, hinfo
->nid
, stream_tag
, format
);
969 static struct hda_pcm_stream generic_hdmi_pcm_playback
= {
973 .open
= hdmi_pcm_open
,
974 .prepare
= generic_hdmi_playback_pcm_prepare
,
978 static int generic_hdmi_build_pcms(struct hda_codec
*codec
)
980 struct hdmi_spec
*spec
= codec
->spec
;
981 struct hda_pcm
*info
= spec
->pcm_rec
;
984 codec
->num_pcms
= spec
->num_cvts
;
985 codec
->pcm_info
= info
;
987 for (i
= 0; i
< codec
->num_pcms
; i
++, info
++) {
989 struct hda_pcm_stream
*pstr
;
991 chans
= get_wcaps(codec
, spec
->cvt
[i
]);
992 chans
= get_wcaps_channels(chans
);
994 info
->name
= generic_hdmi_pcm_names
[i
];
995 info
->pcm_type
= HDA_PCM_TYPE_HDMI
;
996 pstr
= &info
->stream
[SNDRV_PCM_STREAM_PLAYBACK
];
997 if (spec
->pcm_playback
)
998 *pstr
= *spec
->pcm_playback
;
1000 *pstr
= generic_hdmi_pcm_playback
;
1001 pstr
->nid
= spec
->cvt
[i
];
1002 if (pstr
->channels_max
<= 2 && chans
&& chans
<= 16)
1003 pstr
->channels_max
= chans
;
1009 static int generic_hdmi_build_controls(struct hda_codec
*codec
)
1011 struct hdmi_spec
*spec
= codec
->spec
;
1015 for (i
= 0; i
< codec
->num_pcms
; i
++) {
1016 err
= snd_hda_create_spdif_out_ctls(codec
, spec
->cvt
[i
]);
1024 static int generic_hdmi_init(struct hda_codec
*codec
)
1026 struct hdmi_spec
*spec
= codec
->spec
;
1029 for (i
= 0; spec
->pin
[i
]; i
++) {
1030 hdmi_enable_output(codec
, spec
->pin
[i
]);
1031 snd_hda_codec_write(codec
, spec
->pin
[i
], 0,
1032 AC_VERB_SET_UNSOLICITED_ENABLE
,
1033 AC_USRSP_EN
| spec
->pin
[i
]);
1038 static void generic_hdmi_free(struct hda_codec
*codec
)
1040 struct hdmi_spec
*spec
= codec
->spec
;
1043 for (i
= 0; i
< spec
->num_pins
; i
++)
1044 snd_hda_eld_proc_free(codec
, &spec
->sink_eld
[i
]);
1049 static struct hda_codec_ops generic_hdmi_patch_ops
= {
1050 .init
= generic_hdmi_init
,
1051 .free
= generic_hdmi_free
,
1052 .build_pcms
= generic_hdmi_build_pcms
,
1053 .build_controls
= generic_hdmi_build_controls
,
1054 .unsol_event
= hdmi_unsol_event
,
1057 static int patch_generic_hdmi(struct hda_codec
*codec
)
1059 struct hdmi_spec
*spec
;
1062 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
1067 if (hdmi_parse_codec(codec
) < 0) {
1072 codec
->patch_ops
= generic_hdmi_patch_ops
;
1074 for (i
= 0; i
< spec
->num_pins
; i
++)
1075 snd_hda_eld_proc_new(codec
, &spec
->sink_eld
[i
], i
);
1077 init_channel_allocations();
1083 * Nvidia specific implementations
1086 #define Nv_VERB_SET_Channel_Allocation 0xF79
1087 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
1088 #define Nv_VERB_SET_Audio_Protection_On 0xF98
1089 #define Nv_VERB_SET_Audio_Protection_Off 0xF99
1091 #define nvhdmi_master_con_nid_7x 0x04
1092 #define nvhdmi_master_pin_nid_7x 0x05
1094 static hda_nid_t nvhdmi_con_nids_7x
[4] = {
1095 /*front, rear, clfe, rear_surr */
1099 static struct hda_verb nvhdmi_basic_init_7x
[] = {
1100 /* set audio protect on */
1101 { 0x1, Nv_VERB_SET_Audio_Protection_On
, 0x1},
1102 /* enable digital output on pin widget */
1103 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1104 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1105 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1106 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1107 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
| 0x5 },
1111 #ifdef LIMITED_RATE_FMT_SUPPORT
1112 /* support only the safe format and rate */
1113 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
1114 #define SUPPORTED_MAXBPS 16
1115 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
1117 /* support all rates and formats */
1118 #define SUPPORTED_RATES \
1119 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
1120 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
1121 SNDRV_PCM_RATE_192000)
1122 #define SUPPORTED_MAXBPS 24
1123 #define SUPPORTED_FORMATS \
1124 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
1127 static int nvhdmi_7x_init(struct hda_codec
*codec
)
1129 snd_hda_sequence_write(codec
, nvhdmi_basic_init_7x
);
1133 static int simple_playback_pcm_open(struct hda_pcm_stream
*hinfo
,
1134 struct hda_codec
*codec
,
1135 struct snd_pcm_substream
*substream
)
1137 struct hdmi_spec
*spec
= codec
->spec
;
1138 return snd_hda_multi_out_dig_open(codec
, &spec
->multiout
);
1141 static int simple_playback_pcm_close(struct hda_pcm_stream
*hinfo
,
1142 struct hda_codec
*codec
,
1143 struct snd_pcm_substream
*substream
)
1145 struct hdmi_spec
*spec
= codec
->spec
;
1146 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
1149 static int simple_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1150 struct hda_codec
*codec
,
1151 unsigned int stream_tag
,
1152 unsigned int format
,
1153 struct snd_pcm_substream
*substream
)
1155 struct hdmi_spec
*spec
= codec
->spec
;
1156 return snd_hda_multi_out_dig_prepare(codec
, &spec
->multiout
,
1157 stream_tag
, format
, substream
);
1160 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream
*hinfo
,
1161 struct hda_codec
*codec
,
1162 struct snd_pcm_substream
*substream
)
1164 struct hdmi_spec
*spec
= codec
->spec
;
1167 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
,
1168 0, AC_VERB_SET_CHANNEL_STREAMID
, 0);
1169 for (i
= 0; i
< 4; i
++) {
1170 /* set the stream id */
1171 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
1172 AC_VERB_SET_CHANNEL_STREAMID
, 0);
1173 /* set the stream format */
1174 snd_hda_codec_write(codec
, nvhdmi_con_nids_7x
[i
], 0,
1175 AC_VERB_SET_STREAM_FORMAT
, 0);
1178 return snd_hda_multi_out_dig_close(codec
, &spec
->multiout
);
1181 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1182 struct hda_codec
*codec
,
1183 unsigned int stream_tag
,
1184 unsigned int format
,
1185 struct snd_pcm_substream
*substream
)
1188 unsigned int dataDCC1
, dataDCC2
, chan
, chanmask
, channel_id
;
1191 mutex_lock(&codec
->spdif_mutex
);
1193 chs
= substream
->runtime
->channels
;
1194 chan
= chs
? (chs
- 1) : 1;
1212 dataDCC1
= AC_DIG1_ENABLE
| AC_DIG1_COPYRIGHT
;
1215 /* set the Audio InforFrame Channel Allocation */
1216 snd_hda_codec_write(codec
, 0x1, 0,
1217 Nv_VERB_SET_Channel_Allocation
, chanmask
);
1219 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
1220 if (codec
->spdif_status_reset
&& (codec
->spdif_ctls
& AC_DIG1_ENABLE
))
1221 snd_hda_codec_write(codec
,
1222 nvhdmi_master_con_nid_7x
,
1224 AC_VERB_SET_DIGI_CONVERT_1
,
1225 codec
->spdif_ctls
& ~AC_DIG1_ENABLE
& 0xff);
1227 /* set the stream id */
1228 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
1229 AC_VERB_SET_CHANNEL_STREAMID
, (stream_tag
<< 4) | 0x0);
1231 /* set the stream format */
1232 snd_hda_codec_write(codec
, nvhdmi_master_con_nid_7x
, 0,
1233 AC_VERB_SET_STREAM_FORMAT
, format
);
1235 /* turn on again (if needed) */
1236 /* enable and set the channel status audio/data flag */
1237 if (codec
->spdif_status_reset
&& (codec
->spdif_ctls
& AC_DIG1_ENABLE
)) {
1238 snd_hda_codec_write(codec
,
1239 nvhdmi_master_con_nid_7x
,
1241 AC_VERB_SET_DIGI_CONVERT_1
,
1242 codec
->spdif_ctls
& 0xff);
1243 snd_hda_codec_write(codec
,
1244 nvhdmi_master_con_nid_7x
,
1246 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
1249 for (i
= 0; i
< 4; i
++) {
1255 /* turn off SPDIF once;
1256 *otherwise the IEC958 bits won't be updated
1258 if (codec
->spdif_status_reset
&&
1259 (codec
->spdif_ctls
& AC_DIG1_ENABLE
))
1260 snd_hda_codec_write(codec
,
1261 nvhdmi_con_nids_7x
[i
],
1263 AC_VERB_SET_DIGI_CONVERT_1
,
1264 codec
->spdif_ctls
& ~AC_DIG1_ENABLE
& 0xff);
1265 /* set the stream id */
1266 snd_hda_codec_write(codec
,
1267 nvhdmi_con_nids_7x
[i
],
1269 AC_VERB_SET_CHANNEL_STREAMID
,
1270 (stream_tag
<< 4) | channel_id
);
1271 /* set the stream format */
1272 snd_hda_codec_write(codec
,
1273 nvhdmi_con_nids_7x
[i
],
1275 AC_VERB_SET_STREAM_FORMAT
,
1277 /* turn on again (if needed) */
1278 /* enable and set the channel status audio/data flag */
1279 if (codec
->spdif_status_reset
&&
1280 (codec
->spdif_ctls
& AC_DIG1_ENABLE
)) {
1281 snd_hda_codec_write(codec
,
1282 nvhdmi_con_nids_7x
[i
],
1284 AC_VERB_SET_DIGI_CONVERT_1
,
1285 codec
->spdif_ctls
& 0xff);
1286 snd_hda_codec_write(codec
,
1287 nvhdmi_con_nids_7x
[i
],
1289 AC_VERB_SET_DIGI_CONVERT_2
, dataDCC2
);
1293 /* set the Audio Info Frame Checksum */
1294 snd_hda_codec_write(codec
, 0x1, 0,
1295 Nv_VERB_SET_Info_Frame_Checksum
,
1296 (0x71 - chan
- chanmask
));
1298 mutex_unlock(&codec
->spdif_mutex
);
1302 static struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x
= {
1306 .nid
= nvhdmi_master_con_nid_7x
,
1307 .rates
= SUPPORTED_RATES
,
1308 .maxbps
= SUPPORTED_MAXBPS
,
1309 .formats
= SUPPORTED_FORMATS
,
1311 .open
= simple_playback_pcm_open
,
1312 .close
= nvhdmi_8ch_7x_pcm_close
,
1313 .prepare
= nvhdmi_8ch_7x_pcm_prepare
1317 static struct hda_pcm_stream nvhdmi_pcm_playback_2ch
= {
1321 .nid
= nvhdmi_master_con_nid_7x
,
1322 .rates
= SUPPORTED_RATES
,
1323 .maxbps
= SUPPORTED_MAXBPS
,
1324 .formats
= SUPPORTED_FORMATS
,
1326 .open
= simple_playback_pcm_open
,
1327 .close
= simple_playback_pcm_close
,
1328 .prepare
= simple_playback_pcm_prepare
1332 static struct hda_codec_ops nvhdmi_patch_ops_8ch_7x
= {
1333 .build_controls
= generic_hdmi_build_controls
,
1334 .build_pcms
= generic_hdmi_build_pcms
,
1335 .init
= nvhdmi_7x_init
,
1336 .free
= generic_hdmi_free
,
1339 static struct hda_codec_ops nvhdmi_patch_ops_2ch
= {
1340 .build_controls
= generic_hdmi_build_controls
,
1341 .build_pcms
= generic_hdmi_build_pcms
,
1342 .init
= nvhdmi_7x_init
,
1343 .free
= generic_hdmi_free
,
1346 static int patch_nvhdmi_8ch_89(struct hda_codec
*codec
)
1348 struct hdmi_spec
*spec
;
1349 int err
= patch_generic_hdmi(codec
);
1354 spec
->old_pin_detect
= 1;
1358 static int patch_nvhdmi_2ch(struct hda_codec
*codec
)
1360 struct hdmi_spec
*spec
;
1362 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
1368 spec
->multiout
.num_dacs
= 0; /* no analog */
1369 spec
->multiout
.max_channels
= 2;
1370 spec
->multiout
.dig_out_nid
= nvhdmi_master_con_nid_7x
;
1371 spec
->old_pin_detect
= 1;
1373 spec
->cvt
[0] = nvhdmi_master_con_nid_7x
;
1374 spec
->pcm_playback
= &nvhdmi_pcm_playback_2ch
;
1376 codec
->patch_ops
= nvhdmi_patch_ops_2ch
;
1381 static int patch_nvhdmi_8ch_7x(struct hda_codec
*codec
)
1383 struct hdmi_spec
*spec
;
1384 int err
= patch_nvhdmi_2ch(codec
);
1389 spec
->multiout
.max_channels
= 8;
1390 spec
->pcm_playback
= &nvhdmi_pcm_playback_8ch_7x
;
1391 codec
->patch_ops
= nvhdmi_patch_ops_8ch_7x
;
1396 * ATI-specific implementations
1398 * FIXME: we may omit the whole this and use the generic code once after
1399 * it's confirmed to work.
1402 #define ATIHDMI_CVT_NID 0x02 /* audio converter */
1403 #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
1405 static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream
*hinfo
,
1406 struct hda_codec
*codec
,
1407 unsigned int stream_tag
,
1408 unsigned int format
,
1409 struct snd_pcm_substream
*substream
)
1411 struct hdmi_spec
*spec
= codec
->spec
;
1412 int chans
= substream
->runtime
->channels
;
1415 err
= simple_playback_pcm_prepare(hinfo
, codec
, stream_tag
, format
,
1419 snd_hda_codec_write(codec
, spec
->cvt
[0], 0, AC_VERB_SET_CVT_CHAN_COUNT
,
1422 for (i
= 0; i
< chans
; i
++) {
1423 snd_hda_codec_write(codec
, spec
->cvt
[0], 0,
1424 AC_VERB_SET_HDMI_CHAN_SLOT
,
1430 static struct hda_pcm_stream atihdmi_pcm_digital_playback
= {
1434 .nid
= ATIHDMI_CVT_NID
,
1436 .open
= simple_playback_pcm_open
,
1437 .close
= simple_playback_pcm_close
,
1438 .prepare
= atihdmi_playback_pcm_prepare
1442 static struct hda_verb atihdmi_basic_init
[] = {
1443 /* enable digital output on pin widget */
1444 { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL
, PIN_OUT
},
1448 static int atihdmi_init(struct hda_codec
*codec
)
1450 struct hdmi_spec
*spec
= codec
->spec
;
1452 snd_hda_sequence_write(codec
, atihdmi_basic_init
);
1453 /* SI codec requires to unmute the pin */
1454 if (get_wcaps(codec
, spec
->pin
[0]) & AC_WCAP_OUT_AMP
)
1455 snd_hda_codec_write(codec
, spec
->pin
[0], 0,
1456 AC_VERB_SET_AMP_GAIN_MUTE
,
1461 static struct hda_codec_ops atihdmi_patch_ops
= {
1462 .build_controls
= generic_hdmi_build_controls
,
1463 .build_pcms
= generic_hdmi_build_pcms
,
1464 .init
= atihdmi_init
,
1465 .free
= generic_hdmi_free
,
1469 static int patch_atihdmi(struct hda_codec
*codec
)
1471 struct hdmi_spec
*spec
;
1473 spec
= kzalloc(sizeof(*spec
), GFP_KERNEL
);
1479 spec
->multiout
.num_dacs
= 0; /* no analog */
1480 spec
->multiout
.max_channels
= 2;
1481 spec
->multiout
.dig_out_nid
= ATIHDMI_CVT_NID
;
1483 spec
->cvt
[0] = ATIHDMI_CVT_NID
;
1484 spec
->pin
[0] = ATIHDMI_PIN_NID
;
1485 spec
->pcm_playback
= &atihdmi_pcm_digital_playback
;
1487 codec
->patch_ops
= atihdmi_patch_ops
;
1496 static struct hda_codec_preset snd_hda_preset_hdmi
[] = {
1497 { .id
= 0x1002793c, .name
= "RS600 HDMI", .patch
= patch_atihdmi
},
1498 { .id
= 0x10027919, .name
= "RS600 HDMI", .patch
= patch_atihdmi
},
1499 { .id
= 0x1002791a, .name
= "RS690/780 HDMI", .patch
= patch_atihdmi
},
1500 { .id
= 0x1002aa01, .name
= "R6xx HDMI", .patch
= patch_atihdmi
},
1501 { .id
= 0x10951390, .name
= "SiI1390 HDMI", .patch
= patch_generic_hdmi
},
1502 { .id
= 0x10951392, .name
= "SiI1392 HDMI", .patch
= patch_generic_hdmi
},
1503 { .id
= 0x17e80047, .name
= "Chrontel HDMI", .patch
= patch_generic_hdmi
},
1504 { .id
= 0x10de0002, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1505 { .id
= 0x10de0003, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1506 { .id
= 0x10de0005, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1507 { .id
= 0x10de0006, .name
= "MCP77/78 HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1508 { .id
= 0x10de0007, .name
= "MCP79/7A HDMI", .patch
= patch_nvhdmi_8ch_7x
},
1509 { .id
= 0x10de000a, .name
= "GPU 0a HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1510 { .id
= 0x10de000b, .name
= "GPU 0b HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1511 { .id
= 0x10de000c, .name
= "MCP89 HDMI", .patch
= patch_nvhdmi_8ch_89
},
1512 { .id
= 0x10de000d, .name
= "GPU 0d HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1513 { .id
= 0x10de0010, .name
= "GPU 10 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1514 { .id
= 0x10de0011, .name
= "GPU 11 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1515 { .id
= 0x10de0012, .name
= "GPU 12 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1516 { .id
= 0x10de0013, .name
= "GPU 13 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1517 { .id
= 0x10de0014, .name
= "GPU 14 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1518 { .id
= 0x10de0018, .name
= "GPU 18 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1519 { .id
= 0x10de0019, .name
= "GPU 19 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1520 { .id
= 0x10de001a, .name
= "GPU 1a HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1521 { .id
= 0x10de001b, .name
= "GPU 1b HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1522 { .id
= 0x10de001c, .name
= "GPU 1c HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1523 { .id
= 0x10de0040, .name
= "GPU 40 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1524 { .id
= 0x10de0041, .name
= "GPU 41 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1525 { .id
= 0x10de0042, .name
= "GPU 42 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1526 { .id
= 0x10de0043, .name
= "GPU 43 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1527 { .id
= 0x10de0044, .name
= "GPU 44 HDMI/DP", .patch
= patch_nvhdmi_8ch_89
},
1528 { .id
= 0x10de0067, .name
= "MCP67 HDMI", .patch
= patch_nvhdmi_2ch
},
1529 { .id
= 0x10de8001, .name
= "MCP73 HDMI", .patch
= patch_nvhdmi_2ch
},
1530 { .id
= 0x80860054, .name
= "IbexPeak HDMI", .patch
= patch_generic_hdmi
},
1531 { .id
= 0x80862801, .name
= "Bearlake HDMI", .patch
= patch_generic_hdmi
},
1532 { .id
= 0x80862802, .name
= "Cantiga HDMI", .patch
= patch_generic_hdmi
},
1533 { .id
= 0x80862803, .name
= "Eaglelake HDMI", .patch
= patch_generic_hdmi
},
1534 { .id
= 0x80862804, .name
= "IbexPeak HDMI", .patch
= patch_generic_hdmi
},
1535 { .id
= 0x80862805, .name
= "CougarPoint HDMI", .patch
= patch_generic_hdmi
},
1536 { .id
= 0x808629fb, .name
= "Crestline HDMI", .patch
= patch_generic_hdmi
},
1540 MODULE_ALIAS("snd-hda-codec-id:1002793c");
1541 MODULE_ALIAS("snd-hda-codec-id:10027919");
1542 MODULE_ALIAS("snd-hda-codec-id:1002791a");
1543 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
1544 MODULE_ALIAS("snd-hda-codec-id:10951390");
1545 MODULE_ALIAS("snd-hda-codec-id:10951392");
1546 MODULE_ALIAS("snd-hda-codec-id:10de0002");
1547 MODULE_ALIAS("snd-hda-codec-id:10de0003");
1548 MODULE_ALIAS("snd-hda-codec-id:10de0005");
1549 MODULE_ALIAS("snd-hda-codec-id:10de0006");
1550 MODULE_ALIAS("snd-hda-codec-id:10de0007");
1551 MODULE_ALIAS("snd-hda-codec-id:10de000a");
1552 MODULE_ALIAS("snd-hda-codec-id:10de000b");
1553 MODULE_ALIAS("snd-hda-codec-id:10de000c");
1554 MODULE_ALIAS("snd-hda-codec-id:10de000d");
1555 MODULE_ALIAS("snd-hda-codec-id:10de0010");
1556 MODULE_ALIAS("snd-hda-codec-id:10de0011");
1557 MODULE_ALIAS("snd-hda-codec-id:10de0012");
1558 MODULE_ALIAS("snd-hda-codec-id:10de0013");
1559 MODULE_ALIAS("snd-hda-codec-id:10de0014");
1560 MODULE_ALIAS("snd-hda-codec-id:10de0018");
1561 MODULE_ALIAS("snd-hda-codec-id:10de0019");
1562 MODULE_ALIAS("snd-hda-codec-id:10de001a");
1563 MODULE_ALIAS("snd-hda-codec-id:10de001b");
1564 MODULE_ALIAS("snd-hda-codec-id:10de001c");
1565 MODULE_ALIAS("snd-hda-codec-id:10de0040");
1566 MODULE_ALIAS("snd-hda-codec-id:10de0041");
1567 MODULE_ALIAS("snd-hda-codec-id:10de0042");
1568 MODULE_ALIAS("snd-hda-codec-id:10de0043");
1569 MODULE_ALIAS("snd-hda-codec-id:10de0044");
1570 MODULE_ALIAS("snd-hda-codec-id:10de0067");
1571 MODULE_ALIAS("snd-hda-codec-id:10de8001");
1572 MODULE_ALIAS("snd-hda-codec-id:17e80047");
1573 MODULE_ALIAS("snd-hda-codec-id:80860054");
1574 MODULE_ALIAS("snd-hda-codec-id:80862801");
1575 MODULE_ALIAS("snd-hda-codec-id:80862802");
1576 MODULE_ALIAS("snd-hda-codec-id:80862803");
1577 MODULE_ALIAS("snd-hda-codec-id:80862804");
1578 MODULE_ALIAS("snd-hda-codec-id:80862805");
1579 MODULE_ALIAS("snd-hda-codec-id:808629fb");
1581 MODULE_LICENSE("GPL");
1582 MODULE_DESCRIPTION("HDMI HD-audio codec");
1583 MODULE_ALIAS("snd-hda-codec-intelhdmi");
1584 MODULE_ALIAS("snd-hda-codec-nvhdmi");
1585 MODULE_ALIAS("snd-hda-codec-atihdmi");
1587 static struct hda_codec_preset_list intel_list
= {
1588 .preset
= snd_hda_preset_hdmi
,
1589 .owner
= THIS_MODULE
,
1592 static int __init
patch_hdmi_init(void)
1594 return snd_hda_add_codec_preset(&intel_list
);
1597 static void __exit
patch_hdmi_exit(void)
1599 snd_hda_delete_codec_preset(&intel_list
);
1602 module_init(patch_hdmi_init
)
1603 module_exit(patch_hdmi_exit
)