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- Factor out bge_{disable,enable}_intr().
[dragonfly/vkernel-mp.git] / sys / dev / netif / bge / if_bge.c
blobbcc6bc22178399980fb2729acaa7acabfb12bcf5
1 /*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.84 2007/06/22 15:26:18 sephe Exp $
35 *
36 */
37
38 /*
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
40 *
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
43 */
44
45 /*
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
56 * into the driver.
57 *
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
60 *
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
64 *
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
67 *
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
72 * ring.
73 */
74
75 #include "opt_polling.h"
76 #include <sys/param.h>
77 #include <sys/bus.h>
78 #include <sys/endian.h>
79 #include <sys/kernel.h>
80 #include <sys/ktr.h>
81 #include <sys/mbuf.h>
82 #include <sys/malloc.h>
83 #include <sys/queue.h>
84 #include <sys/rman.h>
85 #include <sys/serialize.h>
86 #include <sys/socket.h>
87 #include <sys/sockio.h>
88 #include <sys/sysctl.h>
89
90 #include <net/bpf.h>
91 #include <net/ethernet.h>
92 #include <net/if.h>
93 #include <net/if_arp.h>
94 #include <net/if_dl.h>
95 #include <net/if_media.h>
96 #include <net/if_types.h>
97 #include <net/ifq_var.h>
98 #include <net/vlan/if_vlan_var.h>
99
100 #include <dev/netif/mii_layer/mii.h>
101 #include <dev/netif/mii_layer/miivar.h>
102 #include <dev/netif/mii_layer/brgphyreg.h>
103
104 #include <bus/pci/pcidevs.h>
105 #include <bus/pci/pcireg.h>
106 #include <bus/pci/pcivar.h>
107
108 #include <dev/netif/bge/if_bgereg.h>
109
110 /* "device miibus" required. See GENERIC if you get errors here. */
111 #include "miibus_if.h"
112
113 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
114 #define BGE_MIN_FRAME 60
115
116 /*
117 * Various supported device vendors/types and their names. Note: the
118 * spec seems to indicate that the hardware still has Alteon's vendor
119 * ID burned into it, though it will always be overriden by the vendor
120 * ID in the EEPROM. Just to be safe, we cover all possibilities.
121 */
122 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
123
124 static struct bge_type bge_devs[] = {
125 { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
126 "3COM 3C996 Gigabit Ethernet" },
127
128 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
129 "Alteon BCM5700 Gigabit Ethernet" },
130 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
131 "Alteon BCM5701 Gigabit Ethernet" },
132
133 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
134 "Altima AC1000 Gigabit Ethernet" },
135 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
136 "Altima AC1002 Gigabit Ethernet" },
137 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
138 "Altima AC9100 Gigabit Ethernet" },
139
140 { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
141 "Apple BCM5701 Gigabit Ethernet" },
142
143 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
144 "Broadcom BCM5700 Gigabit Ethernet" },
145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
146 "Broadcom BCM5701 Gigabit Ethernet" },
147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
148 "Broadcom BCM5702 Gigabit Ethernet" },
149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
150 "Broadcom BCM5702X Gigabit Ethernet" },
151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
152 "Broadcom BCM5702 Gigabit Ethernet" },
153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
154 "Broadcom BCM5703 Gigabit Ethernet" },
155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
156 "Broadcom BCM5703X Gigabit Ethernet" },
157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
158 "Broadcom BCM5703 Gigabit Ethernet" },
159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
160 "Broadcom BCM5704C Dual Gigabit Ethernet" },
161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
162 "Broadcom BCM5704S Dual Gigabit Ethernet" },
163 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
164 "Broadcom BCM5704S Dual Gigabit Ethernet" },
165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
166 "Broadcom BCM5705 Gigabit Ethernet" },
167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
168 "Broadcom BCM5705F Gigabit Ethernet" },
169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
170 "Broadcom BCM5705K Gigabit Ethernet" },
171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
172 "Broadcom BCM5705M Gigabit Ethernet" },
173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
174 "Broadcom BCM5705M Gigabit Ethernet" },
175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
176 "Broadcom BCM5714C Gigabit Ethernet" },
177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
178 "Broadcom BCM5714S Gigabit Ethernet" },
179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
180 "Broadcom BCM5715 Gigabit Ethernet" },
181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
182 "Broadcom BCM5715S Gigabit Ethernet" },
183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
184 "Broadcom BCM5720 Gigabit Ethernet" },
185 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
186 "Broadcom BCM5721 Gigabit Ethernet" },
187 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
188 "Broadcom BCM5722 Gigabit Ethernet" },
189 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
190 "Broadcom BCM5750 Gigabit Ethernet" },
191 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
192 "Broadcom BCM5750M Gigabit Ethernet" },
193 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
194 "Broadcom BCM5751 Gigabit Ethernet" },
195 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
196 "Broadcom BCM5751F Gigabit Ethernet" },
197 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
198 "Broadcom BCM5751M Gigabit Ethernet" },
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
200 "Broadcom BCM5752 Gigabit Ethernet" },
201 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
202 "Broadcom BCM5752M Gigabit Ethernet" },
203 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
204 "Broadcom BCM5753 Gigabit Ethernet" },
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
206 "Broadcom BCM5753F Gigabit Ethernet" },
207 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
208 "Broadcom BCM5753M Gigabit Ethernet" },
209 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
210 "Broadcom BCM5754 Gigabit Ethernet" },
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
212 "Broadcom BCM5754M Gigabit Ethernet" },
213 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
214 "Broadcom BCM5755 Gigabit Ethernet" },
215 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
216 "Broadcom BCM5755M Gigabit Ethernet" },
217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
218 "Broadcom BCM5756 Gigabit Ethernet" },
219 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
220 "Broadcom BCM5780 Gigabit Ethernet" },
221 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
222 "Broadcom BCM5780S Gigabit Ethernet" },
223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
224 "Broadcom BCM5781 Gigabit Ethernet" },
225 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
226 "Broadcom BCM5782 Gigabit Ethernet" },
227 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
228 "Broadcom BCM5786 Gigabit Ethernet" },
229 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
230 "Broadcom BCM5787 Gigabit Ethernet" },
231 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
232 "Broadcom BCM5787F Gigabit Ethernet" },
233 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
234 "Broadcom BCM5787M Gigabit Ethernet" },
235 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
236 "Broadcom BCM5788 Gigabit Ethernet" },
237 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
238 "Broadcom BCM5789 Gigabit Ethernet" },
239 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
240 "Broadcom BCM5901 Fast Ethernet" },
241 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
242 "Broadcom BCM5901A2 Fast Ethernet" },
243 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
244 "Broadcom BCM5903M Fast Ethernet" },
245
246 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
247 "SysKonnect Gigabit Ethernet" },
248
249 { 0, 0, NULL }
250 };
251
252 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO)
253 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
254 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
255 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
256 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
257
258 static int bge_probe(device_t);
259 static int bge_attach(device_t);
260 static int bge_detach(device_t);
261 static void bge_txeof(struct bge_softc *);
262 static void bge_rxeof(struct bge_softc *);
263
264 static void bge_tick(void *);
265 static void bge_stats_update(struct bge_softc *);
266 static void bge_stats_update_regs(struct bge_softc *);
267 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
268
269 #ifdef DEVICE_POLLING
270 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
271 #endif
272 static void bge_intr(void *);
273 static void bge_enable_intr(struct bge_softc *);
274 static void bge_disable_intr(struct bge_softc *);
275 static void bge_start(struct ifnet *);
276 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
277 static void bge_init(void *);
278 static void bge_stop(struct bge_softc *);
279 static void bge_watchdog(struct ifnet *);
280 static void bge_shutdown(device_t);
281 static int bge_suspend(device_t);
282 static int bge_resume(device_t);
283 static int bge_ifmedia_upd(struct ifnet *);
284 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
285
286 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
287 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
288
289 static void bge_setmulti(struct bge_softc *);
290 static void bge_setpromisc(struct bge_softc *);
291
292 static int bge_alloc_jumbo_mem(struct bge_softc *);
293 static void bge_free_jumbo_mem(struct bge_softc *);
294 static struct bge_jslot
295 *bge_jalloc(struct bge_softc *);
296 static void bge_jfree(void *);
297 static void bge_jref(void *);
298 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
299 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
300 static int bge_init_rx_ring_std(struct bge_softc *);
301 static void bge_free_rx_ring_std(struct bge_softc *);
302 static int bge_init_rx_ring_jumbo(struct bge_softc *);
303 static void bge_free_rx_ring_jumbo(struct bge_softc *);
304 static void bge_free_tx_ring(struct bge_softc *);
305 static int bge_init_tx_ring(struct bge_softc *);
306
307 static int bge_chipinit(struct bge_softc *);
308 static int bge_blockinit(struct bge_softc *);
309
310 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
311 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
312 #ifdef notdef
313 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
314 #endif
315 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
316 static void bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
317
318 static int bge_miibus_readreg(device_t, int, int);
319 static int bge_miibus_writereg(device_t, int, int, int);
320 static void bge_miibus_statchg(device_t);
321 static void bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
322 static void bge_tbi_link_upd(struct bge_softc *, uint32_t);
323 static void bge_copper_link_upd(struct bge_softc *, uint32_t);
324
325 static void bge_reset(struct bge_softc *);
326
327 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
328 static void bge_dma_map_mbuf(void *, bus_dma_segment_t *, int,
329 bus_size_t, int);
330 static int bge_dma_alloc(struct bge_softc *);
331 static void bge_dma_free(struct bge_softc *);
332 static int bge_dma_block_alloc(struct bge_softc *, bus_size_t,
333 bus_dma_tag_t *, bus_dmamap_t *,
334 void **, bus_addr_t *);
335 static void bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
336
337 static void bge_coal_change(struct bge_softc *);
338 static int bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
339 static int bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
340 static int bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS);
341 static int bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS);
342 static int bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *, uint32_t);
343
344 /*
345 * Set following tunable to 1 for some IBM blade servers with the DNLK
346 * switch module. Auto negotiation is broken for those configurations.
347 */
348 static int bge_fake_autoneg = 0;
349 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
350
351 /* Interrupt moderation control variables. */
352 static int bge_rx_coal_ticks = 150; /* usec */
353 static int bge_tx_coal_ticks = 1000000; /* usec */
354 static int bge_rx_max_coal_bds = 16;
355 static int bge_tx_max_coal_bds = 32;
356
357 TUNABLE_INT("hw.bge.rx_coal_ticks", &bge_rx_coal_ticks);
358 TUNABLE_INT("hw.bge.tx_coal_ticks", &bge_tx_coal_ticks);
359 TUNABLE_INT("hw.bge.rx_max_coal_bds", &bge_rx_max_coal_bds);
360 TUNABLE_INT("hw.bge.tx_max_coal_bds", &bge_tx_max_coal_bds);
361
362 #if !defined(KTR_IF_BGE)
363 #define KTR_IF_BGE KTR_ALL
364 #endif
365 KTR_INFO_MASTER(if_bge);
366 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr", 0);
367 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt", 0);
368 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt", 0);
369 #define logif(name) KTR_LOG(if_bge_ ## name)
370
371 static device_method_t bge_methods[] = {
372 /* Device interface */
373 DEVMETHOD(device_probe, bge_probe),
374 DEVMETHOD(device_attach, bge_attach),
375 DEVMETHOD(device_detach, bge_detach),
376 DEVMETHOD(device_shutdown, bge_shutdown),
377 DEVMETHOD(device_suspend, bge_suspend),
378 DEVMETHOD(device_resume, bge_resume),
379
380 /* bus interface */
381 DEVMETHOD(bus_print_child, bus_generic_print_child),
382 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
383
384 /* MII interface */
385 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
386 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
387 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
388
389 { 0, 0 }
390 };
391
392 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
393 static devclass_t bge_devclass;
394
395 DECLARE_DUMMY_MODULE(if_bge);
396 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
397 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
398
399 static uint32_t
400 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
401 {
402 device_t dev = sc->bge_dev;
403 uint32_t val;
404
405 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
406 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
407 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
408 return (val);
409 }
410
411 static void
412 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
413 {
414 device_t dev = sc->bge_dev;
415
416 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
417 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
418 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
419 }
420
421 #ifdef notdef
422 static uint32_t
423 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
424 {
425 device_t dev = sc->bge_dev;
426
427 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
428 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
429 }
430 #endif
431
432 static void
433 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
434 {
435 device_t dev = sc->bge_dev;
436
437 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
438 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
439 }
440
441 static void
442 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
443 {
444 CSR_WRITE_4(sc, off, val);
445 }
446
447 /*
448 * Read a byte of data stored in the EEPROM at address 'addr.' The
449 * BCM570x supports both the traditional bitbang interface and an
450 * auto access interface for reading the EEPROM. We use the auto
451 * access method.
452 */
453 static uint8_t
454 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
455 {
456 int i;
457 uint32_t byte = 0;
458
459 /*
460 * Enable use of auto EEPROM access so we can avoid
461 * having to use the bitbang method.
462 */
463 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
464
465 /* Reset the EEPROM, load the clock period. */
466 CSR_WRITE_4(sc, BGE_EE_ADDR,
467 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
468 DELAY(20);
469
470 /* Issue the read EEPROM command. */
471 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
472
473 /* Wait for completion */
474 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
475 DELAY(10);
476 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
477 break;
478 }
479
480 if (i == BGE_TIMEOUT) {
481 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
482 return(1);
483 }
484
485 /* Get result. */
486 byte = CSR_READ_4(sc, BGE_EE_DATA);
487
488 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
489
490 return(0);
491 }
492
493 /*
494 * Read a sequence of bytes from the EEPROM.
495 */
496 static int
497 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
498 {
499 size_t i;
500 int err;
501 uint8_t byte;
502
503 for (byte = 0, err = 0, i = 0; i < len; i++) {
504 err = bge_eeprom_getbyte(sc, off + i, &byte);
505 if (err)
506 break;
507 *(dest + i) = byte;
508 }
509
510 return(err ? 1 : 0);
511 }
512
513 static int
514 bge_miibus_readreg(device_t dev, int phy, int reg)
515 {
516 struct bge_softc *sc;
517 struct ifnet *ifp;
518 uint32_t val, autopoll;
519 int i;
520
521 sc = device_get_softc(dev);
522 ifp = &sc->arpcom.ac_if;
523
524 /*
525 * Broadcom's own driver always assumes the internal
526 * PHY is at GMII address 1. On some chips, the PHY responds
527 * to accesses at all addresses, which could cause us to
528 * bogusly attach the PHY 32 times at probe type. Always
529 * restricting the lookup to address 1 is simpler than
530 * trying to figure out which chips revisions should be
531 * special-cased.
532 */
533 if (phy != 1)
534 return(0);
535
536 /* Reading with autopolling on may trigger PCI errors */
537 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
538 if (autopoll & BGE_MIMODE_AUTOPOLL) {
539 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
540 DELAY(40);
541 }
542
543 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
544 BGE_MIPHY(phy)|BGE_MIREG(reg));
545
546 for (i = 0; i < BGE_TIMEOUT; i++) {
547 val = CSR_READ_4(sc, BGE_MI_COMM);
548 if (!(val & BGE_MICOMM_BUSY))
549 break;
550 }
551
552 if (i == BGE_TIMEOUT) {
553 if_printf(ifp, "PHY read timed out\n");
554 val = 0;
555 goto done;
556 }
557
558 val = CSR_READ_4(sc, BGE_MI_COMM);
559
560 done:
561 if (autopoll & BGE_MIMODE_AUTOPOLL) {
562 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
563 DELAY(40);
564 }
565
566 if (val & BGE_MICOMM_READFAIL)
567 return(0);
568
569 return(val & 0xFFFF);
570 }
571
572 static int
573 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
574 {
575 struct bge_softc *sc;
576 uint32_t autopoll;
577 int i;
578
579 sc = device_get_softc(dev);
580
581 /* Reading with autopolling on may trigger PCI errors */
582 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
583 if (autopoll & BGE_MIMODE_AUTOPOLL) {
584 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
585 DELAY(40);
586 }
587
588 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
589 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
590
591 for (i = 0; i < BGE_TIMEOUT; i++) {
592 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
593 break;
594 }
595
596 if (autopoll & BGE_MIMODE_AUTOPOLL) {
597 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
598 DELAY(40);
599 }
600
601 if (i == BGE_TIMEOUT) {
602 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
603 return(0);
604 }
605
606 return(0);
607 }
608
609 static void
610 bge_miibus_statchg(device_t dev)
611 {
612 struct bge_softc *sc;
613 struct mii_data *mii;
614
615 sc = device_get_softc(dev);
616 mii = device_get_softc(sc->bge_miibus);
617
618 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
619 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
620 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
621 } else {
622 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
623 }
624
625 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
626 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
627 } else {
628 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
629 }
630 }
631
632 /*
633 * Memory management for jumbo frames.
634 */
635 static int
636 bge_alloc_jumbo_mem(struct bge_softc *sc)
637 {
638 struct ifnet *ifp = &sc->arpcom.ac_if;
639 struct bge_jslot *entry;
640 uint8_t *ptr;
641 bus_addr_t paddr;
642 int i, error;
643
644 /*
645 * Create tag for jumbo mbufs.
646 * This is really a bit of a kludge. We allocate a special
647 * jumbo buffer pool which (thanks to the way our DMA
648 * memory allocation works) will consist of contiguous
649 * pages. This means that even though a jumbo buffer might
650 * be larger than a page size, we don't really need to
651 * map it into more than one DMA segment. However, the
652 * default mbuf tag will result in multi-segment mappings,
653 * so we have to create a special jumbo mbuf tag that
654 * lets us get away with mapping the jumbo buffers as
655 * a single segment. I think eventually the driver should
656 * be changed so that it uses ordinary mbufs and cluster
657 * buffers, i.e. jumbo frames can span multiple DMA
658 * descriptors. But that's a project for another day.
659 */
660
661 /*
662 * Create DMA stuffs for jumbo RX ring.
663 */
664 error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
665 &sc->bge_cdata.bge_rx_jumbo_ring_tag,
666 &sc->bge_cdata.bge_rx_jumbo_ring_map,
667 (void **)&sc->bge_ldata.bge_rx_jumbo_ring,
668 &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
669 if (error) {
670 if_printf(ifp, "could not create jumbo RX ring\n");
671 return error;
672 }
673
674 /*
675 * Create DMA stuffs for jumbo buffer block.
676 */
677 error = bge_dma_block_alloc(sc, BGE_JMEM,
678 &sc->bge_cdata.bge_jumbo_tag,
679 &sc->bge_cdata.bge_jumbo_map,
680 (void **)&sc->bge_ldata.bge_jumbo_buf,
681 &paddr);
682 if (error) {
683 if_printf(ifp, "could not create jumbo buffer\n");
684 return error;
685 }
686
687 SLIST_INIT(&sc->bge_jfree_listhead);
688
689 /*
690 * Now divide it up into 9K pieces and save the addresses
691 * in an array. Note that we play an evil trick here by using
692 * the first few bytes in the buffer to hold the the address
693 * of the softc structure for this interface. This is because
694 * bge_jfree() needs it, but it is called by the mbuf management
695 * code which will not pass it to us explicitly.
696 */
697 for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
698 entry = &sc->bge_cdata.bge_jslots[i];
699 entry->bge_sc = sc;
700 entry->bge_buf = ptr;
701 entry->bge_paddr = paddr;
702 entry->bge_inuse = 0;
703 entry->bge_slot = i;
704 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
705
706 ptr += BGE_JLEN;
707 paddr += BGE_JLEN;
708 }
709 return 0;
710 }
711
712 static void
713 bge_free_jumbo_mem(struct bge_softc *sc)
714 {
715 /* Destroy jumbo RX ring. */
716 bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
717 sc->bge_cdata.bge_rx_jumbo_ring_map,
718 sc->bge_ldata.bge_rx_jumbo_ring);
719
720 /* Destroy jumbo buffer block. */
721 bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
722 sc->bge_cdata.bge_jumbo_map,
723 sc->bge_ldata.bge_jumbo_buf);
724 }
725
726 /*
727 * Allocate a jumbo buffer.
728 */
729 static struct bge_jslot *
730 bge_jalloc(struct bge_softc *sc)
731 {
732 struct bge_jslot *entry;
733
734 lwkt_serialize_enter(&sc->bge_jslot_serializer);
735 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
736 if (entry) {
737 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
738 entry->bge_inuse = 1;
739 } else {
740 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
741 }
742 lwkt_serialize_exit(&sc->bge_jslot_serializer);
743 return(entry);
744 }
745
746 /*
747 * Adjust usage count on a jumbo buffer.
748 */
749 static void
750 bge_jref(void *arg)
751 {
752 struct bge_jslot *entry = (struct bge_jslot *)arg;
753 struct bge_softc *sc = entry->bge_sc;
754
755 if (sc == NULL)
756 panic("bge_jref: can't find softc pointer!");
757
758 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
759 panic("bge_jref: asked to reference buffer "
760 "that we don't manage!");
761 } else if (entry->bge_inuse == 0) {
762 panic("bge_jref: buffer already free!");
763 } else {
764 atomic_add_int(&entry->bge_inuse, 1);
765 }
766 }
767
768 /*
769 * Release a jumbo buffer.
770 */
771 static void
772 bge_jfree(void *arg)
773 {
774 struct bge_jslot *entry = (struct bge_jslot *)arg;
775 struct bge_softc *sc = entry->bge_sc;
776
777 if (sc == NULL)
778 panic("bge_jfree: can't find softc pointer!");
779
780 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
781 panic("bge_jfree: asked to free buffer that we don't manage!");
782 } else if (entry->bge_inuse == 0) {
783 panic("bge_jfree: buffer already free!");
784 } else {
785 /*
786 * Possible MP race to 0, use the serializer. The atomic insn
787 * is still needed for races against bge_jref().
788 */
789 lwkt_serialize_enter(&sc->bge_jslot_serializer);
790 atomic_subtract_int(&entry->bge_inuse, 1);
791 if (entry->bge_inuse == 0) {
792 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
793 entry, jslot_link);
794 }
795 lwkt_serialize_exit(&sc->bge_jslot_serializer);
796 }
797 }
798
799
800 /*
801 * Intialize a standard receive ring descriptor.
802 */
803 static int
804 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
805 {
806 struct mbuf *m_new = NULL;
807 struct bge_dmamap_arg ctx;
808 bus_dma_segment_t seg;
809 struct bge_rx_bd *r;
810 int error;
811
812 if (m == NULL) {
813 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
814 if (m_new == NULL)
815 return ENOBUFS;
816 } else {
817 m_new = m;
818 m_new->m_data = m_new->m_ext.ext_buf;
819 }
820 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
821
822 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
823 m_adj(m_new, ETHER_ALIGN);
824
825 ctx.bge_maxsegs = 1;
826 ctx.bge_segs = &seg;
827 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag,
828 sc->bge_cdata.bge_rx_std_dmamap[i],
829 m_new, bge_dma_map_mbuf, &ctx,
830 BUS_DMA_NOWAIT);
831 if (error || ctx.bge_maxsegs == 0) {
832 if (m == NULL)
833 m_freem(m_new);
834 return ENOMEM;
835 }
836
837 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
838
839 r = &sc->bge_ldata.bge_rx_std_ring[i];
840 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[0].ds_addr);
841 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[0].ds_addr);
842 r->bge_flags = BGE_RXBDFLAG_END;
843 r->bge_len = m_new->m_len;
844 r->bge_idx = i;
845
846 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
847 sc->bge_cdata.bge_rx_std_dmamap[i],
848 BUS_DMASYNC_PREREAD);
849 return 0;
850 }
851
852 /*
853 * Initialize a jumbo receive ring descriptor. This allocates
854 * a jumbo buffer from the pool managed internally by the driver.
855 */
856 static int
857 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
858 {
859 struct mbuf *m_new = NULL;
860 struct bge_jslot *buf;
861 struct bge_rx_bd *r;
862 bus_addr_t paddr;
863
864 if (m == NULL) {
865 /* Allocate the mbuf. */
866 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
867 if (m_new == NULL)
868 return(ENOBUFS);
869
870 /* Allocate the jumbo buffer */
871 buf = bge_jalloc(sc);
872 if (buf == NULL) {
873 m_freem(m_new);
874 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
875 "-- packet dropped!\n");
876 return ENOBUFS;
877 }
878
879 /* Attach the buffer to the mbuf. */
880 m_new->m_ext.ext_arg = buf;
881 m_new->m_ext.ext_buf = buf->bge_buf;
882 m_new->m_ext.ext_free = bge_jfree;
883 m_new->m_ext.ext_ref = bge_jref;
884 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
885
886 m_new->m_flags |= M_EXT;
887 } else {
888 KKASSERT(m->m_flags & M_EXT);
889 m_new = m;
890 buf = m_new->m_ext.ext_arg;
891 }
892 m_new->m_data = m_new->m_ext.ext_buf;
893 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
894
895 paddr = buf->bge_paddr;
896 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
897 m_adj(m_new, ETHER_ALIGN);
898 paddr += ETHER_ALIGN;
899 }
900
901 /* Set up the descriptor. */
902 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
903
904 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
905 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(paddr);
906 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(paddr);
907 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
908 r->bge_len = m_new->m_len;
909 r->bge_idx = i;
910
911 return 0;
912 }
913
914 /*
915 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
916 * that's 1MB or memory, which is a lot. For now, we fill only the first
917 * 256 ring entries and hope that our CPU is fast enough to keep up with
918 * the NIC.
919 */
920 static int
921 bge_init_rx_ring_std(struct bge_softc *sc)
922 {
923 int i;
924
925 for (i = 0; i < BGE_SSLOTS; i++) {
926 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
927 return(ENOBUFS);
928 };
929
930 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
931 sc->bge_cdata.bge_rx_std_ring_map,
932 BUS_DMASYNC_PREWRITE);
933
934 sc->bge_std = i - 1;
935 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
936
937 return(0);
938 }
939
940 static void
941 bge_free_rx_ring_std(struct bge_softc *sc)
942 {
943 int i;
944
945 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
946 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
947 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
948 sc->bge_cdata.bge_rx_std_dmamap[i]);
949 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
950 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
951 }
952 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
953 sizeof(struct bge_rx_bd));
954 }
955 }
956
957 static int
958 bge_init_rx_ring_jumbo(struct bge_softc *sc)
959 {
960 int i;
961 struct bge_rcb *rcb;
962
963 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
964 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
965 return(ENOBUFS);
966 };
967
968 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
969 sc->bge_cdata.bge_rx_jumbo_ring_map,
970 BUS_DMASYNC_PREWRITE);
971
972 sc->bge_jumbo = i - 1;
973
974 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
975 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
976 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
977
978 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
979
980 return(0);
981 }
982
983 static void
984 bge_free_rx_ring_jumbo(struct bge_softc *sc)
985 {
986 int i;
987
988 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
989 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
990 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
991 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
992 }
993 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
994 sizeof(struct bge_rx_bd));
995 }
996 }
997
998 static void
999 bge_free_tx_ring(struct bge_softc *sc)
1000 {
1001 int i;
1002
1003 for (i = 0; i < BGE_TX_RING_CNT; i++) {
1004 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1005 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
1006 sc->bge_cdata.bge_tx_dmamap[i]);
1007 m_freem(sc->bge_cdata.bge_tx_chain[i]);
1008 sc->bge_cdata.bge_tx_chain[i] = NULL;
1009 }
1010 bzero(&sc->bge_ldata.bge_tx_ring[i],
1011 sizeof(struct bge_tx_bd));
1012 }
1013 }
1014
1015 static int
1016 bge_init_tx_ring(struct bge_softc *sc)
1017 {
1018 sc->bge_txcnt = 0;
1019 sc->bge_tx_saved_considx = 0;
1020 sc->bge_tx_prodidx = 0;
1021
1022 /* Initialize transmit producer index for host-memory send ring. */
1023 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1024
1025 /* 5700 b2 errata */
1026 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1027 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
1028
1029 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1030 /* 5700 b2 errata */
1031 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1032 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1033
1034 return(0);
1035 }
1036
1037 static void
1038 bge_setmulti(struct bge_softc *sc)
1039 {
1040 struct ifnet *ifp;
1041 struct ifmultiaddr *ifma;
1042 uint32_t hashes[4] = { 0, 0, 0, 0 };
1043 int h, i;
1044
1045 ifp = &sc->arpcom.ac_if;
1046
1047 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
1048 for (i = 0; i < 4; i++)
1049 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1050 return;
1051 }
1052
1053 /* First, zot all the existing filters. */
1054 for (i = 0; i < 4; i++)
1055 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1056
1057 /* Now program new ones. */
1058 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1059 if (ifma->ifma_addr->sa_family != AF_LINK)
1060 continue;
1061 h = ether_crc32_le(
1062 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1063 ETHER_ADDR_LEN) & 0x7f;
1064 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1065 }
1066
1067 for (i = 0; i < 4; i++)
1068 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1069 }
1070
1071 /*
1072 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1073 * self-test results.
1074 */
1075 static int
1076 bge_chipinit(struct bge_softc *sc)
1077 {
1078 int i;
1079 uint32_t dma_rw_ctl;
1080
1081 /* Set endian type before we access any non-PCI registers. */
1082 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1083
1084 /*
1085 * Check the 'ROM failed' bit on the RX CPU to see if
1086 * self-tests passed.
1087 */
1088 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1089 if_printf(&sc->arpcom.ac_if,
1090 "RX CPU self-diagnostics failed!\n");
1091 return(ENODEV);
1092 }
1093
1094 /* Clear the MAC control register */
1095 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1096
1097 /*
1098 * Clear the MAC statistics block in the NIC's
1099 * internal memory.
1100 */
1101 for (i = BGE_STATS_BLOCK;
1102 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1103 BGE_MEMWIN_WRITE(sc, i, 0);
1104
1105 for (i = BGE_STATUS_BLOCK;
1106 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1107 BGE_MEMWIN_WRITE(sc, i, 0);
1108
1109 /* Set up the PCI DMA control register. */
1110 if (sc->bge_flags & BGE_FLAG_PCIE) {
1111 /* PCI Express */
1112 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1113 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1114 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1115 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1116 /* PCI-X bus */
1117 if (BGE_IS_5714_FAMILY(sc)) {
1118 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD;
1119 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */
1120 /* XXX magic values, Broadcom-supplied Linux driver */
1121 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
1122 dma_rw_ctl |= (1 << 20) | (1 << 18) |
1123 BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1124 } else {
1125 dma_rw_ctl |= (1 << 20) | (1 << 18) | (1 << 15);
1126 }
1127 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1128 /*
1129 * The 5704 uses a different encoding of read/write
1130 * watermarks.
1131 */
1132 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1133 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1134 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1135 } else {
1136 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1137 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1138 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1139 (0x0F);
1140 }
1141
1142 /*
1143 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1144 * for hardware bugs.
1145 */
1146 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1147 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1148 uint32_t tmp;
1149
1150 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1151 if (tmp == 0x6 || tmp == 0x7)
1152 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1153 }
1154 } else {
1155 /* Conventional PCI bus */
1156 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1157 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1158 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1159 (0x0F);
1160 }
1161
1162 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1163 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1164 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1165 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1166 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1167
1168 /*
1169 * Set up general mode register.
1170 */
1171 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1172 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1173 BGE_MODECTL_TX_NO_PHDR_CSUM);
1174
1175 /*
1176 * Disable memory write invalidate. Apparently it is not supported
1177 * properly by these devices.
1178 */
1179 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1180
1181 /* Set the timer prescaler (always 66Mhz) */
1182 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1183
1184 return(0);
1185 }
1186
1187 static int
1188 bge_blockinit(struct bge_softc *sc)
1189 {
1190 struct bge_rcb *rcb;
1191 bus_size_t vrcb;
1192 bge_hostaddr taddr;
1193 uint32_t val;
1194 int i;
1195
1196 /*
1197 * Initialize the memory window pointer register so that
1198 * we can access the first 32K of internal NIC RAM. This will
1199 * allow us to set up the TX send ring RCBs and the RX return
1200 * ring RCBs, plus other things which live in NIC memory.
1201 */
1202 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1203
1204 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1205
1206 if (!BGE_IS_5705_PLUS(sc)) {
1207 /* Configure mbuf memory pool */
1208 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1209 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1210 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1211 else
1212 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1213
1214 /* Configure DMA resource pool */
1215 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1216 BGE_DMA_DESCRIPTORS);
1217 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1218 }
1219
1220 /* Configure mbuf pool watermarks */
1221 if (BGE_IS_5705_PLUS(sc)) {
1222 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1223 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1224 } else {
1225 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1226 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1227 }
1228 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1229
1230 /* Configure DMA resource watermarks */
1231 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1232 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1233
1234 /* Enable buffer manager */
1235 if (!BGE_IS_5705_PLUS(sc)) {
1236 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1237 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1238
1239 /* Poll for buffer manager start indication */
1240 for (i = 0; i < BGE_TIMEOUT; i++) {
1241 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1242 break;
1243 DELAY(10);
1244 }
1245
1246 if (i == BGE_TIMEOUT) {
1247 if_printf(&sc->arpcom.ac_if,
1248 "buffer manager failed to start\n");
1249 return(ENXIO);
1250 }
1251 }
1252
1253 /* Enable flow-through queues */
1254 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1255 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1256
1257 /* Wait until queue initialization is complete */
1258 for (i = 0; i < BGE_TIMEOUT; i++) {
1259 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1260 break;
1261 DELAY(10);
1262 }
1263
1264 if (i == BGE_TIMEOUT) {
1265 if_printf(&sc->arpcom.ac_if,
1266 "flow-through queue init failed\n");
1267 return(ENXIO);
1268 }
1269
1270 /* Initialize the standard RX ring control block */
1271 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1272 rcb->bge_hostaddr.bge_addr_lo =
1273 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1274 rcb->bge_hostaddr.bge_addr_hi =
1275 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1276 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1277 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1278 if (BGE_IS_5705_PLUS(sc))
1279 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1280 else
1281 rcb->bge_maxlen_flags =
1282 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1283 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1284 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1285 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1286 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1287 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1288
1289 /*
1290 * Initialize the jumbo RX ring control block
1291 * We set the 'ring disabled' bit in the flags
1292 * field until we're actually ready to start
1293 * using this ring (i.e. once we set the MTU
1294 * high enough to require it).
1295 */
1296 if (BGE_IS_JUMBO_CAPABLE(sc)) {
1297 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1298
1299 rcb->bge_hostaddr.bge_addr_lo =
1300 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1301 rcb->bge_hostaddr.bge_addr_hi =
1302 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1303 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1304 sc->bge_cdata.bge_rx_jumbo_ring_map,
1305 BUS_DMASYNC_PREREAD);
1306 rcb->bge_maxlen_flags =
1307 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1308 BGE_RCB_FLAG_RING_DISABLED);
1309 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1310 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1311 rcb->bge_hostaddr.bge_addr_hi);
1312 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1313 rcb->bge_hostaddr.bge_addr_lo);
1314 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1315 rcb->bge_maxlen_flags);
1316 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1317
1318 /* Set up dummy disabled mini ring RCB */
1319 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
1320 rcb->bge_maxlen_flags =
1321 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1322 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1323 rcb->bge_maxlen_flags);
1324 }
1325
1326 /*
1327 * Set the BD ring replentish thresholds. The recommended
1328 * values are 1/8th the number of descriptors allocated to
1329 * each ring.
1330 */
1331 if (BGE_IS_5705_PLUS(sc))
1332 val = 8;
1333 else
1334 val = BGE_STD_RX_RING_CNT / 8;
1335 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
1336 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1337
1338 /*
1339 * Disable all unused send rings by setting the 'ring disabled'
1340 * bit in the flags field of all the TX send ring control blocks.
1341 * These are located in NIC memory.
1342 */
1343 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1344 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1345 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1346 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1347 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1348 vrcb += sizeof(struct bge_rcb);
1349 }
1350
1351 /* Configure TX RCB 0 (we use only the first ring) */
1352 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1353 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1354 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1355 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1356 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1357 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1358 if (!BGE_IS_5705_PLUS(sc)) {
1359 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1360 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1361 }
1362
1363 /* Disable all unused RX return rings */
1364 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1365 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1366 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1367 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1368 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1369 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1370 BGE_RCB_FLAG_RING_DISABLED));
1371 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1372 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1373 (i * (sizeof(uint64_t))), 0);
1374 vrcb += sizeof(struct bge_rcb);
1375 }
1376
1377 /* Initialize RX ring indexes */
1378 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1379 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1380 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1381
1382 /*
1383 * Set up RX return ring 0
1384 * Note that the NIC address for RX return rings is 0x00000000.
1385 * The return rings live entirely within the host, so the
1386 * nicaddr field in the RCB isn't used.
1387 */
1388 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1389 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1390 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1391 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1392 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1393 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1394 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1395
1396 /* Set random backoff seed for TX */
1397 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1398 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1399 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1400 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1401 BGE_TX_BACKOFF_SEED_MASK);
1402
1403 /* Set inter-packet gap */
1404 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1405
1406 /*
1407 * Specify which ring to use for packets that don't match
1408 * any RX rules.
1409 */
1410 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1411
1412 /*
1413 * Configure number of RX lists. One interrupt distribution
1414 * list, sixteen active lists, one bad frames class.
1415 */
1416 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1417
1418 /* Inialize RX list placement stats mask. */
1419 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1420 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1421
1422 /* Disable host coalescing until we get it set up */
1423 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1424
1425 /* Poll to make sure it's shut down. */
1426 for (i = 0; i < BGE_TIMEOUT; i++) {
1427 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1428 break;
1429 DELAY(10);
1430 }
1431
1432 if (i == BGE_TIMEOUT) {
1433 if_printf(&sc->arpcom.ac_if,
1434 "host coalescing engine failed to idle\n");
1435 return(ENXIO);
1436 }
1437
1438 /* Set up host coalescing defaults */
1439 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1440 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1441 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1442 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1443 if (!BGE_IS_5705_PLUS(sc)) {
1444 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1445 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1446 }
1447 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
1448 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
1449
1450 /* Set up address of statistics block */
1451 if (!BGE_IS_5705_PLUS(sc)) {
1452 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1453 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1454 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1455 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1456
1457 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1458 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1459 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1460 }
1461
1462 /* Set up address of status block */
1463 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
1464 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
1465 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1466 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
1467 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0;
1468 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0;
1469
1470 /* Turn on host coalescing state machine */
1471 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1472
1473 /* Turn on RX BD completion state machine and enable attentions */
1474 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1475 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1476
1477 /* Turn on RX list placement state machine */
1478 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1479
1480 /* Turn on RX list selector state machine. */
1481 if (!BGE_IS_5705_PLUS(sc))
1482 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1483
1484 /* Turn on DMA, clear stats */
1485 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1486 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1487 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1488 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1489 ((sc->bge_flags & BGE_FLAG_TBI) ?
1490 BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1491
1492 /* Set misc. local control, enable interrupts on attentions */
1493 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1494
1495 #ifdef notdef
1496 /* Assert GPIO pins for PHY reset */
1497 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1498 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1499 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1500 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1501 #endif
1502
1503 /* Turn on DMA completion state machine */
1504 if (!BGE_IS_5705_PLUS(sc))
1505 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1506
1507 /* Turn on write DMA state machine */
1508 val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
1509 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1510 sc->bge_asicrev == BGE_ASICREV_BCM5787)
1511 val |= (1 << 29); /* Enable host coalescing bug fix. */
1512 CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
1513
1514 /* Turn on read DMA state machine */
1515 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1516 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1517
1518 /* Turn on RX data completion state machine */
1519 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1520
1521 /* Turn on RX BD initiator state machine */
1522 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1523
1524 /* Turn on RX data and RX BD initiator state machine */
1525 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1526
1527 /* Turn on Mbuf cluster free state machine */
1528 if (!BGE_IS_5705_PLUS(sc))
1529 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1530
1531 /* Turn on send BD completion state machine */
1532 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1533
1534 /* Turn on send data completion state machine */
1535 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1536
1537 /* Turn on send data initiator state machine */
1538 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1539
1540 /* Turn on send BD initiator state machine */
1541 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1542
1543 /* Turn on send BD selector state machine */
1544 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1545
1546 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1547 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1548 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1549
1550 /* ack/clear link change events */
1551 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1552 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1553 BGE_MACSTAT_LINK_CHANGED);
1554 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1555
1556 /* Enable PHY auto polling (for MII/GMII only) */
1557 if (sc->bge_flags & BGE_FLAG_TBI) {
1558 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1559 } else {
1560 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1561 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1562 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1563 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1564 BGE_EVTENB_MI_INTERRUPT);
1565 }
1566 }
1567
1568 /*
1569 * Clear any pending link state attention.
1570 * Otherwise some link state change events may be lost until attention
1571 * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
1572 * It's not necessary on newer BCM chips - perhaps enabling link
1573 * state change attentions implies clearing pending attention.
1574 */
1575 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1576 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1577 BGE_MACSTAT_LINK_CHANGED);
1578
1579 /* Enable link state change attentions. */
1580 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1581
1582 return(0);
1583 }
1584
1585 /*
1586 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1587 * against our list and return its name if we find a match. Note
1588 * that since the Broadcom controller contains VPD support, we
1589 * can get the device name string from the controller itself instead
1590 * of the compiled-in string. This is a little slow, but it guarantees
1591 * we'll always announce the right product name.
1592 */
1593 static int
1594 bge_probe(device_t dev)
1595 {
1596 struct bge_softc *sc;
1597 struct bge_type *t;
1598 char *descbuf;
1599 uint16_t product, vendor;
1600
1601 product = pci_get_device(dev);
1602 vendor = pci_get_vendor(dev);
1603
1604 for (t = bge_devs; t->bge_name != NULL; t++) {
1605 if (vendor == t->bge_vid && product == t->bge_did)
1606 break;
1607 }
1608
1609 if (t->bge_name == NULL)
1610 return(ENXIO);
1611
1612 sc = device_get_softc(dev);
1613 descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1614 ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1615 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1616 device_set_desc_copy(dev, descbuf);
1617 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1618 sc->bge_flags |= BGE_FLAG_NO_3LED;
1619 kfree(descbuf, M_TEMP);
1620 return(0);
1621 }
1622
1623 static int
1624 bge_attach(device_t dev)
1625 {
1626 struct ifnet *ifp;
1627 struct bge_softc *sc;
1628 uint32_t hwcfg = 0;
1629 uint32_t mac_addr = 0;
1630 int error = 0, rid;
1631 uint8_t ether_addr[ETHER_ADDR_LEN];
1632
1633 sc = device_get_softc(dev);
1634 sc->bge_dev = dev;
1635 callout_init(&sc->bge_stat_timer);
1636 lwkt_serialize_init(&sc->bge_jslot_serializer);
1637
1638 /*
1639 * Map control/status registers.
1640 */
1641 pci_enable_busmaster(dev);
1642
1643 rid = BGE_PCI_BAR0;
1644 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1645 RF_ACTIVE);
1646
1647 if (sc->bge_res == NULL) {
1648 device_printf(dev, "couldn't map memory\n");
1649 return ENXIO;
1650 }
1651
1652 sc->bge_btag = rman_get_bustag(sc->bge_res);
1653 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1654
1655 /* Save ASIC rev. */
1656 sc->bge_chipid =
1657 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1658 BGE_PCIMISCCTL_ASICREV;
1659 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1660 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1661
1662 /* Save chipset family. */
1663 switch (sc->bge_asicrev) {
1664 case BGE_ASICREV_BCM5700:
1665 case BGE_ASICREV_BCM5701:
1666 case BGE_ASICREV_BCM5703:
1667 case BGE_ASICREV_BCM5704:
1668 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
1669 break;
1670
1671 case BGE_ASICREV_BCM5714_A0:
1672 case BGE_ASICREV_BCM5780:
1673 case BGE_ASICREV_BCM5714:
1674 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
1675 /* Fall through */
1676
1677 case BGE_ASICREV_BCM5750:
1678 case BGE_ASICREV_BCM5752:
1679 case BGE_ASICREV_BCM5755:
1680 case BGE_ASICREV_BCM5787:
1681 sc->bge_flags |= BGE_FLAG_575X_PLUS;
1682 /* Fall through */
1683
1684 case BGE_ASICREV_BCM5705:
1685 sc->bge_flags |= BGE_FLAG_5705_PLUS;
1686 break;
1687 }
1688
1689 /*
1690 * Set various quirk flags.
1691 */
1692
1693 sc->bge_flags |= BGE_FLAG_ETH_WIRESPEED;
1694 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1695 (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
1696 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
1697 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
1698 sc->bge_asicrev == BGE_ASICREV_BCM5906)
1699 sc->bge_flags &= ~BGE_FLAG_ETH_WIRESPEED;
1700
1701 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
1702 sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
1703 sc->bge_flags |= BGE_FLAG_CRC_BUG;
1704
1705 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
1706 sc->bge_chiprev == BGE_CHIPREV_5704_AX)
1707 sc->bge_flags |= BGE_FLAG_ADC_BUG;
1708
1709 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
1710 sc->bge_flags |= BGE_FLAG_5704_A0_BUG;
1711
1712 if (BGE_IS_5705_PLUS(sc)) {
1713 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
1714 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
1715 uint32_t product = pci_get_device(dev);
1716
1717 if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
1718 product != PCI_PRODUCT_BROADCOM_BCM5756)
1719 sc->bge_flags |= BGE_FLAG_JITTER_BUG;
1720 if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
1721 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM;
1722 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) {
1723 sc->bge_flags |= BGE_FLAG_BER_BUG;
1724 }
1725 }
1726
1727 /* Allocate interrupt */
1728 rid = 0;
1729
1730 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1731 RF_SHAREABLE | RF_ACTIVE);
1732
1733 if (sc->bge_irq == NULL) {
1734 device_printf(dev, "couldn't map interrupt\n");
1735 error = ENXIO;
1736 goto fail;
1737 }
1738
1739 /*
1740 * Check if this is a PCI-X or PCI Express device.
1741 */
1742 if (BGE_IS_5705_PLUS(sc)) {
1743 uint32_t reg;
1744
1745 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
1746 if ((reg & 0xff) == BGE_PCIE_CAPID)
1747 sc->bge_flags |= BGE_FLAG_PCIE;
1748 } else {
1749 /*
1750 * Check if the device is in PCI-X Mode.
1751 * (This bit is not valid on PCI Express controllers.)
1752 */
1753 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1754 BGE_PCISTATE_PCI_BUSMODE) == 0)
1755 sc->bge_flags |= BGE_FLAG_PCIX;
1756 }
1757
1758 ifp = &sc->arpcom.ac_if;
1759 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1760
1761 /* Try to reset the chip. */
1762 bge_reset(sc);
1763
1764 if (bge_chipinit(sc)) {
1765 device_printf(dev, "chip initialization failed\n");
1766 error = ENXIO;
1767 goto fail;
1768 }
1769
1770 /*
1771 * Get station address from the EEPROM.
1772 */
1773 mac_addr = bge_readmem_ind(sc, 0x0c14);
1774 if ((mac_addr >> 16) == 0x484b) {
1775 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1776 ether_addr[1] = (uint8_t)mac_addr;
1777 mac_addr = bge_readmem_ind(sc, 0x0c18);
1778 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1779 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1780 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1781 ether_addr[5] = (uint8_t)mac_addr;
1782 } else if (bge_read_eeprom(sc, ether_addr,
1783 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1784 device_printf(dev, "failed to read station address\n");
1785 error = ENXIO;
1786 goto fail;
1787 }
1788
1789 /* 5705/5750 limits RX return ring to 512 entries. */
1790 if (BGE_IS_5705_PLUS(sc))
1791 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1792 else
1793 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1794
1795 error = bge_dma_alloc(sc);
1796 if (error)
1797 goto fail;
1798
1799 /* Set default tuneable values. */
1800 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1801 sc->bge_rx_coal_ticks = bge_rx_coal_ticks;
1802 sc->bge_tx_coal_ticks = bge_tx_coal_ticks;
1803 sc->bge_rx_max_coal_bds = bge_rx_max_coal_bds;
1804 sc->bge_tx_max_coal_bds = bge_tx_max_coal_bds;
1805
1806 /* Set up ifnet structure */
1807 ifp->if_softc = sc;
1808 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1809 ifp->if_ioctl = bge_ioctl;
1810 ifp->if_start = bge_start;
1811 #ifdef DEVICE_POLLING
1812 ifp->if_poll = bge_poll;
1813 #endif
1814 ifp->if_watchdog = bge_watchdog;
1815 ifp->if_init = bge_init;
1816 ifp->if_mtu = ETHERMTU;
1817 ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1818 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1819 ifq_set_ready(&ifp->if_snd);
1820
1821 /*
1822 * 5700 B0 chips do not support checksumming correctly due
1823 * to hardware bugs.
1824 */
1825 if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
1826 ifp->if_capabilities |= IFCAP_HWCSUM;
1827 ifp->if_hwassist = BGE_CSUM_FEATURES;
1828 }
1829 ifp->if_capenable = ifp->if_capabilities;
1830
1831 /*
1832 * Figure out what sort of media we have by checking the
1833 * hardware config word in the first 32k of NIC internal memory,
1834 * or fall back to examining the EEPROM if necessary.
1835 * Note: on some BCM5700 cards, this value appears to be unset.
1836 * If that's the case, we have to rely on identifying the NIC
1837 * by its PCI subsystem ID, as we do below for the SysKonnect
1838 * SK-9D41.
1839 */
1840 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1841 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1842 else {
1843 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
1844 sizeof(hwcfg))) {
1845 device_printf(dev, "failed to read EEPROM\n");
1846 error = ENXIO;
1847 goto fail;
1848 }
1849 hwcfg = ntohl(hwcfg);
1850 }
1851
1852 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1853 sc->bge_flags |= BGE_FLAG_TBI;
1854
1855 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1856 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1857 sc->bge_flags |= BGE_FLAG_TBI;
1858
1859 if (sc->bge_flags & BGE_FLAG_TBI) {
1860 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1861 bge_ifmedia_upd, bge_ifmedia_sts);
1862 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1863 ifmedia_add(&sc->bge_ifmedia,
1864 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1865 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1866 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1867 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1868 } else {
1869 /*
1870 * Do transceiver setup.
1871 */
1872 if (mii_phy_probe(dev, &sc->bge_miibus,
1873 bge_ifmedia_upd, bge_ifmedia_sts)) {
1874 device_printf(dev, "MII without any PHY!\n");
1875 error = ENXIO;
1876 goto fail;
1877 }
1878 }
1879
1880 /*
1881 * When using the BCM5701 in PCI-X mode, data corruption has
1882 * been observed in the first few bytes of some received packets.
1883 * Aligning the packet buffer in memory eliminates the corruption.
1884 * Unfortunately, this misaligns the packet payloads. On platforms
1885 * which do not support unaligned accesses, we will realign the
1886 * payloads by copying the received packets.
1887 */
1888 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1889 (sc->bge_flags & BGE_FLAG_PCIX))
1890 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
1891
1892 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
1893 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
1894 sc->bge_link_upd = bge_bcm5700_link_upd;
1895 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
1896 } else if (sc->bge_flags & BGE_FLAG_TBI) {
1897 sc->bge_link_upd = bge_tbi_link_upd;
1898 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1899 } else {
1900 sc->bge_link_upd = bge_copper_link_upd;
1901 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
1902 }
1903
1904 /*
1905 * Create sysctl nodes.
1906 */
1907 sysctl_ctx_init(&sc->bge_sysctl_ctx);
1908 sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
1909 SYSCTL_STATIC_CHILDREN(_hw),
1910 OID_AUTO,
1911 device_get_nameunit(dev),
1912 CTLFLAG_RD, 0, "");
1913 if (sc->bge_sysctl_tree == NULL) {
1914 device_printf(dev, "can't add sysctl node\n");
1915 error = ENXIO;
1916 goto fail;
1917 }
1918
1919 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1920 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1921 OID_AUTO, "rx_coal_ticks",
1922 CTLTYPE_INT | CTLFLAG_RW,
1923 sc, 0, bge_sysctl_rx_coal_ticks, "I",
1924 "Receive coalescing ticks (usec).");
1925 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1926 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1927 OID_AUTO, "tx_coal_ticks",
1928 CTLTYPE_INT | CTLFLAG_RW,
1929 sc, 0, bge_sysctl_tx_coal_ticks, "I",
1930 "Transmit coalescing ticks (usec).");
1931 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1932 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1933 OID_AUTO, "rx_max_coal_bds",
1934 CTLTYPE_INT | CTLFLAG_RW,
1935 sc, 0, bge_sysctl_rx_max_coal_bds, "I",
1936 "Receive max coalesced BD count.");
1937 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
1938 SYSCTL_CHILDREN(sc->bge_sysctl_tree),
1939 OID_AUTO, "tx_max_coal_bds",
1940 CTLTYPE_INT | CTLFLAG_RW,
1941 sc, 0, bge_sysctl_tx_max_coal_bds, "I",
1942 "Transmit max coalesced BD count.");
1943
1944 /*
1945 * Call MI attach routine.
1946 */
1947 ether_ifattach(ifp, ether_addr, NULL);
1948
1949 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1950 bge_intr, sc, &sc->bge_intrhand,
1951 ifp->if_serializer);
1952 if (error) {
1953 ether_ifdetach(ifp);
1954 device_printf(dev, "couldn't set up irq\n");
1955 goto fail;
1956 }
1957 return(0);
1958 fail:
1959 bge_detach(dev);
1960 return(error);
1961 }
1962
1963 static int
1964 bge_detach(device_t dev)
1965 {
1966 struct bge_softc *sc = device_get_softc(dev);
1967
1968 if (device_is_attached(dev)) {
1969 struct ifnet *ifp = &sc->arpcom.ac_if;
1970
1971 lwkt_serialize_enter(ifp->if_serializer);
1972 bge_stop(sc);
1973 bge_reset(sc);
1974 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1975 lwkt_serialize_exit(ifp->if_serializer);
1976
1977 ether_ifdetach(ifp);
1978 }
1979
1980 if (sc->bge_flags & BGE_FLAG_TBI)
1981 ifmedia_removeall(&sc->bge_ifmedia);
1982 if (sc->bge_miibus)
1983 device_delete_child(dev, sc->bge_miibus);
1984 bus_generic_detach(dev);
1985
1986 if (sc->bge_irq != NULL)
1987 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1988
1989 if (sc->bge_res != NULL)
1990 bus_release_resource(dev, SYS_RES_MEMORY,
1991 BGE_PCI_BAR0, sc->bge_res);
1992
1993 if (sc->bge_sysctl_tree != NULL)
1994 sysctl_ctx_free(&sc->bge_sysctl_ctx);
1995
1996 bge_dma_free(sc);
1997
1998 return 0;
1999 }
2000
2001 static void
2002 bge_reset(struct bge_softc *sc)
2003 {
2004 device_t dev;
2005 uint32_t cachesize, command, pcistate, reset;
2006 void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
2007 int i, val = 0;
2008
2009 dev = sc->bge_dev;
2010
2011 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) {
2012 if (sc->bge_flags & BGE_FLAG_PCIE)
2013 write_op = bge_writemem_direct;
2014 else
2015 write_op = bge_writemem_ind;
2016 } else {
2017 write_op = bge_writereg_ind;
2018 }
2019
2020 /* Save some important PCI state. */
2021 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2022 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2023 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2024
2025 pci_write_config(dev, BGE_PCI_MISC_CTL,
2026 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2027 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2028
2029 /* Disable fastboot on controllers that support it. */
2030 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
2031 sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2032 sc->bge_asicrev == BGE_ASICREV_BCM5787) {
2033 if (bootverbose)
2034 if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
2035 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
2036 }
2037
2038 /*
2039 * Write the magic number to SRAM at offset 0xB50.
2040 * When firmware finishes its initialization it will
2041 * write ~BGE_MAGIC_NUMBER to the same location.
2042 */
2043 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2044
2045 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2046
2047 /* XXX: Broadcom Linux driver. */
2048 if (sc->bge_flags & BGE_FLAG_PCIE) {
2049 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2050 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2051 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2052 /* Prevent PCIE link training during global reset */
2053 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2054 reset |= (1<<29);
2055 }
2056 }
2057
2058 /*
2059 * Set GPHY Power Down Override to leave GPHY
2060 * powered up in D0 uninitialized.
2061 */
2062 if (BGE_IS_5705_PLUS(sc))
2063 reset |= 0x04000000;
2064
2065 /* Issue global reset */
2066 write_op(sc, BGE_MISC_CFG, reset);
2067
2068 DELAY(1000);
2069
2070 /* XXX: Broadcom Linux driver. */
2071 if (sc->bge_flags & BGE_FLAG_PCIE) {
2072 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2073 uint32_t v;
2074
2075 DELAY(500000); /* wait for link training to complete */
2076 v = pci_read_config(dev, 0xc4, 4);
2077 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2078 }
2079 /*
2080 * Set PCIE max payload size to 128 bytes and
2081 * clear error status.
2082 */
2083 pci_write_config(dev, 0xd8, 0xf5000, 4);
2084 }
2085
2086 /* Reset some of the PCI state that got zapped by reset */
2087 pci_write_config(dev, BGE_PCI_MISC_CTL,
2088 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2089 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2090 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2091 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2092 write_op(sc, BGE_MISC_CFG, (65 << 1));
2093
2094 /* Enable memory arbiter. */
2095 if (BGE_IS_5714_FAMILY(sc)) {
2096 uint32_t val;
2097
2098 val = CSR_READ_4(sc, BGE_MARB_MODE);
2099 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
2100 } else {
2101 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2102 }
2103
2104 /*
2105 * Poll until we see the 1's complement of the magic number.
2106 * This indicates that the firmware initialization
2107 * is complete.
2108 */
2109 for (i = 0; i < BGE_TIMEOUT; i++) {
2110 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
2111 if (val == ~BGE_MAGIC_NUMBER)
2112 break;
2113 DELAY(10);
2114 }
2115
2116 if (i == BGE_TIMEOUT) {
2117 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out,"
2118 "found 0x%08x\n", val);
2119 return;
2120 }
2121
2122 /*
2123 * XXX Wait for the value of the PCISTATE register to
2124 * return to its original pre-reset state. This is a
2125 * fairly good indicator of reset completion. If we don't
2126 * wait for the reset to fully complete, trying to read
2127 * from the device's non-PCI registers may yield garbage
2128 * results.
2129 */
2130 for (i = 0; i < BGE_TIMEOUT; i++) {
2131 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2132 break;
2133 DELAY(10);
2134 }
2135
2136 if (sc->bge_flags & BGE_FLAG_PCIE) {
2137 reset = bge_readmem_ind(sc, 0x7c00);
2138 bge_writemem_ind(sc, 0x7c00, reset | (1 << 25));
2139 }
2140
2141 /* Fix up byte swapping */
2142 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
2143 BGE_MODECTL_BYTESWAP_DATA);
2144
2145 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2146
2147 /*
2148 * The 5704 in TBI mode apparently needs some special
2149 * adjustment to insure the SERDES drive level is set
2150 * to 1.2V.
2151 */
2152 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
2153 (sc->bge_flags & BGE_FLAG_TBI)) {
2154 uint32_t serdescfg;
2155
2156 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2157 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2158 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2159 }
2160
2161 /* XXX: Broadcom Linux driver. */
2162 if ((sc->bge_flags & BGE_FLAG_PCIE) &&
2163 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2164 uint32_t v;
2165
2166 v = CSR_READ_4(sc, 0x7c00);
2167 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2168 }
2169
2170 DELAY(10000);
2171 }
2172
2173 /*
2174 * Frame reception handling. This is called if there's a frame
2175 * on the receive return list.
2176 *
2177 * Note: we have to be able to handle two possibilities here:
2178 * 1) the frame is from the jumbo recieve ring
2179 * 2) the frame is from the standard receive ring
2180 */
2181
2182 static void
2183 bge_rxeof(struct bge_softc *sc)
2184 {
2185 struct ifnet *ifp;
2186 int stdcnt = 0, jumbocnt = 0;
2187
2188 if (sc->bge_rx_saved_considx ==
2189 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx)
2190 return;
2191
2192 ifp = &sc->arpcom.ac_if;
2193
2194 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2195 sc->bge_cdata.bge_rx_return_ring_map,
2196 BUS_DMASYNC_POSTREAD);
2197 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2198 sc->bge_cdata.bge_rx_std_ring_map,
2199 BUS_DMASYNC_POSTREAD);
2200 if (BGE_IS_JUMBO_CAPABLE(sc)) {
2201 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2202 sc->bge_cdata.bge_rx_jumbo_ring_map,
2203 BUS_DMASYNC_POSTREAD);
2204 }
2205
2206 while (sc->bge_rx_saved_considx !=
2207 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2208 struct bge_rx_bd *cur_rx;
2209 uint32_t rxidx;
2210 struct mbuf *m = NULL;
2211 uint16_t vlan_tag = 0;
2212 int have_tag = 0;
2213
2214 cur_rx =
2215 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
2216
2217 rxidx = cur_rx->bge_idx;
2218 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
2219 logif(rx_pkt);
2220
2221 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
2222 have_tag = 1;
2223 vlan_tag = cur_rx->bge_vlan_tag;
2224 }
2225
2226 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
2227 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
2228 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
2229 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
2230 jumbocnt++;
2231 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2232 ifp->if_ierrors++;
2233 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2234 continue;
2235 }
2236 if (bge_newbuf_jumbo(sc,
2237 sc->bge_jumbo, NULL) == ENOBUFS) {
2238 ifp->if_ierrors++;
2239 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
2240 continue;
2241 }
2242 } else {
2243 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2244 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2245 sc->bge_cdata.bge_rx_std_dmamap[rxidx],
2246 BUS_DMASYNC_POSTREAD);
2247 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2248 sc->bge_cdata.bge_rx_std_dmamap[rxidx]);
2249 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2250 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2251 stdcnt++;
2252 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2253 ifp->if_ierrors++;
2254 bge_newbuf_std(sc, sc->bge_std, m);
2255 continue;
2256 }
2257 if (bge_newbuf_std(sc, sc->bge_std,
2258 NULL) == ENOBUFS) {
2259 ifp->if_ierrors++;
2260 bge_newbuf_std(sc, sc->bge_std, m);
2261 continue;
2262 }
2263 }
2264
2265 ifp->if_ipackets++;
2266 #ifndef __i386__
2267 /*
2268 * The i386 allows unaligned accesses, but for other
2269 * platforms we must make sure the payload is aligned.
2270 */
2271 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
2272 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2273 cur_rx->bge_len);
2274 m->m_data += ETHER_ALIGN;
2275 }
2276 #endif
2277 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2278 m->m_pkthdr.rcvif = ifp;
2279
2280 if (ifp->if_capenable & IFCAP_RXCSUM) {
2281 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
2282 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2283 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2284 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2285 }
2286 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
2287 m->m_pkthdr.len >= BGE_MIN_FRAME) {
2288 m->m_pkthdr.csum_data =
2289 cur_rx->bge_tcp_udp_csum;
2290 m->m_pkthdr.csum_flags |=
2291 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2292 }
2293 }
2294
2295 /*
2296 * If we received a packet with a vlan tag, pass it
2297 * to vlan_input() instead of ether_input().
2298 */
2299 if (have_tag) {
2300 VLAN_INPUT_TAG(m, vlan_tag);
2301 have_tag = vlan_tag = 0;
2302 } else {
2303 ifp->if_input(ifp, m);
2304 }
2305 }
2306
2307 if (stdcnt > 0) {
2308 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2309 sc->bge_cdata.bge_rx_std_ring_map,
2310 BUS_DMASYNC_PREWRITE);
2311 }
2312
2313 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) {
2314 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2315 sc->bge_cdata.bge_rx_jumbo_ring_map,
2316 BUS_DMASYNC_PREWRITE);
2317 }
2318
2319 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2320 if (stdcnt)
2321 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2322 if (jumbocnt)
2323 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2324 }
2325
2326 static void
2327 bge_txeof(struct bge_softc *sc)
2328 {
2329 struct bge_tx_bd *cur_tx = NULL;
2330 struct ifnet *ifp;
2331
2332 if (sc->bge_tx_saved_considx ==
2333 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx)
2334 return;
2335
2336 ifp = &sc->arpcom.ac_if;
2337
2338 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
2339 sc->bge_cdata.bge_tx_ring_map,
2340 BUS_DMASYNC_POSTREAD);
2341
2342 /*
2343 * Go through our tx ring and free mbufs for those
2344 * frames that have been sent.
2345 */
2346 while (sc->bge_tx_saved_considx !=
2347 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {
2348 uint32_t idx = 0;
2349
2350 idx = sc->bge_tx_saved_considx;
2351 cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
2352 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2353 ifp->if_opackets++;
2354 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2355 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
2356 sc->bge_cdata.bge_tx_dmamap[idx],
2357 BUS_DMASYNC_POSTWRITE);
2358 bus_dmamap_unload(sc->bge_cdata.bge_mtag,
2359 sc->bge_cdata.bge_tx_dmamap[idx]);
2360 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2361 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2362 }
2363 sc->bge_txcnt--;
2364 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2365 logif(tx_pkt);
2366 }
2367
2368 if (cur_tx != NULL &&
2369 (BGE_TX_RING_CNT - sc->bge_txcnt) >=
2370 (BGE_NSEG_RSVD + BGE_NSEG_SPARE))
2371 ifp->if_flags &= ~IFF_OACTIVE;
2372
2373 if (sc->bge_txcnt == 0)
2374 ifp->if_timer = 0;
2375
2376 if (!ifq_is_empty(&ifp->if_snd))
2377 ifp->if_start(ifp);
2378 }
2379
2380 #ifdef DEVICE_POLLING
2381
2382 static void
2383 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2384 {
2385 struct bge_softc *sc = ifp->if_softc;
2386 uint32_t status;
2387
2388 switch(cmd) {
2389 case POLL_REGISTER:
2390 bge_disable_intr(sc);
2391 break;
2392 case POLL_DEREGISTER:
2393 bge_enable_intr(sc);
2394 break;
2395 case POLL_AND_CHECK_STATUS:
2396 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2397 sc->bge_cdata.bge_status_map,
2398 BUS_DMASYNC_POSTREAD);
2399
2400 /*
2401 * Process link state changes.
2402 */
2403 status = CSR_READ_4(sc, BGE_MAC_STS);
2404 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2405 sc->bge_link_evt = 0;
2406 sc->bge_link_upd(sc, status);
2407 }
2408 /* fall through */
2409 case POLL_ONLY:
2410 if (ifp->if_flags & IFF_RUNNING) {
2411 bge_rxeof(sc);
2412 bge_txeof(sc);
2413 }
2414 break;
2415 }
2416 }
2417
2418 #endif
2419
2420 static void
2421 bge_intr(void *xsc)
2422 {
2423 struct bge_softc *sc = xsc;
2424 struct ifnet *ifp = &sc->arpcom.ac_if;
2425 uint32_t status;
2426
2427 logif(intr);
2428
2429 /*
2430 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't
2431 * disable interrupts by writing nonzero like we used to, since with
2432 * our current organization this just gives complications and
2433 * pessimizations for re-enabling interrupts. We used to have races
2434 * instead of the necessary complications. Disabling interrupts
2435 * would just reduce the chance of a status update while we are
2436 * running (by switching to the interrupt-mode coalescence
2437 * parameters), but this chance is already very low so it is more
2438 * efficient to get another interrupt than prevent it.
2439 *
2440 * We do the ack first to ensure another interrupt if there is a
2441 * status update after the ack. We don't check for the status
2442 * changing later because it is more efficient to get another
2443 * interrupt than prevent it, not quite as above (not checking is
2444 * a smaller optimization than not toggling the interrupt enable,
2445 * since checking doesn't involve PCI accesses and toggling require
2446 * the status check). So toggling would probably be a pessimization
2447 * even with MSI. It would only be needed for using a task queue.
2448 */
2449 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2450
2451 bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2452 sc->bge_cdata.bge_status_map,
2453 BUS_DMASYNC_POSTREAD);
2454
2455 /*
2456 * Process link state changes.
2457 */
2458 status = CSR_READ_4(sc, BGE_MAC_STS);
2459 if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
2460 sc->bge_link_evt = 0;
2461 sc->bge_link_upd(sc, status);
2462 }
2463
2464 if (ifp->if_flags & IFF_RUNNING) {
2465 /* Check RX return ring producer/consumer */
2466 bge_rxeof(sc);
2467
2468 /* Check TX ring producer/consumer */
2469 bge_txeof(sc);
2470 }
2471
2472 if (sc->bge_coal_chg)
2473 bge_coal_change(sc);
2474 }
2475
2476 static void
2477 bge_tick(void *xsc)
2478 {
2479 struct bge_softc *sc = xsc;
2480 struct ifnet *ifp = &sc->arpcom.ac_if;
2481
2482 lwkt_serialize_enter(ifp->if_serializer);
2483
2484 if (BGE_IS_5705_PLUS(sc))
2485 bge_stats_update_regs(sc);
2486 else
2487 bge_stats_update(sc);
2488
2489 if (sc->bge_flags & BGE_FLAG_TBI) {
2490 /*
2491 * Since in TBI mode auto-polling can't be used we should poll
2492 * link status manually. Here we register pending link event
2493 * and trigger interrupt.
2494 */
2495 sc->bge_link_evt++;
2496 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
2497 } else if (!sc->bge_link) {
2498 mii_tick(device_get_softc(sc->bge_miibus));
2499 }
2500
2501 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2502
2503 lwkt_serialize_exit(ifp->if_serializer);
2504 }
2505
2506 static void
2507 bge_stats_update_regs(struct bge_softc *sc)
2508 {
2509 struct ifnet *ifp = &sc->arpcom.ac_if;
2510 struct bge_mac_stats_regs stats;
2511 uint32_t *s;
2512 int i;
2513
2514 s = (uint32_t *)&stats;
2515 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2516 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2517 s++;
2518 }
2519
2520 ifp->if_collisions +=
2521 (stats.dot3StatsSingleCollisionFrames +
2522 stats.dot3StatsMultipleCollisionFrames +
2523 stats.dot3StatsExcessiveCollisions +
2524 stats.dot3StatsLateCollisions) -
2525 ifp->if_collisions;
2526 }
2527
2528 static void
2529 bge_stats_update(struct bge_softc *sc)
2530 {
2531 struct ifnet *ifp = &sc->arpcom.ac_if;
2532 bus_size_t stats;
2533
2534 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2535
2536 #define READ_STAT(sc, stats, stat) \
2537 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2538
2539 ifp->if_collisions +=
2540 (READ_STAT(sc, stats,
2541 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2542 READ_STAT(sc, stats,
2543 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2544 READ_STAT(sc, stats,
2545 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2546 READ_STAT(sc, stats,
2547 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2548 ifp->if_collisions;
2549
2550 #undef READ_STAT
2551
2552 #ifdef notdef
2553 ifp->if_collisions +=
2554 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2555 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2556 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2557 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2558 ifp->if_collisions;
2559 #endif
2560 }
2561
2562 /*
2563 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2564 * pointers to descriptors.
2565 */
2566 static int
2567 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2568 {
2569 struct bge_tx_bd *d = NULL;
2570 uint16_t csum_flags = 0;
2571 struct ifvlan *ifv = NULL;
2572 struct bge_dmamap_arg ctx;
2573 bus_dma_segment_t segs[BGE_NSEG_NEW];
2574 bus_dmamap_t map;
2575 int error, maxsegs, idx, i;
2576
2577 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2578 m_head->m_pkthdr.rcvif != NULL &&
2579 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2580 ifv = m_head->m_pkthdr.rcvif->if_softc;
2581
2582 if (m_head->m_pkthdr.csum_flags) {
2583 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2584 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2585 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2586 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2587 if (m_head->m_flags & M_LASTFRAG)
2588 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2589 else if (m_head->m_flags & M_FRAG)
2590 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2591 }
2592
2593 idx = *txidx;
2594 map = sc->bge_cdata.bge_tx_dmamap[idx];
2595
2596 maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - BGE_NSEG_RSVD;
2597 KASSERT(maxsegs >= BGE_NSEG_SPARE,
2598 ("not enough segments %d\n", maxsegs));
2599
2600 if (maxsegs > BGE_NSEG_NEW)
2601 maxsegs = BGE_NSEG_NEW;
2602
2603 /*
2604 * Pad outbound frame to BGE_MIN_FRAME for an unusual reason.
2605 * The bge hardware will pad out Tx runts to BGE_MIN_FRAME,
2606 * but when such padded frames employ the bge IP/TCP checksum
2607 * offload, the hardware checksum assist gives incorrect results
2608 * (possibly from incorporating its own padding into the UDP/TCP
2609 * checksum; who knows). If we pad such runts with zeros, the
2610 * onboard checksum comes out correct. We do this by pretending
2611 * the mbuf chain has too many fragments so the coalescing code
2612 * below can assemble the packet into a single buffer that's
2613 * padded out to the mininum frame size.
2614 */
2615 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2616 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2617 error = EFBIG;
2618 } else {
2619 ctx.bge_segs = segs;
2620 ctx.bge_maxsegs = maxsegs;
2621 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2622 m_head, bge_dma_map_mbuf, &ctx,
2623 BUS_DMA_NOWAIT);
2624 }
2625 if (error == EFBIG || ctx.bge_maxsegs == 0) {
2626 struct mbuf *m_new;
2627
2628 m_new = m_defrag(m_head, MB_DONTWAIT);
2629 if (m_new == NULL) {
2630 if_printf(&sc->arpcom.ac_if,
2631 "could not defrag TX mbuf\n");
2632 error = ENOBUFS;
2633 goto back;
2634 } else {
2635 m_head = m_new;
2636 }
2637
2638 /*
2639 * Manually pad short frames, and zero the pad space
2640 * to avoid leaking data.
2641 */
2642 if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
2643 m_head->m_pkthdr.len < BGE_MIN_FRAME) {
2644 int pad_len = BGE_MIN_FRAME - m_head->m_pkthdr.len;
2645
2646 bzero(mtod(m_head, char *) + m_head->m_pkthdr.len,
2647 pad_len);
2648 m_head->m_pkthdr.len += pad_len;
2649 m_head->m_len = m_head->m_pkthdr.len;
2650 }
2651
2652 ctx.bge_segs = segs;
2653 ctx.bge_maxsegs = maxsegs;
2654 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,
2655 m_head, bge_dma_map_mbuf, &ctx,
2656 BUS_DMA_NOWAIT);
2657 if (error || ctx.bge_maxsegs == 0) {
2658 if_printf(&sc->arpcom.ac_if,
2659 "could not defrag TX mbuf\n");
2660 if (error == 0)
2661 error = EFBIG;
2662 goto back;
2663 }
2664 } else if (error) {
2665 if_printf(&sc->arpcom.ac_if, "could not map TX mbuf\n");
2666 goto back;
2667 }
2668
2669 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE);
2670
2671 for (i = 0; ; i++) {
2672 d = &sc->bge_ldata.bge_tx_ring[idx];
2673
2674 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_segs[i].ds_addr);
2675 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_segs[i].ds_addr);
2676 d->bge_len = segs[i].ds_len;
2677 d->bge_flags = csum_flags;
2678
2679 if (i == ctx.bge_maxsegs - 1)
2680 break;
2681 BGE_INC(idx, BGE_TX_RING_CNT);
2682 }
2683 /* Mark the last segment as end of packet... */
2684 d->bge_flags |= BGE_TXBDFLAG_END;
2685
2686 /* Set vlan tag to the first segment of the packet. */
2687 d = &sc->bge_ldata.bge_tx_ring[*txidx];
2688 if (ifv != NULL) {
2689 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2690 d->bge_vlan_tag = ifv->ifv_tag;
2691 } else {
2692 d->bge_vlan_tag = 0;
2693 }
2694
2695 /*
2696 * Insure that the map for this transmission is placed at
2697 * the array index of the last descriptor in this chain.
2698 */
2699 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
2700 sc->bge_cdata.bge_tx_dmamap[idx] = map;
2701 sc->bge_cdata.bge_tx_chain[idx] = m_head;
2702 sc->bge_txcnt += ctx.bge_maxsegs;
2703
2704 BGE_INC(idx, BGE_TX_RING_CNT);
2705 *txidx = idx;
2706 back:
2707 if (error)
2708 m_freem(m_head);
2709 return error;
2710 }
2711
2712 /*
2713 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2714 * to the mbuf data regions directly in the transmit descriptors.
2715 */
2716 static void
2717 bge_start(struct ifnet *ifp)
2718 {
2719 struct bge_softc *sc = ifp->if_softc;
2720 struct mbuf *m_head = NULL;
2721 uint32_t prodidx;
2722 int need_trans;
2723
2724 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
2725 return;
2726
2727 prodidx = sc->bge_tx_prodidx;
2728
2729 need_trans = 0;
2730 while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2731 m_head = ifq_poll(&ifp->if_snd);
2732 if (m_head == NULL)
2733 break;
2734
2735 /*
2736 * XXX
2737 * The code inside the if() block is never reached since we
2738 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
2739 * requests to checksum TCP/UDP in a fragmented packet.
2740 *
2741 * XXX
2742 * safety overkill. If this is a fragmented packet chain
2743 * with delayed TCP/UDP checksums, then only encapsulate
2744 * it if we have enough descriptors to handle the entire
2745 * chain at once.
2746 * (paranoia -- may not actually be needed)
2747 */
2748 if (m_head->m_flags & M_FIRSTFRAG &&
2749 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2750 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2751 m_head->m_pkthdr.csum_data + 16) {
2752 ifp->if_flags |= IFF_OACTIVE;
2753 break;
2754 }
2755 }
2756
2757 /*
2758 * Sanity check: avoid coming within BGE_NSEG_RSVD
2759 * descriptors of the end of the ring. Also make
2760 * sure there are BGE_NSEG_SPARE descriptors for
2761 * jumbo buffers' defragmentation.
2762 */
2763 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2764 (BGE_NSEG_RSVD + BGE_NSEG_SPARE)) {
2765 ifp->if_flags |= IFF_OACTIVE;
2766 break;
2767 }
2768
2769 /*
2770 * Dequeue the packet before encapsulation, since
2771 * bge_encap() may free the packet if error happens.
2772 */
2773 ifq_dequeue(&ifp->if_snd, m_head);
2774
2775 /*
2776 * Pack the data into the transmit ring. If we
2777 * don't have room, set the OACTIVE flag and wait
2778 * for the NIC to drain the ring.
2779 */
2780 if (bge_encap(sc, m_head, &prodidx)) {
2781 ifp->if_flags |= IFF_OACTIVE;
2782 break;
2783 }
2784 need_trans = 1;
2785
2786 BPF_MTAP(ifp, m_head);
2787 }
2788
2789 if (!need_trans)
2790 return;
2791
2792 /* Transmit */
2793 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2794 /* 5700 b2 errata */
2795 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2796 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2797
2798 sc->bge_tx_prodidx = prodidx;
2799
2800 /*
2801 * Set a timeout in case the chip goes out to lunch.
2802 */
2803 ifp->if_timer = 5;
2804 }
2805
2806 static void
2807 bge_init(void *xsc)
2808 {
2809 struct bge_softc *sc = xsc;
2810 struct ifnet *ifp = &sc->arpcom.ac_if;
2811 uint16_t *m;
2812
2813 ASSERT_SERIALIZED(ifp->if_serializer);
2814
2815 if (ifp->if_flags & IFF_RUNNING)
2816 return;
2817
2818 /* Cancel pending I/O and flush buffers. */
2819 bge_stop(sc);
2820 bge_reset(sc);
2821 bge_chipinit(sc);
2822
2823 /*
2824 * Init the various state machines, ring
2825 * control blocks and firmware.
2826 */
2827 if (bge_blockinit(sc)) {
2828 if_printf(ifp, "initialization failure\n");
2829 return;
2830 }
2831
2832 /* Specify MTU. */
2833 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2834 ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2835
2836 /* Load our MAC address. */
2837 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2838 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2839 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2840
2841 /* Enable or disable promiscuous mode as needed. */
2842 bge_setpromisc(sc);
2843
2844 /* Program multicast filter. */
2845 bge_setmulti(sc);
2846
2847 /* Init RX ring. */
2848 bge_init_rx_ring_std(sc);
2849
2850 /*
2851 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2852 * memory to insure that the chip has in fact read the first
2853 * entry of the ring.
2854 */
2855 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2856 uint32_t v, i;
2857 for (i = 0; i < 10; i++) {
2858 DELAY(20);
2859 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2860 if (v == (MCLBYTES - ETHER_ALIGN))
2861 break;
2862 }
2863 if (i == 10)
2864 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2865 }
2866
2867 /* Init jumbo RX ring. */
2868 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2869 bge_init_rx_ring_jumbo(sc);
2870
2871 /* Init our RX return ring index */
2872 sc->bge_rx_saved_considx = 0;
2873
2874 /* Init TX ring. */
2875 bge_init_tx_ring(sc);
2876
2877 /* Turn on transmitter */
2878 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2879
2880 /* Turn on receiver */
2881 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2882
2883 /* Tell firmware we're alive. */
2884 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2885
2886 /* Enable host interrupts if polling(4) is not enabled. */
2887 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2888 #ifdef DEVICE_POLLING
2889 if (ifp->if_flags & IFF_POLLING)
2890 bge_disable_intr(sc);
2891 else
2892 #endif
2893 bge_enable_intr(sc);
2894
2895 bge_ifmedia_upd(ifp);
2896
2897 ifp->if_flags |= IFF_RUNNING;
2898 ifp->if_flags &= ~IFF_OACTIVE;
2899
2900 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2901 }
2902
2903 /*
2904 * Set media options.
2905 */
2906 static int
2907 bge_ifmedia_upd(struct ifnet *ifp)
2908 {
2909 struct bge_softc *sc = ifp->if_softc;
2910
2911 /* If this is a 1000baseX NIC, enable the TBI port. */
2912 if (sc->bge_flags & BGE_FLAG_TBI) {
2913 struct ifmedia *ifm = &sc->bge_ifmedia;
2914
2915 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2916 return(EINVAL);
2917
2918 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2919 case IFM_AUTO:
2920 /*
2921 * The BCM5704 ASIC appears to have a special
2922 * mechanism for programming the autoneg
2923 * advertisement registers in TBI mode.
2924 */
2925 if (!bge_fake_autoneg &&
2926 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2927 uint32_t sgdig;
2928
2929 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2930 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2931 sgdig |= BGE_SGDIGCFG_AUTO |
2932 BGE_SGDIGCFG_PAUSE_CAP |
2933 BGE_SGDIGCFG_ASYM_PAUSE;
2934 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2935 sgdig | BGE_SGDIGCFG_SEND);
2936 DELAY(5);
2937 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2938 }
2939 break;
2940 case IFM_1000_SX:
2941 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2942 BGE_CLRBIT(sc, BGE_MAC_MODE,
2943 BGE_MACMODE_HALF_DUPLEX);
2944 } else {
2945 BGE_SETBIT(sc, BGE_MAC_MODE,
2946 BGE_MACMODE_HALF_DUPLEX);
2947 }
2948 break;
2949 default:
2950 return(EINVAL);
2951 }
2952 } else {
2953 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2954
2955 sc->bge_link_evt++;
2956 sc->bge_link = 0;
2957 if (mii->mii_instance) {
2958 struct mii_softc *miisc;
2959
2960 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2961 mii_phy_reset(miisc);
2962 }
2963 mii_mediachg(mii);
2964 }
2965 return(0);
2966 }
2967
2968 /*
2969 * Report current media status.
2970 */
2971 static void
2972 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2973 {
2974 struct bge_softc *sc = ifp->if_softc;
2975
2976 if (sc->bge_flags & BGE_FLAG_TBI) {
2977 ifmr->ifm_status = IFM_AVALID;
2978 ifmr->ifm_active = IFM_ETHER;
2979 if (CSR_READ_4(sc, BGE_MAC_STS) &
2980 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2981 ifmr->ifm_status |= IFM_ACTIVE;
2982 } else {
2983 ifmr->ifm_active |= IFM_NONE;
2984 return;
2985 }
2986
2987 ifmr->ifm_active |= IFM_1000_SX;
2988 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2989 ifmr->ifm_active |= IFM_HDX;
2990 else
2991 ifmr->ifm_active |= IFM_FDX;
2992 } else {
2993 struct mii_data *mii = device_get_softc(sc->bge_miibus);
2994
2995 mii_pollstat(mii);
2996 ifmr->ifm_active = mii->mii_media_active;
2997 ifmr->ifm_status = mii->mii_media_status;
2998 }
2999 }
3000
3001 static int
3002 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
3003 {
3004 struct bge_softc *sc = ifp->if_softc;
3005 struct ifreq *ifr = (struct ifreq *)data;
3006 int mask, error = 0;
3007
3008 ASSERT_SERIALIZED(ifp->if_serializer);
3009
3010 switch (command) {
3011 case SIOCSIFMTU:
3012 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
3013 (BGE_IS_JUMBO_CAPABLE(sc) &&
3014 ifr->ifr_mtu > BGE_JUMBO_MTU)) {
3015 error = EINVAL;
3016 } else if (ifp->if_mtu != ifr->ifr_mtu) {
3017 ifp->if_mtu = ifr->ifr_mtu;
3018 ifp->if_flags &= ~IFF_RUNNING;
3019 bge_init(sc);
3020 }
3021 break;
3022 case SIOCSIFFLAGS:
3023 if (ifp->if_flags & IFF_UP) {
3024 if (ifp->if_flags & IFF_RUNNING) {
3025 mask = ifp->if_flags ^ sc->bge_if_flags;
3026
3027 /*
3028 * If only the state of the PROMISC flag
3029 * changed, then just use the 'set promisc
3030 * mode' command instead of reinitializing
3031 * the entire NIC. Doing a full re-init
3032 * means reloading the firmware and waiting
3033 * for it to start up, which may take a
3034 * second or two. Similarly for ALLMULTI.
3035 */
3036 if (mask & IFF_PROMISC)
3037 bge_setpromisc(sc);
3038 if (mask & IFF_ALLMULTI)
3039 bge_setmulti(sc);
3040 } else {
3041 bge_init(sc);
3042 }
3043 } else {
3044 if (ifp->if_flags & IFF_RUNNING)
3045 bge_stop(sc);
3046 }
3047 sc->bge_if_flags = ifp->if_flags;
3048 break;
3049 case SIOCADDMULTI:
3050 case SIOCDELMULTI:
3051 if (ifp->if_flags & IFF_RUNNING)
3052 bge_setmulti(sc);
3053 break;
3054 case SIOCSIFMEDIA:
3055 case SIOCGIFMEDIA:
3056 if (sc->bge_flags & BGE_FLAG_TBI) {
3057 error = ifmedia_ioctl(ifp, ifr,
3058 &sc->bge_ifmedia, command);
3059 } else {
3060 struct mii_data *mii;
3061
3062 mii = device_get_softc(sc->bge_miibus);
3063 error = ifmedia_ioctl(ifp, ifr,
3064 &mii->mii_media, command);
3065 }
3066 break;
3067 case SIOCSIFCAP:
3068 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3069 if (mask & IFCAP_HWCSUM) {
3070 ifp->if_capenable ^= IFCAP_HWCSUM;
3071 if (IFCAP_HWCSUM & ifp->if_capenable)
3072 ifp->if_hwassist = BGE_CSUM_FEATURES;
3073 else
3074 ifp->if_hwassist = 0;
3075 }
3076 break;
3077 default:
3078 error = ether_ioctl(ifp, command, data);
3079 break;
3080 }
3081 return error;
3082 }
3083
3084 static void
3085 bge_watchdog(struct ifnet *ifp)
3086 {
3087 struct bge_softc *sc = ifp->if_softc;
3088
3089 if_printf(ifp, "watchdog timeout -- resetting\n");
3090
3091 ifp->if_flags &= ~IFF_RUNNING;
3092 bge_init(sc);
3093
3094 ifp->if_oerrors++;
3095
3096 if (!ifq_is_empty(&ifp->if_snd))
3097 ifp->if_start(ifp);
3098 }
3099
3100 /*
3101 * Stop the adapter and free any mbufs allocated to the
3102 * RX and TX lists.
3103 */
3104 static void
3105 bge_stop(struct bge_softc *sc)
3106 {
3107 struct ifnet *ifp = &sc->arpcom.ac_if;
3108 struct ifmedia_entry *ifm;
3109 struct mii_data *mii = NULL;
3110 int mtmp, itmp;
3111
3112 ASSERT_SERIALIZED(ifp->if_serializer);
3113
3114 if ((sc->bge_flags & BGE_FLAG_TBI) == 0)
3115 mii = device_get_softc(sc->bge_miibus);
3116
3117 callout_stop(&sc->bge_stat_timer);
3118
3119 /*
3120 * Disable all of the receiver blocks
3121 */
3122 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3123 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3124 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3125 if (!BGE_IS_5705_PLUS(sc))
3126 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3127 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3128 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3129 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3130
3131 /*
3132 * Disable all of the transmit blocks
3133 */
3134 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3135 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3136 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3137 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3138 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3139 if (!BGE_IS_5705_PLUS(sc))
3140 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3141 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3142
3143 /*
3144 * Shut down all of the memory managers and related
3145 * state machines.
3146 */
3147 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3148 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3149 if (!BGE_IS_5705_PLUS(sc))
3150 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3151 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3152 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3153 if (!BGE_IS_5705_PLUS(sc)) {
3154 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3155 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3156 }
3157
3158 /* Disable host interrupts. */
3159 bge_disable_intr(sc);
3160
3161 /*
3162 * Tell firmware we're shutting down.
3163 */
3164 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3165
3166 /* Free the RX lists. */
3167 bge_free_rx_ring_std(sc);
3168
3169 /* Free jumbo RX list. */
3170 if (BGE_IS_JUMBO_CAPABLE(sc))
3171 bge_free_rx_ring_jumbo(sc);
3172
3173 /* Free TX buffers. */
3174 bge_free_tx_ring(sc);
3175
3176 /*
3177 * Isolate/power down the PHY, but leave the media selection
3178 * unchanged so that things will be put back to normal when
3179 * we bring the interface back up.
3180 */
3181 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
3182 itmp = ifp->if_flags;
3183 ifp->if_flags |= IFF_UP;
3184 ifm = mii->mii_media.ifm_cur;
3185 mtmp = ifm->ifm_media;
3186 ifm->ifm_media = IFM_ETHER|IFM_NONE;
3187 mii_mediachg(mii);
3188 ifm->ifm_media = mtmp;
3189 ifp->if_flags = itmp;
3190 }
3191
3192 sc->bge_link = 0;
3193 sc->bge_coal_chg = 0;
3194
3195 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
3196
3197 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3198 ifp->if_timer = 0;
3199 }
3200
3201 /*
3202 * Stop all chip I/O so that the kernel's probe routines don't
3203 * get confused by errant DMAs when rebooting.
3204 */
3205 static void
3206 bge_shutdown(device_t dev)
3207 {
3208 struct bge_softc *sc = device_get_softc(dev);
3209 struct ifnet *ifp = &sc->arpcom.ac_if;
3210
3211 lwkt_serialize_enter(ifp->if_serializer);
3212 bge_stop(sc);
3213 bge_reset(sc);
3214 lwkt_serialize_exit(ifp->if_serializer);
3215 }
3216
3217 static int
3218 bge_suspend(device_t dev)
3219 {
3220 struct bge_softc *sc = device_get_softc(dev);
3221 struct ifnet *ifp = &sc->arpcom.ac_if;
3222
3223 lwkt_serialize_enter(ifp->if_serializer);
3224 bge_stop(sc);
3225 lwkt_serialize_exit(ifp->if_serializer);
3226
3227 return 0;
3228 }
3229
3230 static int
3231 bge_resume(device_t dev)
3232 {
3233 struct bge_softc *sc = device_get_softc(dev);
3234 struct ifnet *ifp = &sc->arpcom.ac_if;
3235
3236 lwkt_serialize_enter(ifp->if_serializer);
3237
3238 if (ifp->if_flags & IFF_UP) {
3239 bge_init(sc);
3240
3241 if (!ifq_is_empty(&ifp->if_snd))
3242 ifp->if_start(ifp);
3243 }
3244
3245 lwkt_serialize_exit(ifp->if_serializer);
3246
3247 return 0;
3248 }
3249
3250 static void
3251 bge_setpromisc(struct bge_softc *sc)
3252 {
3253 struct ifnet *ifp = &sc->arpcom.ac_if;
3254
3255 if (ifp->if_flags & IFF_PROMISC)
3256 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3257 else
3258 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
3259 }
3260
3261 static void
3262 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3263 {
3264 struct bge_dmamap_arg *ctx = arg;
3265
3266 if (error)
3267 return;
3268
3269 KASSERT(nsegs == 1 && ctx->bge_maxsegs == 1,
3270 ("only one segment is allowed\n"));
3271
3272 ctx->bge_segs[0] = *segs;
3273 }
3274
3275 static void
3276 bge_dma_map_mbuf(void *arg, bus_dma_segment_t *segs, int nsegs,
3277 bus_size_t mapsz __unused, int error)
3278 {
3279 struct bge_dmamap_arg *ctx = arg;
3280 int i;
3281
3282 if (error)
3283 return;
3284
3285 if (nsegs > ctx->bge_maxsegs) {
3286 ctx->bge_maxsegs = 0;
3287 return;
3288 }
3289
3290 ctx->bge_maxsegs = nsegs;
3291 for (i = 0; i < nsegs; ++i)
3292 ctx->bge_segs[i] = segs[i];
3293 }
3294
3295 static void
3296 bge_dma_free(struct bge_softc *sc)
3297 {
3298 int i;
3299
3300 /* Destroy RX/TX mbuf DMA stuffs. */
3301 if (sc->bge_cdata.bge_mtag != NULL) {
3302 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3303 if (sc->bge_cdata.bge_rx_std_dmamap[i]) {
3304 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3305 sc->bge_cdata.bge_rx_std_dmamap[i]);
3306 }
3307 }
3308
3309 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3310 if (sc->bge_cdata.bge_tx_dmamap[i]) {
3311 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3312 sc->bge_cdata.bge_tx_dmamap[i]);
3313 }
3314 }
3315 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3316 }
3317
3318 /* Destroy standard RX ring */
3319 bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
3320 sc->bge_cdata.bge_rx_std_ring_map,
3321 sc->bge_ldata.bge_rx_std_ring);
3322
3323 if (BGE_IS_JUMBO_CAPABLE(sc))
3324 bge_free_jumbo_mem(sc);
3325
3326 /* Destroy RX return ring */
3327 bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
3328 sc->bge_cdata.bge_rx_return_ring_map,
3329 sc->bge_ldata.bge_rx_return_ring);
3330
3331 /* Destroy TX ring */
3332 bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
3333 sc->bge_cdata.bge_tx_ring_map,
3334 sc->bge_ldata.bge_tx_ring);
3335
3336 /* Destroy status block */
3337 bge_dma_block_free(sc->bge_cdata.bge_status_tag,
3338 sc->bge_cdata.bge_status_map,
3339 sc->bge_ldata.bge_status_block);
3340
3341 /* Destroy statistics block */
3342 bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
3343 sc->bge_cdata.bge_stats_map,
3344 sc->bge_ldata.bge_stats);
3345
3346 /* Destroy the parent tag */
3347 if (sc->bge_cdata.bge_parent_tag != NULL)
3348 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
3349 }
3350
3351 static int
3352 bge_dma_alloc(struct bge_softc *sc)
3353 {
3354 struct ifnet *ifp = &sc->arpcom.ac_if;
3355 int nseg, i, error;
3356
3357 /*
3358 * Allocate the parent bus DMA tag appropriate for PCI.
3359 */
3360 error = bus_dma_tag_create(NULL, 1, 0,
3361 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3362 NULL, NULL,
3363 MAXBSIZE, BGE_NSEG_NEW,
3364 BUS_SPACE_MAXSIZE_32BIT,
3365 0, &sc->bge_cdata.bge_parent_tag);
3366 if (error) {
3367 if_printf(ifp, "could not allocate parent dma tag\n");
3368 return error;
3369 }
3370
3371 /*
3372 * Create DMA tag for mbufs.
3373 */
3374 nseg = BGE_NSEG_NEW;
3375 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
3376 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3377 NULL, NULL,
3378 MCLBYTES * nseg, nseg, MCLBYTES,
3379 BUS_DMA_ALLOCNOW, &sc->bge_cdata.bge_mtag);
3380 if (error) {
3381 if_printf(ifp, "could not allocate mbuf dma tag\n");
3382 return error;
3383 }
3384
3385 /*
3386 * Create DMA maps for TX/RX mbufs.
3387 */
3388 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3389 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3390 &sc->bge_cdata.bge_rx_std_dmamap[i]);
3391 if (error) {
3392 int j;
3393
3394 for (j = 0; j < i; ++j) {
3395 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3396 sc->bge_cdata.bge_rx_std_dmamap[j]);
3397 }
3398 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3399 sc->bge_cdata.bge_mtag = NULL;
3400
3401 if_printf(ifp, "could not create DMA map for RX\n");
3402 return error;
3403 }
3404 }
3405
3406 for (i = 0; i < BGE_TX_RING_CNT; i++) {
3407 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,
3408 &sc->bge_cdata.bge_tx_dmamap[i]);
3409 if (error) {
3410 int j;
3411
3412 for (j = 0; j < BGE_STD_RX_RING_CNT; ++j) {
3413 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3414 sc->bge_cdata.bge_rx_std_dmamap[j]);
3415 }
3416 for (j = 0; j < i; ++j) {
3417 bus_dmamap_destroy(sc->bge_cdata.bge_mtag,
3418 sc->bge_cdata.bge_tx_dmamap[j]);
3419 }
3420 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);
3421 sc->bge_cdata.bge_mtag = NULL;
3422
3423 if_printf(ifp, "could not create DMA map for TX\n");
3424 return error;
3425 }
3426 }
3427
3428 /*
3429 * Create DMA stuffs for standard RX ring.
3430 */
3431 error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
3432 &sc->bge_cdata.bge_rx_std_ring_tag,
3433 &sc->bge_cdata.bge_rx_std_ring_map,
3434 (void **)&sc->bge_ldata.bge_rx_std_ring,
3435 &sc->bge_ldata.bge_rx_std_ring_paddr);
3436 if (error) {
3437 if_printf(ifp, "could not create std RX ring\n");
3438 return error;
3439 }
3440
3441 /*
3442 * Create jumbo buffer pool.
3443 */
3444 if (BGE_IS_JUMBO_CAPABLE(sc)) {
3445 error = bge_alloc_jumbo_mem(sc);
3446 if (error) {
3447 if_printf(ifp, "could not create jumbo buffer pool\n");
3448 return error;
3449 }
3450 }
3451
3452 /*
3453 * Create DMA stuffs for RX return ring.
3454 */
3455 error = bge_dma_block_alloc(sc, BGE_RX_RTN_RING_SZ(sc),
3456 &sc->bge_cdata.bge_rx_return_ring_tag,
3457 &sc->bge_cdata.bge_rx_return_ring_map,
3458 (void **)&sc->bge_ldata.bge_rx_return_ring,
3459 &sc->bge_ldata.bge_rx_return_ring_paddr);
3460 if (error) {
3461 if_printf(ifp, "could not create RX ret ring\n");
3462 return error;
3463 }
3464
3465 /*
3466 * Create DMA stuffs for TX ring.
3467 */
3468 error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
3469 &sc->bge_cdata.bge_tx_ring_tag,
3470 &sc->bge_cdata.bge_tx_ring_map,
3471 (void **)&sc->bge_ldata.bge_tx_ring,
3472 &sc->bge_ldata.bge_tx_ring_paddr);
3473 if (error) {
3474 if_printf(ifp, "could not create TX ring\n");
3475 return error;
3476 }
3477
3478 /*
3479 * Create DMA stuffs for status block.
3480 */
3481 error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
3482 &sc->bge_cdata.bge_status_tag,
3483 &sc->bge_cdata.bge_status_map,
3484 (void **)&sc->bge_ldata.bge_status_block,
3485 &sc->bge_ldata.bge_status_block_paddr);
3486 if (error) {
3487 if_printf(ifp, "could not create status block\n");
3488 return error;
3489 }
3490
3491 /*
3492 * Create DMA stuffs for statistics block.
3493 */
3494 error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
3495 &sc->bge_cdata.bge_stats_tag,
3496 &sc->bge_cdata.bge_stats_map,
3497 (void **)&sc->bge_ldata.bge_stats,
3498 &sc->bge_ldata.bge_stats_paddr);
3499 if (error) {
3500 if_printf(ifp, "could not create stats block\n");
3501 return error;
3502 }
3503 return 0;
3504 }
3505
3506 static int
3507 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
3508 bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
3509 {
3510 struct ifnet *ifp = &sc->arpcom.ac_if;
3511 struct bge_dmamap_arg ctx;
3512 bus_dma_segment_t seg;
3513 int error;
3514
3515 /*
3516 * Create DMA tag
3517 */
3518 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
3519 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3520 NULL, NULL, size, 1, size, 0, tag);
3521 if (error) {
3522 if_printf(ifp, "could not allocate dma tag\n");
3523 return error;
3524 }
3525
3526 /*
3527 * Allocate DMA'able memory
3528 */
3529 error = bus_dmamem_alloc(*tag, addr, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3530 map);
3531 if (error) {
3532 if_printf(ifp, "could not allocate dma memory\n");
3533 bus_dma_tag_destroy(*tag);
3534 *tag = NULL;
3535 return error;
3536 }
3537
3538 /*
3539 * Load the DMA'able memory
3540 */
3541 ctx.bge_maxsegs = 1;
3542 ctx.bge_segs = &seg;
3543 error = bus_dmamap_load(*tag, *map, *addr, size, bge_dma_map_addr, &ctx,
3544 BUS_DMA_WAITOK);
3545 if (error) {
3546 if_printf(ifp, "could not load dma memory\n");
3547 bus_dmamem_free(*tag, *addr, *map);
3548 bus_dma_tag_destroy(*tag);
3549 *tag = NULL;
3550 return error;
3551 }
3552 *paddr = ctx.bge_segs[0].ds_addr;
3553
3554 return 0;
3555 }
3556
3557 static void
3558 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
3559 {
3560 if (tag != NULL) {
3561 bus_dmamap_unload(tag, map);
3562 bus_dmamem_free(tag, addr, map);
3563 bus_dma_tag_destroy(tag);
3564 }
3565 }
3566
3567 /*
3568 * Grrr. The link status word in the status block does
3569 * not work correctly on the BCM5700 rev AX and BX chips,
3570 * according to all available information. Hence, we have
3571 * to enable MII interrupts in order to properly obtain
3572 * async link changes. Unfortunately, this also means that
3573 * we have to read the MAC status register to detect link
3574 * changes, thereby adding an additional register access to
3575 * the interrupt handler.
3576 *
3577 * XXX: perhaps link state detection procedure used for
3578 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
3579 */
3580 static void
3581 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
3582 {
3583 struct ifnet *ifp = &sc->arpcom.ac_if;
3584 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3585
3586 mii_pollstat(mii);
3587
3588 if (!sc->bge_link &&
3589 (mii->mii_media_status & IFM_ACTIVE) &&
3590 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3591 sc->bge_link++;
3592 if (bootverbose)
3593 if_printf(ifp, "link UP\n");
3594 } else if (sc->bge_link &&
3595 (!(mii->mii_media_status & IFM_ACTIVE) ||
3596 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3597 sc->bge_link = 0;
3598 if (bootverbose)
3599 if_printf(ifp, "link DOWN\n");
3600 }
3601
3602 /* Clear the interrupt. */
3603 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
3604 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
3605 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
3606 }
3607
3608 static void
3609 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
3610 {
3611 struct ifnet *ifp = &sc->arpcom.ac_if;
3612
3613 #define PCS_ENCODE_ERR (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
3614
3615 /*
3616 * Sometimes PCS encoding errors are detected in
3617 * TBI mode (on fiber NICs), and for some reason
3618 * the chip will signal them as link changes.
3619 * If we get a link change event, but the 'PCS
3620 * encoding error' bit in the MAC status register
3621 * is set, don't bother doing a link check.
3622 * This avoids spurious "gigabit link up" messages
3623 * that sometimes appear on fiber NICs during
3624 * periods of heavy traffic.
3625 */
3626 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
3627 if (!sc->bge_link) {
3628 sc->bge_link++;
3629 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
3630 BGE_CLRBIT(sc, BGE_MAC_MODE,
3631 BGE_MACMODE_TBI_SEND_CFGS);
3632 }
3633 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
3634
3635 if (bootverbose)
3636 if_printf(ifp, "link UP\n");
3637
3638 ifp->if_link_state = LINK_STATE_UP;
3639 if_link_state_change(ifp);
3640 }
3641 } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
3642 if (sc->bge_link) {
3643 sc->bge_link = 0;
3644
3645 if (bootverbose)
3646 if_printf(ifp, "link DOWN\n");
3647
3648 ifp->if_link_state = LINK_STATE_DOWN;
3649 if_link_state_change(ifp);
3650 }
3651 }
3652
3653 #undef PCS_ENCODE_ERR
3654
3655 /* Clear the attention. */
3656 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3657 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3658 BGE_MACSTAT_LINK_CHANGED);
3659 }
3660
3661 static void
3662 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
3663 {
3664 /*
3665 * Check that the AUTOPOLL bit is set before
3666 * processing the event as a real link change.
3667 * Turning AUTOPOLL on and off in the MII read/write
3668 * functions will often trigger a link status
3669 * interrupt for no reason.
3670 */
3671 if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) {
3672 struct ifnet *ifp = &sc->arpcom.ac_if;
3673 struct mii_data *mii = device_get_softc(sc->bge_miibus);
3674
3675 mii_pollstat(mii);
3676
3677 if (!sc->bge_link &&
3678 (mii->mii_media_status & IFM_ACTIVE) &&
3679 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
3680 sc->bge_link++;
3681 if (bootverbose)
3682 if_printf(ifp, "link UP\n");
3683 } else if (sc->bge_link &&
3684 (!(mii->mii_media_status & IFM_ACTIVE) ||
3685 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
3686 sc->bge_link = 0;
3687 if (bootverbose)
3688 if_printf(ifp, "link DOWN\n");
3689 }
3690 }
3691
3692 /* Clear the attention. */
3693 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
3694 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
3695 BGE_MACSTAT_LINK_CHANGED);
3696 }
3697
3698 static int
3699 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
3700 {
3701 struct bge_softc *sc = arg1;
3702
3703 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3704 &sc->bge_rx_coal_ticks,
3705 BGE_RX_COAL_TICKS_CHG);
3706 }
3707
3708 static int
3709 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
3710 {
3711 struct bge_softc *sc = arg1;
3712
3713 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3714 &sc->bge_tx_coal_ticks,
3715 BGE_TX_COAL_TICKS_CHG);
3716 }
3717
3718 static int
3719 bge_sysctl_rx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3720 {
3721 struct bge_softc *sc = arg1;
3722
3723 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3724 &sc->bge_rx_max_coal_bds,
3725 BGE_RX_MAX_COAL_BDS_CHG);
3726 }
3727
3728 static int
3729 bge_sysctl_tx_max_coal_bds(SYSCTL_HANDLER_ARGS)
3730 {
3731 struct bge_softc *sc = arg1;
3732
3733 return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
3734 &sc->bge_tx_max_coal_bds,
3735 BGE_TX_MAX_COAL_BDS_CHG);
3736 }
3737
3738 static int
3739 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
3740 uint32_t coal_chg_mask)
3741 {
3742 struct bge_softc *sc = arg1;
3743 struct ifnet *ifp = &sc->arpcom.ac_if;
3744 int error = 0, v;
3745
3746 lwkt_serialize_enter(ifp->if_serializer);
3747
3748 v = *coal;
3749 error = sysctl_handle_int(oidp, &v, 0, req);
3750 if (!error && req->newptr != NULL) {
3751 if (v < 0) {
3752 error = EINVAL;
3753 } else {
3754 *coal = v;
3755 sc->bge_coal_chg |= coal_chg_mask;
3756 }
3757 }
3758
3759 lwkt_serialize_exit(ifp->if_serializer);
3760 return error;
3761 }
3762
3763 static void
3764 bge_coal_change(struct bge_softc *sc)
3765 {
3766 struct ifnet *ifp = &sc->arpcom.ac_if;
3767 uint32_t val;
3768
3769 ASSERT_SERIALIZED(ifp->if_serializer);
3770
3771 if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
3772 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
3773 sc->bge_rx_coal_ticks);
3774 DELAY(10);
3775 val = CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
3776
3777 if (bootverbose) {
3778 if_printf(ifp, "rx_coal_ticks -> %u\n",
3779 sc->bge_rx_coal_ticks);
3780 }
3781 }
3782
3783 if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
3784 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
3785 sc->bge_tx_coal_ticks);
3786 DELAY(10);
3787 val = CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
3788
3789 if (bootverbose) {
3790 if_printf(ifp, "tx_coal_ticks -> %u\n",
3791 sc->bge_tx_coal_ticks);
3792 }
3793 }
3794
3795 if (sc->bge_coal_chg & BGE_RX_MAX_COAL_BDS_CHG) {
3796 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
3797 sc->bge_rx_max_coal_bds);
3798 DELAY(10);
3799 val = CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
3800
3801 if (bootverbose) {
3802 if_printf(ifp, "rx_max_coal_bds -> %u\n",
3803 sc->bge_rx_max_coal_bds);
3804 }
3805 }
3806
3807 if (sc->bge_coal_chg & BGE_TX_MAX_COAL_BDS_CHG) {
3808 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
3809 sc->bge_tx_max_coal_bds);
3810 DELAY(10);
3811 val = CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
3812
3813 if (bootverbose) {
3814 if_printf(ifp, "tx_max_coal_bds -> %u\n",
3815 sc->bge_tx_max_coal_bds);
3816 }
3817 }
3818
3819 sc->bge_coal_chg = 0;
3820 }
3821
3822 static void
3823 bge_enable_intr(struct bge_softc *sc)
3824 {
3825 struct ifnet *ifp = &sc->arpcom.ac_if;
3826
3827 lwkt_serialize_handler_enable(ifp->if_serializer);
3828
3829 /*
3830 * Enable interrupt.
3831 */
3832 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
3833
3834 /*
3835 * Unmask the interrupt when we stop polling.
3836 */
3837 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3838
3839 /*
3840 * Trigger another interrupt, since above writing
3841 * to interrupt mailbox0 may acknowledge pending
3842 * interrupt.
3843 */
3844 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
3845 }
3846
3847 static void
3848 bge_disable_intr(struct bge_softc *sc)
3849 {
3850 struct ifnet *ifp = &sc->arpcom.ac_if;
3851
3852 /*
3853 * Mask the interrupt when we start polling.
3854 */
3855 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3856
3857 /*
3858 * Acknowledge possible asserted interrupt.
3859 */
3860 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3861
3862 lwkt_serialize_handler_disable(ifp->if_serializer);
3863 }
DragonFly vkernel multiprocessor port