2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.5 2007/09/16 08:25:41 sephe Exp $
40 #define BWI_ALIGN 0x1000
41 #define BWI_RING_ALIGN BWI_ALIGN
42 #define BWI_BUS_SPACE_MAXADDR 0x3fffffff
44 #define BWI_TX_NRING 6
45 #define BWI_TXRX_NRING 6
46 #define BWI_TX_NDESC 128
47 #define BWI_RX_NDESC 64
48 #define BWI_TXSTATS_NDESC 64
49 #define BWI_TX_NSPRDESC 2
50 #define BWI_TX_DATA_RING 1
52 /* XXX Onoe/Sample/AMRR probably need different configuration */
55 #define BWI_SHRETRY_FB 3
56 #define BWI_LGRETRY_FB 2
58 #define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */
59 #define BWI_FRAME_MIN_LEN(hdr) \
60 ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
62 #define CSR_READ_4(sc, reg) \
63 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
64 #define CSR_READ_2(sc, reg) \
65 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
67 #define CSR_WRITE_4(sc, reg, val) \
68 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
69 #define CSR_WRITE_2(sc, reg, val) \
70 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
72 #define CSR_SETBITS_4(sc, reg, bits) \
73 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
74 #define CSR_SETBITS_2(sc, reg, bits) \
75 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
77 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
78 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
79 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
80 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
82 #define CSR_CLRBITS_4(sc, reg, bits) \
83 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
84 #define CSR_CLRBITS_2(sc, reg, bits) \
85 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
89 #define DPRINTF(sc, fmt, ...) if_printf(&sc->sc_ic.ic_if, fmt, __VA_ARGS__)
91 #define DPRINTF(sc, fmt, ...) ((void)0)
97 uint32_t addr
; /* BWI_DESC32_A_ */
100 #define BWI_DESC32_A_FUNC_TXRX 0x1
101 #define BWI_DESC32_A_FUNC_MASK __BITS(31, 30)
102 #define BWI_DESC32_A_ADDR_MASK __BITS(29, 0)
104 #define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0)
105 #define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16)
106 #define BWI_DESC32_C_EOR __BIT(28)
107 #define BWI_DESC32_C_INTR __BIT(29)
108 #define BWI_DESC32_C_FRAME_END __BIT(30)
109 #define BWI_DESC32_C_FRAME_START __BIT(31)
119 struct bwi_rxbuf_hdr
{
121 uint16_t rxh_buflen
; /* exclude bwi_rxbuf_hdr */
123 uint16_t rxh_flags1
; /* BWI_RXH_F1_ */
126 uint16_t rxh_phyinfo
; /* BWI_RXH_PHYINFO_ */
127 uint16_t rxh_flags3
; /* BWI_RXH_F3_ */
128 uint16_t rxh_flags2
; /* BWI_RXH_F2_ */
130 uint8_t rxh_pad3
[14]; /* Padded to 30bytes */
133 #define BWI_RXH_F1_BCM2053_RSSI __BIT(14)
134 #define BWI_RXH_F1_SHPREAMBLE __BIT(7)
135 #define BWI_RXH_F1_OFDM __BIT(0)
137 #define BWI_RXH_F2_TYPE2FRAME __BIT(2)
139 #define BWI_RXH_F3_BCM2050_RSSI __BIT(10)
141 #define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
143 struct bwi_txbuf_hdr
{
145 uint32_t txh_mac_ctrl
; /* BWI_TXH_MAC_C_ */
147 uint16_t txh_unknown1
;
148 uint16_t txh_phy_ctrl
; /* BWI_TXH_PHY_C_ */
150 uint8_t txh_addr1
[IEEE80211_ADDR_LEN
];
151 uint16_t txh_unknown2
;
152 uint8_t txh_rts_fb_plcp
[4];
153 uint16_t txh_rts_fb_duration
;
154 uint8_t txh_fb_plcp
[4];
155 uint16_t txh_fb_duration
;
157 uint16_t txh_id
; /* BWI_TXH_ID_ */
158 uint16_t txh_unknown3
;
159 uint8_t txh_rts_plcp
[6];
160 uint8_t txh_rts_fc
[2];
161 uint16_t txh_rts_duration
;
162 uint8_t txh_rts_ra
[IEEE80211_ADDR_LEN
];
163 uint8_t txh_rts_ta
[IEEE80211_ADDR_LEN
];
168 #define BWI_TXH_ID_RING_MASK __BITS(15, 13)
169 #define BWI_TXH_ID_IDX_MASK __BITS(12, 0)
171 #define BWI_TXH_PHY_C_OFDM __BIT(0)
172 #define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4)
173 #define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8)
175 #define BWI_TXH_MAC_C_ACK __BIT(0)
176 #define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3)
177 #define BWI_TXH_MAC_C_HWSEQ __BIT(4)
178 #define BWI_TXH_MAC_C_FB_OFDM __BIT(8)
184 uint8_t txs_flags
; /* BWI_TXS_F_ */
185 uint8_t txs_txcnt
; /* BWI_TXS_TXCNT_ */
188 uint16_t txs_unknown
;
189 uint8_t txs_pad3
[2]; /* Padded to 16bytes */
192 #define BWI_TXS_TXCNT_DATA __BITS(7, 4)
194 #define BWI_TXS_F_ACKED __BIT(0)
195 #define BWI_TXS_F_PENDING __BIT(5)
197 struct bwi_ring_data
{
198 uint32_t rdata_txrx_ctrl
;
199 bus_dmamap_t rdata_dmap
;
200 bus_addr_t rdata_paddr
;
205 struct mbuf
*tb_mbuf
;
206 bus_dmamap_t tb_dmap
;
208 struct ieee80211_node
*tb_ni
;
212 struct bwi_txbuf_data
{
213 struct bwi_txbuf tbd_buf
[BWI_TX_NDESC
];
219 struct mbuf
*rb_mbuf
;
221 bus_dmamap_t rb_dmap
;
224 struct bwi_rxbuf_data
{
225 struct bwi_rxbuf rbd_buf
[BWI_RX_NDESC
];
226 bus_dmamap_t rbd_tmp_dmap
;
230 struct bwi_txstats_data
{
231 bus_dma_tag_t stats_ring_dtag
;
232 bus_dmamap_t stats_ring_dmap
;
233 bus_addr_t stats_ring_paddr
;
236 bus_dma_tag_t stats_dtag
;
237 bus_dmamap_t stats_dmap
;
238 bus_addr_t stats_paddr
;
239 struct bwi_txstats
*stats
;
241 uint32_t stats_ctrl_base
;
247 uint8_t fw_type
; /* BWI_FW_T_ */
248 uint8_t fw_gen
; /* BWI_FW_GEN */
251 #define fw_iv_cnt fw_size
254 #define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr)
256 #define BWI_FW_T_UCODE 'u'
257 #define BWI_FW_T_PCM 'p'
258 #define BWI_FW_T_IV 'i'
260 #define BWI_FW_GEN_1 1
262 #define BWI_FW_VERSION3 3
263 #define BWI_FW_VERSION4 4
264 #define BWI_FW_VERSION3_REVMAX 0x128
266 #define BWI_FW_PATH "bwi/v%d/"
267 #define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d.fw"
268 #define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d.fw"
269 #define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d.fw"
270 #define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d.fw"
281 #define BWI_FW_IV_OFS_MASK __BITS(14, 0)
282 #define BWI_FW_IV_IS_32BIT __BIT(15)
284 enum bwi_clock_mode
{
291 uint32_t rw_flags
; /* BWI_REGWIN_F_ */
292 uint16_t rw_type
; /* BWI_REGWIN_T_ */
297 #define BWI_REGWIN_F_EXIST 0x1
299 #define BWI_CREATE_REGWIN(rw, id, type, rev) \
301 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \
302 (rw)->rw_type = (type); \
303 (rw)->rw_id = (id); \
304 (rw)->rw_rev = (rev); \
307 #define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
308 #define BWI_GPIO_REGWIN(sc) \
309 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
310 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
315 enum ieee80211_phymode phy_mode
;
319 uint32_t phy_flags
; /* BWI_PHY_F_ */
320 uint16_t phy_tbl_ctrl
;
321 uint16_t phy_tbl_data_lo
;
322 uint16_t phy_tbl_data_hi
;
324 void (*phy_init
)(struct bwi_mac
*);
327 #define BWI_PHY_F_CALIBRATED 0x1
328 #define BWI_PHY_F_LINKED 0x2
329 #define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED)
331 /* TX power control */
333 uint16_t bbp_atten
; /* BBP attenuation: 4bits */
334 uint16_t rf_atten
; /* RF attenuation */
335 uint16_t tp_ctrl1
; /* ??: 3bits */
336 uint16_t tp_ctrl2
; /* ??: 4bits */
339 #define BWI_RF_ATTEN_FACTOR 4
340 #define BWI_RF_ATTEN_MAX0 9
341 #define BWI_RF_ATTEN_MAX1 31
342 #define BWI_BBP_ATTEN_MAX 11
343 #define BWI_TPCTL1_MAX 7
351 uint16_t rf_type
; /* BWI_RF_T_ */
355 uint32_t rf_flags
; /* BWI_RF_F_ */
357 #define BWI_RFLO_MAX 56
358 struct bwi_rf_lo rf_lo
[BWI_RFLO_MAX
];
359 uint8_t rf_lo_used
[8];
361 #define BWI_INVALID_NRSSI -1000
362 int16_t rf_nrssi
[2]; /* Narrow RSSI */
363 int32_t rf_nrssi_slope
;
365 #define BWI_NRSSI_TBLSZ 64
366 int8_t rf_nrssi_table
[BWI_NRSSI_TBLSZ
];
368 uint16_t rf_lo_gain
; /* loopback gain */
369 uint16_t rf_rx_gain
; /* TRSW RX gain */
371 uint16_t rf_calib
; /* RF calibration value */
372 u_int rf_curchan
; /* current channel */
376 void (*rf_off
)(struct bwi_mac
*);
377 void (*rf_on
)(struct bwi_mac
*);
379 void (*rf_set_nrssi_thr
)(struct bwi_mac
*);
380 void (*rf_calc_nrssi_slope
)(struct bwi_mac
*);
383 const struct bwi_rxbuf_hdr
*);
385 #define BWI_TSSI_MAX 64
386 int8_t rf_txpower_map0
[BWI_TSSI_MAX
];
387 /* Indexed by TSSI */
390 int8_t rf_txpower_map
[BWI_TSSI_MAX
];
395 int rf_txpower_max
; /* dBm */
397 int rf_ant_mode
; /* BWI_ANT_MODE_ */
400 #define BWI_RF_F_INITED 0x1
401 #define BWI_RF_F_ON 0x2
402 #define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED)
404 #define BWI_ANT_MODE_0 0
405 #define BWI_ANT_MODE_1 1
406 #define BWI_ANT_MODE_UNKN 2
407 #define BWI_ANT_MODE_AUTO 3
413 struct bwi_regwin mac_regwin
; /* MUST be first field */
414 #define mac_rw_flags mac_regwin.rw_flags
415 #define mac_type mac_regwin.rw_type
416 #define mac_id mac_regwin.rw_id
417 #define mac_rev mac_regwin.rw_rev
419 struct bwi_softc
*mac_sc
;
421 struct bwi_phy mac_phy
; /* PHY I/F */
422 struct bwi_rf mac_rf
; /* RF I/F */
424 struct bwi_tpctl mac_tpctl
; /* TX power control */
425 uint32_t mac_flags
; /* BWI_MAC_F_ */
427 struct fw_image
*mac_ucode
;
428 struct fw_image
*mac_pcm
;
429 struct fw_image
*mac_iv
;
430 struct fw_image
*mac_iv_ext
;
433 #define BWI_MAC_F_BSWAP 0x1
434 #define BWI_MAC_F_TPCTL_INITED 0x2
435 #define BWI_MAC_F_HAS_TXSTATS 0x4
436 #define BWI_MAC_F_INITED 0x8
437 #define BWI_MAC_F_ENABLED 0x10
438 #define BWI_MAC_F_LOCKED 0x20 /* for debug */
439 #define BWI_MAC_F_TPCTL_ERROR 0x40
441 #define BWI_CREATE_MAC(mac, sc, id, rev) \
443 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \
447 (mac)->mac_sc = (sc); \
450 #define BWI_MAC_MAX 2
453 BWI_BUS_SPACE_30BIT
= 1,
458 #define BWI_TX_RADIOTAP_PRESENT \
459 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
460 (1 << IEEE80211_RADIOTAP_RATE) | \
461 (1 << IEEE80211_RADIOTAP_CHANNEL))
463 struct bwi_tx_radiotap_hdr
{
464 struct ieee80211_radiotap_header wt_ihdr
;
467 uint16_t wt_chan_freq
;
468 uint16_t wt_chan_flags
;
471 #define BWI_RX_RADIOTAP_PRESENT \
472 ((1 << IEEE80211_RADIOTAP_TSFT) | \
473 (1 << IEEE80211_RADIOTAP_FLAGS) | \
474 (1 << IEEE80211_RADIOTAP_RATE) | \
475 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
476 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
477 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
479 struct bwi_rx_radiotap_hdr
{
480 struct ieee80211_radiotap_header wr_ihdr
;
484 uint16_t wr_chan_freq
;
485 uint16_t wr_chan_flags
;
492 struct ieee80211com sc_ic
;
493 uint32_t sc_flags
; /* BWI_F_ */
496 uint32_t sc_cap
; /* BWI_CAP_ */
497 uint16_t sc_bbp_id
; /* BWI_BBPID_ */
501 uint8_t sc_pci_revid
;
502 uint16_t sc_pci_subvid
;
503 uint16_t sc_pci_subdid
;
505 uint16_t sc_card_flags
; /* BWI_CARD_F_ */
506 uint16_t sc_pwron_delay
;
510 struct resource
*sc_irq_res
;
514 struct resource
*sc_mem_res
;
515 bus_space_tag_t sc_mem_bt
;
516 bus_space_handle_t sc_mem_bh
;
518 struct callout sc_scan_ch
;
519 struct callout sc_calib_ch
;
521 struct bwi_regwin
*sc_cur_regwin
;
522 struct bwi_regwin sc_com_regwin
;
523 struct bwi_regwin sc_bus_regwin
;
526 struct bwi_mac sc_mac
[BWI_MAC_MAX
];
528 enum bwi_bus_space sc_bus_space
;
529 bus_dma_tag_t sc_parent_dtag
;
531 bus_dma_tag_t sc_buf_dtag
;
532 struct bwi_txbuf_data sc_tx_bdata
[BWI_TX_NRING
];
533 struct bwi_rxbuf_data sc_rx_bdata
;
535 bus_dma_tag_t sc_txring_dtag
;
536 struct bwi_ring_data sc_tx_rdata
[BWI_TX_NRING
];
537 bus_dma_tag_t sc_rxring_dtag
;
538 struct bwi_ring_data sc_rx_rdata
;
540 struct bwi_txstats_data
*sc_txstats
;
544 struct bpf_if
*sc_drvbpf
;
547 struct bwi_tx_radiotap_hdr u_tx_th
;
548 uint8_t u_pad
[IEEE80211_RADIOTAP_HDRLEN
];
550 #define sc_tx_th sc_u_tx_th.u_tx_th
554 struct bwi_rx_radiotap_hdr u_rx_th
;
555 uint8_t u_pad
[IEEE80211_RADIOTAP_HDRLEN
];
557 #define sc_rx_th sc_u_rx_th.u_rx_th
561 (struct ieee80211com
*,
562 enum ieee80211_state
, int);
564 int (*sc_init_tx_ring
)(struct bwi_softc
*, int);
565 void (*sc_free_tx_ring
)(struct bwi_softc
*, int);
567 int (*sc_init_rx_ring
)(struct bwi_softc
*);
568 void (*sc_free_rx_ring
)(struct bwi_softc
*);
570 int (*sc_init_txstats
)(struct bwi_softc
*);
571 void (*sc_free_txstats
)(struct bwi_softc
*);
573 void (*sc_setup_rxdesc
)
574 (struct bwi_softc
*, int, bus_addr_t
, int);
575 void (*sc_rxeof
)(struct bwi_softc
*);
577 void (*sc_setup_txdesc
)
578 (struct bwi_softc
*, struct bwi_ring_data
*,
579 int, bus_addr_t
, int);
581 (struct bwi_softc
*, uint32_t, int);
583 void (*sc_txeof_status
)(struct bwi_softc
*);
585 /* Sysctl variables */
586 int sc_fw_version
; /* BWI_FW_VERSION[34] */
587 int sc_dwell_time
; /* milliseconds */
590 #define BWI_F_BUS_INITED 0x1
591 #define BWI_F_PROMISC 0x2
593 uint16_t bwi_read_sprom(struct bwi_softc
*, uint16_t);
594 int bwi_regwin_switch(struct bwi_softc
*, struct bwi_regwin
*,
595 struct bwi_regwin
**);
596 int bwi_regwin_is_enabled(struct bwi_softc
*, struct bwi_regwin
*);
597 void bwi_regwin_enable(struct bwi_softc
*, struct bwi_regwin
*,
599 void bwi_regwin_disable(struct bwi_softc
*, struct bwi_regwin
*,
601 int bwi_bus_init(struct bwi_softc
*, struct bwi_mac
*);
602 uint8_t bwi_rate2plcp(uint8_t); /* XXX belongs to 802.11 */
604 #define abs(a) __builtin_abs(a)
606 #endif /* !_IF_BWIVAR_H */