sys/dev/netif/bwi/if_bwivar.h

   1 /*
   2  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   3  *
   4  * This code is derived from software contributed to The DragonFly Project
   5  * by Sepherosa Ziehau <sepherosa@gmail.com>
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of The DragonFly Project nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific, prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  32  * SUCH DAMAGE.
  33  *
  34  * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.7 2007/09/17 12:13:24 sephe Exp $
  35  */
  36
  37 #ifndef _IF_BWIVAR_H
  38 #define _IF_BWIVAR_H
  39
  40 #define BWI_ALIGN               0x1000
  41 #define BWI_RING_ALIGN          BWI_ALIGN
  42 #define BWI_BUS_SPACE_MAXADDR   0x3fffffff
  43
  44 #define BWI_TX_NRING            6
  45 #define BWI_TXRX_NRING          6
  46 #define BWI_TX_NDESC            128
  47 #define BWI_RX_NDESC            64
  48 #define BWI_TXSTATS_NDESC       64
  49 #define BWI_TX_NSPRDESC         2
  50 #define BWI_TX_DATA_RING        1
  51
  52 /* XXX Onoe/Sample/AMRR probably need different configuration */
  53 #define BWI_SHRETRY             7
  54 #define BWI_LGRETRY             4
  55 #define BWI_SHRETRY_FB          3
  56 #define BWI_LGRETRY_FB          2
  57
  58 #define BWI_NOISE_FLOOR         -95     /* TODO: noise floor calc */
  59 #define BWI_FRAME_MIN_LEN(hdr)  \
  60         ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
  61
  62 #define CSR_READ_4(sc, reg)             \
  63         bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
  64 #define CSR_READ_2(sc, reg)             \
  65         bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
  66
  67 #define CSR_WRITE_4(sc, reg, val)       \
  68         bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
  69 #define CSR_WRITE_2(sc, reg, val)       \
  70         bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
  71
  72 #define CSR_SETBITS_4(sc, reg, bits)    \
  73         CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
  74 #define CSR_SETBITS_2(sc, reg, bits)    \
  75         CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
  76
  77 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
  78         CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
  79 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
  80         CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
  81
  82 #define CSR_CLRBITS_4(sc, reg, bits)    \
  83         CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
  84 #define CSR_CLRBITS_2(sc, reg, bits)    \
  85         CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
  86
  87 #define BWI_DEBUG
  88 #ifdef BWI_DEBUG
  89
  90 #define DPRINTF(sc, dbg, fmt, ...) \
  91 do { \
  92         if ((sc)->sc_debug & (dbg)) \
  93                 if_printf(&(sc)->sc_ic.ic_if, fmt, __VA_ARGS__); \
  94 } while (0)
  95
  96 #define _DPRINTF(sc, dbg, fmt, ...) \
  97 do { \
  98         if ((sc)->sc_debug & (dbg)) \
  99                 kprintf(fmt, __VA_ARGS__); \
 100 } while (0)
 101
 102 #else   /* !BWI_DEBUG */
 103
 104 #define DPRINTF(sc, dbg, fmt, ...)      ((void)0)
 105 #define _DPRINTF(sc, dbg, fmt, ...)     ((void)0)
 106
 107 #endif  /* BWI_DEBUG */
 108
 109 struct bwi_desc32 {
 110         /* Little endian */
 111         uint32_t        ctrl;
 112         uint32_t        addr;   /* BWI_DESC32_A_ */
 113 } __packed;
 114
 115 #define BWI_DESC32_A_FUNC_TXRX          0x1
 116 #define BWI_DESC32_A_FUNC_MASK          __BITS(31, 30)
 117 #define BWI_DESC32_A_ADDR_MASK          __BITS(29, 0)
 118
 119 #define BWI_DESC32_C_BUFLEN_MASK        __BITS(12, 0)
 120 #define BWI_DESC32_C_ADDRHI_MASK        __BITS(17, 16)
 121 #define BWI_DESC32_C_EOR                __BIT(28)
 122 #define BWI_DESC32_C_INTR               __BIT(29)
 123 #define BWI_DESC32_C_FRAME_END          __BIT(30)
 124 #define BWI_DESC32_C_FRAME_START        __BIT(31)
 125
 126 struct bwi_desc64 {
 127         /* Little endian */
 128         uint32_t        ctrl0;
 129         uint32_t        ctrl1;
 130         uint32_t        addr_lo;
 131         uint32_t        addr_hi;
 132 } __packed;
 133
 134 struct bwi_rxbuf_hdr {
 135         /* Little endian */
 136         uint16_t        rxh_buflen;     /* exclude bwi_rxbuf_hdr */
 137         uint8_t         rxh_pad1[2];
 138         uint16_t        rxh_flags1;     /* BWI_RXH_F1_ */
 139         uint8_t         rxh_rssi;
 140         uint8_t         rxh_sq;
 141         uint16_t        rxh_phyinfo;    /* BWI_RXH_PHYINFO_ */
 142         uint16_t        rxh_flags3;     /* BWI_RXH_F3_ */
 143         uint16_t        rxh_flags2;     /* BWI_RXH_F2_ */
 144         uint16_t        rxh_tsf;
 145         uint8_t         rxh_pad3[14];   /* Padded to 30bytes */
 146 } __packed;
 147
 148 #define BWI_RXH_F1_BCM2053_RSSI __BIT(14)
 149 #define BWI_RXH_F1_SHPREAMBLE   __BIT(7)
 150 #define BWI_RXH_F1_OFDM         __BIT(0)
 151
 152 #define BWI_RXH_F2_TYPE2FRAME   __BIT(2)
 153
 154 #define BWI_RXH_F3_BCM2050_RSSI __BIT(10)
 155
 156 #define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
 157
 158 struct bwi_txbuf_hdr {
 159         /* Little endian */
 160         uint32_t        txh_mac_ctrl;   /* BWI_TXH_MAC_C_ */
 161         uint8_t         txh_fc[2];
 162         uint16_t        txh_unknown1;
 163         uint16_t        txh_phy_ctrl;   /* BWI_TXH_PHY_C_ */
 164         uint8_t         txh_ivs[16];
 165         uint8_t         txh_addr1[IEEE80211_ADDR_LEN];
 166         uint16_t        txh_unknown2;
 167         uint8_t         txh_rts_fb_plcp[4];
 168         uint16_t        txh_rts_fb_duration;
 169         uint8_t         txh_fb_plcp[4];
 170         uint16_t        txh_fb_duration;
 171         uint8_t         txh_pad2[2];
 172         uint16_t        txh_id;         /* BWI_TXH_ID_ */
 173         uint16_t        txh_unknown3;
 174         uint8_t         txh_rts_plcp[6];
 175         uint8_t         txh_rts_fc[2];
 176         uint16_t        txh_rts_duration;
 177         uint8_t         txh_rts_ra[IEEE80211_ADDR_LEN];
 178         uint8_t         txh_rts_ta[IEEE80211_ADDR_LEN];
 179         uint8_t         txh_pad3[2];
 180         uint8_t         txh_plcp[6];
 181 } __packed;
 182
 183 #define BWI_TXH_ID_RING_MASK            __BITS(15, 13)
 184 #define BWI_TXH_ID_IDX_MASK             __BITS(12, 0)
 185
 186 #define BWI_TXH_PHY_C_OFDM              __BIT(0)
 187 #define BWI_TXH_PHY_C_SHPREAMBLE        __BIT(4)
 188 #define BWI_TXH_PHY_C_ANTMODE_MASK      __BITS(9, 8)
 189
 190 #define BWI_TXH_MAC_C_ACK               __BIT(0)
 191 #define BWI_TXH_MAC_C_FIRST_FRAG        __BIT(3)
 192 #define BWI_TXH_MAC_C_HWSEQ             __BIT(4)
 193 #define BWI_TXH_MAC_C_FB_OFDM           __BIT(8)
 194
 195 struct bwi_txstats {
 196         /* Little endian */
 197         uint8_t         txs_pad1[4];
 198         uint16_t        txs_id;
 199         uint8_t         txs_flags;      /* BWI_TXS_F_ */
 200         uint8_t         txs_txcnt;      /* BWI_TXS_TXCNT_ */
 201         uint8_t         txs_pad2[2];
 202         uint16_t        txs_seq;
 203         uint16_t        txs_unknown;
 204         uint8_t         txs_pad3[2];    /* Padded to 16bytes */
 205 } __packed;
 206
 207 #define BWI_TXS_TXCNT_DATA      __BITS(7, 4)
 208
 209 #define BWI_TXS_F_ACKED         __BIT(0)
 210 #define BWI_TXS_F_PENDING       __BIT(5)
 211
 212 struct bwi_ring_data {
 213         uint32_t                rdata_txrx_ctrl;
 214         bus_dmamap_t            rdata_dmap;
 215         bus_addr_t              rdata_paddr;
 216         void                    *rdata_desc;
 217 };
 218
 219 struct bwi_txbuf {
 220         struct mbuf             *tb_mbuf;
 221         bus_dmamap_t            tb_dmap;
 222
 223         struct ieee80211_node   *tb_ni;
 224         int                     tb_rate_idx[2];
 225 };
 226
 227 struct bwi_txbuf_data {
 228         struct bwi_txbuf        tbd_buf[BWI_TX_NDESC];
 229         int                     tbd_used;
 230         int                     tbd_idx;
 231 };
 232
 233 struct bwi_rxbuf {
 234         struct mbuf             *rb_mbuf;
 235         bus_addr_t              rb_paddr;
 236         bus_dmamap_t            rb_dmap;
 237 };
 238
 239 struct bwi_rxbuf_data {
 240         struct bwi_rxbuf        rbd_buf[BWI_RX_NDESC];
 241         bus_dmamap_t            rbd_tmp_dmap;
 242         int                     rbd_idx;
 243 };
 244
 245 struct bwi_txstats_data {
 246         bus_dma_tag_t           stats_ring_dtag;
 247         bus_dmamap_t            stats_ring_dmap;
 248         bus_addr_t              stats_ring_paddr;
 249         void                    *stats_ring;
 250
 251         bus_dma_tag_t           stats_dtag;
 252         bus_dmamap_t            stats_dmap;
 253         bus_addr_t              stats_paddr;
 254         struct bwi_txstats      *stats;
 255
 256         uint32_t                stats_ctrl_base;
 257         int                     stats_idx;
 258 };
 259
 260 struct bwi_fwhdr {
 261         /* Big endian */
 262         uint8_t         fw_type;        /* BWI_FW_T_ */
 263         uint8_t         fw_gen;         /* BWI_FW_GEN */
 264         uint8_t         fw_pad[2];
 265         uint32_t        fw_size;
 266 #define fw_iv_cnt       fw_size
 267 } __packed;
 268
 269 #define BWI_FWHDR_SZ            sizeof(struct bwi_fwhdr)
 270
 271 #define BWI_FW_T_UCODE          'u'
 272 #define BWI_FW_T_PCM            'p'
 273 #define BWI_FW_T_IV             'i'
 274
 275 #define BWI_FW_GEN_1            1
 276
 277 #define BWI_FW_VERSION3         3
 278 #define BWI_FW_VERSION4         4
 279 #define BWI_FW_VERSION3_REVMAX  0x128
 280
 281 #define BWI_FW_PATH             "bwi/v%d/"
 282 #define BWI_FW_UCODE_PATH       BWI_FW_PATH "ucode%d.fw"
 283 #define BWI_FW_PCM_PATH         BWI_FW_PATH "pcm%d.fw"
 284 #define BWI_FW_IV_PATH          BWI_FW_PATH "b0g0initvals%d.fw"
 285 #define BWI_FW_IV_EXT_PATH      BWI_FW_PATH "b0g0bsinitvals%d.fw"
 286
 287 struct bwi_fw_iv {
 288         /* Big endian */
 289         uint16_t                iv_ofs;
 290         union {
 291                 uint32_t        val32;
 292                 uint16_t        val16;
 293         }                       iv_val;
 294 } __packed;
 295
 296 #define BWI_FW_IV_OFS_MASK      __BITS(14, 0)
 297 #define BWI_FW_IV_IS_32BIT      __BIT(15)
 298
 299 enum bwi_clock_mode {
 300         BWI_CLOCK_MODE_SLOW,
 301         BWI_CLOCK_MODE_FAST,
 302         BWI_CLOCK_MODE_DYN
 303 };
 304
 305 struct bwi_regwin {
 306         uint32_t                rw_flags;       /* BWI_REGWIN_F_ */
 307         uint16_t                rw_type;        /* BWI_REGWIN_T_ */
 308         uint8_t                 rw_id;
 309         uint8_t                 rw_rev;
 310 };
 311
 312 #define BWI_REGWIN_F_EXIST      0x1
 313
 314 #define BWI_CREATE_REGWIN(rw, id, type, rev)    \
 315 do {                                            \
 316         (rw)->rw_flags = BWI_REGWIN_F_EXIST;    \
 317         (rw)->rw_type = (type);                 \
 318         (rw)->rw_id = (id);                     \
 319         (rw)->rw_rev = (rev);                   \
 320 } while (0)
 321
 322 #define BWI_REGWIN_EXIST(rw)    ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
 323 #define BWI_GPIO_REGWIN(sc) \
 324         (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
 325                 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
 326
 327 struct bwi_mac;
 328
 329 struct bwi_phy {
 330         enum ieee80211_phymode  phy_mode;
 331         int                     phy_rev;
 332         int                     phy_version;
 333
 334         uint32_t                phy_flags;              /* BWI_PHY_F_ */
 335         uint16_t                phy_tbl_ctrl;
 336         uint16_t                phy_tbl_data_lo;
 337         uint16_t                phy_tbl_data_hi;
 338
 339         void                    (*phy_init)(struct bwi_mac *);
 340 };
 341
 342 #define BWI_PHY_F_CALIBRATED    0x1
 343 #define BWI_PHY_F_LINKED        0x2
 344 #define BWI_CLEAR_PHY_FLAGS     (BWI_PHY_F_CALIBRATED)
 345
 346 /* TX power control */
 347 struct bwi_tpctl {
 348         uint16_t                bbp_atten;      /* BBP attenuation: 4bits */
 349         uint16_t                rf_atten;       /* RF attenuation */
 350         uint16_t                tp_ctrl1;       /* ??: 3bits */
 351         uint16_t                tp_ctrl2;       /* ??: 4bits */
 352 };
 353
 354 #define BWI_RF_ATTEN_FACTOR     4
 355 #define BWI_RF_ATTEN_MAX0       9
 356 #define BWI_RF_ATTEN_MAX1       31
 357 #define BWI_BBP_ATTEN_MAX       11
 358 #define BWI_TPCTL1_MAX          7
 359
 360 struct bwi_rf_lo {
 361         int8_t                  ctrl_lo;
 362         int8_t                  ctrl_hi;
 363 };
 364
 365 struct bwi_rf {
 366         uint16_t                rf_type;        /* BWI_RF_T_ */
 367         uint16_t                rf_manu;
 368         int                     rf_rev;
 369
 370         uint32_t                rf_flags;       /* BWI_RF_F_ */
 371
 372 #define BWI_RFLO_MAX            56
 373         struct bwi_rf_lo        rf_lo[BWI_RFLO_MAX];
 374         uint8_t                 rf_lo_used[8];
 375
 376 #define BWI_INVALID_NRSSI       -1000
 377         int16_t                 rf_nrssi[2];    /* Narrow RSSI */
 378         int32_t                 rf_nrssi_slope;
 379
 380 #define BWI_NRSSI_TBLSZ         64
 381         int8_t                  rf_nrssi_table[BWI_NRSSI_TBLSZ];
 382
 383         uint16_t                rf_lo_gain;     /* loopback gain */
 384         uint16_t                rf_rx_gain;     /* TRSW RX gain */
 385
 386         uint16_t                rf_calib;       /* RF calibration value */
 387         u_int                   rf_curchan;     /* current channel */
 388
 389         uint16_t                rf_ctrl_rd;
 390         int                     rf_ctrl_adj;
 391         void                    (*rf_off)(struct bwi_mac *);
 392         void                    (*rf_on)(struct bwi_mac *);
 393
 394         void                    (*rf_set_nrssi_thr)(struct bwi_mac *);
 395         void                    (*rf_calc_nrssi_slope)(struct bwi_mac *);
 396         int                     (*rf_calc_rssi)
 397                                 (struct bwi_mac *,
 398                                  const struct bwi_rxbuf_hdr *);
 399
 400 #define BWI_TSSI_MAX            64
 401         int8_t                  rf_txpower_map0[BWI_TSSI_MAX];
 402                                                 /* Indexed by TSSI */
 403         int                     rf_idle_tssi0;
 404
 405         int8_t                  rf_txpower_map[BWI_TSSI_MAX];
 406         int                     rf_idle_tssi;
 407
 408         int                     rf_base_tssi;
 409
 410         int                     rf_txpower_max; /* dBm */
 411
 412         int                     rf_ant_mode;    /* BWI_ANT_MODE_ */
 413 };
 414
 415 #define BWI_RF_F_INITED         0x1
 416 #define BWI_RF_F_ON             0x2
 417 #define BWI_RF_CLEAR_FLAGS      (BWI_RF_F_INITED)
 418
 419 #define BWI_ANT_MODE_0          0
 420 #define BWI_ANT_MODE_1          1
 421 #define BWI_ANT_MODE_UNKN       2
 422 #define BWI_ANT_MODE_AUTO       3
 423
 424 struct bwi_softc;
 425 struct fw_image;
 426
 427 struct bwi_mac {
 428         struct bwi_regwin       mac_regwin;     /* MUST be first field */
 429 #define mac_rw_flags    mac_regwin.rw_flags
 430 #define mac_type        mac_regwin.rw_type
 431 #define mac_id          mac_regwin.rw_id
 432 #define mac_rev         mac_regwin.rw_rev
 433
 434         struct bwi_softc        *mac_sc;
 435
 436         struct bwi_phy          mac_phy;        /* PHY I/F */
 437         struct bwi_rf           mac_rf;         /* RF I/F */
 438
 439         struct bwi_tpctl        mac_tpctl;      /* TX power control */
 440         uint32_t                mac_flags;      /* BWI_MAC_F_ */
 441
 442         struct fw_image         *mac_ucode;
 443         struct fw_image         *mac_pcm;
 444         struct fw_image         *mac_iv;
 445         struct fw_image         *mac_iv_ext;
 446 };
 447
 448 #define BWI_MAC_F_BSWAP         0x1
 449 #define BWI_MAC_F_TPCTL_INITED  0x2
 450 #define BWI_MAC_F_HAS_TXSTATS   0x4
 451 #define BWI_MAC_F_INITED        0x8
 452 #define BWI_MAC_F_ENABLED       0x10
 453 #define BWI_MAC_F_LOCKED        0x20    /* for debug */
 454 #define BWI_MAC_F_TPCTL_ERROR   0x40
 455
 456 #define BWI_CREATE_MAC(mac, sc, id, rev)        \
 457 do {                                            \
 458         BWI_CREATE_REGWIN(&(mac)->mac_regwin,   \
 459                           (id),                 \
 460                           BWI_REGWIN_T_MAC,     \
 461                           (rev));               \
 462         (mac)->mac_sc = (sc);                   \
 463 } while (0)
 464
 465 #define BWI_MAC_MAX             2
 466
 467 enum bwi_bus_space {
 468         BWI_BUS_SPACE_30BIT = 1,
 469         BWI_BUS_SPACE_32BIT,
 470         BWI_BUS_SPACE_64BIT
 471 };
 472
 473 #define BWI_TX_RADIOTAP_PRESENT                 \
 474         ((1 << IEEE80211_RADIOTAP_FLAGS) |      \
 475          (1 << IEEE80211_RADIOTAP_RATE) |       \
 476          (1 << IEEE80211_RADIOTAP_CHANNEL))
 477
 478 struct bwi_tx_radiotap_hdr {
 479         struct ieee80211_radiotap_header wt_ihdr;
 480         uint8_t         wt_flags;
 481         uint8_t         wt_rate;
 482         uint16_t        wt_chan_freq;
 483         uint16_t        wt_chan_flags;
 484 };
 485
 486 #define BWI_RX_RADIOTAP_PRESENT                         \
 487         ((1 << IEEE80211_RADIOTAP_TSFT) |               \
 488          (1 << IEEE80211_RADIOTAP_FLAGS) |              \
 489          (1 << IEEE80211_RADIOTAP_RATE) |               \
 490          (1 << IEEE80211_RADIOTAP_CHANNEL) |            \
 491          (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |      \
 492          (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
 493
 494 struct bwi_rx_radiotap_hdr {
 495         struct ieee80211_radiotap_header wr_ihdr;
 496         uint64_t        wr_tsf;
 497         uint8_t         wr_flags;
 498         uint8_t         wr_rate;
 499         uint16_t        wr_chan_freq;
 500         uint16_t        wr_chan_flags;
 501         int8_t          wr_antsignal;
 502         int8_t          wr_antnoise;
 503         /* TODO: sq */
 504 };
 505
 506 struct bwi_softc {
 507         struct ieee80211com     sc_ic;
 508         uint32_t                sc_flags;       /* BWI_F_ */
 509         device_t                sc_dev;
 510
 511         uint32_t                sc_cap;         /* BWI_CAP_ */
 512         uint16_t                sc_bbp_id;      /* BWI_BBPID_ */
 513         uint8_t                 sc_bbp_rev;
 514         uint8_t                 sc_bbp_pkg;
 515
 516         uint8_t                 sc_pci_revid;
 517         uint16_t                sc_pci_subvid;
 518         uint16_t                sc_pci_subdid;
 519
 520         uint16_t                sc_card_flags;  /* BWI_CARD_F_ */
 521         uint16_t                sc_pwron_delay;
 522         int                     sc_locale;
 523
 524         int                     sc_irq_rid;
 525         struct resource         *sc_irq_res;
 526         void                    *sc_irq_handle;
 527
 528         int                     sc_mem_rid;
 529         struct resource         *sc_mem_res;
 530         bus_space_tag_t         sc_mem_bt;
 531         bus_space_handle_t      sc_mem_bh;
 532
 533         struct callout          sc_scan_ch;
 534         struct callout          sc_calib_ch;
 535
 536         struct bwi_regwin       *sc_cur_regwin;
 537         struct bwi_regwin       sc_com_regwin;
 538         struct bwi_regwin       sc_bus_regwin;
 539
 540         int                     sc_nmac;
 541         struct bwi_mac          sc_mac[BWI_MAC_MAX];
 542
 543         enum bwi_bus_space      sc_bus_space;
 544         bus_dma_tag_t           sc_parent_dtag;
 545
 546         bus_dma_tag_t           sc_buf_dtag;
 547         struct bwi_txbuf_data   sc_tx_bdata[BWI_TX_NRING];
 548         struct bwi_rxbuf_data   sc_rx_bdata;
 549
 550         bus_dma_tag_t           sc_txring_dtag;
 551         struct bwi_ring_data    sc_tx_rdata[BWI_TX_NRING];
 552         bus_dma_tag_t           sc_rxring_dtag;
 553         struct bwi_ring_data    sc_rx_rdata;
 554
 555         struct bwi_txstats_data *sc_txstats;
 556
 557         int                     sc_tx_timer;
 558
 559         struct bpf_if           *sc_drvbpf;
 560
 561         union {
 562                 struct bwi_tx_radiotap_hdr u_tx_th;
 563                 uint8_t         u_pad[IEEE80211_RADIOTAP_HDRLEN];
 564         } sc_u_tx_th;
 565 #define sc_tx_th        sc_u_tx_th.u_tx_th
 566         int                     sc_tx_th_len;
 567
 568         union {
 569                 struct bwi_rx_radiotap_hdr u_rx_th;
 570                 uint8_t         u_pad[IEEE80211_RADIOTAP_HDRLEN];
 571         } sc_u_rx_th;
 572 #define sc_rx_th        sc_u_rx_th.u_rx_th
 573         int                     sc_rx_th_len;
 574
 575         int                     (*sc_newstate)
 576                                 (struct ieee80211com *,
 577                                  enum ieee80211_state, int);
 578
 579         int                     (*sc_init_tx_ring)(struct bwi_softc *, int);
 580         void                    (*sc_free_tx_ring)(struct bwi_softc *, int);
 581
 582         int                     (*sc_init_rx_ring)(struct bwi_softc *);
 583         void                    (*sc_free_rx_ring)(struct bwi_softc *);
 584
 585         int                     (*sc_init_txstats)(struct bwi_softc *);
 586         void                    (*sc_free_txstats)(struct bwi_softc *);
 587
 588         void                    (*sc_setup_rxdesc)
 589                                 (struct bwi_softc *, int, bus_addr_t, int);
 590         void                    (*sc_rxeof)(struct bwi_softc *);
 591
 592         void                    (*sc_setup_txdesc)
 593                                 (struct bwi_softc *, struct bwi_ring_data *,
 594                                  int, bus_addr_t, int);
 595         void                    (*sc_start_tx)
 596                                 (struct bwi_softc *, uint32_t, int);
 597
 598         void                    (*sc_txeof_status)(struct bwi_softc *);
 599
 600         struct sysctl_ctx_list  sc_sysctl_ctx;
 601         struct sysctl_oid       *sc_sysctl_tree;
 602
 603         /*
 604          * Sysctl variables
 605          */
 606         int                     sc_fw_version;  /* BWI_FW_VERSION[34] */
 607         int                     sc_dwell_time;  /* milliseconds */
 608         uint32_t                sc_debug;       /* BWI_DBG_ */
 609 };
 610
 611 #define BWI_F_BUS_INITED        0x1
 612 #define BWI_F_PROMISC           0x2
 613
 614 #define BWI_DBG_MAC             0x00000001
 615 #define BWI_DBG_RF              0x00000002
 616 #define BWI_DBG_PHY             0x00000004
 617 #define BWI_DBG_MISC            0x00000008
 618
 619 #define BWI_DBG_ATTACH          0x00000010
 620 #define BWI_DBG_INIT            0x00000020
 621 #define BWI_DBG_FIRMWARE        0x00000040
 622 #define BWI_DBG_80211           0x00000080
 623 #define BWI_DBG_TXPOWER         0x00000100
 624 #define BWI_DBG_INTR            0x00000200
 625 #define BWI_DBG_RX              0x00000400
 626 #define BWI_DBG_TX              0x00000800
 627 #define BWI_DBG_TXEOF           0x00001000
 628
 629 uint16_t        bwi_read_sprom(struct bwi_softc *, uint16_t);
 630 int             bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *,
 631                                   struct bwi_regwin **);
 632 int             bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *);
 633 void            bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *,
 634                                   uint32_t);
 635 void            bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *,
 636                                    uint32_t);
 637 int             bwi_bus_init(struct bwi_softc *, struct bwi_mac *);
 638 uint8_t         bwi_rate2plcp(uint8_t); /* XXX belongs to 802.11 */
 639
 640 #define abs(a)  __builtin_abs(a)
 641
 642 #endif  /* !_IF_BWIVAR_H */