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Add WIP support for Broadcom wireless chips:
[dragonfly/port-amd64.git] / sys / dev / netif / bwi / bwirf.c
blobabecc60376722eaebe8716e3e1d1dbf955da18d4
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/bwirf.c,v 1.1 2007/09/08 06:15:54 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/bus.h>
41 #include <sys/malloc.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46
47 #include <net/ethernet.h>
48 #include <net/if.h>
49 #include <net/bpf.h>
50 #include <net/if_arp.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53 #include <net/ifq_var.h>
54
55 #include <netproto/802_11/ieee80211_var.h>
56
57 #include <bus/pci/pcireg.h>
58 #include <bus/pci/pcivar.h>
59 #include <bus/pci/pcidevs.h>
60
61 #include "bitops.h"
62 #include "if_bwireg.h"
63 #include "if_bwivar.h"
64 #include "bwiphy.h"
65 #include "bwirf.h"
66 #include "bwimac.h"
67
68 #define RF_LO_WRITE(mac, lo) bwi_rf_lo_write((mac), (lo))
69
70 #define BWI_RF_2GHZ_CHAN(chan) \
71 (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
72
73 #define BWI_DEFAULT_IDLE_TSSI 52
74
75 struct rf_saveregs {
76 uint16_t phy_15;
77 uint16_t phy_2a;
78 uint16_t phy_35;
79 uint16_t phy_60;
80 uint16_t phy_429;
81 uint16_t phy_802;
82 uint16_t phy_811;
83 uint16_t phy_812;
84 uint16_t phy_814;
85 uint16_t phy_815;
86
87 uint16_t rf_43;
88 uint16_t rf_52;
89 uint16_t rf_7a;
90 };
91
92 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)
93 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)
94
95 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)
96 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
97
98 static int bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
99 static void bwi_rf_work_around(struct bwi_mac *, u_int);
100 static int bwi_rf_gain_max_reached(struct bwi_mac *, int);
101 static uint16_t bwi_rf_calibval(struct bwi_mac *);
102 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *);
103 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
104 static void bwi_rf_lo_measure(struct bwi_mac *,
105 const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
106 static uint8_t _bwi_rf_lo_update(struct bwi_mac *, uint16_t);
107
108 static void bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
109
110 static void bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
111 static void bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
112 static void bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
113 static void bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
114 static void bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
115
116 static void bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
117
118 static void bwi_rf_on_11a(struct bwi_mac *);
119 static void bwi_rf_on_11bg(struct bwi_mac *);
120
121 static void bwi_rf_off_11a(struct bwi_mac *);
122 static void bwi_rf_off_11bg(struct bwi_mac *);
123 static void bwi_rf_off_11g_rev5(struct bwi_mac *);
124
125 static const int8_t bwi_txpower_map_11b[BWI_TSSI_MAX] =
126 { BWI_TXPOWER_MAP_11B };
127 static const int8_t bwi_txpower_map_11g[BWI_TSSI_MAX] =
128 { BWI_TXPOWER_MAP_11G };
129
130 static __inline int16_t
131 bwi_nrssi_11g(struct bwi_mac *mac)
132 {
133 int16_t val;
134
135 #define NRSSI_11G_MASK __BITS(13, 8)
136
137 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
138 if (val >= 32)
139 val -= 64;
140 return val;
141
142 #undef NRSSI_11G_MASK
143 }
144
145 static __inline struct bwi_rf_lo *
146 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten)
147 {
148 int n;
149
150 n = rf_atten + (14 * (bbp_atten / 2));
151 KKASSERT(n < BWI_RFLO_MAX);
152
153 return &mac->mac_rf.rf_lo[n];
154 }
155
156 static __inline int
157 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
158 {
159 struct bwi_rf *rf = &mac->mac_rf;
160 int idx;
161
162 idx = lo - rf->rf_lo;
163 KKASSERT(idx >= 0 && idx < BWI_RFLO_MAX);
164
165 return isset(rf->rf_lo_used, idx);
166 }
167
168 void
169 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
170 {
171 struct bwi_softc *sc = mac->mac_sc;
172
173 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
174 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
175 }
176
177 uint16_t
178 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
179 {
180 struct bwi_rf *rf = &mac->mac_rf;
181 struct bwi_softc *sc = mac->mac_sc;
182
183 ctrl |= rf->rf_ctrl_rd;
184 if (rf->rf_ctrl_adj) {
185 /* XXX */
186 if (ctrl < 0x70)
187 ctrl += 0x80;
188 else if (ctrl < 0x80)
189 ctrl += 0x70;
190 }
191
192 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
193 return CSR_READ_2(sc, BWI_RF_DATA_LO);
194 }
195
196 int
197 bwi_rf_attach(struct bwi_mac *mac)
198 {
199 struct bwi_softc *sc = mac->mac_sc;
200 struct bwi_rf *rf = &mac->mac_rf;
201 uint16_t type, manu;
202 uint8_t rev;
203
204 /*
205 * Get RF manufacture/type/revision
206 */
207 if (sc->sc_bbp_id == BWI_BBPID_BCM4317) {
208 /*
209 * Fake a BCM2050 RF
210 */
211 manu = BWI_RF_MANUFACT_BCM;
212 type = BWI_RF_T_BCM2050;
213 if (sc->sc_bbp_rev == 0)
214 rev = 3;
215 else if (sc->sc_bbp_rev == 1)
216 rev = 4;
217 else
218 rev = 5;
219 } else {
220 uint32_t val;
221
222 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
223 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
224 val <<= 16;
225
226 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
227 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
228
229 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
230 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
231 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
232 }
233 device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n",
234 manu, type, rev);
235
236 /*
237 * Verify whether the RF is supported
238 */
239 rf->rf_ctrl_rd = 0;
240 rf->rf_ctrl_adj = 0;
241 switch (mac->mac_phy.phy_mode) {
242 case IEEE80211_MODE_11A:
243 if (manu != BWI_RF_MANUFACT_BCM ||
244 type != BWI_RF_T_BCM2060 ||
245 rev != 1) {
246 device_printf(sc->sc_dev, "only BCM2060 rev 1 RF "
247 "is supported for 11A PHY\n");
248 return ENXIO;
249 }
250 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A;
251 rf->rf_on = bwi_rf_on_11a;
252 rf->rf_off = bwi_rf_off_11a;
253 break;
254 case IEEE80211_MODE_11B:
255 if (type == BWI_RF_T_BCM2050) {
256 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
257 } else if (type == BWI_RF_T_BCM2053) {
258 rf->rf_ctrl_adj = 1;
259 } else {
260 device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF "
261 "is supported for 11B PHY\n");
262 return ENXIO;
263 }
264 rf->rf_on = bwi_rf_on_11bg;
265 rf->rf_off = bwi_rf_off_11bg;
266 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b;
267 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b;
268 break;
269 case IEEE80211_MODE_11G:
270 if (type != BWI_RF_T_BCM2050) {
271 device_printf(sc->sc_dev, "only BCM2050 RF "
272 "is supported for 11G PHY\n");
273 return ENXIO;
274 }
275 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
276 rf->rf_on = bwi_rf_on_11bg;
277 if (mac->mac_rev >= 5)
278 rf->rf_off = bwi_rf_off_11g_rev5;
279 else
280 rf->rf_off = bwi_rf_off_11bg;
281 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g;
282 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g;
283 break;
284 default:
285 device_printf(sc->sc_dev, "unsupported PHY mode\n");
286 return ENXIO;
287 }
288
289 rf->rf_type = type;
290 rf->rf_rev = rev;
291 rf->rf_manu = manu;
292 rf->rf_curchan = IEEE80211_CHAN_ANY;
293 rf->rf_ant_mode = BWI_ANT_MODE_AUTO;
294 return 0;
295 }
296
297 void
298 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around)
299 {
300 struct bwi_softc *sc = mac->mac_sc;
301
302 if (chan == IEEE80211_CHAN_ANY)
303 return;
304
305 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan);
306
307 /* TODO: 11A */
308
309 if (work_around)
310 bwi_rf_work_around(mac, chan);
311
312 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
313
314 if (chan == 14) {
315 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN)
316 HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN);
317 else
318 HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN);
319 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */
320 } else {
321 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */
322 }
323 DELAY(8000); /* DELAY(2000); */
324
325 mac->mac_rf.rf_curchan = chan;
326 }
327
328 void
329 bwi_rf_get_gains(struct bwi_mac *mac)
330 {
331 #define SAVE_PHY_MAX 15
332 #define SAVE_RF_MAX 3
333
334 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
335 { 0x52, 0x43, 0x7a };
336 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = {
337 0x0429, 0x0001, 0x0811, 0x0812,
338 0x0814, 0x0815, 0x005a, 0x0059,
339 0x0058, 0x000a, 0x0003, 0x080f,
340 0x0810, 0x002b, 0x0015
341 };
342
343 struct bwi_phy *phy = &mac->mac_phy;
344 struct bwi_rf *rf = &mac->mac_rf;
345 uint16_t save_phy[SAVE_PHY_MAX];
346 uint16_t save_rf[SAVE_RF_MAX];
347 uint16_t trsw;
348 int i, j, loop1_max, loop1, loop2;
349
350 /*
351 * Save PHY/RF registers for later restoration
352 */
353 for (i = 0; i < SAVE_PHY_MAX; ++i)
354 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
355 PHY_READ(mac, 0x2d); /* dummy read */
356
357 for (i = 0; i < SAVE_RF_MAX; ++i)
358 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
359
360 PHY_CLRBITS(mac, 0x429, 0xc000);
361 PHY_SETBITS(mac, 0x1, 0x8000);
362
363 PHY_SETBITS(mac, 0x811, 0x2);
364 PHY_CLRBITS(mac, 0x812, 0x2);
365 PHY_SETBITS(mac, 0x811, 0x1);
366 PHY_CLRBITS(mac, 0x812, 0x1);
367
368 PHY_SETBITS(mac, 0x814, 0x1);
369 PHY_CLRBITS(mac, 0x815, 0x1);
370 PHY_SETBITS(mac, 0x814, 0x2);
371 PHY_CLRBITS(mac, 0x815, 0x2);
372
373 PHY_SETBITS(mac, 0x811, 0xc);
374 PHY_SETBITS(mac, 0x812, 0xc);
375 PHY_SETBITS(mac, 0x811, 0x30);
376 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
377
378 PHY_WRITE(mac, 0x5a, 0x780);
379 PHY_WRITE(mac, 0x59, 0xc810);
380 PHY_WRITE(mac, 0x58, 0xd);
381 PHY_SETBITS(mac, 0xa, 0x2000);
382
383 PHY_SETBITS(mac, 0x814, 0x4);
384 PHY_CLRBITS(mac, 0x815, 0x4);
385
386 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
387
388 if (rf->rf_rev == 8) {
389 loop1_max = 15;
390 RF_WRITE(mac, 0x43, loop1_max);
391 } else {
392 loop1_max = 9;
393 RF_WRITE(mac, 0x52, 0x0);
394 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max);
395 }
396
397 bwi_phy_set_bbp_atten(mac, 11);
398
399 if (phy->phy_rev >= 3)
400 PHY_WRITE(mac, 0x80f, 0xc020);
401 else
402 PHY_WRITE(mac, 0x80f, 0x8020);
403 PHY_WRITE(mac, 0x810, 0);
404
405 PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1);
406 PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800);
407 PHY_SETBITS(mac, 0x811, 0x100);
408 PHY_CLRBITS(mac, 0x812, 0x3000);
409
410 if ((mac->mac_sc->sc_card_flags & BWI_CARD_F_EXT_LNA) &&
411 phy->phy_rev >= 7) {
412 PHY_SETBITS(mac, 0x811, 0x800);
413 PHY_SETBITS(mac, 0x812, 0x8000);
414 }
415 RF_CLRBITS(mac, 0x7a, 0xff08);
416
417 /*
418 * Find out 'loop1/loop2', which will be used to calculate
419 * max loopback gain later
420 */
421 j = 0;
422 for (i = 0; i < loop1_max; ++i) {
423 for (j = 0; j < 16; ++j) {
424 RF_WRITE(mac, 0x43, i);
425
426 if (bwi_rf_gain_max_reached(mac, j))
427 goto loop1_exit;
428 }
429 }
430 loop1_exit:
431 loop1 = i;
432 loop2 = j;
433
434 /*
435 * Find out 'trsw', which will be used to calculate
436 * TRSW(TX/RX switch) RX gain later
437 */
438 if (loop2 >= 8) {
439 PHY_SETBITS(mac, 0x812, 0x30);
440 trsw = 0x1b;
441 for (i = loop2 - 8; i < 16; ++i) {
442 trsw -= 3;
443 if (bwi_rf_gain_max_reached(mac, i))
444 break;
445 }
446 } else {
447 trsw = 0x18;
448 }
449
450 /*
451 * Restore saved PHY/RF registers
452 */
453 /* First 4 saved PHY registers need special processing */
454 for (i = 4; i < SAVE_PHY_MAX; ++i)
455 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
456
457 bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten);
458
459 for (i = 0; i < SAVE_RF_MAX; ++i)
460 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
461
462 PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3);
463 DELAY(10);
464 PHY_WRITE(mac, save_phy_regs[2], save_phy[2]);
465 PHY_WRITE(mac, save_phy_regs[3], save_phy[3]);
466 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
467 PHY_WRITE(mac, save_phy_regs[1], save_phy[1]);
468
469 /*
470 * Calculate gains
471 */
472 rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11;
473 rf->rf_rx_gain = trsw * 2;
474 DPRINTF(mac->mac_sc, "lo gain: %u, rx gain: %u\n",
475 rf->rf_lo_gain, rf->rf_rx_gain);
476
477 #undef SAVE_RF_MAX
478 #undef SAVE_PHY_MAX
479 }
480
481 void
482 bwi_rf_init(struct bwi_mac *mac)
483 {
484 struct bwi_rf *rf = &mac->mac_rf;
485
486 if (rf->rf_type == BWI_RF_T_BCM2060) {
487 /* TODO: 11A */
488 } else {
489 if (rf->rf_flags & BWI_RF_F_INITED)
490 RF_WRITE(mac, 0x78, rf->rf_calib);
491 else
492 bwi_rf_init_bcm2050(mac);
493 }
494 }
495
496 static void
497 bwi_rf_off_11a(struct bwi_mac *mac)
498 {
499 RF_WRITE(mac, 0x4, 0xff);
500 RF_WRITE(mac, 0x5, 0xfb);
501
502 PHY_SETBITS(mac, 0x10, 0x8);
503 PHY_SETBITS(mac, 0x11, 0x8);
504
505 PHY_WRITE(mac, 0x15, 0xaa00);
506 }
507
508 static void
509 bwi_rf_off_11bg(struct bwi_mac *mac)
510 {
511 PHY_WRITE(mac, 0x15, 0xaa00);
512 }
513
514 static void
515 bwi_rf_off_11g_rev5(struct bwi_mac *mac)
516 {
517 PHY_SETBITS(mac, 0x811, 0x8c);
518 PHY_CLRBITS(mac, 0x812, 0x8c);
519 }
520
521 static void
522 bwi_rf_work_around(struct bwi_mac *mac, u_int chan)
523 {
524 struct bwi_softc *sc = mac->mac_sc;
525 struct bwi_rf *rf = &mac->mac_rf;
526
527 if (chan == IEEE80211_CHAN_ANY) {
528 if_printf(&mac->mac_sc->sc_ic.ic_if,
529 "%s invalid channel!!\n", __func__);
530 return;
531 }
532
533 if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6)
534 return;
535
536 if (chan <= 10)
537 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
538 else
539 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
540 DELAY(1000);
541 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
542 }
543
544 static __inline struct bwi_rf_lo *
545 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
546 {
547 uint16_t rf_atten, bbp_atten;
548 int remap_rf_atten;
549
550 remap_rf_atten = 1;
551 if (tpctl == NULL) {
552 bbp_atten = 2;
553 rf_atten = 3;
554 } else {
555 if (tpctl->tp_ctrl1 == 3)
556 remap_rf_atten = 0;
557
558 bbp_atten = tpctl->bbp_atten;
559 rf_atten = tpctl->rf_atten;
560
561 if (bbp_atten > 6)
562 bbp_atten = 6;
563 }
564
565 if (remap_rf_atten) {
566 #define MAP_MAX 10
567 static const uint16_t map[MAP_MAX] =
568 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
569
570 #if 0
571 KKASSERT(rf_atten < MAP_MAX);
572 rf_atten = map[rf_atten];
573 #else
574 if (rf_atten >= MAP_MAX) {
575 rf_atten = 0; /* XXX */
576 } else {
577 rf_atten = map[rf_atten];
578 }
579 #endif
580 #undef MAP_MAX
581 }
582
583 return bwi_get_rf_lo(mac, rf_atten, bbp_atten);
584 }
585
586 void
587 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
588 {
589 const struct bwi_rf_lo *lo;
590
591 lo = bwi_rf_lo_find(mac, tpctl);
592 RF_LO_WRITE(mac, lo);
593 }
594
595 static void
596 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
597 {
598 uint16_t val;
599
600 val = (uint8_t)lo->ctrl_lo;
601 val |= ((uint8_t)lo->ctrl_hi) << 8;
602
603 PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
604 }
605
606 static int
607 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx)
608 {
609 PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8);
610 PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000);
611 PHY_SETBITS(mac, 0x15, 0xf000);
612
613 DELAY(20);
614
615 return (PHY_READ(mac, 0x2d) >= 0xdfc);
616 }
617
618 /* XXX use bitmap array */
619 static __inline uint16_t
620 bitswap4(uint16_t val)
621 {
622 uint16_t ret;
623
624 ret = (val & 0x8) >> 3;
625 ret |= (val & 0x4) >> 1;
626 ret |= (val & 0x2) << 1;
627 ret |= (val & 0x1) << 3;
628 return ret;
629 }
630
631 static __inline uint16_t
632 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd)
633 {
634 struct bwi_softc *sc = mac->mac_sc;
635 struct bwi_phy *phy = &mac->mac_phy;
636 struct bwi_rf *rf = &mac->mac_rf;
637 uint16_t lo_gain, ext_lna, loop;
638
639 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
640 return 0;
641
642 lo_gain = rf->rf_lo_gain;
643 if (rf->rf_rev == 8)
644 lo_gain += 0x3e;
645 else
646 lo_gain += 0x26;
647
648 if (lo_gain >= 0x46) {
649 lo_gain -= 0x46;
650 ext_lna = 0x3000;
651 } else if (lo_gain >= 0x3a) {
652 lo_gain -= 0x3a;
653 ext_lna = 0x1000;
654 } else if (lo_gain >= 0x2e) {
655 lo_gain -= 0x2e;
656 ext_lna = 0x2000;
657 } else {
658 lo_gain -= 0x10;
659 ext_lna = 0;
660 }
661
662 for (loop = 0; loop < 16; ++loop) {
663 lo_gain -= (6 * loop);
664 if (lo_gain < 6)
665 break;
666 }
667
668 if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {
669 if (ext_lna)
670 ext_lna |= 0x8000;
671 ext_lna |= (loop << 8);
672 switch (lpd) {
673 case 0x011:
674 return 0x8f92;
675 case 0x001:
676 return (0x8092 | ext_lna);
677 case 0x101:
678 return (0x2092 | ext_lna);
679 case 0x100:
680 return (0x2093 | ext_lna);
681 default:
682 panic("unsupported lpd\n");
683 }
684 } else {
685 ext_lna |= (loop << 8);
686 switch (lpd) {
687 case 0x011:
688 return 0xf92;
689 case 0x001:
690 case 0x101:
691 return (0x92 | ext_lna);
692 case 0x100:
693 return (0x93 | ext_lna);
694 default:
695 panic("unsupported lpd\n");
696 }
697 }
698
699 panic("never reached\n");
700 return 0;
701 }
702
703 void
704 bwi_rf_init_bcm2050(struct bwi_mac *mac)
705 {
706 #define SAVE_RF_MAX 3
707 #define SAVE_PHY_COMM_MAX 4
708 #define SAVE_PHY_11G_MAX 6
709
710 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
711 { 0x0043, 0x0051, 0x0052 };
712 static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] =
713 { 0x0015, 0x005a, 0x0059, 0x0058 };
714 static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] =
715 { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 };
716
717 uint16_t save_rf[SAVE_RF_MAX];
718 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
719 uint16_t save_phy_11g[SAVE_PHY_11G_MAX];
720 uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0;
721 uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex;
722 uint16_t phy812_val;
723 uint16_t calib;
724 uint32_t test_lim, test;
725 struct bwi_softc *sc = mac->mac_sc;
726 struct bwi_phy *phy = &mac->mac_phy;
727 struct bwi_rf *rf = &mac->mac_rf;
728 int i;
729
730 /*
731 * Save registers for later restoring
732 */
733 for (i = 0; i < SAVE_RF_MAX; ++i)
734 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
735 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
736 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]);
737
738 if (phy->phy_mode == IEEE80211_MODE_11B) {
739 phyr_30 = PHY_READ(mac, 0x30);
740 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
741
742 PHY_WRITE(mac, 0x30, 0xff);
743 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
744 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
745 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
746 save_phy_11g[i] =
747 PHY_READ(mac, save_phy_regs_11g[i]);
748 }
749
750 PHY_SETBITS(mac, 0x814, 0x3);
751 PHY_CLRBITS(mac, 0x815, 0x3);
752 PHY_CLRBITS(mac, 0x429, 0x8000);
753 PHY_CLRBITS(mac, 0x802, 0x3);
754
755 phyr_80f = PHY_READ(mac, 0x80f);
756 phyr_810 = PHY_READ(mac, 0x810);
757
758 if (phy->phy_rev >= 3)
759 PHY_WRITE(mac, 0x80f, 0xc020);
760 else
761 PHY_WRITE(mac, 0x80f, 0x8020);
762 PHY_WRITE(mac, 0x810, 0);
763
764 phy812_val = bwi_phy812_value(mac, 0x011);
765 PHY_WRITE(mac, 0x812, phy812_val);
766 if (phy->phy_rev < 7 ||
767 (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0)
768 PHY_WRITE(mac, 0x811, 0x1b3);
769 else
770 PHY_WRITE(mac, 0x811, 0x9b3);
771 }
772 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
773
774 phyr_35 = PHY_READ(mac, 0x35);
775 PHY_CLRBITS(mac, 0x35, 0x80);
776
777 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
778 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
779
780 if (phy->phy_version == 0) {
781 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
782 } else {
783 if (phy->phy_version >= 2)
784 PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40);
785 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
786 }
787
788 calib = bwi_rf_calibval(mac);
789
790 if (phy->phy_mode == IEEE80211_MODE_11B)
791 RF_WRITE(mac, 0x78, 0x26);
792
793 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
794 phy812_val = bwi_phy812_value(mac, 0x011);
795 PHY_WRITE(mac, 0x812, phy812_val);
796 }
797
798 PHY_WRITE(mac, 0x15, 0xbfaf);
799 PHY_WRITE(mac, 0x2b, 0x1403);
800
801 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
802 phy812_val = bwi_phy812_value(mac, 0x001);
803 PHY_WRITE(mac, 0x812, phy812_val);
804 }
805
806 PHY_WRITE(mac, 0x15, 0xbfa0);
807
808 RF_SETBITS(mac, 0x51, 0x4);
809 if (rf->rf_rev == 8) {
810 RF_WRITE(mac, 0x43, 0x1f);
811 } else {
812 RF_WRITE(mac, 0x52, 0);
813 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
814 }
815
816 test_lim = 0;
817 PHY_WRITE(mac, 0x58, 0);
818 for (i = 0; i < 16; ++i) {
819 PHY_WRITE(mac, 0x5a, 0x480);
820 PHY_WRITE(mac, 0x59, 0xc810);
821
822 PHY_WRITE(mac, 0x58, 0xd);
823 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
824 phy812_val = bwi_phy812_value(mac, 0x101);
825 PHY_WRITE(mac, 0x812, phy812_val);
826 }
827 PHY_WRITE(mac, 0x15, 0xafb0);
828 DELAY(10);
829
830 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
831 phy812_val = bwi_phy812_value(mac, 0x101);
832 PHY_WRITE(mac, 0x812, phy812_val);
833 }
834 PHY_WRITE(mac, 0x15, 0xefb0);
835 DELAY(10);
836
837 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
838 phy812_val = bwi_phy812_value(mac, 0x100);
839 PHY_WRITE(mac, 0x812, phy812_val);
840 }
841 PHY_WRITE(mac, 0x15, 0xfff0);
842 DELAY(20);
843
844 test_lim += PHY_READ(mac, 0x2d);
845
846 PHY_WRITE(mac, 0x58, 0);
847 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
848 phy812_val = bwi_phy812_value(mac, 0x101);
849 PHY_WRITE(mac, 0x812, phy812_val);
850 }
851 PHY_WRITE(mac, 0x15, 0xafb0);
852 }
853 ++test_lim;
854 test_lim >>= 9;
855
856 DELAY(10);
857
858 test = 0;
859 PHY_WRITE(mac, 0x58, 0);
860 for (i = 0; i < 16; ++i) {
861 int j;
862
863 rfr_78 = (bitswap4(i) << 1) | 0x20;
864 RF_WRITE(mac, 0x78, rfr_78);
865 DELAY(10);
866
867 /* NB: This block is slight different than the above one */
868 for (j = 0; j < 16; ++j) {
869 PHY_WRITE(mac, 0x5a, 0xd80);
870 PHY_WRITE(mac, 0x59, 0xc810);
871
872 PHY_WRITE(mac, 0x58, 0xd);
873 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
874 phy->phy_rev >= 2) {
875 phy812_val = bwi_phy812_value(mac, 0x101);
876 PHY_WRITE(mac, 0x812, phy812_val);
877 }
878 PHY_WRITE(mac, 0x15, 0xafb0);
879 DELAY(10);
880
881 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
882 phy->phy_rev >= 2) {
883 phy812_val = bwi_phy812_value(mac, 0x101);
884 PHY_WRITE(mac, 0x812, phy812_val);
885 }
886 PHY_WRITE(mac, 0x15, 0xefb0);
887 DELAY(10);
888
889 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
890 phy->phy_rev >= 2) {
891 phy812_val = bwi_phy812_value(mac, 0x100);
892 PHY_WRITE(mac, 0x812, phy812_val);
893 }
894 PHY_WRITE(mac, 0x15, 0xfff0);
895 DELAY(10);
896
897 test += PHY_READ(mac, 0x2d);
898
899 PHY_WRITE(mac, 0x58, 0);
900 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
901 phy->phy_rev >= 2) {
902 phy812_val = bwi_phy812_value(mac, 0x101);
903 PHY_WRITE(mac, 0x812, phy812_val);
904 }
905 PHY_WRITE(mac, 0x15, 0xafb0);
906 }
907
908 ++test;
909 test >>= 8;
910
911 if (test > test_lim)
912 break;
913 }
914 if (i > 15)
915 rf->rf_calib = rfr_78;
916 else
917 rf->rf_calib = calib;
918 if (rf->rf_calib != 0xffff) {
919 DPRINTF(sc, "RF calibration value: 0x%04x\n", rf->rf_calib);
920 rf->rf_flags |= BWI_RF_F_INITED;
921 }
922
923 /*
924 * Restore trashes registers
925 */
926 PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]);
927
928 for (i = 0; i < SAVE_RF_MAX; ++i) {
929 int pos = (i + 1) % SAVE_RF_MAX;
930
931 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]);
932 }
933 for (i = 1; i < SAVE_PHY_COMM_MAX; ++i)
934 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]);
935
936 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
937 if (phy->phy_version != 0)
938 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
939
940 PHY_WRITE(mac, 0x35, phyr_35);
941 bwi_rf_work_around(mac, rf->rf_curchan);
942
943 if (phy->phy_mode == IEEE80211_MODE_11B) {
944 PHY_WRITE(mac, 0x30, phyr_30);
945 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
946 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
947 /* XXX Spec only says when PHY is linked (gmode) */
948 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
949
950 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
951 PHY_WRITE(mac, save_phy_regs_11g[i],
952 save_phy_11g[i]);
953 }
954
955 PHY_WRITE(mac, 0x80f, phyr_80f);
956 PHY_WRITE(mac, 0x810, phyr_810);
957 }
958
959 #undef SAVE_PHY_11G_MAX
960 #undef SAVE_PHY_COMM_MAX
961 #undef SAVE_RF_MAX
962 }
963
964 static uint16_t
965 bwi_rf_calibval(struct bwi_mac *mac)
966 {
967 /* http://bcm-specs.sipsolutions.net/RCCTable */
968 static const uint16_t rf_calibvals[] = {
969 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf,
970 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf
971 };
972 uint16_t val, calib;
973 int idx;
974
975 val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
976 idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
977 KKASSERT(idx < (int)(sizeof(rf_calibvals) / sizeof(rf_calibvals[0])));
978
979 calib = rf_calibvals[idx] << 1;
980 if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
981 calib |= 0x1;
982 calib |= 0x20;
983
984 return calib;
985 }
986
987 static __inline int32_t
988 _bwi_adjust_devide(int32_t num, int32_t den)
989 {
990 if (num < 0)
991 return (num / den);
992 else
993 return (num + den / 2) / den;
994 }
995
996 /*
997 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
998 * "calculating table entries"
999 */
1000 static int
1001 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[])
1002 {
1003 int32_t m1, m2, f, dbm;
1004 int i;
1005
1006 m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32);
1007 m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1);
1008
1009 #define ITER_MAX 16
1010
1011 f = 256;
1012 for (i = 0; i < ITER_MAX; ++i) {
1013 int32_t q, d;
1014
1015 q = _bwi_adjust_devide(
1016 f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048);
1017 d = abs(q - f);
1018 f = q;
1019
1020 if (d < 2)
1021 break;
1022 }
1023 if (i == ITER_MAX)
1024 return EINVAL;
1025
1026 #undef ITER_MAX
1027
1028 dbm = _bwi_adjust_devide(m1 * f, 8192);
1029 if (dbm < -127)
1030 dbm = -127;
1031 else if (dbm > 128)
1032 dbm = 128;
1033
1034 *txpwr = dbm;
1035 return 0;
1036 }
1037
1038 int
1039 bwi_rf_map_txpower(struct bwi_mac *mac)
1040 {
1041 struct bwi_softc *sc = mac->mac_sc;
1042 struct bwi_rf *rf = &mac->mac_rf;
1043 struct bwi_phy *phy = &mac->mac_phy;
1044 uint16_t sprom_ofs, val, mask;
1045 int16_t pa_params[3];
1046 int error = 0, i, ant_gain, reg_txpower_max;
1047
1048 /*
1049 * Find out max TX power
1050 */
1051 val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
1052 if (phy->phy_mode == IEEE80211_MODE_11A) {
1053 rf->rf_txpower_max = __SHIFTOUT(val,
1054 BWI_SPROM_MAX_TXPWR_MASK_11A);
1055 } else {
1056 rf->rf_txpower_max = __SHIFTOUT(val,
1057 BWI_SPROM_MAX_TXPWR_MASK_11BG);
1058
1059 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) &&
1060 phy->phy_mode == IEEE80211_MODE_11G)
1061 rf->rf_txpower_max -= 3;
1062 }
1063 if (rf->rf_txpower_max <= 0) {
1064 device_printf(sc->sc_dev, "invalid max txpower in sprom\n");
1065 rf->rf_txpower_max = 74;
1066 }
1067 DPRINTF(sc, "max txpower from sprom: %d dBm\n", rf->rf_txpower_max);
1068
1069 /*
1070 * Find out region/domain max TX power, which is adjusted
1071 * by antenna gain and 1.5 dBm fluctuation as mentioned
1072 * in v3 spec.
1073 */
1074 val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
1075 if (phy->phy_mode == IEEE80211_MODE_11A)
1076 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
1077 else
1078 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
1079 if (ant_gain == 0xff) {
1080 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n");
1081 ant_gain = 2;
1082 }
1083 ant_gain *= 4;
1084 DPRINTF(sc, "ant gain %d dBm\n", ant_gain);
1085
1086 reg_txpower_max = 90 - ant_gain - 6; /* XXX magic number */
1087 DPRINTF(sc, "region/domain max txpower %d dBm\n", reg_txpower_max);
1088
1089 /*
1090 * Force max TX power within region/domain TX power limit
1091 */
1092 if (rf->rf_txpower_max > reg_txpower_max)
1093 rf->rf_txpower_max = reg_txpower_max;
1094 DPRINTF(sc, "max txpower %d dBm\n", rf->rf_txpower_max);
1095
1096 /*
1097 * Create TSSI to TX power mapping
1098 */
1099
1100 if (sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1101 rf->rf_type != BWI_RF_T_BCM2050) {
1102 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1103 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0,
1104 sizeof(rf->rf_txpower_map0));
1105 goto back;
1106 }
1107
1108 #define IS_VALID_PA_PARAM(p) ((p) != 0 && (p) != -1)
1109 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
1110
1111 /*
1112 * Extract PA parameters
1113 */
1114 if (phy->phy_mode == IEEE80211_MODE_11A)
1115 sprom_ofs = BWI_SPROM_PA_PARAM_11A;
1116 else
1117 sprom_ofs = BWI_SPROM_PA_PARAM_11BG;
1118 for (i = 0; i < N(pa_params); ++i)
1119 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2));
1120
1121 for (i = 0; i < N(pa_params); ++i) {
1122 /*
1123 * If one of the PA parameters from SPROM is not valid,
1124 * fall back to the default values, if there are any.
1125 */
1126 if (!IS_VALID_PA_PARAM(pa_params[i])) {
1127 const int8_t *txpower_map;
1128
1129 if (phy->phy_mode == IEEE80211_MODE_11A) {
1130 if_printf(&sc->sc_ic.ic_if,
1131 "no tssi2dbm table for 11a PHY\n");
1132 return ENXIO;
1133 }
1134
1135 if (phy->phy_mode == IEEE80211_MODE_11G) {
1136 DPRINTF(sc, "%s\n", "use default 11g TSSI map");
1137 txpower_map = bwi_txpower_map_11g;
1138 } else {
1139 txpower_map = bwi_txpower_map_11b;
1140 }
1141
1142 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1143 bcopy(txpower_map, rf->rf_txpower_map0,
1144 sizeof(rf->rf_txpower_map0));
1145 goto back;
1146 }
1147 }
1148
1149 #undef N
1150
1151 /*
1152 * All of the PA parameters from SPROM are valid.
1153 */
1154
1155 /*
1156 * Extract idle TSSI from SPROM.
1157 */
1158 val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
1159 DPRINTF(sc, "sprom idle tssi: 0x%04x\n", val);
1160
1161 if (phy->phy_mode == IEEE80211_MODE_11A)
1162 mask = BWI_SPROM_IDLE_TSSI_MASK_11A;
1163 else
1164 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;
1165
1166 rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
1167 if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0))
1168 rf->rf_idle_tssi0 = 62;
1169
1170 #undef IS_VALID_PA_PARAM
1171
1172 /*
1173 * Calculate TX power map, which is indexed by TSSI
1174 */
1175 device_printf(sc->sc_dev, "TSSI-TX power map:\n");
1176 for (i = 0; i < BWI_TSSI_MAX; ++i) {
1177 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i,
1178 pa_params);
1179 if (error) {
1180 if_printf(&sc->sc_ic.ic_if,
1181 "bwi_rf_calc_txpower failed\n");
1182 break;
1183 }
1184 if (i != 0 && i % 8 == 0)
1185 kprintf("\n");
1186 kprintf("%d ", rf->rf_txpower_map0[i]);
1187 }
1188 kprintf("\n");
1189 back:
1190 DPRINTF(sc, "idle tssi0: %d\n", rf->rf_idle_tssi0);
1191 return error;
1192 }
1193
1194 void
1195 bwi_rf_lo_update(struct bwi_mac *mac)
1196 {
1197 struct bwi_softc *sc = mac->mac_sc;
1198 struct ifnet *ifp = &sc->sc_ic.ic_if;
1199 struct bwi_rf *rf = &mac->mac_rf;
1200 struct bwi_phy *phy = &mac->mac_phy;
1201 struct bwi_tpctl *tpctl = &mac->mac_tpctl;
1202 struct rf_saveregs regs;
1203 uint16_t ant_div, chan_ex;
1204 uint8_t devi_ctrl;
1205 u_int orig_chan;
1206
1207 /*
1208 * Save RF/PHY registers for later restoration
1209 */
1210 orig_chan = rf->rf_curchan;
1211 bzero(&regs, sizeof(regs));
1212
1213 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1214 SAVE_PHY_REG(mac, &regs, 429);
1215 SAVE_PHY_REG(mac, &regs, 802);
1216
1217 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1218 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1219 }
1220
1221 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1222 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
1223 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1224
1225 SAVE_PHY_REG(mac, &regs, 15);
1226 SAVE_PHY_REG(mac, &regs, 2a);
1227 SAVE_PHY_REG(mac, &regs, 35);
1228 SAVE_PHY_REG(mac, &regs, 60);
1229 SAVE_RF_REG(mac, &regs, 43);
1230 SAVE_RF_REG(mac, &regs, 7a);
1231 SAVE_RF_REG(mac, &regs, 52);
1232 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1233 SAVE_PHY_REG(mac, &regs, 811);
1234 SAVE_PHY_REG(mac, &regs, 812);
1235 SAVE_PHY_REG(mac, &regs, 814);
1236 SAVE_PHY_REG(mac, &regs, 815);
1237 }
1238
1239 /* Force to channel 6 */
1240 bwi_rf_set_chan(mac, 6, 0);
1241
1242 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1243 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1244 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1245 bwi_mac_dummy_xmit(mac);
1246 }
1247 RF_WRITE(mac, 0x43, 0x6);
1248
1249 bwi_phy_set_bbp_atten(mac, 2);
1250
1251 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
1252
1253 PHY_WRITE(mac, 0x2e, 0x7f);
1254 PHY_WRITE(mac, 0x80f, 0x78);
1255 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
1256 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
1257 PHY_WRITE(mac, 0x2b, 0x203);
1258 PHY_WRITE(mac, 0x2a, 0x8a3);
1259
1260 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1261 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);
1262 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);
1263 PHY_WRITE(mac, 0x811, 0x1b3);
1264 PHY_WRITE(mac, 0x812, 0xb2);
1265 }
1266
1267 if ((ifp->if_flags & IFF_RUNNING) == 0)
1268 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac);
1269 PHY_WRITE(mac, 0x80f, 0x8078);
1270
1271 /*
1272 * Measure all RF LO
1273 */
1274 devi_ctrl = _bwi_rf_lo_update(mac, regs.rf_7a);
1275
1276 /*
1277 * Restore saved RF/PHY registers
1278 */
1279 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1280 PHY_WRITE(mac, 0x15, 0xe300);
1281 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0);
1282 DELAY(5);
1283 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2);
1284 DELAY(2);
1285 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3);
1286 } else {
1287 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0);
1288 }
1289
1290 if ((ifp->if_flags & IFF_RUNNING) == 0)
1291 tpctl = NULL;
1292 bwi_rf_lo_adjust(mac, tpctl);
1293
1294 PHY_WRITE(mac, 0x2e, 0x807f);
1295 if (phy->phy_flags & BWI_PHY_F_LINKED)
1296 PHY_WRITE(mac, 0x2f, 0x202);
1297 else
1298 PHY_WRITE(mac, 0x2f, 0x101);
1299
1300 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1301
1302 RESTORE_PHY_REG(mac, &regs, 15);
1303 RESTORE_PHY_REG(mac, &regs, 2a);
1304 RESTORE_PHY_REG(mac, &regs, 35);
1305 RESTORE_PHY_REG(mac, &regs, 60);
1306
1307 RESTORE_RF_REG(mac, &regs, 43);
1308 RESTORE_RF_REG(mac, &regs, 7a);
1309
1310 regs.rf_52 &= 0xf0;
1311 regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);
1312 RF_WRITE(mac, 0x52, regs.rf_52);
1313
1314 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1315
1316 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1317 RESTORE_PHY_REG(mac, &regs, 811);
1318 RESTORE_PHY_REG(mac, &regs, 812);
1319 RESTORE_PHY_REG(mac, &regs, 814);
1320 RESTORE_PHY_REG(mac, &regs, 815);
1321 RESTORE_PHY_REG(mac, &regs, 429);
1322 RESTORE_PHY_REG(mac, &regs, 802);
1323 }
1324
1325 bwi_rf_set_chan(mac, orig_chan, 1);
1326 }
1327
1328 static uint32_t
1329 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
1330 {
1331 struct bwi_phy *phy = &mac->mac_phy;
1332 uint32_t devi = 0;
1333 int i;
1334
1335 if (phy->phy_flags & BWI_PHY_F_LINKED)
1336 ctrl <<= 8;
1337
1338 for (i = 0; i < 8; ++i) {
1339 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1340 PHY_WRITE(mac, 0x15, 0xe300);
1341 PHY_WRITE(mac, 0x812, ctrl | 0xb0);
1342 DELAY(5);
1343 PHY_WRITE(mac, 0x812, ctrl | 0xb2);
1344 DELAY(2);
1345 PHY_WRITE(mac, 0x812, ctrl | 0xb3);
1346 DELAY(4);
1347 PHY_WRITE(mac, 0x15, 0xf300);
1348 } else {
1349 PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
1350 DELAY(2);
1351 PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
1352 DELAY(4);
1353 PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
1354 }
1355 DELAY(8);
1356 devi += PHY_READ(mac, 0x2d);
1357 }
1358 return devi;
1359 }
1360
1361 static uint16_t
1362 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac)
1363 {
1364 uint32_t devi_min;
1365 uint16_t tp_ctrl2 = 0;
1366 int i;
1367
1368 RF_WRITE(mac, 0x52, 0);
1369 DELAY(10);
1370 devi_min = bwi_rf_lo_devi_measure(mac, 0);
1371
1372 for (i = 0; i < 16; ++i) {
1373 uint32_t devi;
1374
1375 RF_WRITE(mac, 0x52, i);
1376 DELAY(10);
1377 devi = bwi_rf_lo_devi_measure(mac, 0);
1378
1379 if (devi < devi_min) {
1380 devi_min = devi;
1381 tp_ctrl2 = i;
1382 }
1383 }
1384 return tp_ctrl2;
1385 }
1386
1387 static uint8_t
1388 _bwi_rf_lo_update(struct bwi_mac *mac, uint16_t orig_rf7a)
1389 {
1390 #define RF_ATTEN_LISTSZ 14
1391 #define BBP_ATTEN_MAX 4 /* half */
1392
1393 static const int rf_atten_list[RF_ATTEN_LISTSZ] =
1394 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 };
1395 static const int rf_atten_init_list[RF_ATTEN_LISTSZ] =
1396 { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 };
1397 static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] =
1398 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 };
1399
1400 struct ifnet *ifp = &mac->mac_sc->sc_ic.ic_if;
1401 struct bwi_rf_lo lo_save, *lo;
1402 uint8_t devi_ctrl = 0;
1403 int idx, adj_rf7a = 0;
1404
1405 bzero(&lo_save, sizeof(lo_save));
1406 for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) {
1407 int init_rf_atten = rf_atten_init_list[idx];
1408 int rf_atten = rf_atten_list[idx];
1409 int bbp_atten;
1410
1411 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) {
1412 uint16_t tp_ctrl2, rf7a;
1413
1414 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1415 if (idx == 0) {
1416 bzero(&lo_save, sizeof(lo_save));
1417 } else if (init_rf_atten < 0) {
1418 lo = bwi_get_rf_lo(mac,
1419 rf_atten, 2 * bbp_atten);
1420 bcopy(lo, &lo_save, sizeof(lo_save));
1421 } else {
1422 lo = bwi_get_rf_lo(mac,
1423 init_rf_atten, 0);
1424 bcopy(lo, &lo_save, sizeof(lo_save));
1425 }
1426
1427 devi_ctrl = 0;
1428 adj_rf7a = 0;
1429
1430 /*
1431 * XXX
1432 * Linux driver overflows 'val'
1433 */
1434 if (init_rf_atten >= 0) {
1435 int val;
1436
1437 val = rf_atten * 2 + bbp_atten;
1438 if (val > 14) {
1439 adj_rf7a = 1;
1440 if (val > 17)
1441 devi_ctrl = 1;
1442 if (val > 19)
1443 devi_ctrl = 2;
1444 }
1445 }
1446 } else {
1447 lo = bwi_get_rf_lo(mac,
1448 rf_atten, 2 * bbp_atten);
1449 if (!bwi_rf_lo_isused(mac, lo))
1450 continue;
1451 bcopy(lo, &lo_save, sizeof(lo_save));
1452
1453 devi_ctrl = 3;
1454 adj_rf7a = 0;
1455 }
1456
1457 RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten);
1458
1459 tp_ctrl2 = mac->mac_tpctl.tp_ctrl2;
1460 if (init_rf_atten < 0)
1461 tp_ctrl2 |= (3 << 4);
1462 RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2);
1463
1464 DELAY(10);
1465
1466 bwi_phy_set_bbp_atten(mac, bbp_atten * 2);
1467
1468 rf7a = orig_rf7a & 0xfff0;
1469 if (adj_rf7a)
1470 rf7a |= 0x8;
1471 RF_WRITE(mac, 0x7a, rf7a);
1472
1473 lo = bwi_get_rf_lo(mac,
1474 rf_lo_measure_order[idx], bbp_atten * 2);
1475 bwi_rf_lo_measure(mac, &lo_save, lo, devi_ctrl);
1476 }
1477 }
1478 return devi_ctrl;
1479
1480 #undef RF_ATTEN_LISTSZ
1481 #undef BBP_ATTEN_MAX
1482 }
1483
1484 static void
1485 bwi_rf_lo_measure(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo,
1486 struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl)
1487 {
1488 #define LO_ADJUST_MIN 1
1489 #define LO_ADJUST_MAX 8
1490 #define LO_ADJUST(hi, lo) { .ctrl_hi = hi, .ctrl_lo = lo }
1491 static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = {
1492 LO_ADJUST(1, 1),
1493 LO_ADJUST(1, 0),
1494 LO_ADJUST(1, -1),
1495 LO_ADJUST(0, -1),
1496 LO_ADJUST(-1, -1),
1497 LO_ADJUST(-1, 0),
1498 LO_ADJUST(-1, 1),
1499 LO_ADJUST(0, 1)
1500 };
1501 #undef LO_ADJUST
1502
1503 struct bwi_rf_lo lo_min;
1504 uint32_t devi_min;
1505 int found, loop_count, adjust_state;
1506
1507 bcopy(src_lo, &lo_min, sizeof(lo_min));
1508 RF_LO_WRITE(mac, &lo_min);
1509 devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1510
1511 loop_count = 12; /* XXX */
1512 adjust_state = 0;
1513 do {
1514 struct bwi_rf_lo lo_base;
1515 int i, fin;
1516
1517 found = 0;
1518 if (adjust_state == 0) {
1519 i = LO_ADJUST_MIN;
1520 fin = LO_ADJUST_MAX;
1521 } else if (adjust_state % 2 == 0) {
1522 i = adjust_state - 1;
1523 fin = adjust_state + 1;
1524 } else {
1525 i = adjust_state - 2;
1526 fin = adjust_state + 2;
1527 }
1528
1529 if (i < LO_ADJUST_MIN)
1530 i += LO_ADJUST_MAX;
1531 KKASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN);
1532
1533 if (fin > LO_ADJUST_MAX)
1534 fin -= LO_ADJUST_MAX;
1535 KKASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN);
1536
1537 bcopy(&lo_min, &lo_base, sizeof(lo_base));
1538 for (;;) {
1539 struct bwi_rf_lo lo;
1540
1541 lo.ctrl_hi = lo_base.ctrl_hi +
1542 rf_lo_adjust[i - 1].ctrl_hi;
1543 lo.ctrl_lo = lo_base.ctrl_lo +
1544 rf_lo_adjust[i - 1].ctrl_lo;
1545
1546 if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) {
1547 uint32_t devi;
1548
1549 RF_LO_WRITE(mac, &lo);
1550 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1551 if (devi < devi_min) {
1552 devi_min = devi;
1553 adjust_state = i;
1554 found = 1;
1555 bcopy(&lo, &lo_min, sizeof(lo_min));
1556 }
1557 }
1558 if (i == fin)
1559 break;
1560 if (i == LO_ADJUST_MAX)
1561 i = LO_ADJUST_MIN;
1562 else
1563 ++i;
1564 }
1565 } while (loop_count-- && found);
1566
1567 bcopy(&lo_min, dst_lo, sizeof(*dst_lo));
1568
1569 #undef LO_ADJUST_MIN
1570 #undef LO_ADJUST_MAX
1571 }
1572
1573 static void
1574 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac)
1575 {
1576 #define SAVE_RF_MAX 3
1577 #define SAVE_PHY_MAX 8
1578
1579 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1580 { 0x7a, 0x52, 0x43 };
1581 static const uint16_t save_phy_regs[SAVE_PHY_MAX] =
1582 { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 };
1583
1584 struct bwi_softc *sc = mac->mac_sc;
1585 struct bwi_rf *rf = &mac->mac_rf;
1586 struct bwi_phy *phy = &mac->mac_phy;
1587 uint16_t save_rf[SAVE_RF_MAX];
1588 uint16_t save_phy[SAVE_PHY_MAX];
1589 uint16_t ant_div, bbp_atten, chan_ex;
1590 int16_t nrssi[2];
1591 int i;
1592
1593 /*
1594 * Save RF/PHY registers for later restoration
1595 */
1596 for (i = 0; i < SAVE_RF_MAX; ++i)
1597 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1598 for (i = 0; i < SAVE_PHY_MAX; ++i)
1599 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
1600
1601 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1602 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1603 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1604
1605 /*
1606 * Calculate nrssi0
1607 */
1608 if (phy->phy_rev >= 5)
1609 RF_CLRBITS(mac, 0x7a, 0xff80);
1610 else
1611 RF_CLRBITS(mac, 0x7a, 0xfff0);
1612 PHY_WRITE(mac, 0x30, 0xff);
1613
1614 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
1615
1616 PHY_WRITE(mac, 0x26, 0);
1617 PHY_SETBITS(mac, 0x15, 0x20);
1618 PHY_WRITE(mac, 0x2a, 0x8a3);
1619 RF_SETBITS(mac, 0x7a, 0x80);
1620
1621 nrssi[0] = (int16_t)PHY_READ(mac, 0x27);
1622
1623 /*
1624 * Calculate nrssi1
1625 */
1626 RF_CLRBITS(mac, 0x7a, 0xff80);
1627 if (phy->phy_version >= 2)
1628 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
1629 else if (phy->phy_version == 0)
1630 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
1631 else
1632 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff);
1633
1634 PHY_WRITE(mac, 0x20, 0x3f3f);
1635 PHY_WRITE(mac, 0x15, 0xf330);
1636
1637 RF_WRITE(mac, 0x5a, 0x60);
1638 RF_CLRBITS(mac, 0x43, 0xff0f);
1639
1640 PHY_WRITE(mac, 0x5a, 0x480);
1641 PHY_WRITE(mac, 0x59, 0x810);
1642 PHY_WRITE(mac, 0x58, 0xd);
1643
1644 DELAY(20);
1645
1646 nrssi[1] = (int16_t)PHY_READ(mac, 0x27);
1647
1648 /*
1649 * Restore saved RF/PHY registers
1650 */
1651 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
1652 RF_WRITE(mac, save_rf_regs[0], save_rf[0]);
1653
1654 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1655
1656 for (i = 1; i < 4; ++i)
1657 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1658
1659 bwi_rf_work_around(mac, rf->rf_curchan);
1660
1661 if (phy->phy_version != 0)
1662 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1663
1664 for (; i < SAVE_PHY_MAX; ++i)
1665 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1666
1667 for (i = 1; i < SAVE_RF_MAX; ++i)
1668 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1669
1670 /*
1671 * Install calculated narrow RSSI values
1672 */
1673 if (nrssi[0] == nrssi[1])
1674 rf->rf_nrssi_slope = 0x10000;
1675 else
1676 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1677 if (nrssi[0] <= -4) {
1678 rf->rf_nrssi[0] = nrssi[0];
1679 rf->rf_nrssi[1] = nrssi[1];
1680 }
1681
1682 #undef SAVE_RF_MAX
1683 #undef SAVE_PHY_MAX
1684 }
1685
1686 static void
1687 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac)
1688 {
1689 #define SAVE_RF_MAX 2
1690 #define SAVE_PHY_COMM_MAX 10
1691 #define SAVE_PHY6_MAX 8
1692
1693 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1694 { 0x7a, 0x43 };
1695 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = {
1696 0x0001, 0x0811, 0x0812, 0x0814,
1697 0x0815, 0x005a, 0x0059, 0x0058,
1698 0x000a, 0x0003
1699 };
1700 static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = {
1701 0x002e, 0x002f, 0x080f, 0x0810,
1702 0x0801, 0x0060, 0x0014, 0x0478
1703 };
1704
1705 struct bwi_phy *phy = &mac->mac_phy;
1706 uint16_t save_rf[SAVE_RF_MAX];
1707 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1708 uint16_t save_phy6[SAVE_PHY6_MAX];
1709 uint16_t rf7b = 0xffff;
1710 int16_t nrssi;
1711 int i, phy6_idx = 0;
1712
1713 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1714 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1715 for (i = 0; i < SAVE_RF_MAX; ++i)
1716 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1717
1718 PHY_CLRBITS(mac, 0x429, 0x8000);
1719 PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000);
1720 PHY_SETBITS(mac, 0x811, 0xc);
1721 PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4);
1722 PHY_CLRBITS(mac, 0x802, 0x3);
1723
1724 if (phy->phy_rev >= 6) {
1725 for (i = 0; i < SAVE_PHY6_MAX; ++i)
1726 save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]);
1727
1728 PHY_WRITE(mac, 0x2e, 0);
1729 PHY_WRITE(mac, 0x2f, 0);
1730 PHY_WRITE(mac, 0x80f, 0);
1731 PHY_WRITE(mac, 0x810, 0);
1732 PHY_SETBITS(mac, 0x478, 0x100);
1733 PHY_SETBITS(mac, 0x801, 0x40);
1734 PHY_SETBITS(mac, 0x60, 0x40);
1735 PHY_SETBITS(mac, 0x14, 0x200);
1736 }
1737
1738 RF_SETBITS(mac, 0x7a, 0x70);
1739 RF_SETBITS(mac, 0x7a, 0x80);
1740
1741 DELAY(30);
1742
1743 nrssi = bwi_nrssi_11g(mac);
1744 if (nrssi == 31) {
1745 for (i = 7; i >= 4; --i) {
1746 RF_WRITE(mac, 0x7b, i);
1747 DELAY(20);
1748 nrssi = bwi_nrssi_11g(mac);
1749 if (nrssi < 31 && rf7b == 0xffff)
1750 rf7b = i;
1751 }
1752 if (rf7b == 0xffff)
1753 rf7b = 4;
1754 } else {
1755 struct bwi_gains gains;
1756
1757 RF_CLRBITS(mac, 0x7a, 0xff80);
1758
1759 PHY_SETBITS(mac, 0x814, 0x1);
1760 PHY_CLRBITS(mac, 0x815, 0x1);
1761 PHY_SETBITS(mac, 0x811, 0xc);
1762 PHY_SETBITS(mac, 0x812, 0xc);
1763 PHY_SETBITS(mac, 0x811, 0x30);
1764 PHY_SETBITS(mac, 0x812, 0x30);
1765 PHY_WRITE(mac, 0x5a, 0x480);
1766 PHY_WRITE(mac, 0x59, 0x810);
1767 PHY_WRITE(mac, 0x58, 0xd);
1768 if (phy->phy_version == 0)
1769 PHY_WRITE(mac, 0x3, 0x122);
1770 else
1771 PHY_SETBITS(mac, 0xa, 0x2000);
1772 PHY_SETBITS(mac, 0x814, 0x4);
1773 PHY_CLRBITS(mac, 0x815, 0x4);
1774 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1775 RF_SETBITS(mac, 0x7a, 0xf);
1776
1777 bzero(&gains, sizeof(gains));
1778 gains.tbl_gain1 = 3;
1779 gains.tbl_gain2 = 0;
1780 gains.phy_gain = 1;
1781 bwi_set_gains(mac, &gains);
1782
1783 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf);
1784 DELAY(30);
1785
1786 nrssi = bwi_nrssi_11g(mac);
1787 if (nrssi == -32) {
1788 for (i = 0; i < 4; ++i) {
1789 RF_WRITE(mac, 0x7b, i);
1790 DELAY(20);
1791 nrssi = bwi_nrssi_11g(mac);
1792 if (nrssi > -31 && rf7b == 0xffff)
1793 rf7b = i;
1794 }
1795 if (rf7b == 0xffff)
1796 rf7b = 3;
1797 } else {
1798 rf7b = 0;
1799 }
1800 }
1801 RF_WRITE(mac, 0x7b, rf7b);
1802
1803 /*
1804 * Restore saved RF/PHY registers
1805 */
1806 if (phy->phy_rev >= 6) {
1807 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) {
1808 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1809 save_phy6[phy6_idx]);
1810 }
1811 }
1812
1813 /* Saved PHY registers 0, 1, 2 are handled later */
1814 for (i = 3; i < SAVE_PHY_COMM_MAX; ++i)
1815 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1816
1817 for (i = SAVE_RF_MAX - 1; i >= 0; --i)
1818 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1819
1820 PHY_SETBITS(mac, 0x802, 0x3);
1821 PHY_SETBITS(mac, 0x429, 0x8000);
1822
1823 bwi_set_gains(mac, NULL);
1824
1825 if (phy->phy_rev >= 6) {
1826 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) {
1827 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1828 save_phy6[phy6_idx]);
1829 }
1830 }
1831
1832 PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]);
1833 PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]);
1834 PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]);
1835
1836 #undef SAVE_RF_MAX
1837 #undef SAVE_PHY_COMM_MAX
1838 #undef SAVE_PHY6_MAX
1839 }
1840
1841 static void
1842 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac)
1843 {
1844 #define SAVE_RF_MAX 3
1845 #define SAVE_PHY_COMM_MAX 4
1846 #define SAVE_PHY3_MAX 8
1847
1848 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1849 { 0x7a, 0x52, 0x43 };
1850 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] =
1851 { 0x15, 0x5a, 0x59, 0x58 };
1852 static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = {
1853 0x002e, 0x002f, 0x080f, 0x0810,
1854 0x0801, 0x0060, 0x0014, 0x0478
1855 };
1856
1857 struct bwi_softc *sc = mac->mac_sc;
1858 struct bwi_phy *phy = &mac->mac_phy;
1859 struct bwi_rf *rf = &mac->mac_rf;
1860 uint16_t save_rf[SAVE_RF_MAX];
1861 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1862 uint16_t save_phy3[SAVE_PHY3_MAX];
1863 uint16_t ant_div, bbp_atten, chan_ex;
1864 struct bwi_gains gains;
1865 int16_t nrssi[2];
1866 int i, phy3_idx = 0;
1867
1868 if (rf->rf_rev >= 9)
1869 return;
1870 else if (rf->rf_rev == 8)
1871 bwi_rf_set_nrssi_ofs_11g(mac);
1872
1873 PHY_CLRBITS(mac, 0x429, 0x8000);
1874 PHY_CLRBITS(mac, 0x802, 0x3);
1875
1876 /*
1877 * Save RF/PHY registers for later restoration
1878 */
1879 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1880 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
1881
1882 for (i = 0; i < SAVE_RF_MAX; ++i)
1883 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1884 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1885 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1886
1887 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1888 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1889
1890 if (phy->phy_rev >= 3) {
1891 for (i = 0; i < SAVE_PHY3_MAX; ++i)
1892 save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]);
1893
1894 PHY_WRITE(mac, 0x2e, 0);
1895 PHY_WRITE(mac, 0x810, 0);
1896
1897 if (phy->phy_rev == 4 || phy->phy_rev == 6 ||
1898 phy->phy_rev == 7) {
1899 PHY_SETBITS(mac, 0x478, 0x100);
1900 PHY_SETBITS(mac, 0x810, 0x40);
1901 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) {
1902 PHY_CLRBITS(mac, 0x810, 0x40);
1903 }
1904
1905 PHY_SETBITS(mac, 0x60, 0x40);
1906 PHY_SETBITS(mac, 0x14, 0x200);
1907 }
1908
1909 /*
1910 * Calculate nrssi0
1911 */
1912 RF_SETBITS(mac, 0x7a, 0x70);
1913
1914 bzero(&gains, sizeof(gains));
1915 gains.tbl_gain1 = 0;
1916 gains.tbl_gain2 = 8;
1917 gains.phy_gain = 0;
1918 bwi_set_gains(mac, &gains);
1919
1920 RF_CLRBITS(mac, 0x7a, 0xff08);
1921 if (phy->phy_rev >= 2) {
1922 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30);
1923 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
1924 }
1925
1926 RF_SETBITS(mac, 0x7a, 0x80);
1927 DELAY(20);
1928 nrssi[0] = bwi_nrssi_11g(mac);
1929
1930 /*
1931 * Calculate nrssi1
1932 */
1933 RF_CLRBITS(mac, 0x7a, 0xff80);
1934 if (phy->phy_version >= 2)
1935 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1936 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
1937
1938 RF_SETBITS(mac, 0x7a, 0xf);
1939 PHY_WRITE(mac, 0x15, 0xf330);
1940 if (phy->phy_rev >= 2) {
1941 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20);
1942 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20);
1943 }
1944
1945 bzero(&gains, sizeof(gains));
1946 gains.tbl_gain1 = 3;
1947 gains.tbl_gain2 = 0;
1948 gains.phy_gain = 1;
1949 bwi_set_gains(mac, &gains);
1950
1951 if (rf->rf_rev == 8) {
1952 RF_WRITE(mac, 0x43, 0x1f);
1953 } else {
1954 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60);
1955 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
1956 }
1957 PHY_WRITE(mac, 0x5a, 0x480);
1958 PHY_WRITE(mac, 0x59, 0x810);
1959 PHY_WRITE(mac, 0x58, 0xd);
1960 DELAY(20);
1961
1962 nrssi[1] = bwi_nrssi_11g(mac);
1963
1964 /*
1965 * Install calculated narrow RSSI values
1966 */
1967 if (nrssi[1] == nrssi[0])
1968 rf->rf_nrssi_slope = 0x10000;
1969 else
1970 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1971 if (nrssi[0] >= -4) {
1972 rf->rf_nrssi[0] = nrssi[1];
1973 rf->rf_nrssi[1] = nrssi[0];
1974 }
1975
1976 /*
1977 * Restore saved RF/PHY registers
1978 */
1979 if (phy->phy_rev >= 3) {
1980 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) {
1981 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
1982 save_phy3[phy3_idx]);
1983 }
1984 }
1985 if (phy->phy_rev >= 2) {
1986 PHY_CLRBITS(mac, 0x812, 0x30);
1987 PHY_CLRBITS(mac, 0x811, 0x30);
1988 }
1989
1990 for (i = 0; i < SAVE_RF_MAX; ++i)
1991 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1992
1993 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1994 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
1995 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1996
1997 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1998 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1999
2000 bwi_rf_work_around(mac, rf->rf_curchan);
2001 PHY_SETBITS(mac, 0x802, 0x3);
2002 bwi_set_gains(mac, NULL);
2003 PHY_SETBITS(mac, 0x429, 0x8000);
2004
2005 if (phy->phy_rev >= 3) {
2006 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) {
2007 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2008 save_phy3[phy3_idx]);
2009 }
2010 }
2011
2012 bwi_rf_init_sw_nrssi_table(mac);
2013 bwi_rf_set_nrssi_thr_11g(mac);
2014
2015 #undef SAVE_RF_MAX
2016 #undef SAVE_PHY_COMM_MAX
2017 #undef SAVE_PHY3_MAX
2018 }
2019
2020 static void
2021 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac)
2022 {
2023 struct bwi_rf *rf = &mac->mac_rf;
2024 int d, i;
2025
2026 d = 0x1f - rf->rf_nrssi[0];
2027 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2028 int val;
2029
2030 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
2031 if (val < 0)
2032 val = 0;
2033 else if (val > 0x3f)
2034 val = 0x3f;
2035
2036 rf->rf_nrssi_table[i] = val;
2037 }
2038 }
2039
2040 void
2041 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust)
2042 {
2043 int i;
2044
2045 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2046 int16_t val;
2047
2048 val = bwi_nrssi_read(mac, i);
2049
2050 val -= adjust;
2051 if (val < -32)
2052 val = -32;
2053 else if (val > 31);
2054 val = 31;
2055
2056 bwi_nrssi_write(mac, i, val);
2057 }
2058 }
2059
2060 static void
2061 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac)
2062 {
2063 struct bwi_rf *rf = &mac->mac_rf;
2064 int32_t thr;
2065
2066 if (rf->rf_type != BWI_RF_T_BCM2050 ||
2067 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0)
2068 return;
2069
2070 /*
2071 * Calculate nrssi threshold
2072 */
2073 if (rf->rf_rev >= 6) {
2074 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32;
2075 thr += 20 * (rf->rf_nrssi[0] + 1);
2076 thr /= 40;
2077 } else {
2078 thr = rf->rf_nrssi[1] - 5;
2079 }
2080 if (thr < 0)
2081 thr = 0;
2082 else if (thr > 0x3e)
2083 thr = 0x3e;
2084
2085 PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B); /* dummy read */
2086 PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c);
2087
2088 if (rf->rf_rev >= 6) {
2089 PHY_WRITE(mac, 0x87, 0xe0d);
2090 PHY_WRITE(mac, 0x86, 0xc0b);
2091 PHY_WRITE(mac, 0x85, 0xa09);
2092 PHY_WRITE(mac, 0x84, 0x808);
2093 PHY_WRITE(mac, 0x83, 0x808);
2094 PHY_WRITE(mac, 0x82, 0x604);
2095 PHY_WRITE(mac, 0x81, 0x302);
2096 PHY_WRITE(mac, 0x80, 0x100);
2097 }
2098 }
2099
2100 static __inline int32_t
2101 _nrssi_threshold(const struct bwi_rf *rf, int32_t val)
2102 {
2103 val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
2104 val += (rf->rf_nrssi[0] << 6);
2105 if (val < 32)
2106 val += 31;
2107 else
2108 val += 32;
2109 val >>= 6;
2110 if (val < -31)
2111 val = -31;
2112 else if (val > 31)
2113 val = 31;
2114 return val;
2115 }
2116
2117 static void
2118 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac)
2119 {
2120 int32_t thr1, thr2;
2121 uint16_t thr;
2122
2123 /*
2124 * Find the two nrssi thresholds
2125 */
2126 if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 ||
2127 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
2128 int16_t nrssi;
2129
2130 nrssi = bwi_nrssi_read(mac, 0x20);
2131 if (nrssi >= 32)
2132 nrssi -= 64;
2133
2134 if (nrssi < 3) {
2135 thr1 = 0x2b;
2136 thr2 = 0x27;
2137 } else {
2138 thr1 = 0x2d;
2139 thr2 = 0x2b;
2140 }
2141 } else {
2142 /* TODO Interfere mode */
2143 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11);
2144 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe);
2145 }
2146
2147 #define NRSSI_THR1_MASK __BITS(5, 0)
2148 #define NRSSI_THR2_MASK __BITS(11, 6)
2149
2150 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
2151 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
2152 PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr);
2153
2154 #undef NRSSI_THR1_MASK
2155 #undef NRSSI_THR2_MASK
2156 }
2157
2158 void
2159 bwi_rf_clear_tssi(struct bwi_mac *mac)
2160 {
2161 /* XXX use function pointer */
2162 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) {
2163 /* TODO:11A */
2164 } else {
2165 uint16_t val;
2166 int i;
2167
2168 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
2169 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
2170
2171 for (i = 0; i < 2; ++i) {
2172 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2173 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
2174 }
2175
2176 for (i = 0; i < 2; ++i) {
2177 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2178 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
2179 }
2180 }
2181 }
2182
2183 void
2184 bwi_rf_clear_state(struct bwi_rf *rf)
2185 {
2186 int i;
2187
2188 rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS;
2189 bzero(rf->rf_lo, sizeof(rf->rf_lo));
2190 bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used));
2191
2192 rf->rf_nrssi_slope = 0;
2193 rf->rf_nrssi[0] = BWI_INVALID_NRSSI;
2194 rf->rf_nrssi[1] = BWI_INVALID_NRSSI;
2195
2196 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i)
2197 rf->rf_nrssi_table[i] = i;
2198
2199 rf->rf_lo_gain = 0;
2200 rf->rf_rx_gain = 0;
2201
2202 bcopy(rf->rf_txpower_map0, rf->rf_txpower_map,
2203 sizeof(rf->rf_txpower_map));
2204 rf->rf_idle_tssi = rf->rf_idle_tssi0;
2205 }
2206
2207 static void
2208 bwi_rf_on_11a(struct bwi_mac *mac)
2209 {
2210 /* TODO:11A */
2211 }
2212
2213 static void
2214 bwi_rf_on_11bg(struct bwi_mac *mac)
2215 {
2216 struct bwi_phy *phy = &mac->mac_phy;
2217
2218 PHY_WRITE(mac, 0x15, 0x8000);
2219 PHY_WRITE(mac, 0x15, 0xcc00);
2220 if (phy->phy_flags & BWI_PHY_F_LINKED)
2221 PHY_WRITE(mac, 0x15, 0xc0);
2222 else
2223 PHY_WRITE(mac, 0x15, 0);
2224
2225 bwi_rf_set_chan(mac, 6 /* XXX */, 1);
2226 }
2227
2228 void
2229 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode)
2230 {
2231 struct bwi_softc *sc = mac->mac_sc;
2232 struct bwi_phy *phy = &mac->mac_phy;
2233 uint16_t val;
2234
2235 KKASSERT(ant_mode == BWI_ANT_MODE_0 ||
2236 ant_mode == BWI_ANT_MODE_1 ||
2237 ant_mode == BWI_ANT_MODE_AUTO);
2238
2239 HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2240
2241 if (phy->phy_mode == IEEE80211_MODE_11B) {
2242 /* NOTE: v4/v3 conflicts, take v3 */
2243 if (mac->mac_rev == 2)
2244 val = BWI_ANT_MODE_AUTO;
2245 else
2246 val = ant_mode;
2247 val <<= 7;
2248 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
2249 } else { /* 11a/g */
2250 /* XXX reg/value naming */
2251 val = ant_mode << 7;
2252 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
2253
2254 if (ant_mode == BWI_ANT_MODE_AUTO)
2255 PHY_CLRBITS(mac, 0x42b, 0x100);
2256
2257 if (phy->phy_mode == IEEE80211_MODE_11A) {
2258 /* TODO:11A */
2259 } else { /* 11g */
2260 if (ant_mode == BWI_ANT_MODE_AUTO)
2261 PHY_SETBITS(mac, 0x48c, 0x2000);
2262 else
2263 PHY_CLRBITS(mac, 0x48c, 0x2000);
2264
2265 if (phy->phy_rev >= 2) {
2266 PHY_SETBITS(mac, 0x461, 0x10);
2267 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15);
2268 if (phy->phy_rev == 2) {
2269 PHY_WRITE(mac, 0x427, 0x8);
2270 } else {
2271 PHY_FILT_SETBITS(mac, 0x427,
2272 0xff00, 0x8);
2273 }
2274
2275 if (phy->phy_rev >= 6)
2276 PHY_WRITE(mac, 0x49b, 0xdc);
2277 }
2278 }
2279 }
2280
2281 /* XXX v4 set AUTO_ANTDIV unconditionally */
2282 if (ant_mode == BWI_ANT_MODE_AUTO)
2283 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2284
2285 val = ant_mode << 8;
2286 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON,
2287 0xfc3f, val);
2288 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK,
2289 0xfc3f, val);
2290 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP,
2291 0xfc3f, val);
2292
2293 /* XXX what's these */
2294 if (phy->phy_mode == IEEE80211_MODE_11B)
2295 CSR_SETBITS_2(sc, 0x5e, 0x4);
2296
2297 CSR_WRITE_4(sc, 0x100, 0x1000000);
2298 if (mac->mac_rev < 5)
2299 CSR_WRITE_4(sc, 0x10c, 0x1000000);
2300
2301 mac->mac_rf.rf_ant_mode = ant_mode;
2302 }
2303
2304 int
2305 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs)
2306 {
2307 int i;
2308
2309 for (i = 0; i < 4; ) {
2310 uint16_t val;
2311
2312 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
2313 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
2314 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
2315 }
2316
2317 for (i = 0; i < 4; ++i) {
2318 if (tssi[i] == BWI_INVALID_TSSI)
2319 return EINVAL;
2320 }
2321 return 0;
2322 }
2323
2324 int
2325 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr)
2326 {
2327 struct bwi_rf *rf = &mac->mac_rf;
2328 int pwr_idx;
2329
2330 pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi;
2331 #if 0
2332 if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX)
2333 return EINVAL;
2334 #else
2335 if (pwr_idx < 0)
2336 pwr_idx = 0;
2337 else if (pwr_idx >= BWI_TSSI_MAX)
2338 pwr_idx = BWI_TSSI_MAX - 1;
2339 #endif
2340
2341 *txpwr = rf->rf_txpower_map[pwr_idx];
2342 return 0;
2343 }
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