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amd64 port: mainly on the pmap headers, identify_cpu and initcpu
[dragonfly/port-amd64.git] / sys / dev / netif / bwi / bwirf.c
blobb66bb9d12dbf83479dff8aa7de0faca458b4451d
1 /*
2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * $DragonFly: src/sys/dev/netif/bwi/bwirf.c,v 1.5 2007/09/17 12:13:24 sephe Exp $
35 */
36
37 #include <sys/param.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/bus.h>
41 #include <sys/malloc.h>
42 #include <sys/proc.h>
43 #include <sys/rman.h>
44 #include <sys/serialize.h>
45 #include <sys/socket.h>
46 #include <sys/sysctl.h>
47
48 #include <net/ethernet.h>
49 #include <net/if.h>
50 #include <net/bpf.h>
51 #include <net/if_arp.h>
52 #include <net/if_dl.h>
53 #include <net/if_media.h>
54 #include <net/ifq_var.h>
55
56 #include <netproto/802_11/ieee80211_radiotap.h>
57 #include <netproto/802_11/ieee80211_var.h>
58
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pcidevs.h>
62
63 #include "bitops.h"
64 #include "if_bwireg.h"
65 #include "if_bwivar.h"
66 #include "bwiphy.h"
67 #include "bwirf.h"
68 #include "bwimac.h"
69
70 #define RF_LO_WRITE(mac, lo) bwi_rf_lo_write((mac), (lo))
71
72 #define BWI_RF_2GHZ_CHAN(chan) \
73 (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
74
75 #define BWI_DEFAULT_IDLE_TSSI 52
76
77 struct rf_saveregs {
78 uint16_t phy_15;
79 uint16_t phy_2a;
80 uint16_t phy_35;
81 uint16_t phy_60;
82 uint16_t phy_429;
83 uint16_t phy_802;
84 uint16_t phy_811;
85 uint16_t phy_812;
86 uint16_t phy_814;
87 uint16_t phy_815;
88
89 uint16_t rf_43;
90 uint16_t rf_52;
91 uint16_t rf_7a;
92 };
93
94 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)
95 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)
96
97 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)
98 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
99
100 static int bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
101 static void bwi_rf_work_around(struct bwi_mac *, u_int);
102 static int bwi_rf_gain_max_reached(struct bwi_mac *, int);
103 static uint16_t bwi_rf_calibval(struct bwi_mac *);
104 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *);
105 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
106 static void bwi_rf_lo_measure(struct bwi_mac *,
107 const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
108 static uint8_t _bwi_rf_lo_update(struct bwi_mac *, uint16_t);
109
110 static void bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
111
112 static void bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
113 static void bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
114 static void bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
115 static void bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
116 static void bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
117
118 static void bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
119
120 static int bwi_rf_calc_rssi_bcm2050(struct bwi_mac *,
121 const struct bwi_rxbuf_hdr *);
122 static int bwi_rf_calc_rssi_bcm2053(struct bwi_mac *,
123 const struct bwi_rxbuf_hdr *);
124 static int bwi_rf_calc_rssi_bcm2060(struct bwi_mac *,
125 const struct bwi_rxbuf_hdr *);
126
127 static void bwi_rf_on_11a(struct bwi_mac *);
128 static void bwi_rf_on_11bg(struct bwi_mac *);
129
130 static void bwi_rf_off_11a(struct bwi_mac *);
131 static void bwi_rf_off_11bg(struct bwi_mac *);
132 static void bwi_rf_off_11g_rev5(struct bwi_mac *);
133
134 static const int8_t bwi_txpower_map_11b[BWI_TSSI_MAX] =
135 { BWI_TXPOWER_MAP_11B };
136 static const int8_t bwi_txpower_map_11g[BWI_TSSI_MAX] =
137 { BWI_TXPOWER_MAP_11G };
138
139 static __inline int16_t
140 bwi_nrssi_11g(struct bwi_mac *mac)
141 {
142 int16_t val;
143
144 #define NRSSI_11G_MASK __BITS(13, 8)
145
146 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
147 if (val >= 32)
148 val -= 64;
149 return val;
150
151 #undef NRSSI_11G_MASK
152 }
153
154 static __inline struct bwi_rf_lo *
155 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten)
156 {
157 int n;
158
159 n = rf_atten + (14 * (bbp_atten / 2));
160 KKASSERT(n < BWI_RFLO_MAX);
161
162 return &mac->mac_rf.rf_lo[n];
163 }
164
165 static __inline int
166 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
167 {
168 struct bwi_rf *rf = &mac->mac_rf;
169 int idx;
170
171 idx = lo - rf->rf_lo;
172 KKASSERT(idx >= 0 && idx < BWI_RFLO_MAX);
173
174 return isset(rf->rf_lo_used, idx);
175 }
176
177 void
178 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
179 {
180 struct bwi_softc *sc = mac->mac_sc;
181
182 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
183 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
184 }
185
186 uint16_t
187 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
188 {
189 struct bwi_rf *rf = &mac->mac_rf;
190 struct bwi_softc *sc = mac->mac_sc;
191
192 ctrl |= rf->rf_ctrl_rd;
193 if (rf->rf_ctrl_adj) {
194 /* XXX */
195 if (ctrl < 0x70)
196 ctrl += 0x80;
197 else if (ctrl < 0x80)
198 ctrl += 0x70;
199 }
200
201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
202 return CSR_READ_2(sc, BWI_RF_DATA_LO);
203 }
204
205 int
206 bwi_rf_attach(struct bwi_mac *mac)
207 {
208 struct bwi_softc *sc = mac->mac_sc;
209 struct bwi_rf *rf = &mac->mac_rf;
210 uint16_t type, manu;
211 uint8_t rev;
212
213 /*
214 * Get RF manufacture/type/revision
215 */
216 if (sc->sc_bbp_id == BWI_BBPID_BCM4317) {
217 /*
218 * Fake a BCM2050 RF
219 */
220 manu = BWI_RF_MANUFACT_BCM;
221 type = BWI_RF_T_BCM2050;
222 if (sc->sc_bbp_rev == 0)
223 rev = 3;
224 else if (sc->sc_bbp_rev == 1)
225 rev = 4;
226 else
227 rev = 5;
228 } else {
229 uint32_t val;
230
231 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
232 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
233 val <<= 16;
234
235 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
236 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
237
238 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
239 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
240 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
241 }
242 device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n",
243 manu, type, rev);
244
245 /*
246 * Verify whether the RF is supported
247 */
248 rf->rf_ctrl_rd = 0;
249 rf->rf_ctrl_adj = 0;
250 switch (mac->mac_phy.phy_mode) {
251 case IEEE80211_MODE_11A:
252 if (manu != BWI_RF_MANUFACT_BCM ||
253 type != BWI_RF_T_BCM2060 ||
254 rev != 1) {
255 device_printf(sc->sc_dev, "only BCM2060 rev 1 RF "
256 "is supported for 11A PHY\n");
257 return ENXIO;
258 }
259 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A;
260 rf->rf_on = bwi_rf_on_11a;
261 rf->rf_off = bwi_rf_off_11a;
262 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2060;
263 break;
264 case IEEE80211_MODE_11B:
265 if (type == BWI_RF_T_BCM2050) {
266 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
267 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
268 } else if (type == BWI_RF_T_BCM2053) {
269 rf->rf_ctrl_adj = 1;
270 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2053;
271 } else {
272 device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF "
273 "is supported for 11B PHY\n");
274 return ENXIO;
275 }
276 rf->rf_on = bwi_rf_on_11bg;
277 rf->rf_off = bwi_rf_off_11bg;
278 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b;
279 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b;
280 break;
281 case IEEE80211_MODE_11G:
282 if (type != BWI_RF_T_BCM2050) {
283 device_printf(sc->sc_dev, "only BCM2050 RF "
284 "is supported for 11G PHY\n");
285 return ENXIO;
286 }
287 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
288 rf->rf_on = bwi_rf_on_11bg;
289 if (mac->mac_rev >= 5)
290 rf->rf_off = bwi_rf_off_11g_rev5;
291 else
292 rf->rf_off = bwi_rf_off_11bg;
293 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g;
294 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g;
295 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
296 break;
297 default:
298 device_printf(sc->sc_dev, "unsupported PHY mode\n");
299 return ENXIO;
300 }
301
302 rf->rf_type = type;
303 rf->rf_rev = rev;
304 rf->rf_manu = manu;
305 rf->rf_curchan = IEEE80211_CHAN_ANY;
306 rf->rf_ant_mode = BWI_ANT_MODE_AUTO;
307 return 0;
308 }
309
310 void
311 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around)
312 {
313 struct bwi_softc *sc = mac->mac_sc;
314
315 if (chan == IEEE80211_CHAN_ANY)
316 return;
317
318 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan);
319
320 /* TODO: 11A */
321
322 if (work_around)
323 bwi_rf_work_around(mac, chan);
324
325 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
326
327 if (chan == 14) {
328 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN)
329 HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN);
330 else
331 HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN);
332 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */
333 } else {
334 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */
335 }
336 DELAY(8000); /* DELAY(2000); */
337
338 mac->mac_rf.rf_curchan = chan;
339 }
340
341 void
342 bwi_rf_get_gains(struct bwi_mac *mac)
343 {
344 #define SAVE_PHY_MAX 15
345 #define SAVE_RF_MAX 3
346
347 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
348 { 0x52, 0x43, 0x7a };
349 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = {
350 0x0429, 0x0001, 0x0811, 0x0812,
351 0x0814, 0x0815, 0x005a, 0x0059,
352 0x0058, 0x000a, 0x0003, 0x080f,
353 0x0810, 0x002b, 0x0015
354 };
355
356 struct bwi_phy *phy = &mac->mac_phy;
357 struct bwi_rf *rf = &mac->mac_rf;
358 uint16_t save_phy[SAVE_PHY_MAX];
359 uint16_t save_rf[SAVE_RF_MAX];
360 uint16_t trsw;
361 int i, j, loop1_max, loop1, loop2;
362
363 /*
364 * Save PHY/RF registers for later restoration
365 */
366 for (i = 0; i < SAVE_PHY_MAX; ++i)
367 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
368 PHY_READ(mac, 0x2d); /* dummy read */
369
370 for (i = 0; i < SAVE_RF_MAX; ++i)
371 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
372
373 PHY_CLRBITS(mac, 0x429, 0xc000);
374 PHY_SETBITS(mac, 0x1, 0x8000);
375
376 PHY_SETBITS(mac, 0x811, 0x2);
377 PHY_CLRBITS(mac, 0x812, 0x2);
378 PHY_SETBITS(mac, 0x811, 0x1);
379 PHY_CLRBITS(mac, 0x812, 0x1);
380
381 PHY_SETBITS(mac, 0x814, 0x1);
382 PHY_CLRBITS(mac, 0x815, 0x1);
383 PHY_SETBITS(mac, 0x814, 0x2);
384 PHY_CLRBITS(mac, 0x815, 0x2);
385
386 PHY_SETBITS(mac, 0x811, 0xc);
387 PHY_SETBITS(mac, 0x812, 0xc);
388 PHY_SETBITS(mac, 0x811, 0x30);
389 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
390
391 PHY_WRITE(mac, 0x5a, 0x780);
392 PHY_WRITE(mac, 0x59, 0xc810);
393 PHY_WRITE(mac, 0x58, 0xd);
394 PHY_SETBITS(mac, 0xa, 0x2000);
395
396 PHY_SETBITS(mac, 0x814, 0x4);
397 PHY_CLRBITS(mac, 0x815, 0x4);
398
399 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
400
401 if (rf->rf_rev == 8) {
402 loop1_max = 15;
403 RF_WRITE(mac, 0x43, loop1_max);
404 } else {
405 loop1_max = 9;
406 RF_WRITE(mac, 0x52, 0x0);
407 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max);
408 }
409
410 bwi_phy_set_bbp_atten(mac, 11);
411
412 if (phy->phy_rev >= 3)
413 PHY_WRITE(mac, 0x80f, 0xc020);
414 else
415 PHY_WRITE(mac, 0x80f, 0x8020);
416 PHY_WRITE(mac, 0x810, 0);
417
418 PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1);
419 PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800);
420 PHY_SETBITS(mac, 0x811, 0x100);
421 PHY_CLRBITS(mac, 0x812, 0x3000);
422
423 if ((mac->mac_sc->sc_card_flags & BWI_CARD_F_EXT_LNA) &&
424 phy->phy_rev >= 7) {
425 PHY_SETBITS(mac, 0x811, 0x800);
426 PHY_SETBITS(mac, 0x812, 0x8000);
427 }
428 RF_CLRBITS(mac, 0x7a, 0xff08);
429
430 /*
431 * Find out 'loop1/loop2', which will be used to calculate
432 * max loopback gain later
433 */
434 j = 0;
435 for (i = 0; i < loop1_max; ++i) {
436 for (j = 0; j < 16; ++j) {
437 RF_WRITE(mac, 0x43, i);
438
439 if (bwi_rf_gain_max_reached(mac, j))
440 goto loop1_exit;
441 }
442 }
443 loop1_exit:
444 loop1 = i;
445 loop2 = j;
446
447 /*
448 * Find out 'trsw', which will be used to calculate
449 * TRSW(TX/RX switch) RX gain later
450 */
451 if (loop2 >= 8) {
452 PHY_SETBITS(mac, 0x812, 0x30);
453 trsw = 0x1b;
454 for (i = loop2 - 8; i < 16; ++i) {
455 trsw -= 3;
456 if (bwi_rf_gain_max_reached(mac, i))
457 break;
458 }
459 } else {
460 trsw = 0x18;
461 }
462
463 /*
464 * Restore saved PHY/RF registers
465 */
466 /* First 4 saved PHY registers need special processing */
467 for (i = 4; i < SAVE_PHY_MAX; ++i)
468 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
469
470 bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten);
471
472 for (i = 0; i < SAVE_RF_MAX; ++i)
473 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
474
475 PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3);
476 DELAY(10);
477 PHY_WRITE(mac, save_phy_regs[2], save_phy[2]);
478 PHY_WRITE(mac, save_phy_regs[3], save_phy[3]);
479 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
480 PHY_WRITE(mac, save_phy_regs[1], save_phy[1]);
481
482 /*
483 * Calculate gains
484 */
485 rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11;
486 rf->rf_rx_gain = trsw * 2;
487 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_INIT,
488 "lo gain: %u, rx gain: %u\n",
489 rf->rf_lo_gain, rf->rf_rx_gain);
490
491 #undef SAVE_RF_MAX
492 #undef SAVE_PHY_MAX
493 }
494
495 void
496 bwi_rf_init(struct bwi_mac *mac)
497 {
498 struct bwi_rf *rf = &mac->mac_rf;
499
500 if (rf->rf_type == BWI_RF_T_BCM2060) {
501 /* TODO: 11A */
502 } else {
503 if (rf->rf_flags & BWI_RF_F_INITED)
504 RF_WRITE(mac, 0x78, rf->rf_calib);
505 else
506 bwi_rf_init_bcm2050(mac);
507 }
508 }
509
510 static void
511 bwi_rf_off_11a(struct bwi_mac *mac)
512 {
513 RF_WRITE(mac, 0x4, 0xff);
514 RF_WRITE(mac, 0x5, 0xfb);
515
516 PHY_SETBITS(mac, 0x10, 0x8);
517 PHY_SETBITS(mac, 0x11, 0x8);
518
519 PHY_WRITE(mac, 0x15, 0xaa00);
520 }
521
522 static void
523 bwi_rf_off_11bg(struct bwi_mac *mac)
524 {
525 PHY_WRITE(mac, 0x15, 0xaa00);
526 }
527
528 static void
529 bwi_rf_off_11g_rev5(struct bwi_mac *mac)
530 {
531 PHY_SETBITS(mac, 0x811, 0x8c);
532 PHY_CLRBITS(mac, 0x812, 0x8c);
533 }
534
535 static void
536 bwi_rf_work_around(struct bwi_mac *mac, u_int chan)
537 {
538 struct bwi_softc *sc = mac->mac_sc;
539 struct bwi_rf *rf = &mac->mac_rf;
540
541 if (chan == IEEE80211_CHAN_ANY) {
542 if_printf(&mac->mac_sc->sc_ic.ic_if,
543 "%s invalid channel!!\n", __func__);
544 return;
545 }
546
547 if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6)
548 return;
549
550 if (chan <= 10)
551 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
552 else
553 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
554 DELAY(1000);
555 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
556 }
557
558 static __inline struct bwi_rf_lo *
559 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
560 {
561 uint16_t rf_atten, bbp_atten;
562 int remap_rf_atten;
563
564 remap_rf_atten = 1;
565 if (tpctl == NULL) {
566 bbp_atten = 2;
567 rf_atten = 3;
568 } else {
569 if (tpctl->tp_ctrl1 == 3)
570 remap_rf_atten = 0;
571
572 bbp_atten = tpctl->bbp_atten;
573 rf_atten = tpctl->rf_atten;
574
575 if (bbp_atten > 6)
576 bbp_atten = 6;
577 }
578
579 if (remap_rf_atten) {
580 #define MAP_MAX 10
581 static const uint16_t map[MAP_MAX] =
582 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
583
584 #if 0
585 KKASSERT(rf_atten < MAP_MAX);
586 rf_atten = map[rf_atten];
587 #else
588 if (rf_atten >= MAP_MAX) {
589 rf_atten = 0; /* XXX */
590 } else {
591 rf_atten = map[rf_atten];
592 }
593 #endif
594 #undef MAP_MAX
595 }
596
597 return bwi_get_rf_lo(mac, rf_atten, bbp_atten);
598 }
599
600 void
601 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
602 {
603 const struct bwi_rf_lo *lo;
604
605 lo = bwi_rf_lo_find(mac, tpctl);
606 RF_LO_WRITE(mac, lo);
607 }
608
609 static void
610 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
611 {
612 uint16_t val;
613
614 val = (uint8_t)lo->ctrl_lo;
615 val |= ((uint8_t)lo->ctrl_hi) << 8;
616
617 PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
618 }
619
620 static int
621 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx)
622 {
623 PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8);
624 PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000);
625 PHY_SETBITS(mac, 0x15, 0xf000);
626
627 DELAY(20);
628
629 return (PHY_READ(mac, 0x2d) >= 0xdfc);
630 }
631
632 /* XXX use bitmap array */
633 static __inline uint16_t
634 bitswap4(uint16_t val)
635 {
636 uint16_t ret;
637
638 ret = (val & 0x8) >> 3;
639 ret |= (val & 0x4) >> 1;
640 ret |= (val & 0x2) << 1;
641 ret |= (val & 0x1) << 3;
642 return ret;
643 }
644
645 static __inline uint16_t
646 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd)
647 {
648 struct bwi_softc *sc = mac->mac_sc;
649 struct bwi_phy *phy = &mac->mac_phy;
650 struct bwi_rf *rf = &mac->mac_rf;
651 uint16_t lo_gain, ext_lna, loop;
652
653 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
654 return 0;
655
656 lo_gain = rf->rf_lo_gain;
657 if (rf->rf_rev == 8)
658 lo_gain += 0x3e;
659 else
660 lo_gain += 0x26;
661
662 if (lo_gain >= 0x46) {
663 lo_gain -= 0x46;
664 ext_lna = 0x3000;
665 } else if (lo_gain >= 0x3a) {
666 lo_gain -= 0x3a;
667 ext_lna = 0x1000;
668 } else if (lo_gain >= 0x2e) {
669 lo_gain -= 0x2e;
670 ext_lna = 0x2000;
671 } else {
672 lo_gain -= 0x10;
673 ext_lna = 0;
674 }
675
676 for (loop = 0; loop < 16; ++loop) {
677 lo_gain -= (6 * loop);
678 if (lo_gain < 6)
679 break;
680 }
681
682 if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {
683 if (ext_lna)
684 ext_lna |= 0x8000;
685 ext_lna |= (loop << 8);
686 switch (lpd) {
687 case 0x011:
688 return 0x8f92;
689 case 0x001:
690 return (0x8092 | ext_lna);
691 case 0x101:
692 return (0x2092 | ext_lna);
693 case 0x100:
694 return (0x2093 | ext_lna);
695 default:
696 panic("unsupported lpd\n");
697 }
698 } else {
699 ext_lna |= (loop << 8);
700 switch (lpd) {
701 case 0x011:
702 return 0xf92;
703 case 0x001:
704 case 0x101:
705 return (0x92 | ext_lna);
706 case 0x100:
707 return (0x93 | ext_lna);
708 default:
709 panic("unsupported lpd\n");
710 }
711 }
712
713 panic("never reached\n");
714 return 0;
715 }
716
717 void
718 bwi_rf_init_bcm2050(struct bwi_mac *mac)
719 {
720 #define SAVE_RF_MAX 3
721 #define SAVE_PHY_COMM_MAX 4
722 #define SAVE_PHY_11G_MAX 6
723
724 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
725 { 0x0043, 0x0051, 0x0052 };
726 static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] =
727 { 0x0015, 0x005a, 0x0059, 0x0058 };
728 static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] =
729 { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 };
730
731 uint16_t save_rf[SAVE_RF_MAX];
732 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
733 uint16_t save_phy_11g[SAVE_PHY_11G_MAX];
734 uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0;
735 uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex;
736 uint16_t phy812_val;
737 uint16_t calib;
738 uint32_t test_lim, test;
739 struct bwi_softc *sc = mac->mac_sc;
740 struct bwi_phy *phy = &mac->mac_phy;
741 struct bwi_rf *rf = &mac->mac_rf;
742 int i;
743
744 /*
745 * Save registers for later restoring
746 */
747 for (i = 0; i < SAVE_RF_MAX; ++i)
748 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
749 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
750 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]);
751
752 if (phy->phy_mode == IEEE80211_MODE_11B) {
753 phyr_30 = PHY_READ(mac, 0x30);
754 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
755
756 PHY_WRITE(mac, 0x30, 0xff);
757 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
758 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
759 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
760 save_phy_11g[i] =
761 PHY_READ(mac, save_phy_regs_11g[i]);
762 }
763
764 PHY_SETBITS(mac, 0x814, 0x3);
765 PHY_CLRBITS(mac, 0x815, 0x3);
766 PHY_CLRBITS(mac, 0x429, 0x8000);
767 PHY_CLRBITS(mac, 0x802, 0x3);
768
769 phyr_80f = PHY_READ(mac, 0x80f);
770 phyr_810 = PHY_READ(mac, 0x810);
771
772 if (phy->phy_rev >= 3)
773 PHY_WRITE(mac, 0x80f, 0xc020);
774 else
775 PHY_WRITE(mac, 0x80f, 0x8020);
776 PHY_WRITE(mac, 0x810, 0);
777
778 phy812_val = bwi_phy812_value(mac, 0x011);
779 PHY_WRITE(mac, 0x812, phy812_val);
780 if (phy->phy_rev < 7 ||
781 (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0)
782 PHY_WRITE(mac, 0x811, 0x1b3);
783 else
784 PHY_WRITE(mac, 0x811, 0x9b3);
785 }
786 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
787
788 phyr_35 = PHY_READ(mac, 0x35);
789 PHY_CLRBITS(mac, 0x35, 0x80);
790
791 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
792 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
793
794 if (phy->phy_version == 0) {
795 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
796 } else {
797 if (phy->phy_version >= 2)
798 PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40);
799 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
800 }
801
802 calib = bwi_rf_calibval(mac);
803
804 if (phy->phy_mode == IEEE80211_MODE_11B)
805 RF_WRITE(mac, 0x78, 0x26);
806
807 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
808 phy812_val = bwi_phy812_value(mac, 0x011);
809 PHY_WRITE(mac, 0x812, phy812_val);
810 }
811
812 PHY_WRITE(mac, 0x15, 0xbfaf);
813 PHY_WRITE(mac, 0x2b, 0x1403);
814
815 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
816 phy812_val = bwi_phy812_value(mac, 0x001);
817 PHY_WRITE(mac, 0x812, phy812_val);
818 }
819
820 PHY_WRITE(mac, 0x15, 0xbfa0);
821
822 RF_SETBITS(mac, 0x51, 0x4);
823 if (rf->rf_rev == 8) {
824 RF_WRITE(mac, 0x43, 0x1f);
825 } else {
826 RF_WRITE(mac, 0x52, 0);
827 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
828 }
829
830 test_lim = 0;
831 PHY_WRITE(mac, 0x58, 0);
832 for (i = 0; i < 16; ++i) {
833 PHY_WRITE(mac, 0x5a, 0x480);
834 PHY_WRITE(mac, 0x59, 0xc810);
835
836 PHY_WRITE(mac, 0x58, 0xd);
837 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
838 phy812_val = bwi_phy812_value(mac, 0x101);
839 PHY_WRITE(mac, 0x812, phy812_val);
840 }
841 PHY_WRITE(mac, 0x15, 0xafb0);
842 DELAY(10);
843
844 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
845 phy812_val = bwi_phy812_value(mac, 0x101);
846 PHY_WRITE(mac, 0x812, phy812_val);
847 }
848 PHY_WRITE(mac, 0x15, 0xefb0);
849 DELAY(10);
850
851 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
852 phy812_val = bwi_phy812_value(mac, 0x100);
853 PHY_WRITE(mac, 0x812, phy812_val);
854 }
855 PHY_WRITE(mac, 0x15, 0xfff0);
856 DELAY(20);
857
858 test_lim += PHY_READ(mac, 0x2d);
859
860 PHY_WRITE(mac, 0x58, 0);
861 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
862 phy812_val = bwi_phy812_value(mac, 0x101);
863 PHY_WRITE(mac, 0x812, phy812_val);
864 }
865 PHY_WRITE(mac, 0x15, 0xafb0);
866 }
867 ++test_lim;
868 test_lim >>= 9;
869
870 DELAY(10);
871
872 test = 0;
873 PHY_WRITE(mac, 0x58, 0);
874 for (i = 0; i < 16; ++i) {
875 int j;
876
877 rfr_78 = (bitswap4(i) << 1) | 0x20;
878 RF_WRITE(mac, 0x78, rfr_78);
879 DELAY(10);
880
881 /* NB: This block is slight different than the above one */
882 for (j = 0; j < 16; ++j) {
883 PHY_WRITE(mac, 0x5a, 0xd80);
884 PHY_WRITE(mac, 0x59, 0xc810);
885
886 PHY_WRITE(mac, 0x58, 0xd);
887 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
888 phy->phy_rev >= 2) {
889 phy812_val = bwi_phy812_value(mac, 0x101);
890 PHY_WRITE(mac, 0x812, phy812_val);
891 }
892 PHY_WRITE(mac, 0x15, 0xafb0);
893 DELAY(10);
894
895 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
896 phy->phy_rev >= 2) {
897 phy812_val = bwi_phy812_value(mac, 0x101);
898 PHY_WRITE(mac, 0x812, phy812_val);
899 }
900 PHY_WRITE(mac, 0x15, 0xefb0);
901 DELAY(10);
902
903 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
904 phy->phy_rev >= 2) {
905 phy812_val = bwi_phy812_value(mac, 0x100);
906 PHY_WRITE(mac, 0x812, phy812_val);
907 }
908 PHY_WRITE(mac, 0x15, 0xfff0);
909 DELAY(10);
910
911 test += PHY_READ(mac, 0x2d);
912
913 PHY_WRITE(mac, 0x58, 0);
914 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
915 phy->phy_rev >= 2) {
916 phy812_val = bwi_phy812_value(mac, 0x101);
917 PHY_WRITE(mac, 0x812, phy812_val);
918 }
919 PHY_WRITE(mac, 0x15, 0xafb0);
920 }
921
922 ++test;
923 test >>= 8;
924
925 if (test > test_lim)
926 break;
927 }
928 if (i > 15)
929 rf->rf_calib = rfr_78;
930 else
931 rf->rf_calib = calib;
932 if (rf->rf_calib != 0xffff) {
933 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT,
934 "RF calibration value: 0x%04x\n", rf->rf_calib);
935 rf->rf_flags |= BWI_RF_F_INITED;
936 }
937
938 /*
939 * Restore trashes registers
940 */
941 PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]);
942
943 for (i = 0; i < SAVE_RF_MAX; ++i) {
944 int pos = (i + 1) % SAVE_RF_MAX;
945
946 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]);
947 }
948 for (i = 1; i < SAVE_PHY_COMM_MAX; ++i)
949 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]);
950
951 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
952 if (phy->phy_version != 0)
953 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
954
955 PHY_WRITE(mac, 0x35, phyr_35);
956 bwi_rf_work_around(mac, rf->rf_curchan);
957
958 if (phy->phy_mode == IEEE80211_MODE_11B) {
959 PHY_WRITE(mac, 0x30, phyr_30);
960 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
961 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
962 /* XXX Spec only says when PHY is linked (gmode) */
963 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
964
965 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
966 PHY_WRITE(mac, save_phy_regs_11g[i],
967 save_phy_11g[i]);
968 }
969
970 PHY_WRITE(mac, 0x80f, phyr_80f);
971 PHY_WRITE(mac, 0x810, phyr_810);
972 }
973
974 #undef SAVE_PHY_11G_MAX
975 #undef SAVE_PHY_COMM_MAX
976 #undef SAVE_RF_MAX
977 }
978
979 static uint16_t
980 bwi_rf_calibval(struct bwi_mac *mac)
981 {
982 /* http://bcm-specs.sipsolutions.net/RCCTable */
983 static const uint16_t rf_calibvals[] = {
984 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf,
985 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf
986 };
987 uint16_t val, calib;
988 int idx;
989
990 val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
991 idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
992 KKASSERT(idx < (int)(sizeof(rf_calibvals) / sizeof(rf_calibvals[0])));
993
994 calib = rf_calibvals[idx] << 1;
995 if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
996 calib |= 0x1;
997 calib |= 0x20;
998
999 return calib;
1000 }
1001
1002 static __inline int32_t
1003 _bwi_adjust_devide(int32_t num, int32_t den)
1004 {
1005 if (num < 0)
1006 return (num / den);
1007 else
1008 return (num + den / 2) / den;
1009 }
1010
1011 /*
1012 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
1013 * "calculating table entries"
1014 */
1015 static int
1016 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[])
1017 {
1018 int32_t m1, m2, f, dbm;
1019 int i;
1020
1021 m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32);
1022 m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1);
1023
1024 #define ITER_MAX 16
1025
1026 f = 256;
1027 for (i = 0; i < ITER_MAX; ++i) {
1028 int32_t q, d;
1029
1030 q = _bwi_adjust_devide(
1031 f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048);
1032 d = abs(q - f);
1033 f = q;
1034
1035 if (d < 2)
1036 break;
1037 }
1038 if (i == ITER_MAX)
1039 return EINVAL;
1040
1041 #undef ITER_MAX
1042
1043 dbm = _bwi_adjust_devide(m1 * f, 8192);
1044 if (dbm < -127)
1045 dbm = -127;
1046 else if (dbm > 128)
1047 dbm = 128;
1048
1049 *txpwr = dbm;
1050 return 0;
1051 }
1052
1053 int
1054 bwi_rf_map_txpower(struct bwi_mac *mac)
1055 {
1056 struct bwi_softc *sc = mac->mac_sc;
1057 struct bwi_rf *rf = &mac->mac_rf;
1058 struct bwi_phy *phy = &mac->mac_phy;
1059 uint16_t sprom_ofs, val, mask;
1060 int16_t pa_params[3];
1061 int error = 0, i, ant_gain, reg_txpower_max;
1062
1063 /*
1064 * Find out max TX power
1065 */
1066 val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
1067 if (phy->phy_mode == IEEE80211_MODE_11A) {
1068 rf->rf_txpower_max = __SHIFTOUT(val,
1069 BWI_SPROM_MAX_TXPWR_MASK_11A);
1070 } else {
1071 rf->rf_txpower_max = __SHIFTOUT(val,
1072 BWI_SPROM_MAX_TXPWR_MASK_11BG);
1073
1074 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) &&
1075 phy->phy_mode == IEEE80211_MODE_11G)
1076 rf->rf_txpower_max -= 3;
1077 }
1078 if (rf->rf_txpower_max <= 0) {
1079 device_printf(sc->sc_dev, "invalid max txpower in sprom\n");
1080 rf->rf_txpower_max = 74;
1081 }
1082 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1083 "max txpower from sprom: %d dBm\n", rf->rf_txpower_max);
1084
1085 /*
1086 * Find out region/domain max TX power, which is adjusted
1087 * by antenna gain and 1.5 dBm fluctuation as mentioned
1088 * in v3 spec.
1089 */
1090 val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
1091 if (phy->phy_mode == IEEE80211_MODE_11A)
1092 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
1093 else
1094 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
1095 if (ant_gain == 0xff) {
1096 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n");
1097 ant_gain = 2;
1098 }
1099 ant_gain *= 4;
1100 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1101 "ant gain %d dBm\n", ant_gain);
1102
1103 reg_txpower_max = 90 - ant_gain - 6; /* XXX magic number */
1104 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1105 "region/domain max txpower %d dBm\n", reg_txpower_max);
1106
1107 /*
1108 * Force max TX power within region/domain TX power limit
1109 */
1110 if (rf->rf_txpower_max > reg_txpower_max)
1111 rf->rf_txpower_max = reg_txpower_max;
1112 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1113 "max txpower %d dBm\n", rf->rf_txpower_max);
1114
1115 /*
1116 * Create TSSI to TX power mapping
1117 */
1118
1119 if (sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1120 rf->rf_type != BWI_RF_T_BCM2050) {
1121 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1122 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0,
1123 sizeof(rf->rf_txpower_map0));
1124 goto back;
1125 }
1126
1127 #define IS_VALID_PA_PARAM(p) ((p) != 0 && (p) != -1)
1128 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
1129
1130 /*
1131 * Extract PA parameters
1132 */
1133 if (phy->phy_mode == IEEE80211_MODE_11A)
1134 sprom_ofs = BWI_SPROM_PA_PARAM_11A;
1135 else
1136 sprom_ofs = BWI_SPROM_PA_PARAM_11BG;
1137 for (i = 0; i < N(pa_params); ++i)
1138 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2));
1139
1140 for (i = 0; i < N(pa_params); ++i) {
1141 /*
1142 * If one of the PA parameters from SPROM is not valid,
1143 * fall back to the default values, if there are any.
1144 */
1145 if (!IS_VALID_PA_PARAM(pa_params[i])) {
1146 const int8_t *txpower_map;
1147
1148 if (phy->phy_mode == IEEE80211_MODE_11A) {
1149 if_printf(&sc->sc_ic.ic_if,
1150 "no tssi2dbm table for 11a PHY\n");
1151 return ENXIO;
1152 }
1153
1154 if (phy->phy_mode == IEEE80211_MODE_11G) {
1155 DPRINTF(sc,
1156 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1157 "%s\n", "use default 11g TSSI map");
1158 txpower_map = bwi_txpower_map_11g;
1159 } else {
1160 DPRINTF(sc,
1161 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1162 "%s\n", "use default 11b TSSI map");
1163 txpower_map = bwi_txpower_map_11b;
1164 }
1165
1166 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1167 bcopy(txpower_map, rf->rf_txpower_map0,
1168 sizeof(rf->rf_txpower_map0));
1169 goto back;
1170 }
1171 }
1172
1173 #undef N
1174
1175 /*
1176 * All of the PA parameters from SPROM are valid.
1177 */
1178
1179 /*
1180 * Extract idle TSSI from SPROM.
1181 */
1182 val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
1183 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1184 "sprom idle tssi: 0x%04x\n", val);
1185
1186 if (phy->phy_mode == IEEE80211_MODE_11A)
1187 mask = BWI_SPROM_IDLE_TSSI_MASK_11A;
1188 else
1189 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;
1190
1191 rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
1192 if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0))
1193 rf->rf_idle_tssi0 = 62;
1194
1195 #undef IS_VALID_PA_PARAM
1196
1197 /*
1198 * Calculate TX power map, which is indexed by TSSI
1199 */
1200 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1201 "%s\n", "TSSI-TX power map:");
1202 for (i = 0; i < BWI_TSSI_MAX; ++i) {
1203 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i,
1204 pa_params);
1205 if (error) {
1206 if_printf(&sc->sc_ic.ic_if,
1207 "bwi_rf_calc_txpower failed\n");
1208 break;
1209 }
1210
1211 #ifdef BWI_DEBUG
1212 if (i != 0 && i % 8 == 0) {
1213 _DPRINTF(sc,
1214 BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1215 "%s\n", "");
1216 }
1217 #endif
1218 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1219 "%d ", rf->rf_txpower_map0[i]);
1220 }
1221 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1222 "%s\n", "");
1223 back:
1224 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1225 "idle tssi0: %d\n", rf->rf_idle_tssi0);
1226 return error;
1227 }
1228
1229 void
1230 bwi_rf_lo_update(struct bwi_mac *mac)
1231 {
1232 struct bwi_softc *sc = mac->mac_sc;
1233 struct ifnet *ifp = &sc->sc_ic.ic_if;
1234 struct bwi_rf *rf = &mac->mac_rf;
1235 struct bwi_phy *phy = &mac->mac_phy;
1236 struct bwi_tpctl *tpctl = &mac->mac_tpctl;
1237 struct rf_saveregs regs;
1238 uint16_t ant_div, chan_ex;
1239 uint8_t devi_ctrl;
1240 u_int orig_chan;
1241
1242 /*
1243 * Save RF/PHY registers for later restoration
1244 */
1245 orig_chan = rf->rf_curchan;
1246 bzero(&regs, sizeof(regs));
1247
1248 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1249 SAVE_PHY_REG(mac, &regs, 429);
1250 SAVE_PHY_REG(mac, &regs, 802);
1251
1252 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1253 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1254 }
1255
1256 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1257 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
1258 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1259
1260 SAVE_PHY_REG(mac, &regs, 15);
1261 SAVE_PHY_REG(mac, &regs, 2a);
1262 SAVE_PHY_REG(mac, &regs, 35);
1263 SAVE_PHY_REG(mac, &regs, 60);
1264 SAVE_RF_REG(mac, &regs, 43);
1265 SAVE_RF_REG(mac, &regs, 7a);
1266 SAVE_RF_REG(mac, &regs, 52);
1267 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1268 SAVE_PHY_REG(mac, &regs, 811);
1269 SAVE_PHY_REG(mac, &regs, 812);
1270 SAVE_PHY_REG(mac, &regs, 814);
1271 SAVE_PHY_REG(mac, &regs, 815);
1272 }
1273
1274 /* Force to channel 6 */
1275 bwi_rf_set_chan(mac, 6, 0);
1276
1277 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1278 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1279 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1280 bwi_mac_dummy_xmit(mac);
1281 }
1282 RF_WRITE(mac, 0x43, 0x6);
1283
1284 bwi_phy_set_bbp_atten(mac, 2);
1285
1286 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
1287
1288 PHY_WRITE(mac, 0x2e, 0x7f);
1289 PHY_WRITE(mac, 0x80f, 0x78);
1290 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
1291 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
1292 PHY_WRITE(mac, 0x2b, 0x203);
1293 PHY_WRITE(mac, 0x2a, 0x8a3);
1294
1295 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1296 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);
1297 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);
1298 PHY_WRITE(mac, 0x811, 0x1b3);
1299 PHY_WRITE(mac, 0x812, 0xb2);
1300 }
1301
1302 if ((ifp->if_flags & IFF_RUNNING) == 0)
1303 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac);
1304 PHY_WRITE(mac, 0x80f, 0x8078);
1305
1306 /*
1307 * Measure all RF LO
1308 */
1309 devi_ctrl = _bwi_rf_lo_update(mac, regs.rf_7a);
1310
1311 /*
1312 * Restore saved RF/PHY registers
1313 */
1314 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1315 PHY_WRITE(mac, 0x15, 0xe300);
1316 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0);
1317 DELAY(5);
1318 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2);
1319 DELAY(2);
1320 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3);
1321 } else {
1322 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0);
1323 }
1324
1325 if ((ifp->if_flags & IFF_RUNNING) == 0)
1326 tpctl = NULL;
1327 bwi_rf_lo_adjust(mac, tpctl);
1328
1329 PHY_WRITE(mac, 0x2e, 0x807f);
1330 if (phy->phy_flags & BWI_PHY_F_LINKED)
1331 PHY_WRITE(mac, 0x2f, 0x202);
1332 else
1333 PHY_WRITE(mac, 0x2f, 0x101);
1334
1335 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1336
1337 RESTORE_PHY_REG(mac, &regs, 15);
1338 RESTORE_PHY_REG(mac, &regs, 2a);
1339 RESTORE_PHY_REG(mac, &regs, 35);
1340 RESTORE_PHY_REG(mac, &regs, 60);
1341
1342 RESTORE_RF_REG(mac, &regs, 43);
1343 RESTORE_RF_REG(mac, &regs, 7a);
1344
1345 regs.rf_52 &= 0xf0;
1346 regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);
1347 RF_WRITE(mac, 0x52, regs.rf_52);
1348
1349 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1350
1351 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1352 RESTORE_PHY_REG(mac, &regs, 811);
1353 RESTORE_PHY_REG(mac, &regs, 812);
1354 RESTORE_PHY_REG(mac, &regs, 814);
1355 RESTORE_PHY_REG(mac, &regs, 815);
1356 RESTORE_PHY_REG(mac, &regs, 429);
1357 RESTORE_PHY_REG(mac, &regs, 802);
1358 }
1359
1360 bwi_rf_set_chan(mac, orig_chan, 1);
1361 }
1362
1363 static uint32_t
1364 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
1365 {
1366 struct bwi_phy *phy = &mac->mac_phy;
1367 uint32_t devi = 0;
1368 int i;
1369
1370 if (phy->phy_flags & BWI_PHY_F_LINKED)
1371 ctrl <<= 8;
1372
1373 for (i = 0; i < 8; ++i) {
1374 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1375 PHY_WRITE(mac, 0x15, 0xe300);
1376 PHY_WRITE(mac, 0x812, ctrl | 0xb0);
1377 DELAY(5);
1378 PHY_WRITE(mac, 0x812, ctrl | 0xb2);
1379 DELAY(2);
1380 PHY_WRITE(mac, 0x812, ctrl | 0xb3);
1381 DELAY(4);
1382 PHY_WRITE(mac, 0x15, 0xf300);
1383 } else {
1384 PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
1385 DELAY(2);
1386 PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
1387 DELAY(4);
1388 PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
1389 }
1390 DELAY(8);
1391 devi += PHY_READ(mac, 0x2d);
1392 }
1393 return devi;
1394 }
1395
1396 static uint16_t
1397 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac)
1398 {
1399 uint32_t devi_min;
1400 uint16_t tp_ctrl2 = 0;
1401 int i;
1402
1403 RF_WRITE(mac, 0x52, 0);
1404 DELAY(10);
1405 devi_min = bwi_rf_lo_devi_measure(mac, 0);
1406
1407 for (i = 0; i < 16; ++i) {
1408 uint32_t devi;
1409
1410 RF_WRITE(mac, 0x52, i);
1411 DELAY(10);
1412 devi = bwi_rf_lo_devi_measure(mac, 0);
1413
1414 if (devi < devi_min) {
1415 devi_min = devi;
1416 tp_ctrl2 = i;
1417 }
1418 }
1419 return tp_ctrl2;
1420 }
1421
1422 static uint8_t
1423 _bwi_rf_lo_update(struct bwi_mac *mac, uint16_t orig_rf7a)
1424 {
1425 #define RF_ATTEN_LISTSZ 14
1426 #define BBP_ATTEN_MAX 4 /* half */
1427
1428 static const int rf_atten_list[RF_ATTEN_LISTSZ] =
1429 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 };
1430 static const int rf_atten_init_list[RF_ATTEN_LISTSZ] =
1431 { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 };
1432 static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] =
1433 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 };
1434
1435 struct ifnet *ifp = &mac->mac_sc->sc_ic.ic_if;
1436 struct bwi_rf_lo lo_save, *lo;
1437 uint8_t devi_ctrl = 0;
1438 int idx, adj_rf7a = 0;
1439
1440 bzero(&lo_save, sizeof(lo_save));
1441 for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) {
1442 int init_rf_atten = rf_atten_init_list[idx];
1443 int rf_atten = rf_atten_list[idx];
1444 int bbp_atten;
1445
1446 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) {
1447 uint16_t tp_ctrl2, rf7a;
1448
1449 if ((ifp->if_flags & IFF_RUNNING) == 0) {
1450 if (idx == 0) {
1451 bzero(&lo_save, sizeof(lo_save));
1452 } else if (init_rf_atten < 0) {
1453 lo = bwi_get_rf_lo(mac,
1454 rf_atten, 2 * bbp_atten);
1455 bcopy(lo, &lo_save, sizeof(lo_save));
1456 } else {
1457 lo = bwi_get_rf_lo(mac,
1458 init_rf_atten, 0);
1459 bcopy(lo, &lo_save, sizeof(lo_save));
1460 }
1461
1462 devi_ctrl = 0;
1463 adj_rf7a = 0;
1464
1465 /*
1466 * XXX
1467 * Linux driver overflows 'val'
1468 */
1469 if (init_rf_atten >= 0) {
1470 int val;
1471
1472 val = rf_atten * 2 + bbp_atten;
1473 if (val > 14) {
1474 adj_rf7a = 1;
1475 if (val > 17)
1476 devi_ctrl = 1;
1477 if (val > 19)
1478 devi_ctrl = 2;
1479 }
1480 }
1481 } else {
1482 lo = bwi_get_rf_lo(mac,
1483 rf_atten, 2 * bbp_atten);
1484 if (!bwi_rf_lo_isused(mac, lo))
1485 continue;
1486 bcopy(lo, &lo_save, sizeof(lo_save));
1487
1488 devi_ctrl = 3;
1489 adj_rf7a = 0;
1490 }
1491
1492 RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten);
1493
1494 tp_ctrl2 = mac->mac_tpctl.tp_ctrl2;
1495 if (init_rf_atten < 0)
1496 tp_ctrl2 |= (3 << 4);
1497 RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2);
1498
1499 DELAY(10);
1500
1501 bwi_phy_set_bbp_atten(mac, bbp_atten * 2);
1502
1503 rf7a = orig_rf7a & 0xfff0;
1504 if (adj_rf7a)
1505 rf7a |= 0x8;
1506 RF_WRITE(mac, 0x7a, rf7a);
1507
1508 lo = bwi_get_rf_lo(mac,
1509 rf_lo_measure_order[idx], bbp_atten * 2);
1510 bwi_rf_lo_measure(mac, &lo_save, lo, devi_ctrl);
1511 }
1512 }
1513 return devi_ctrl;
1514
1515 #undef RF_ATTEN_LISTSZ
1516 #undef BBP_ATTEN_MAX
1517 }
1518
1519 static void
1520 bwi_rf_lo_measure(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo,
1521 struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl)
1522 {
1523 #define LO_ADJUST_MIN 1
1524 #define LO_ADJUST_MAX 8
1525 #define LO_ADJUST(hi, lo) { .ctrl_hi = hi, .ctrl_lo = lo }
1526 static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = {
1527 LO_ADJUST(1, 1),
1528 LO_ADJUST(1, 0),
1529 LO_ADJUST(1, -1),
1530 LO_ADJUST(0, -1),
1531 LO_ADJUST(-1, -1),
1532 LO_ADJUST(-1, 0),
1533 LO_ADJUST(-1, 1),
1534 LO_ADJUST(0, 1)
1535 };
1536 #undef LO_ADJUST
1537
1538 struct bwi_rf_lo lo_min;
1539 uint32_t devi_min;
1540 int found, loop_count, adjust_state;
1541
1542 bcopy(src_lo, &lo_min, sizeof(lo_min));
1543 RF_LO_WRITE(mac, &lo_min);
1544 devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1545
1546 loop_count = 12; /* XXX */
1547 adjust_state = 0;
1548 do {
1549 struct bwi_rf_lo lo_base;
1550 int i, fin;
1551
1552 found = 0;
1553 if (adjust_state == 0) {
1554 i = LO_ADJUST_MIN;
1555 fin = LO_ADJUST_MAX;
1556 } else if (adjust_state % 2 == 0) {
1557 i = adjust_state - 1;
1558 fin = adjust_state + 1;
1559 } else {
1560 i = adjust_state - 2;
1561 fin = adjust_state + 2;
1562 }
1563
1564 if (i < LO_ADJUST_MIN)
1565 i += LO_ADJUST_MAX;
1566 KKASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN);
1567
1568 if (fin > LO_ADJUST_MAX)
1569 fin -= LO_ADJUST_MAX;
1570 KKASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN);
1571
1572 bcopy(&lo_min, &lo_base, sizeof(lo_base));
1573 for (;;) {
1574 struct bwi_rf_lo lo;
1575
1576 lo.ctrl_hi = lo_base.ctrl_hi +
1577 rf_lo_adjust[i - 1].ctrl_hi;
1578 lo.ctrl_lo = lo_base.ctrl_lo +
1579 rf_lo_adjust[i - 1].ctrl_lo;
1580
1581 if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) {
1582 uint32_t devi;
1583
1584 RF_LO_WRITE(mac, &lo);
1585 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1586 if (devi < devi_min) {
1587 devi_min = devi;
1588 adjust_state = i;
1589 found = 1;
1590 bcopy(&lo, &lo_min, sizeof(lo_min));
1591 }
1592 }
1593 if (i == fin)
1594 break;
1595 if (i == LO_ADJUST_MAX)
1596 i = LO_ADJUST_MIN;
1597 else
1598 ++i;
1599 }
1600 } while (loop_count-- && found);
1601
1602 bcopy(&lo_min, dst_lo, sizeof(*dst_lo));
1603
1604 #undef LO_ADJUST_MIN
1605 #undef LO_ADJUST_MAX
1606 }
1607
1608 static void
1609 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac)
1610 {
1611 #define SAVE_RF_MAX 3
1612 #define SAVE_PHY_MAX 8
1613
1614 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1615 { 0x7a, 0x52, 0x43 };
1616 static const uint16_t save_phy_regs[SAVE_PHY_MAX] =
1617 { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 };
1618
1619 struct bwi_softc *sc = mac->mac_sc;
1620 struct bwi_rf *rf = &mac->mac_rf;
1621 struct bwi_phy *phy = &mac->mac_phy;
1622 uint16_t save_rf[SAVE_RF_MAX];
1623 uint16_t save_phy[SAVE_PHY_MAX];
1624 uint16_t ant_div, bbp_atten, chan_ex;
1625 int16_t nrssi[2];
1626 int i;
1627
1628 /*
1629 * Save RF/PHY registers for later restoration
1630 */
1631 for (i = 0; i < SAVE_RF_MAX; ++i)
1632 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1633 for (i = 0; i < SAVE_PHY_MAX; ++i)
1634 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
1635
1636 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1637 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1638 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1639
1640 /*
1641 * Calculate nrssi0
1642 */
1643 if (phy->phy_rev >= 5)
1644 RF_CLRBITS(mac, 0x7a, 0xff80);
1645 else
1646 RF_CLRBITS(mac, 0x7a, 0xfff0);
1647 PHY_WRITE(mac, 0x30, 0xff);
1648
1649 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
1650
1651 PHY_WRITE(mac, 0x26, 0);
1652 PHY_SETBITS(mac, 0x15, 0x20);
1653 PHY_WRITE(mac, 0x2a, 0x8a3);
1654 RF_SETBITS(mac, 0x7a, 0x80);
1655
1656 nrssi[0] = (int16_t)PHY_READ(mac, 0x27);
1657
1658 /*
1659 * Calculate nrssi1
1660 */
1661 RF_CLRBITS(mac, 0x7a, 0xff80);
1662 if (phy->phy_version >= 2)
1663 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
1664 else if (phy->phy_version == 0)
1665 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
1666 else
1667 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff);
1668
1669 PHY_WRITE(mac, 0x20, 0x3f3f);
1670 PHY_WRITE(mac, 0x15, 0xf330);
1671
1672 RF_WRITE(mac, 0x5a, 0x60);
1673 RF_CLRBITS(mac, 0x43, 0xff0f);
1674
1675 PHY_WRITE(mac, 0x5a, 0x480);
1676 PHY_WRITE(mac, 0x59, 0x810);
1677 PHY_WRITE(mac, 0x58, 0xd);
1678
1679 DELAY(20);
1680
1681 nrssi[1] = (int16_t)PHY_READ(mac, 0x27);
1682
1683 /*
1684 * Restore saved RF/PHY registers
1685 */
1686 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
1687 RF_WRITE(mac, save_rf_regs[0], save_rf[0]);
1688
1689 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1690
1691 for (i = 1; i < 4; ++i)
1692 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1693
1694 bwi_rf_work_around(mac, rf->rf_curchan);
1695
1696 if (phy->phy_version != 0)
1697 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1698
1699 for (; i < SAVE_PHY_MAX; ++i)
1700 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1701
1702 for (i = 1; i < SAVE_RF_MAX; ++i)
1703 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1704
1705 /*
1706 * Install calculated narrow RSSI values
1707 */
1708 if (nrssi[0] == nrssi[1])
1709 rf->rf_nrssi_slope = 0x10000;
1710 else
1711 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1712 if (nrssi[0] <= -4) {
1713 rf->rf_nrssi[0] = nrssi[0];
1714 rf->rf_nrssi[1] = nrssi[1];
1715 }
1716
1717 #undef SAVE_RF_MAX
1718 #undef SAVE_PHY_MAX
1719 }
1720
1721 static void
1722 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac)
1723 {
1724 #define SAVE_RF_MAX 2
1725 #define SAVE_PHY_COMM_MAX 10
1726 #define SAVE_PHY6_MAX 8
1727
1728 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1729 { 0x7a, 0x43 };
1730 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = {
1731 0x0001, 0x0811, 0x0812, 0x0814,
1732 0x0815, 0x005a, 0x0059, 0x0058,
1733 0x000a, 0x0003
1734 };
1735 static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = {
1736 0x002e, 0x002f, 0x080f, 0x0810,
1737 0x0801, 0x0060, 0x0014, 0x0478
1738 };
1739
1740 struct bwi_phy *phy = &mac->mac_phy;
1741 uint16_t save_rf[SAVE_RF_MAX];
1742 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1743 uint16_t save_phy6[SAVE_PHY6_MAX];
1744 uint16_t rf7b = 0xffff;
1745 int16_t nrssi;
1746 int i, phy6_idx = 0;
1747
1748 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1749 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1750 for (i = 0; i < SAVE_RF_MAX; ++i)
1751 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1752
1753 PHY_CLRBITS(mac, 0x429, 0x8000);
1754 PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000);
1755 PHY_SETBITS(mac, 0x811, 0xc);
1756 PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4);
1757 PHY_CLRBITS(mac, 0x802, 0x3);
1758
1759 if (phy->phy_rev >= 6) {
1760 for (i = 0; i < SAVE_PHY6_MAX; ++i)
1761 save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]);
1762
1763 PHY_WRITE(mac, 0x2e, 0);
1764 PHY_WRITE(mac, 0x2f, 0);
1765 PHY_WRITE(mac, 0x80f, 0);
1766 PHY_WRITE(mac, 0x810, 0);
1767 PHY_SETBITS(mac, 0x478, 0x100);
1768 PHY_SETBITS(mac, 0x801, 0x40);
1769 PHY_SETBITS(mac, 0x60, 0x40);
1770 PHY_SETBITS(mac, 0x14, 0x200);
1771 }
1772
1773 RF_SETBITS(mac, 0x7a, 0x70);
1774 RF_SETBITS(mac, 0x7a, 0x80);
1775
1776 DELAY(30);
1777
1778 nrssi = bwi_nrssi_11g(mac);
1779 if (nrssi == 31) {
1780 for (i = 7; i >= 4; --i) {
1781 RF_WRITE(mac, 0x7b, i);
1782 DELAY(20);
1783 nrssi = bwi_nrssi_11g(mac);
1784 if (nrssi < 31 && rf7b == 0xffff)
1785 rf7b = i;
1786 }
1787 if (rf7b == 0xffff)
1788 rf7b = 4;
1789 } else {
1790 struct bwi_gains gains;
1791
1792 RF_CLRBITS(mac, 0x7a, 0xff80);
1793
1794 PHY_SETBITS(mac, 0x814, 0x1);
1795 PHY_CLRBITS(mac, 0x815, 0x1);
1796 PHY_SETBITS(mac, 0x811, 0xc);
1797 PHY_SETBITS(mac, 0x812, 0xc);
1798 PHY_SETBITS(mac, 0x811, 0x30);
1799 PHY_SETBITS(mac, 0x812, 0x30);
1800 PHY_WRITE(mac, 0x5a, 0x480);
1801 PHY_WRITE(mac, 0x59, 0x810);
1802 PHY_WRITE(mac, 0x58, 0xd);
1803 if (phy->phy_version == 0)
1804 PHY_WRITE(mac, 0x3, 0x122);
1805 else
1806 PHY_SETBITS(mac, 0xa, 0x2000);
1807 PHY_SETBITS(mac, 0x814, 0x4);
1808 PHY_CLRBITS(mac, 0x815, 0x4);
1809 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1810 RF_SETBITS(mac, 0x7a, 0xf);
1811
1812 bzero(&gains, sizeof(gains));
1813 gains.tbl_gain1 = 3;
1814 gains.tbl_gain2 = 0;
1815 gains.phy_gain = 1;
1816 bwi_set_gains(mac, &gains);
1817
1818 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf);
1819 DELAY(30);
1820
1821 nrssi = bwi_nrssi_11g(mac);
1822 if (nrssi == -32) {
1823 for (i = 0; i < 4; ++i) {
1824 RF_WRITE(mac, 0x7b, i);
1825 DELAY(20);
1826 nrssi = bwi_nrssi_11g(mac);
1827 if (nrssi > -31 && rf7b == 0xffff)
1828 rf7b = i;
1829 }
1830 if (rf7b == 0xffff)
1831 rf7b = 3;
1832 } else {
1833 rf7b = 0;
1834 }
1835 }
1836 RF_WRITE(mac, 0x7b, rf7b);
1837
1838 /*
1839 * Restore saved RF/PHY registers
1840 */
1841 if (phy->phy_rev >= 6) {
1842 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) {
1843 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1844 save_phy6[phy6_idx]);
1845 }
1846 }
1847
1848 /* Saved PHY registers 0, 1, 2 are handled later */
1849 for (i = 3; i < SAVE_PHY_COMM_MAX; ++i)
1850 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1851
1852 for (i = SAVE_RF_MAX - 1; i >= 0; --i)
1853 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1854
1855 PHY_SETBITS(mac, 0x802, 0x3);
1856 PHY_SETBITS(mac, 0x429, 0x8000);
1857
1858 bwi_set_gains(mac, NULL);
1859
1860 if (phy->phy_rev >= 6) {
1861 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) {
1862 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1863 save_phy6[phy6_idx]);
1864 }
1865 }
1866
1867 PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]);
1868 PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]);
1869 PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]);
1870
1871 #undef SAVE_RF_MAX
1872 #undef SAVE_PHY_COMM_MAX
1873 #undef SAVE_PHY6_MAX
1874 }
1875
1876 static void
1877 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac)
1878 {
1879 #define SAVE_RF_MAX 3
1880 #define SAVE_PHY_COMM_MAX 4
1881 #define SAVE_PHY3_MAX 8
1882
1883 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1884 { 0x7a, 0x52, 0x43 };
1885 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] =
1886 { 0x15, 0x5a, 0x59, 0x58 };
1887 static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = {
1888 0x002e, 0x002f, 0x080f, 0x0810,
1889 0x0801, 0x0060, 0x0014, 0x0478
1890 };
1891
1892 struct bwi_softc *sc = mac->mac_sc;
1893 struct bwi_phy *phy = &mac->mac_phy;
1894 struct bwi_rf *rf = &mac->mac_rf;
1895 uint16_t save_rf[SAVE_RF_MAX];
1896 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1897 uint16_t save_phy3[SAVE_PHY3_MAX];
1898 uint16_t ant_div, bbp_atten, chan_ex;
1899 struct bwi_gains gains;
1900 int16_t nrssi[2];
1901 int i, phy3_idx = 0;
1902
1903 if (rf->rf_rev >= 9)
1904 return;
1905 else if (rf->rf_rev == 8)
1906 bwi_rf_set_nrssi_ofs_11g(mac);
1907
1908 PHY_CLRBITS(mac, 0x429, 0x8000);
1909 PHY_CLRBITS(mac, 0x802, 0x3);
1910
1911 /*
1912 * Save RF/PHY registers for later restoration
1913 */
1914 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1915 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
1916
1917 for (i = 0; i < SAVE_RF_MAX; ++i)
1918 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1919 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1920 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1921
1922 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1923 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1924
1925 if (phy->phy_rev >= 3) {
1926 for (i = 0; i < SAVE_PHY3_MAX; ++i)
1927 save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]);
1928
1929 PHY_WRITE(mac, 0x2e, 0);
1930 PHY_WRITE(mac, 0x810, 0);
1931
1932 if (phy->phy_rev == 4 || phy->phy_rev == 6 ||
1933 phy->phy_rev == 7) {
1934 PHY_SETBITS(mac, 0x478, 0x100);
1935 PHY_SETBITS(mac, 0x810, 0x40);
1936 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) {
1937 PHY_CLRBITS(mac, 0x810, 0x40);
1938 }
1939
1940 PHY_SETBITS(mac, 0x60, 0x40);
1941 PHY_SETBITS(mac, 0x14, 0x200);
1942 }
1943
1944 /*
1945 * Calculate nrssi0
1946 */
1947 RF_SETBITS(mac, 0x7a, 0x70);
1948
1949 bzero(&gains, sizeof(gains));
1950 gains.tbl_gain1 = 0;
1951 gains.tbl_gain2 = 8;
1952 gains.phy_gain = 0;
1953 bwi_set_gains(mac, &gains);
1954
1955 RF_CLRBITS(mac, 0x7a, 0xff08);
1956 if (phy->phy_rev >= 2) {
1957 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30);
1958 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
1959 }
1960
1961 RF_SETBITS(mac, 0x7a, 0x80);
1962 DELAY(20);
1963 nrssi[0] = bwi_nrssi_11g(mac);
1964
1965 /*
1966 * Calculate nrssi1
1967 */
1968 RF_CLRBITS(mac, 0x7a, 0xff80);
1969 if (phy->phy_version >= 2)
1970 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1971 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
1972
1973 RF_SETBITS(mac, 0x7a, 0xf);
1974 PHY_WRITE(mac, 0x15, 0xf330);
1975 if (phy->phy_rev >= 2) {
1976 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20);
1977 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20);
1978 }
1979
1980 bzero(&gains, sizeof(gains));
1981 gains.tbl_gain1 = 3;
1982 gains.tbl_gain2 = 0;
1983 gains.phy_gain = 1;
1984 bwi_set_gains(mac, &gains);
1985
1986 if (rf->rf_rev == 8) {
1987 RF_WRITE(mac, 0x43, 0x1f);
1988 } else {
1989 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60);
1990 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
1991 }
1992 PHY_WRITE(mac, 0x5a, 0x480);
1993 PHY_WRITE(mac, 0x59, 0x810);
1994 PHY_WRITE(mac, 0x58, 0xd);
1995 DELAY(20);
1996
1997 nrssi[1] = bwi_nrssi_11g(mac);
1998
1999 /*
2000 * Install calculated narrow RSSI values
2001 */
2002 if (nrssi[1] == nrssi[0])
2003 rf->rf_nrssi_slope = 0x10000;
2004 else
2005 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
2006 if (nrssi[0] >= -4) {
2007 rf->rf_nrssi[0] = nrssi[1];
2008 rf->rf_nrssi[1] = nrssi[0];
2009 }
2010
2011 /*
2012 * Restore saved RF/PHY registers
2013 */
2014 if (phy->phy_rev >= 3) {
2015 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) {
2016 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2017 save_phy3[phy3_idx]);
2018 }
2019 }
2020 if (phy->phy_rev >= 2) {
2021 PHY_CLRBITS(mac, 0x812, 0x30);
2022 PHY_CLRBITS(mac, 0x811, 0x30);
2023 }
2024
2025 for (i = 0; i < SAVE_RF_MAX; ++i)
2026 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
2027
2028 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
2029 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
2030 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
2031
2032 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
2033 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
2034
2035 bwi_rf_work_around(mac, rf->rf_curchan);
2036 PHY_SETBITS(mac, 0x802, 0x3);
2037 bwi_set_gains(mac, NULL);
2038 PHY_SETBITS(mac, 0x429, 0x8000);
2039
2040 if (phy->phy_rev >= 3) {
2041 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) {
2042 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2043 save_phy3[phy3_idx]);
2044 }
2045 }
2046
2047 bwi_rf_init_sw_nrssi_table(mac);
2048 bwi_rf_set_nrssi_thr_11g(mac);
2049
2050 #undef SAVE_RF_MAX
2051 #undef SAVE_PHY_COMM_MAX
2052 #undef SAVE_PHY3_MAX
2053 }
2054
2055 static void
2056 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac)
2057 {
2058 struct bwi_rf *rf = &mac->mac_rf;
2059 int d, i;
2060
2061 d = 0x1f - rf->rf_nrssi[0];
2062 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2063 int val;
2064
2065 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
2066 if (val < 0)
2067 val = 0;
2068 else if (val > 0x3f)
2069 val = 0x3f;
2070
2071 rf->rf_nrssi_table[i] = val;
2072 }
2073 }
2074
2075 void
2076 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust)
2077 {
2078 int i;
2079
2080 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2081 int16_t val;
2082
2083 val = bwi_nrssi_read(mac, i);
2084
2085 val -= adjust;
2086 if (val < -32)
2087 val = -32;
2088 else if (val > 31);
2089 val = 31;
2090
2091 bwi_nrssi_write(mac, i, val);
2092 }
2093 }
2094
2095 static void
2096 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac)
2097 {
2098 struct bwi_rf *rf = &mac->mac_rf;
2099 int32_t thr;
2100
2101 if (rf->rf_type != BWI_RF_T_BCM2050 ||
2102 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0)
2103 return;
2104
2105 /*
2106 * Calculate nrssi threshold
2107 */
2108 if (rf->rf_rev >= 6) {
2109 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32;
2110 thr += 20 * (rf->rf_nrssi[0] + 1);
2111 thr /= 40;
2112 } else {
2113 thr = rf->rf_nrssi[1] - 5;
2114 }
2115 if (thr < 0)
2116 thr = 0;
2117 else if (thr > 0x3e)
2118 thr = 0x3e;
2119
2120 PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B); /* dummy read */
2121 PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c);
2122
2123 if (rf->rf_rev >= 6) {
2124 PHY_WRITE(mac, 0x87, 0xe0d);
2125 PHY_WRITE(mac, 0x86, 0xc0b);
2126 PHY_WRITE(mac, 0x85, 0xa09);
2127 PHY_WRITE(mac, 0x84, 0x808);
2128 PHY_WRITE(mac, 0x83, 0x808);
2129 PHY_WRITE(mac, 0x82, 0x604);
2130 PHY_WRITE(mac, 0x81, 0x302);
2131 PHY_WRITE(mac, 0x80, 0x100);
2132 }
2133 }
2134
2135 static __inline int32_t
2136 _nrssi_threshold(const struct bwi_rf *rf, int32_t val)
2137 {
2138 val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
2139 val += (rf->rf_nrssi[0] << 6);
2140 if (val < 32)
2141 val += 31;
2142 else
2143 val += 32;
2144 val >>= 6;
2145 if (val < -31)
2146 val = -31;
2147 else if (val > 31)
2148 val = 31;
2149 return val;
2150 }
2151
2152 static void
2153 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac)
2154 {
2155 int32_t thr1, thr2;
2156 uint16_t thr;
2157
2158 /*
2159 * Find the two nrssi thresholds
2160 */
2161 if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 ||
2162 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
2163 int16_t nrssi;
2164
2165 nrssi = bwi_nrssi_read(mac, 0x20);
2166 if (nrssi >= 32)
2167 nrssi -= 64;
2168
2169 if (nrssi < 3) {
2170 thr1 = 0x2b;
2171 thr2 = 0x27;
2172 } else {
2173 thr1 = 0x2d;
2174 thr2 = 0x2b;
2175 }
2176 } else {
2177 /* TODO Interfere mode */
2178 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11);
2179 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe);
2180 }
2181
2182 #define NRSSI_THR1_MASK __BITS(5, 0)
2183 #define NRSSI_THR2_MASK __BITS(11, 6)
2184
2185 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
2186 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
2187 PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr);
2188
2189 #undef NRSSI_THR1_MASK
2190 #undef NRSSI_THR2_MASK
2191 }
2192
2193 void
2194 bwi_rf_clear_tssi(struct bwi_mac *mac)
2195 {
2196 /* XXX use function pointer */
2197 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) {
2198 /* TODO:11A */
2199 } else {
2200 uint16_t val;
2201 int i;
2202
2203 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
2204 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
2205
2206 for (i = 0; i < 2; ++i) {
2207 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2208 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
2209 }
2210
2211 for (i = 0; i < 2; ++i) {
2212 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2213 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
2214 }
2215 }
2216 }
2217
2218 void
2219 bwi_rf_clear_state(struct bwi_rf *rf)
2220 {
2221 int i;
2222
2223 rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS;
2224 bzero(rf->rf_lo, sizeof(rf->rf_lo));
2225 bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used));
2226
2227 rf->rf_nrssi_slope = 0;
2228 rf->rf_nrssi[0] = BWI_INVALID_NRSSI;
2229 rf->rf_nrssi[1] = BWI_INVALID_NRSSI;
2230
2231 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i)
2232 rf->rf_nrssi_table[i] = i;
2233
2234 rf->rf_lo_gain = 0;
2235 rf->rf_rx_gain = 0;
2236
2237 bcopy(rf->rf_txpower_map0, rf->rf_txpower_map,
2238 sizeof(rf->rf_txpower_map));
2239 rf->rf_idle_tssi = rf->rf_idle_tssi0;
2240 }
2241
2242 static void
2243 bwi_rf_on_11a(struct bwi_mac *mac)
2244 {
2245 /* TODO:11A */
2246 }
2247
2248 static void
2249 bwi_rf_on_11bg(struct bwi_mac *mac)
2250 {
2251 struct bwi_phy *phy = &mac->mac_phy;
2252
2253 PHY_WRITE(mac, 0x15, 0x8000);
2254 PHY_WRITE(mac, 0x15, 0xcc00);
2255 if (phy->phy_flags & BWI_PHY_F_LINKED)
2256 PHY_WRITE(mac, 0x15, 0xc0);
2257 else
2258 PHY_WRITE(mac, 0x15, 0);
2259
2260 bwi_rf_set_chan(mac, 6 /* XXX */, 1);
2261 }
2262
2263 void
2264 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode)
2265 {
2266 struct bwi_softc *sc = mac->mac_sc;
2267 struct bwi_phy *phy = &mac->mac_phy;
2268 uint16_t val;
2269
2270 KKASSERT(ant_mode == BWI_ANT_MODE_0 ||
2271 ant_mode == BWI_ANT_MODE_1 ||
2272 ant_mode == BWI_ANT_MODE_AUTO);
2273
2274 HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2275
2276 if (phy->phy_mode == IEEE80211_MODE_11B) {
2277 /* NOTE: v4/v3 conflicts, take v3 */
2278 if (mac->mac_rev == 2)
2279 val = BWI_ANT_MODE_AUTO;
2280 else
2281 val = ant_mode;
2282 val <<= 7;
2283 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
2284 } else { /* 11a/g */
2285 /* XXX reg/value naming */
2286 val = ant_mode << 7;
2287 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
2288
2289 if (ant_mode == BWI_ANT_MODE_AUTO)
2290 PHY_CLRBITS(mac, 0x42b, 0x100);
2291
2292 if (phy->phy_mode == IEEE80211_MODE_11A) {
2293 /* TODO:11A */
2294 } else { /* 11g */
2295 if (ant_mode == BWI_ANT_MODE_AUTO)
2296 PHY_SETBITS(mac, 0x48c, 0x2000);
2297 else
2298 PHY_CLRBITS(mac, 0x48c, 0x2000);
2299
2300 if (phy->phy_rev >= 2) {
2301 PHY_SETBITS(mac, 0x461, 0x10);
2302 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15);
2303 if (phy->phy_rev == 2) {
2304 PHY_WRITE(mac, 0x427, 0x8);
2305 } else {
2306 PHY_FILT_SETBITS(mac, 0x427,
2307 0xff00, 0x8);
2308 }
2309
2310 if (phy->phy_rev >= 6)
2311 PHY_WRITE(mac, 0x49b, 0xdc);
2312 }
2313 }
2314 }
2315
2316 /* XXX v4 set AUTO_ANTDIV unconditionally */
2317 if (ant_mode == BWI_ANT_MODE_AUTO)
2318 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2319
2320 val = ant_mode << 8;
2321 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON,
2322 0xfc3f, val);
2323 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK,
2324 0xfc3f, val);
2325 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP,
2326 0xfc3f, val);
2327
2328 /* XXX what's these */
2329 if (phy->phy_mode == IEEE80211_MODE_11B)
2330 CSR_SETBITS_2(sc, 0x5e, 0x4);
2331
2332 CSR_WRITE_4(sc, 0x100, 0x1000000);
2333 if (mac->mac_rev < 5)
2334 CSR_WRITE_4(sc, 0x10c, 0x1000000);
2335
2336 mac->mac_rf.rf_ant_mode = ant_mode;
2337 }
2338
2339 int
2340 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs)
2341 {
2342 int i;
2343
2344 for (i = 0; i < 4; ) {
2345 uint16_t val;
2346
2347 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
2348 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
2349 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
2350 }
2351
2352 for (i = 0; i < 4; ++i) {
2353 if (tssi[i] == BWI_INVALID_TSSI)
2354 return EINVAL;
2355 }
2356 return 0;
2357 }
2358
2359 int
2360 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr)
2361 {
2362 struct bwi_rf *rf = &mac->mac_rf;
2363 int pwr_idx;
2364
2365 pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi;
2366 #if 0
2367 if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX)
2368 return EINVAL;
2369 #else
2370 if (pwr_idx < 0)
2371 pwr_idx = 0;
2372 else if (pwr_idx >= BWI_TSSI_MAX)
2373 pwr_idx = BWI_TSSI_MAX - 1;
2374 #endif
2375
2376 *txpwr = rf->rf_txpower_map[pwr_idx];
2377 return 0;
2378 }
2379
2380 static int
2381 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2382 {
2383 uint16_t flags1, flags3;
2384 int rssi, lna_gain;
2385
2386 rssi = hdr->rxh_rssi;
2387 flags1 = le16toh(hdr->rxh_flags1);
2388 flags3 = le16toh(hdr->rxh_flags3);
2389
2390 #define NEW_BCM2050_RSSI
2391 #ifdef NEW_BCM2050_RSSI
2392 if (flags1 & BWI_RXH_F1_OFDM) {
2393 if (rssi > 127)
2394 rssi -= 256;
2395 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2396 rssi += 17;
2397 else
2398 rssi -= 4;
2399 return rssi;
2400 }
2401
2402 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2403 struct bwi_rf *rf = &mac->mac_rf;
2404
2405 if (rssi >= BWI_NRSSI_TBLSZ)
2406 rssi = BWI_NRSSI_TBLSZ - 1;
2407
2408 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2409 rssi -= 67;
2410 } else {
2411 rssi = ((31 - rssi) * -149) / 128;
2412 rssi -= 68;
2413 }
2414
2415 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2416 return rssi;
2417
2418 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2419 rssi += 20;
2420
2421 lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),
2422 BWI_RXH_PHYINFO_LNAGAIN);
2423 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_RX,
2424 "lna_gain %d, phyinfo 0x%04x\n",
2425 lna_gain, le16toh(hdr->rxh_phyinfo));
2426 switch (lna_gain) {
2427 case 0:
2428 rssi += 27;
2429 break;
2430 case 1:
2431 rssi += 6;
2432 break;
2433 case 2:
2434 rssi += 12;
2435 break;
2436 case 3:
2437 /*
2438 * XXX
2439 * According to v3 spec, we should do _nothing_ here,
2440 * but it seems that the result RSSI will be too low
2441 * (relative to what ath(4) says). Raise it a little
2442 * bit.
2443 */
2444 rssi += 5;
2445 break;
2446 default:
2447 panic("impossible lna gain %d", lna_gain);
2448 }
2449 #else /* !NEW_BCM2050_RSSI */
2450 lna_gain = 0; /* shut up gcc warning */
2451
2452 if (flags1 & BWI_RXH_F1_OFDM) {
2453 if (rssi > 127)
2454 rssi -= 256;
2455 rssi = (rssi * 73) / 64;
2456
2457 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2458 rssi += 25;
2459 else
2460 rssi -= 3;
2461 return rssi;
2462 }
2463
2464 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2465 struct bwi_rf *rf = &mac->mac_rf;
2466
2467 if (rssi >= BWI_NRSSI_TBLSZ)
2468 rssi = BWI_NRSSI_TBLSZ - 1;
2469
2470 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2471 rssi -= 57;
2472 } else {
2473 rssi = ((31 - rssi) * -149) / 128;
2474 rssi -= 68;
2475 }
2476
2477 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2478 return rssi;
2479
2480 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2481 rssi += 25;
2482 #endif /* NEW_BCM2050_RSSI */
2483 return rssi;
2484 }
2485
2486 static int
2487 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2488 {
2489 uint16_t flags1;
2490 int rssi;
2491
2492 rssi = (((int)hdr->rxh_rssi - 11) * 103) / 64;
2493
2494 flags1 = le16toh(hdr->rxh_flags1);
2495 if (flags1 & BWI_RXH_F1_BCM2053_RSSI)
2496 rssi -= 109;
2497 else
2498 rssi -= 83;
2499 return rssi;
2500 }
2501
2502 static int
2503 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2504 {
2505 int rssi;
2506
2507 rssi = hdr->rxh_rssi;
2508 if (rssi > 127)
2509 rssi -= 256;
2510 return rssi;
2511 }
A repo for keeping AMD64 port code before merging with the master