sys/platform/pc64/x86_64/swtch.s

   1 /*
   2  * Copyright (c) 2003,2004,2008 The DragonFly Project.  All rights reserved.
   3  * Copyright (c) 2008 Jordan Gordeev.
   4  *
   5  * This code is derived from software contributed to The DragonFly Project
   6  * by Matthew Dillon <dillon@backplane.com>
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  *
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in
  16  *    the documentation and/or other materials provided with the
  17  *    distribution.
  18  * 3. Neither the name of The DragonFly Project nor the names of its
  19  *    contributors may be used to endorse or promote products derived
  20  *    from this software without specific, prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  25  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  26  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  28  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  30  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  32  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  33  * SUCH DAMAGE.
  34  *
  35  * Copyright (c) 1990 The Regents of the University of California.
  36  * All rights reserved.
  37  *
  38  * This code is derived from software contributed to Berkeley by
  39  * William Jolitz.
  40  *
  41  * Redistribution and use in source and binary forms, with or without
  42  * modification, are permitted provided that the following conditions
  43  * are met:
  44  * 1. Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
  46  * 2. Redistributions in binary form must reproduce the above copyright
  47  *    notice, this list of conditions and the following disclaimer in the
  48  *    documentation and/or other materials provided with the distribution.
  49  * 3. Neither the name of the University nor the names of its contributors
  50  *    may be used to endorse or promote products derived from this software
  51  *    without specific prior written permission.
  52  *
  53  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  54  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  55  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  56  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  57  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  58  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  59  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  60  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  61  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  62  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  63  * SUCH DAMAGE.
  64  *
  65  * $FreeBSD: src/sys/i386/i386/swtch.s,v 1.89.2.10 2003/01/23 03:36:24 ps Exp $
  66  */
  67
  68 //#include "use_npx.h"
  69
  70 #include <sys/rtprio.h>
  71
  72 #include <machine/asmacros.h>
  73 #include <machine/segments.h>
  74
  75 #include <machine/pmap.h>
  76 #if 0 /* JG */
  77 #include <machine_base/apic/apicreg.h>
  78 #endif
  79 #include <machine/lock.h>
  80
  81 #include "assym.s"
  82
  83 #define MPLOCKED        lock ;
  84
  85 /*
  86  * PREEMPT_OPTIMIZE
  87  *
  88  * This feature allows the preempting (interrupt) kernel thread to borrow
  89  * %cr3 from the user process it interrupts, allowing us to do-away with
  90  * two %cr3 stores, two atomic ops (pm_active is not modified), and pmap
  91  * lock tests (not needed since pm_active is not modified).
  92  *
  93  * Unfortunately, I couldn't really measure any result so for now the
  94  * optimization is disabled.
  95  */
  96 #undef PREEMPT_OPTIMIZE
  97
  98 /*
  99  * LWP_SWITCH_OPTIMIZE
 100  *
 101  * This optimization attempted to avoid a %cr3 store and atomic op, and
 102  * it might have been useful on older cpus but newer cpus (and more
 103  * importantly multi-core cpus) generally do not switch between LWPs on
 104  * the same cpu.  Multiple user threads are more likely to be distributed
 105  * across multiple cpus.  In cpu-bound situations the scheduler will already
 106  * be in batch-mode (meaning relatively few context-switches/sec), and
 107  * otherwise the lwp(s) are likely to be blocked waiting for events.
 108  *
 109  * On the flip side, the conditionals this option uses measurably reduce
 110  * performance (just slightly, honestly).  So this option is disabled.
 111  */
 112 #undef LWP_SWITCH_OPTIMIZE
 113
 114         /*
 115          * Global Declarations
 116          */
 117         .data
 118
 119         .globl  panic
 120         .globl  lwkt_switch_return
 121
 122 #if defined(SWTCH_OPTIM_STATS)
 123         .globl  swtch_optim_stats, tlb_flush_count
 124 swtch_optim_stats:      .long   0               /* number of _swtch_optims */
 125 tlb_flush_count:        .long   0
 126 #endif
 127
 128         /*
 129          * Code
 130          */
 131         .text
 132
 133 /*
 134  * cpu_heavy_switch(struct thread *next_thread)
 135  *
 136  *      Switch from the current thread to a new thread.  This entry
 137  *      is normally called via the thread->td_switch function, and will
 138  *      only be called when the current thread is a heavy weight process.
 139  *
 140  *      Some instructions have been reordered to reduce pipeline stalls.
 141  *
 142  *      YYY disable interrupts once giant is removed.
 143  */
 144 ENTRY(cpu_heavy_switch)
 145         /*
 146          * Save RIP, RSP and callee-saved registers (RBX, RBP, R12-R15).
 147          */
 148         movq    PCPU(curthread),%rcx
 149         /* On top of the stack is the return adress. */
 150         movq    (%rsp),%rax                     /* (reorder optimization) */
 151         movq    TD_PCB(%rcx),%rdx               /* RDX = PCB */
 152         movq    %rax,PCB_RIP(%rdx)              /* return PC may be modified */
 153         movq    %rbx,PCB_RBX(%rdx)
 154         movq    %rsp,PCB_RSP(%rdx)
 155         movq    %rbp,PCB_RBP(%rdx)
 156         movq    %r12,PCB_R12(%rdx)
 157         movq    %r13,PCB_R13(%rdx)
 158         movq    %r14,PCB_R14(%rdx)
 159         movq    %r15,PCB_R15(%rdx)
 160
 161         /*
 162          * Clear the cpu bit in the pmap active mask.  The restore
 163          * function will set the bit in the pmap active mask.
 164          *
 165          * If we are switching away due to a preempt, TD_PREEMPTED(%rdi)
 166          * will be non-NULL.  In this situation we do want to avoid extra
 167          * atomic ops and %cr3 reloads (see top of file for reasoning).
 168          *
 169          * NOTE: Do not try to optimize avoiding the %cr3 reload or pm_active
 170          *       adjustment.  This mattered on uni-processor systems but in
 171          *       multi-core systems we are highly unlikely to be switching
 172          *       to another thread belonging to the same process on this cpu.
 173          *
 174          *       (more likely the target thread is still sleeping, or if cpu-
 175          *       bound the scheduler is in batch mode and the switch rate is
 176          *       already low).
 177          */
 178         movq    %rcx,%rbx                       /* RBX = oldthread */
 179 #ifdef PREEMPT_OPTIMIZE
 180         /*
 181          * If we are being preempted the target thread borrows our %cr3
 182          * and we leave our pmap bits intact for the duration.
 183          */
 184         movq    TD_PREEMPTED(%rdi),%r13
 185         testq   %r13,%r13
 186         jne     2f
 187 #endif
 188
 189         movq    TD_LWP(%rcx),%rcx               /* RCX = oldlwp */
 190         movq    LWP_VMSPACE(%rcx), %rcx         /* RCX = oldvmspace */
 191 #ifdef LWP_SWITCH_OPTIMIZE
 192         movq    TD_LWP(%rdi),%r13               /* R13 = newlwp */
 193         testq   %r13,%r13                       /* might not be a heavy */
 194         jz      1f
 195         cmpq    LWP_VMSPACE(%r13),%rcx          /* same vmspace? */
 196         je      2f
 197 1:
 198 #endif
 199         movq    PCPU(cpumask_simple),%rsi
 200         movq    PCPU(cpumask_offset),%r12
 201         xorq    $-1,%rsi
 202         MPLOCKED andq %rsi, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1)
 203 2:
 204
 205         /*
 206          * Push the LWKT switch restore function, which resumes a heavy
 207          * weight process.  Note that the LWKT switcher is based on
 208          * TD_SP, while the heavy weight process switcher is based on
 209          * PCB_RSP.  TD_SP is usually two ints pushed relative to
 210          * PCB_RSP.  We push the flags for later restore by cpu_heavy_restore.
 211          */
 212         pushfq
 213         cli
 214         movq    $cpu_heavy_restore, %rax
 215         pushq   %rax
 216         movq    %rsp,TD_SP(%rbx)
 217
 218         /*
 219          * Save debug regs if necessary
 220          */
 221         movq    PCB_FLAGS(%rdx),%rax
 222         andq    $PCB_DBREGS,%rax
 223         jz      1f                              /* no, skip over */
 224         movq    %dr7,%rax                       /* yes, do the save */
 225         movq    %rax,PCB_DR7(%rdx)
 226         /* JG correct value? */
 227         andq    $0x0000fc00, %rax               /* disable all watchpoints */
 228         movq    %rax,%dr7
 229         movq    %dr6,%rax
 230         movq    %rax,PCB_DR6(%rdx)
 231         movq    %dr3,%rax
 232         movq    %rax,PCB_DR3(%rdx)
 233         movq    %dr2,%rax
 234         movq    %rax,PCB_DR2(%rdx)
 235         movq    %dr1,%rax
 236         movq    %rax,PCB_DR1(%rdx)
 237         movq    %dr0,%rax
 238         movq    %rax,PCB_DR0(%rdx)
 239 1:
 240
 241 #if 1
 242         /*
 243          * Save the FP state if we have used the FP.  Note that calling
 244          * npxsave will NULL out PCPU(npxthread).
 245          */
 246         cmpq    %rbx,PCPU(npxthread)
 247         jne     1f
 248         movq    %rdi,%r12               /* save %rdi. %r12 is callee-saved */
 249         movq    TD_SAVEFPU(%rbx),%rdi
 250         call    npxsave                 /* do it in a big C function */
 251         movq    %r12,%rdi               /* restore %rdi */
 252 1:
 253 #endif
 254
 255         /*
 256          * Switch to the next thread, which was passed as an argument
 257          * to cpu_heavy_switch().  The argument is in %rdi.
 258          * Set the current thread, load the stack pointer,
 259          * and 'ret' into the switch-restore function.
 260          *
 261          * The switch restore function expects the new thread to be in %rax
 262          * and the old one to be in %rbx.
 263          *
 264          * There is a one-instruction window where curthread is the new
 265          * thread but %rsp still points to the old thread's stack, but
 266          * we are protected by a critical section so it is ok.
 267          */
 268         movq    %rdi,%rax               /* RAX = newtd, RBX = oldtd */
 269         movq    %rax,PCPU(curthread)
 270         movq    TD_SP(%rax),%rsp
 271         ret
 272
 273 /*
 274  *  cpu_exit_switch(struct thread *next)
 275  *
 276  *      The switch function is changed to this when a thread is going away
 277  *      for good.  We have to ensure that the MMU state is not cached, and
 278  *      we don't bother saving the existing thread state before switching.
 279  *
 280  *      At this point we are in a critical section and this cpu owns the
 281  *      thread's token, which serves as an interlock until the switchout is
 282  *      complete.
 283  */
 284 ENTRY(cpu_exit_switch)
 285
 286 #ifdef PREEMPT_OPTIMIZE
 287         /*
 288          * If we were preempting we are switching back to the original thread.
 289          * In this situation we already have the original thread's %cr3 and
 290          * should not replace it!
 291          */
 292         testl   $TDF_PREEMPT_DONE, TD_FLAGS(%rdi)
 293         jne     1f
 294 #endif
 295
 296         /*
 297          * Get us out of the vmspace
 298          */
 299         movq    KPML4phys,%rcx
 300         movq    %cr3,%rax
 301         cmpq    %rcx,%rax
 302         je      1f
 303
 304         movq    %rcx,%cr3
 305 1:
 306         movq    PCPU(curthread),%rbx
 307
 308         /*
 309          * If this is a process/lwp, deactivate the pmap after we've
 310          * switched it out.
 311          */
 312         movq    TD_LWP(%rbx),%rcx
 313         testq   %rcx,%rcx
 314         jz      2f
 315         movq    LWP_VMSPACE(%rcx), %rcx         /* RCX = vmspace */
 316
 317         movq    PCPU(cpumask_simple),%rax
 318         movq    PCPU(cpumask_offset),%r12
 319         xorq    $-1,%rax
 320         MPLOCKED andq %rax, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1)
 321 2:
 322         /*
 323          * Switch to the next thread.  RET into the restore function, which
 324          * expects the new thread in RAX and the old in RBX.
 325          *
 326          * There is a one-instruction window where curthread is the new
 327          * thread but %rsp still points to the old thread's stack, but
 328          * we are protected by a critical section so it is ok.
 329          */
 330         cli
 331         movq    %rdi,%rax
 332         movq    %rax,PCPU(curthread)
 333         movq    TD_SP(%rax),%rsp
 334         ret
 335
 336 /*
 337  * cpu_heavy_restore()  (current thread in %rax on entry, old thread in %rbx)
 338  *
 339  *      Restore the thread after an LWKT switch.  This entry is normally
 340  *      called via the LWKT switch restore function, which was pulled
 341  *      off the thread stack and jumped to.
 342  *
 343  *      This entry is only called if the thread was previously saved
 344  *      using cpu_heavy_switch() (the heavy weight process thread switcher),
 345  *      or when a new process is initially scheduled.
 346  *
 347  *      NOTE: The lwp may be in any state, not necessarily LSRUN, because
 348  *      a preemption switch may interrupt the process and then return via
 349  *      cpu_heavy_restore.
 350  *
 351  *      YYY theoretically we do not have to restore everything here, a lot
 352  *      of this junk can wait until we return to usermode.  But for now
 353  *      we restore everything.
 354  *
 355  *      YYY the PCB crap is really crap, it makes startup a bitch because
 356  *      we can't switch away.
 357  *
 358  *      YYY note: spl check is done in mi_switch when it splx()'s.
 359  */
 360
 361 ENTRY(cpu_heavy_restore)
 362         movq    TD_PCB(%rax),%rdx               /* RDX = PCB */
 363         movq    %rdx, PCPU(common_tss) + TSS_RSP0
 364         popfq
 365
 366 #if defined(SWTCH_OPTIM_STATS)
 367         incl    _swtch_optim_stats
 368 #endif
 369 #ifdef PREEMPT_OPTIMIZE
 370         /*
 371          * If restoring our thread after a preemption has returned to
 372          * us, our %cr3 and pmap were borrowed and are being returned to
 373          * us and no further action on those items need be taken.
 374          */
 375         testl   $TDF_PREEMPT_DONE, TD_FLAGS(%rax)
 376         jne     4f
 377 #endif
 378
 379         /*
 380          * Tell the pmap that our cpu is using the VMSPACE now.  We cannot
 381          * safely test/reload %cr3 until after we have set the bit in the
 382          * pmap.
 383          *
 384          * We must do an interlocked test of the CPULOCK_EXCL at the same
 385          * time.  If found to be set we will have to wait for it to clear
 386          * and then do a forced reload of %cr3 (even if the value matches).
 387          *
 388          * XXX When switching between two LWPs sharing the same vmspace
 389          *     the cpu_heavy_switch() code currently avoids clearing the
 390          *     cpu bit in PM_ACTIVE.  So if the bit is already set we can
 391          *     avoid checking for the interlock via CPULOCK_EXCL.  We currently
 392          *     do not perform this optimization.
 393          */
 394         movq    TD_LWP(%rax),%rcx
 395         movq    LWP_VMSPACE(%rcx),%rcx          /* RCX = vmspace */
 396
 397         movq    PCPU(cpumask_simple),%rsi
 398         movq    PCPU(cpumask_offset),%r12
 399         MPLOCKED orq %rsi, VM_PMAP+PM_ACTIVE(%rcx, %r12, 1)
 400
 401         movl    VM_PMAP+PM_ACTIVE_LOCK(%rcx),%esi
 402         testl   $CPULOCK_EXCL,%esi
 403         jz      1f
 404
 405         movq    %rax,%r12               /* save newthread ptr */
 406         movq    %rcx,%rdi               /* (found to be set) */
 407         call    pmap_interlock_wait     /* pmap_interlock_wait(%rdi:vm) */
 408         movq    %r12,%rax
 409
 410         /*
 411          * Need unconditional load cr3
 412          */
 413         movq    TD_PCB(%rax),%rdx       /* RDX = PCB */
 414         movq    PCB_CR3(%rdx),%rcx      /* RCX = desired CR3 */
 415         jmp     2f                      /* unconditional reload */
 416 1:
 417         /*
 418          * Restore the MMU address space.  If it is the same as the last
 419          * thread we don't have to invalidate the tlb (i.e. reload cr3).
 420          * YYY which naturally also means that the PM_ACTIVE bit had better
 421          * already have been set before we set it above, check? YYY
 422          */
 423         movq    TD_PCB(%rax),%rdx               /* RDX = PCB */
 424         movq    %cr3,%rsi                       /* RSI = current CR3 */
 425         movq    PCB_CR3(%rdx),%rcx              /* RCX = desired CR3 */
 426         cmpq    %rsi,%rcx
 427         je      4f
 428 2:
 429 #if defined(SWTCH_OPTIM_STATS)
 430         decl    _swtch_optim_stats
 431         incl    _tlb_flush_count
 432 #endif
 433         movq    %rcx,%cr3
 434 4:
 435
 436         /*
 437          * NOTE: %rbx is the previous thread and %rax is the new thread.
 438          *       %rbx is retained throughout so we can return it.
 439          *
 440          *       lwkt_switch[_return] is responsible for handling TDF_RUNNING.
 441          */
 442
 443         /*
 444          * Deal with the PCB extension, restore the private tss
 445          */
 446         movq    PCB_EXT(%rdx),%rdi      /* check for a PCB extension */
 447         movq    $1,%rcx                 /* maybe mark use of a private tss */
 448         testq   %rdi,%rdi
 449 #if 0 /* JG */
 450         jnz     2f
 451 #endif
 452
 453         /*
 454          * Going back to the common_tss.  We may need to update TSS_RSP0
 455          * which sets the top of the supervisor stack when entering from
 456          * usermode.  The PCB is at the top of the stack but we need another
 457          * 16 bytes to take vm86 into account.
 458          */
 459         movq    %rdx,%rcx
 460         /*leaq  -TF_SIZE(%rdx),%rcx*/
 461         movq    %rcx, PCPU(common_tss) + TSS_RSP0
 462
 463 #if 0 /* JG */
 464         cmpl    $0,PCPU(private_tss)    /* don't have to reload if      */
 465         je      3f                      /* already using the common TSS */
 466
 467         /* JG? */
 468         subq    %rcx,%rcx               /* unmark use of private tss */
 469
 470         /*
 471          * Get the address of the common TSS descriptor for the ltr.
 472          * There is no way to get the address of a segment-accessed variable
 473          * so we store a self-referential pointer at the base of the per-cpu
 474          * data area and add the appropriate offset.
 475          */
 476         /* JG movl? */
 477         movq    $gd_common_tssd, %rdi
 478         /* JG name for "%gs:0"? */
 479         addq    %gs:0, %rdi
 480
 481         /*
 482          * Move the correct TSS descriptor into the GDT slot, then reload
 483          * ltr.
 484          */
 485 2:
 486         /* JG */
 487         movl    %rcx,PCPU(private_tss)          /* mark/unmark private tss */
 488         movq    PCPU(tss_gdt), %rbx             /* entry in GDT */
 489         movq    0(%rdi), %rax
 490         movq    %rax, 0(%rbx)
 491         movl    $GPROC0_SEL*8, %esi             /* GSEL(entry, SEL_KPL) */
 492         ltr     %si
 493 #endif
 494
 495 3:
 496         /*
 497          * Restore the user %gs and %fs
 498          */
 499         movq    PCB_FSBASE(%rdx),%r9
 500         cmpq    PCPU(user_fs),%r9
 501         je      4f
 502         movq    %rdx,%r10
 503         movq    %r9,PCPU(user_fs)
 504         movl    $MSR_FSBASE,%ecx
 505         movl    PCB_FSBASE(%r10),%eax
 506         movl    PCB_FSBASE+4(%r10),%edx
 507         wrmsr
 508         movq    %r10,%rdx
 509 4:
 510         movq    PCB_GSBASE(%rdx),%r9
 511         cmpq    PCPU(user_gs),%r9
 512         je      5f
 513         movq    %rdx,%r10
 514         movq    %r9,PCPU(user_gs)
 515         movl    $MSR_KGSBASE,%ecx       /* later swapgs moves it to GSBASE */
 516         movl    PCB_GSBASE(%r10),%eax
 517         movl    PCB_GSBASE+4(%r10),%edx
 518         wrmsr
 519         movq    %r10,%rdx
 520 5:
 521
 522         /*
 523          * Restore general registers.  %rbx is restored later.
 524          */
 525         movq    PCB_RSP(%rdx), %rsp
 526         movq    PCB_RBP(%rdx), %rbp
 527         movq    PCB_R12(%rdx), %r12
 528         movq    PCB_R13(%rdx), %r13
 529         movq    PCB_R14(%rdx), %r14
 530         movq    PCB_R15(%rdx), %r15
 531         movq    PCB_RIP(%rdx), %rax
 532         movq    %rax, (%rsp)
 533         movw    $KDSEL,%ax
 534         movw    %ax,%es
 535
 536 #if 0 /* JG */
 537         /*
 538          * Restore the user LDT if we have one
 539          */
 540         cmpl    $0, PCB_USERLDT(%edx)
 541         jnz     1f
 542         movl    _default_ldt,%eax
 543         cmpl    PCPU(currentldt),%eax
 544         je      2f
 545         lldt    _default_ldt
 546         movl    %eax,PCPU(currentldt)
 547         jmp     2f
 548 1:      pushl   %edx
 549         call    set_user_ldt
 550         popl    %edx
 551 2:
 552 #endif
 553 #if 0 /* JG */
 554         /*
 555          * Restore the user TLS if we have one
 556          */
 557         pushl   %edx
 558         call    set_user_TLS
 559         popl    %edx
 560 #endif
 561
 562         /*
 563          * Restore the DEBUG register state if necessary.
 564          */
 565         movq    PCB_FLAGS(%rdx),%rax
 566         andq    $PCB_DBREGS,%rax
 567         jz      1f                              /* no, skip over */
 568         movq    PCB_DR6(%rdx),%rax              /* yes, do the restore */
 569         movq    %rax,%dr6
 570         movq    PCB_DR3(%rdx),%rax
 571         movq    %rax,%dr3
 572         movq    PCB_DR2(%rdx),%rax
 573         movq    %rax,%dr2
 574         movq    PCB_DR1(%rdx),%rax
 575         movq    %rax,%dr1
 576         movq    PCB_DR0(%rdx),%rax
 577         movq    %rax,%dr0
 578         movq    %dr7,%rax                /* load dr7 so as not to disturb */
 579         /* JG correct value? */
 580         andq    $0x0000fc00,%rax         /*   reserved bits               */
 581         /* JG we've got more registers on x86_64 */
 582         movq    PCB_DR7(%rdx),%rcx
 583         /* JG correct value? */
 584         andq    $~0x0000fc00,%rcx
 585         orq     %rcx,%rax
 586         movq    %rax,%dr7
 587
 588         /*
 589          * Clear the QUICKRET flag when restoring a user process context
 590          * so we don't try to do a quick syscall return.
 591          */
 592 1:
 593         andl    $~RQF_QUICKRET,PCPU(reqflags)
 594         movq    %rbx,%rax
 595         movq    PCB_RBX(%rdx),%rbx
 596         ret
 597
 598 /*
 599  * savectx(struct pcb *pcb)
 600  *
 601  * Update pcb, saving current processor state.
 602  */
 603 ENTRY(savectx)
 604         /* fetch PCB */
 605         /* JG use %rdi instead of %rcx everywhere? */
 606         movq    %rdi,%rcx
 607
 608         /* caller's return address - child won't execute this routine */
 609         movq    (%rsp),%rax
 610         movq    %rax,PCB_RIP(%rcx)
 611
 612         movq    %cr3,%rax
 613         movq    %rax,PCB_CR3(%rcx)
 614
 615         movq    %rbx,PCB_RBX(%rcx)
 616         movq    %rsp,PCB_RSP(%rcx)
 617         movq    %rbp,PCB_RBP(%rcx)
 618         movq    %r12,PCB_R12(%rcx)
 619         movq    %r13,PCB_R13(%rcx)
 620         movq    %r14,PCB_R14(%rcx)
 621         movq    %r15,PCB_R15(%rcx)
 622
 623 #if 1
 624         /*
 625          * If npxthread == NULL, then the npx h/w state is irrelevant and the
 626          * state had better already be in the pcb.  This is true for forks
 627          * but not for dumps (the old book-keeping with FP flags in the pcb
 628          * always lost for dumps because the dump pcb has 0 flags).
 629          *
 630          * If npxthread != NULL, then we have to save the npx h/w state to
 631          * npxthread's pcb and copy it to the requested pcb, or save to the
 632          * requested pcb and reload.  Copying is easier because we would
 633          * have to handle h/w bugs for reloading.  We used to lose the
 634          * parent's npx state for forks by forgetting to reload.
 635          */
 636         movq    PCPU(npxthread),%rax
 637         testq   %rax,%rax
 638         jz      1f
 639
 640         pushq   %rcx                    /* target pcb */
 641         movq    TD_SAVEFPU(%rax),%rax   /* originating savefpu area */
 642         pushq   %rax
 643
 644         movq    %rax,%rdi
 645         call    npxsave
 646
 647         popq    %rax
 648         popq    %rcx
 649
 650         movq    $PCB_SAVEFPU_SIZE,%rdx
 651         leaq    PCB_SAVEFPU(%rcx),%rcx
 652         movq    %rcx,%rsi
 653         movq    %rax,%rdi
 654         call    bcopy
 655 #endif
 656
 657 1:
 658         ret
 659
 660 /*
 661  * cpu_idle_restore()   (current thread in %rax on entry, old thread in %rbx)
 662  *                      (one-time entry)
 663  *
 664  *      Don't bother setting up any regs other than %rbp so backtraces
 665  *      don't die.  This restore function is used to bootstrap into the
 666  *      cpu_idle() LWKT only, after that cpu_lwkt_*() will be used for
 667  *      switching.
 668  *
 669  *      Clear TDF_RUNNING in old thread only after we've cleaned up %cr3.
 670  *      This only occurs during system boot so no special handling is
 671  *      required for migration.
 672  *
 673  *      If we are an AP we have to call ap_init() before jumping to
 674  *      cpu_idle().  ap_init() will synchronize with the BP and finish
 675  *      setting up various ncpu-dependant globaldata fields.  This may
 676  *      happen on UP as well as SMP if we happen to be simulating multiple
 677  *      cpus.
 678  */
 679 ENTRY(cpu_idle_restore)
 680         /* cli */
 681         movq    KPML4phys,%rcx
 682         xorq    %rbp,%rbp               /* dummy frame pointer */
 683         pushq   $0                      /* dummy return pc */
 684
 685         /* NOTE: idle thread can never preempt */
 686         movq    %rcx,%cr3
 687         cmpl    $0,PCPU(cpuid)
 688         je      1f
 689         andl    $~TDF_RUNNING,TD_FLAGS(%rbx)
 690         orl     $TDF_RUNNING,TD_FLAGS(%rax)     /* manual, no switch_return */
 691         call    ap_init
 692         /*
 693          * ap_init can decide to enable interrupts early, but otherwise, or if
 694          * we are UP, do it here.
 695          */
 696         sti
 697         jmp     cpu_idle
 698
 699         /*
 700          * cpu 0's idle thread entry for the first time must use normal
 701          * lwkt_switch_return() semantics or a pending cpu migration on
 702          * thread0 will deadlock.
 703          */
 704 1:
 705         sti
 706         pushq   %rax
 707         movq    %rbx,%rdi
 708         call    lwkt_switch_return
 709         popq    %rax
 710         jmp     cpu_idle
 711
 712 /*
 713  * cpu_kthread_restore() (current thread is %rax on entry, previous is %rbx)
 714  *                       (one-time execution)
 715  *
 716  *      Don't bother setting up any regs other then %rbp so backtraces
 717  *      don't die.  This restore function is used to bootstrap into an
 718  *      LWKT based kernel thread only.  cpu_lwkt_switch() will be used
 719  *      after this.
 720  *
 721  *      Because this switch target does not 'return' to lwkt_switch()
 722  *      we have to call lwkt_switch_return(otd) to clean up otd.
 723  *      otd is in %ebx.
 724  *
 725  *      Since all of our context is on the stack we are reentrant and
 726  *      we can release our critical section and enable interrupts early.
 727  */
 728 ENTRY(cpu_kthread_restore)
 729         sti
 730         movq    KPML4phys,%rcx
 731         movq    TD_PCB(%rax),%r13
 732         xorq    %rbp,%rbp
 733
 734 #ifdef PREEMPT_OPTIMIZE
 735         /*
 736          * If we are preempting someone we borrow their %cr3, do not overwrite
 737          * it!
 738          */
 739         movq    TD_PREEMPTED(%rax),%r14
 740         testq   %r14,%r14
 741         jne     1f
 742 #endif
 743         movq    %rcx,%cr3
 744 1:
 745
 746         /*
 747          * rax and rbx come from the switchout code.  Call
 748          * lwkt_switch_return(otd).
 749          *
 750          * NOTE: unlike i386, %rsi and %rdi are not call-saved regs.
 751          */
 752         pushq   %rax
 753         movq    %rbx,%rdi
 754         call    lwkt_switch_return
 755         popq    %rax
 756         decl    TD_CRITCOUNT(%rax)
 757         movq    PCB_R12(%r13),%rdi      /* argument to RBX function */
 758         movq    PCB_RBX(%r13),%rax      /* thread function */
 759         /* note: top of stack return address inherited by function */
 760         jmp     *%rax
 761
 762 /*
 763  * cpu_lwkt_switch(struct thread *)
 764  *
 765  *      Standard LWKT switching function.  Only non-scratch registers are
 766  *      saved and we don't bother with the MMU state or anything else.
 767  *
 768  *      This function is always called while in a critical section.
 769  *
 770  *      There is a one-instruction window where curthread is the new
 771  *      thread but %rsp still points to the old thread's stack, but
 772  *      we are protected by a critical section so it is ok.
 773  */
 774 ENTRY(cpu_lwkt_switch)
 775         pushq   %rbp    /* JG note: GDB hacked to locate ebp rel to td_sp */
 776         pushq   %rbx
 777         movq    PCPU(curthread),%rbx    /* becomes old thread in restore */
 778         pushq   %r12
 779         pushq   %r13
 780         pushq   %r14
 781         pushq   %r15
 782         pushfq
 783         cli
 784
 785 #if 1
 786         /*
 787          * Save the FP state if we have used the FP.  Note that calling
 788          * npxsave will NULL out PCPU(npxthread).
 789          *
 790          * We have to deal with the FP state for LWKT threads in case they
 791          * happen to get preempted or block while doing an optimized
 792          * bzero/bcopy/memcpy.
 793          */
 794         cmpq    %rbx,PCPU(npxthread)
 795         jne     1f
 796         movq    %rdi,%r12               /* save %rdi. %r12 is callee-saved */
 797         movq    TD_SAVEFPU(%rbx),%rdi
 798         call    npxsave                 /* do it in a big C function */
 799         movq    %r12,%rdi               /* restore %rdi */
 800 1:
 801 #endif
 802
 803         movq    %rdi,%rax               /* switch to this thread */
 804         pushq   $cpu_lwkt_restore
 805         movq    %rsp,TD_SP(%rbx)
 806         /*
 807          * %rax contains new thread, %rbx contains old thread.
 808          */
 809         movq    %rax,PCPU(curthread)
 810         movq    TD_SP(%rax),%rsp
 811         ret
 812
 813 /*
 814  * cpu_lwkt_restore()   (current thread in %rax on entry)
 815  *
 816  * Standard LWKT restore function.  This function is always called
 817  * while in a critical section.
 818  *
 819  * WARNING! Due to preemption the restore function can be used to 'return'
 820  *          to the original thread.   Interrupt disablement must be
 821  *          protected through the switch so we cannot run splz here.
 822  */
 823 ENTRY(cpu_lwkt_restore)
 824 #ifdef PREEMPT_OPTIMIZE
 825         /*
 826          * If we are preempting someone we borrow their %cr3 and pmap
 827          */
 828         movq    TD_PREEMPTED(%rax),%r14 /* kernel thread preempting? */
 829         testq   %r14,%r14
 830         jne     1f                      /* yes, borrow %cr3 from old thread */
 831 #endif
 832         movq    KPML4phys,%rcx  /* YYY borrow but beware desched/cpuchg/exit */
 833         movq    %cr3,%rdx
 834         cmpq    %rcx,%rdx
 835         je      1f
 836         movq    %rcx,%cr3
 837 1:
 838         /*
 839          * Safety, clear RSP0 in the tss so it isn't pointing at the
 840          * previous thread's kstack (if a heavy weight user thread).
 841          * RSP0 should only be used in ring 3 transitions and kernel
 842          * threads run in ring 0 so there should be none.
 843          */
 844         xorq    %rdx,%rdx
 845         movq    %rdx, PCPU(common_tss) + TSS_RSP0
 846
 847         /*
 848          * NOTE: %rbx is the previous thread and %rax is the new thread.
 849          *       %rbx is retained throughout so we can return it.
 850          *
 851          *       lwkt_switch[_return] is responsible for handling TDF_RUNNING.
 852          */
 853         movq    %rbx,%rax
 854         popfq
 855         popq    %r15
 856         popq    %r14
 857         popq    %r13
 858         popq    %r12
 859         popq    %rbx
 860         popq    %rbp
 861         ret