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kernel/mrsas: Fix a double assignment.
[dragonfly.git] / sys / dev / drm / drm_edid.c
blob42a91e43e035f3c717b31e23561756470932c69b
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include "opt_drm.h"
31
32 #include <linux/kernel.h>
33 #include <linux/hdmi.h>
34 #include <linux/i2c.h>
35 #include <linux/module.h>
36 #include <linux/vga_switcheroo.h>
37 #include <drm/drmP.h>
38 #include <drm/drm_edid.h>
39 #include <drm/drm_displayid.h>
40 #include <linux/string.h>
41
42 #include <bus/iicbus/iic.h>
43 #include <bus/iicbus/iiconf.h>
44 #include "iicbus_if.h"
45
46 #define version_greater(edid, maj, min) \
47 (((edid)->version > (maj)) || \
48 ((edid)->version == (maj) && (edid)->revision > (min)))
49
50 #define EDID_EST_TIMINGS 16
51 #define EDID_STD_TIMINGS 8
52 #define EDID_DETAILED_TIMINGS 4
53
54 /*
55 * EDID blocks out in the wild have a variety of bugs, try to collect
56 * them here (note that userspace may work around broken monitors first,
57 * but fixes should make their way here so that the kernel "just works"
58 * on as many displays as possible).
59 */
60
61 /* First detailed mode wrong, use largest 60Hz mode */
62 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
63 /* Reported 135MHz pixel clock is too high, needs adjustment */
64 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
65 /* Prefer the largest mode at 75 Hz */
66 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
67 /* Detail timing is in cm not mm */
68 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
69 /* Detailed timing descriptors have bogus size values, so just take the
70 * maximum size and use that.
71 */
72 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
73 /* Monitor forgot to set the first detailed is preferred bit. */
74 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
75 /* use +hsync +vsync for detailed mode */
76 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
77 /* Force reduced-blanking timings for detailed modes */
78 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
79 /* Force 8bpc */
80 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
81 /* Force 12bpc */
82 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
83 /* Force 6bpc */
84 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
85
86 struct detailed_mode_closure {
87 struct drm_connector *connector;
88 struct edid *edid;
89 bool preferred;
90 u32 quirks;
91 int modes;
92 };
93
94 #define LEVEL_DMT 0
95 #define LEVEL_GTF 1
96 #define LEVEL_GTF2 2
97 #define LEVEL_CVT 3
98
99 static struct edid_quirk {
100 char vendor[4];
101 int product_id;
102 u32 quirks;
103 } edid_quirk_list[] = {
104 /* Acer AL1706 */
105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
106 /* Acer F51 */
107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
108 /* Unknown Acer */
109 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
110
111 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
112 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
113
114 /* Belinea 10 15 55 */
115 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
116 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
117
118 /* Envision Peripherals, Inc. EN-7100e */
119 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
120 /* Envision EN2028 */
121 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
122
123 /* Funai Electronics PM36B */
124 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
125 EDID_QUIRK_DETAILED_IN_CM },
126
127 /* LG Philips LCD LP154W01-A5 */
128 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
129 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
130
131 /* Philips 107p5 CRT */
132 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
133
134 /* Proview AY765C */
135 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
136
137 /* Samsung SyncMaster 205BW. Note: irony */
138 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
139 /* Samsung SyncMaster 22[5-6]BW */
140 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
141 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
142
143 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
144 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
145
146 /* ViewSonic VA2026w */
147 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
148
149 /* Medion MD 30217 PG */
150 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
151
152 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
153 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
154 };
155
156 /*
157 * Autogenerated from the DMT spec.
158 * This table is copied from xfree86/modes/xf86EdidModes.c.
159 */
160 static const struct drm_display_mode drm_dmt_modes[] = {
161 /* 0x01 - 640x350@85Hz */
162 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
163 736, 832, 0, 350, 382, 385, 445, 0,
164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
165 /* 0x02 - 640x400@85Hz */
166 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
167 736, 832, 0, 400, 401, 404, 445, 0,
168 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
169 /* 0x03 - 720x400@85Hz */
170 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
171 828, 936, 0, 400, 401, 404, 446, 0,
172 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
173 /* 0x04 - 640x480@60Hz */
174 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
175 752, 800, 0, 480, 490, 492, 525, 0,
176 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
177 /* 0x05 - 640x480@72Hz */
178 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
179 704, 832, 0, 480, 489, 492, 520, 0,
180 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
181 /* 0x06 - 640x480@75Hz */
182 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
183 720, 840, 0, 480, 481, 484, 500, 0,
184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
185 /* 0x07 - 640x480@85Hz */
186 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
187 752, 832, 0, 480, 481, 484, 509, 0,
188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
189 /* 0x08 - 800x600@56Hz */
190 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
191 896, 1024, 0, 600, 601, 603, 625, 0,
192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
193 /* 0x09 - 800x600@60Hz */
194 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
195 968, 1056, 0, 600, 601, 605, 628, 0,
196 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
197 /* 0x0a - 800x600@72Hz */
198 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
199 976, 1040, 0, 600, 637, 643, 666, 0,
200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
201 /* 0x0b - 800x600@75Hz */
202 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
203 896, 1056, 0, 600, 601, 604, 625, 0,
204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
205 /* 0x0c - 800x600@85Hz */
206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
207 896, 1048, 0, 600, 601, 604, 631, 0,
208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
209 /* 0x0d - 800x600@120Hz RB */
210 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
211 880, 960, 0, 600, 603, 607, 636, 0,
212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
213 /* 0x0e - 848x480@60Hz */
214 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
215 976, 1088, 0, 480, 486, 494, 517, 0,
216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
217 /* 0x0f - 1024x768@43Hz, interlace */
218 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
219 1208, 1264, 0, 768, 768, 776, 817, 0,
220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
221 DRM_MODE_FLAG_INTERLACE) },
222 /* 0x10 - 1024x768@60Hz */
223 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
224 1184, 1344, 0, 768, 771, 777, 806, 0,
225 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
226 /* 0x11 - 1024x768@70Hz */
227 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
228 1184, 1328, 0, 768, 771, 777, 806, 0,
229 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
230 /* 0x12 - 1024x768@75Hz */
231 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
232 1136, 1312, 0, 768, 769, 772, 800, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
234 /* 0x13 - 1024x768@85Hz */
235 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
236 1168, 1376, 0, 768, 769, 772, 808, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
238 /* 0x14 - 1024x768@120Hz RB */
239 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
240 1104, 1184, 0, 768, 771, 775, 813, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
242 /* 0x15 - 1152x864@75Hz */
243 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
244 1344, 1600, 0, 864, 865, 868, 900, 0,
245 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
246 /* 0x55 - 1280x720@60Hz */
247 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
248 1430, 1650, 0, 720, 725, 730, 750, 0,
249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
250 /* 0x16 - 1280x768@60Hz RB */
251 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
252 1360, 1440, 0, 768, 771, 778, 790, 0,
253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
254 /* 0x17 - 1280x768@60Hz */
255 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
256 1472, 1664, 0, 768, 771, 778, 798, 0,
257 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
258 /* 0x18 - 1280x768@75Hz */
259 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
260 1488, 1696, 0, 768, 771, 778, 805, 0,
261 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
262 /* 0x19 - 1280x768@85Hz */
263 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
264 1496, 1712, 0, 768, 771, 778, 809, 0,
265 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
266 /* 0x1a - 1280x768@120Hz RB */
267 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
268 1360, 1440, 0, 768, 771, 778, 813, 0,
269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
270 /* 0x1b - 1280x800@60Hz RB */
271 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
272 1360, 1440, 0, 800, 803, 809, 823, 0,
273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
274 /* 0x1c - 1280x800@60Hz */
275 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
276 1480, 1680, 0, 800, 803, 809, 831, 0,
277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
278 /* 0x1d - 1280x800@75Hz */
279 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
280 1488, 1696, 0, 800, 803, 809, 838, 0,
281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
282 /* 0x1e - 1280x800@85Hz */
283 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
284 1496, 1712, 0, 800, 803, 809, 843, 0,
285 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
286 /* 0x1f - 1280x800@120Hz RB */
287 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
288 1360, 1440, 0, 800, 803, 809, 847, 0,
289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x20 - 1280x960@60Hz */
291 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
292 1488, 1800, 0, 960, 961, 964, 1000, 0,
293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
294 /* 0x21 - 1280x960@85Hz */
295 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
296 1504, 1728, 0, 960, 961, 964, 1011, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x22 - 1280x960@120Hz RB */
299 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
300 1360, 1440, 0, 960, 963, 967, 1017, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
302 /* 0x23 - 1280x1024@60Hz */
303 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
304 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
306 /* 0x24 - 1280x1024@75Hz */
307 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
308 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x25 - 1280x1024@85Hz */
311 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
312 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x26 - 1280x1024@120Hz RB */
315 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
316 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x27 - 1360x768@60Hz */
319 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
320 1536, 1792, 0, 768, 771, 777, 795, 0,
321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x28 - 1360x768@120Hz RB */
323 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
324 1440, 1520, 0, 768, 771, 776, 813, 0,
325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
326 /* 0x51 - 1366x768@60Hz */
327 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
328 1579, 1792, 0, 768, 771, 774, 798, 0,
329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x56 - 1366x768@60Hz */
331 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
332 1436, 1500, 0, 768, 769, 772, 800, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
334 /* 0x29 - 1400x1050@60Hz RB */
335 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
336 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x2a - 1400x1050@60Hz */
339 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
340 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x2b - 1400x1050@75Hz */
343 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
344 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x2c - 1400x1050@85Hz */
347 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
348 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x2d - 1400x1050@120Hz RB */
351 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
352 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x2e - 1440x900@60Hz RB */
355 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
356 1520, 1600, 0, 900, 903, 909, 926, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
358 /* 0x2f - 1440x900@60Hz */
359 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
360 1672, 1904, 0, 900, 903, 909, 934, 0,
361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x30 - 1440x900@75Hz */
363 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
364 1688, 1936, 0, 900, 903, 909, 942, 0,
365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
366 /* 0x31 - 1440x900@85Hz */
367 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
368 1696, 1952, 0, 900, 903, 909, 948, 0,
369 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x32 - 1440x900@120Hz RB */
371 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
372 1520, 1600, 0, 900, 903, 909, 953, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
374 /* 0x53 - 1600x900@60Hz */
375 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
376 1704, 1800, 0, 900, 901, 904, 1000, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x33 - 1600x1200@60Hz */
379 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
380 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
382 /* 0x34 - 1600x1200@65Hz */
383 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
384 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x35 - 1600x1200@70Hz */
387 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
388 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
390 /* 0x36 - 1600x1200@75Hz */
391 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
392 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x37 - 1600x1200@85Hz */
395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
396 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x38 - 1600x1200@120Hz RB */
399 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
400 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x39 - 1680x1050@60Hz RB */
403 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
404 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
406 /* 0x3a - 1680x1050@60Hz */
407 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
408 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x3b - 1680x1050@75Hz */
411 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
412 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x3c - 1680x1050@85Hz */
415 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
416 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
417 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
418 /* 0x3d - 1680x1050@120Hz RB */
419 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
420 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x3e - 1792x1344@60Hz */
423 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
424 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x3f - 1792x1344@75Hz */
427 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
428 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x40 - 1792x1344@120Hz RB */
431 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
432 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
433 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
434 /* 0x41 - 1856x1392@60Hz */
435 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
436 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
437 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
438 /* 0x42 - 1856x1392@75Hz */
439 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
440 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x43 - 1856x1392@120Hz RB */
443 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
444 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
446 /* 0x52 - 1920x1080@60Hz */
447 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
448 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
449 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
450 /* 0x44 - 1920x1200@60Hz RB */
451 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
452 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
454 /* 0x45 - 1920x1200@60Hz */
455 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
456 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x46 - 1920x1200@75Hz */
459 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
460 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
461 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x47 - 1920x1200@85Hz */
463 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
464 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
466 /* 0x48 - 1920x1200@120Hz RB */
467 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
468 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x49 - 1920x1440@60Hz */
471 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
472 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x4a - 1920x1440@75Hz */
475 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
476 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x4b - 1920x1440@120Hz RB */
479 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
480 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
482 /* 0x54 - 2048x1152@60Hz */
483 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
484 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
486 /* 0x4c - 2560x1600@60Hz RB */
487 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
488 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
490 /* 0x4d - 2560x1600@60Hz */
491 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
492 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x4e - 2560x1600@75Hz */
495 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
496 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
498 /* 0x4f - 2560x1600@85Hz */
499 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
500 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x50 - 2560x1600@120Hz RB */
503 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
504 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
506 /* 0x57 - 4096x2160@60Hz RB */
507 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
508 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x58 - 4096x2160@59.94Hz RB */
511 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
512 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 };
515
516 /*
517 * These more or less come from the DMT spec. The 720x400 modes are
518 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
519 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
520 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
521 * mode.
522 *
523 * The DMT modes have been fact-checked; the rest are mild guesses.
524 */
525 static const struct drm_display_mode edid_est_modes[] = {
526 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
527 968, 1056, 0, 600, 601, 605, 628, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
529 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
530 896, 1024, 0, 600, 601, 603, 625, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
533 720, 840, 0, 480, 481, 484, 500, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
535 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
536 704, 832, 0, 480, 489, 492, 520, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
538 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
539 768, 864, 0, 480, 483, 486, 525, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
541 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
542 752, 800, 0, 480, 490, 492, 525, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
544 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
545 846, 900, 0, 400, 421, 423, 449, 0,
546 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
547 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
548 846, 900, 0, 400, 412, 414, 449, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
550 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
551 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
553 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
554 1136, 1312, 0, 768, 769, 772, 800, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
556 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
557 1184, 1328, 0, 768, 771, 777, 806, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
559 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
560 1184, 1344, 0, 768, 771, 777, 806, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
562 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
563 1208, 1264, 0, 768, 768, 776, 817, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
565 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
566 928, 1152, 0, 624, 625, 628, 667, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
568 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
569 896, 1056, 0, 600, 601, 604, 625, 0,
570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
571 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
572 976, 1040, 0, 600, 637, 643, 666, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
574 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
575 1344, 1600, 0, 864, 865, 868, 900, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
577 };
578
579 struct minimode {
580 short w;
581 short h;
582 short r;
583 short rb;
584 };
585
586 static const struct minimode est3_modes[] = {
587 /* byte 6 */
588 { 640, 350, 85, 0 },
589 { 640, 400, 85, 0 },
590 { 720, 400, 85, 0 },
591 { 640, 480, 85, 0 },
592 { 848, 480, 60, 0 },
593 { 800, 600, 85, 0 },
594 { 1024, 768, 85, 0 },
595 { 1152, 864, 75, 0 },
596 /* byte 7 */
597 { 1280, 768, 60, 1 },
598 { 1280, 768, 60, 0 },
599 { 1280, 768, 75, 0 },
600 { 1280, 768, 85, 0 },
601 { 1280, 960, 60, 0 },
602 { 1280, 960, 85, 0 },
603 { 1280, 1024, 60, 0 },
604 { 1280, 1024, 85, 0 },
605 /* byte 8 */
606 { 1360, 768, 60, 0 },
607 { 1440, 900, 60, 1 },
608 { 1440, 900, 60, 0 },
609 { 1440, 900, 75, 0 },
610 { 1440, 900, 85, 0 },
611 { 1400, 1050, 60, 1 },
612 { 1400, 1050, 60, 0 },
613 { 1400, 1050, 75, 0 },
614 /* byte 9 */
615 { 1400, 1050, 85, 0 },
616 { 1680, 1050, 60, 1 },
617 { 1680, 1050, 60, 0 },
618 { 1680, 1050, 75, 0 },
619 { 1680, 1050, 85, 0 },
620 { 1600, 1200, 60, 0 },
621 { 1600, 1200, 65, 0 },
622 { 1600, 1200, 70, 0 },
623 /* byte 10 */
624 { 1600, 1200, 75, 0 },
625 { 1600, 1200, 85, 0 },
626 { 1792, 1344, 60, 0 },
627 { 1792, 1344, 75, 0 },
628 { 1856, 1392, 60, 0 },
629 { 1856, 1392, 75, 0 },
630 { 1920, 1200, 60, 1 },
631 { 1920, 1200, 60, 0 },
632 /* byte 11 */
633 { 1920, 1200, 75, 0 },
634 { 1920, 1200, 85, 0 },
635 { 1920, 1440, 60, 0 },
636 { 1920, 1440, 75, 0 },
637 };
638
639 static const struct minimode extra_modes[] = {
640 { 1024, 576, 60, 0 },
641 { 1366, 768, 60, 0 },
642 { 1600, 900, 60, 0 },
643 { 1680, 945, 60, 0 },
644 { 1920, 1080, 60, 0 },
645 { 2048, 1152, 60, 0 },
646 { 2048, 1536, 60, 0 },
647 };
648
649 /*
650 * Probably taken from CEA-861 spec.
651 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
652 *
653 * Index using the VIC.
654 */
655 static const struct drm_display_mode edid_cea_modes[] = {
656 /* 0 - dummy, VICs start at 1 */
657 { },
658 /* 1 - 640x480@60Hz */
659 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
660 752, 800, 0, 480, 490, 492, 525, 0,
661 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
662 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
663 /* 2 - 720x480@60Hz */
664 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
665 798, 858, 0, 480, 489, 495, 525, 0,
666 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
667 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
668 /* 3 - 720x480@60Hz */
669 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
670 798, 858, 0, 480, 489, 495, 525, 0,
671 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
672 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
673 /* 4 - 1280x720@60Hz */
674 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
675 1430, 1650, 0, 720, 725, 730, 750, 0,
676 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
677 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
678 /* 5 - 1920x1080i@60Hz */
679 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
680 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
681 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
682 DRM_MODE_FLAG_INTERLACE),
683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
684 /* 6 - 720(1440)x480i@60Hz */
685 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
686 801, 858, 0, 480, 488, 494, 525, 0,
687 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
688 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
690 /* 7 - 720(1440)x480i@60Hz */
691 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
692 801, 858, 0, 480, 488, 494, 525, 0,
693 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
694 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
696 /* 8 - 720(1440)x240@60Hz */
697 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
698 801, 858, 0, 240, 244, 247, 262, 0,
699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
700 DRM_MODE_FLAG_DBLCLK),
701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
702 /* 9 - 720(1440)x240@60Hz */
703 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
704 801, 858, 0, 240, 244, 247, 262, 0,
705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
706 DRM_MODE_FLAG_DBLCLK),
707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
708 /* 10 - 2880x480i@60Hz */
709 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
710 3204, 3432, 0, 480, 488, 494, 525, 0,
711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
712 DRM_MODE_FLAG_INTERLACE),
713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
714 /* 11 - 2880x480i@60Hz */
715 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
716 3204, 3432, 0, 480, 488, 494, 525, 0,
717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
718 DRM_MODE_FLAG_INTERLACE),
719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
720 /* 12 - 2880x240@60Hz */
721 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
722 3204, 3432, 0, 240, 244, 247, 262, 0,
723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
724 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
725 /* 13 - 2880x240@60Hz */
726 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
727 3204, 3432, 0, 240, 244, 247, 262, 0,
728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
729 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
730 /* 14 - 1440x480@60Hz */
731 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
732 1596, 1716, 0, 480, 489, 495, 525, 0,
733 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
735 /* 15 - 1440x480@60Hz */
736 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
737 1596, 1716, 0, 480, 489, 495, 525, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
739 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
740 /* 16 - 1920x1080@60Hz */
741 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
742 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
743 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
744 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
745 /* 17 - 720x576@50Hz */
746 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
747 796, 864, 0, 576, 581, 586, 625, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
749 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
750 /* 18 - 720x576@50Hz */
751 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
752 796, 864, 0, 576, 581, 586, 625, 0,
753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
754 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
755 /* 19 - 1280x720@50Hz */
756 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
757 1760, 1980, 0, 720, 725, 730, 750, 0,
758 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
759 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
760 /* 20 - 1920x1080i@50Hz */
761 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
762 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
763 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
764 DRM_MODE_FLAG_INTERLACE),
765 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
766 /* 21 - 720(1440)x576i@50Hz */
767 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
768 795, 864, 0, 576, 580, 586, 625, 0,
769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
770 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
772 /* 22 - 720(1440)x576i@50Hz */
773 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
774 795, 864, 0, 576, 580, 586, 625, 0,
775 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
776 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
778 /* 23 - 720(1440)x288@50Hz */
779 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
780 795, 864, 0, 288, 290, 293, 312, 0,
781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
782 DRM_MODE_FLAG_DBLCLK),
783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
784 /* 24 - 720(1440)x288@50Hz */
785 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
786 795, 864, 0, 288, 290, 293, 312, 0,
787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
788 DRM_MODE_FLAG_DBLCLK),
789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
790 /* 25 - 2880x576i@50Hz */
791 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
792 3180, 3456, 0, 576, 580, 586, 625, 0,
793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
794 DRM_MODE_FLAG_INTERLACE),
795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 26 - 2880x576i@50Hz */
797 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
798 3180, 3456, 0, 576, 580, 586, 625, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
800 DRM_MODE_FLAG_INTERLACE),
801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
802 /* 27 - 2880x288@50Hz */
803 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
804 3180, 3456, 0, 288, 290, 293, 312, 0,
805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
806 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
807 /* 28 - 2880x288@50Hz */
808 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
809 3180, 3456, 0, 288, 290, 293, 312, 0,
810 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
811 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
812 /* 29 - 1440x576@50Hz */
813 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
814 1592, 1728, 0, 576, 581, 586, 625, 0,
815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 30 - 1440x576@50Hz */
818 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
819 1592, 1728, 0, 576, 581, 586, 625, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
821 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
822 /* 31 - 1920x1080@50Hz */
823 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
824 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
826 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 32 - 1920x1080@24Hz */
828 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
829 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
831 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
832 /* 33 - 1920x1080@25Hz */
833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
834 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
836 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
837 /* 34 - 1920x1080@30Hz */
838 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
839 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
841 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
842 /* 35 - 2880x480@60Hz */
843 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
844 3192, 3432, 0, 480, 489, 495, 525, 0,
845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
846 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
847 /* 36 - 2880x480@60Hz */
848 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
849 3192, 3432, 0, 480, 489, 495, 525, 0,
850 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
851 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
852 /* 37 - 2880x576@50Hz */
853 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
854 3184, 3456, 0, 576, 581, 586, 625, 0,
855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
856 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 38 - 2880x576@50Hz */
858 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
859 3184, 3456, 0, 576, 581, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
861 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
862 /* 39 - 1920x1080i@50Hz */
863 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
864 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
865 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
866 DRM_MODE_FLAG_INTERLACE),
867 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
868 /* 40 - 1920x1080i@100Hz */
869 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
870 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
871 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
872 DRM_MODE_FLAG_INTERLACE),
873 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
874 /* 41 - 1280x720@100Hz */
875 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
876 1760, 1980, 0, 720, 725, 730, 750, 0,
877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
878 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
879 /* 42 - 720x576@100Hz */
880 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
881 796, 864, 0, 576, 581, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
883 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
884 /* 43 - 720x576@100Hz */
885 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
886 796, 864, 0, 576, 581, 586, 625, 0,
887 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
888 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 44 - 720(1440)x576i@100Hz */
890 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
891 795, 864, 0, 576, 580, 586, 625, 0,
892 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
893 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
895 /* 45 - 720(1440)x576i@100Hz */
896 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
897 795, 864, 0, 576, 580, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
899 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
900 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
901 /* 46 - 1920x1080i@120Hz */
902 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
903 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
904 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
905 DRM_MODE_FLAG_INTERLACE),
906 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
907 /* 47 - 1280x720@120Hz */
908 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
909 1430, 1650, 0, 720, 725, 730, 750, 0,
910 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
911 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
912 /* 48 - 720x480@120Hz */
913 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
914 798, 858, 0, 480, 489, 495, 525, 0,
915 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
916 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
917 /* 49 - 720x480@120Hz */
918 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
919 798, 858, 0, 480, 489, 495, 525, 0,
920 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
921 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 50 - 720(1440)x480i@120Hz */
923 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
924 801, 858, 0, 480, 488, 494, 525, 0,
925 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
926 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
928 /* 51 - 720(1440)x480i@120Hz */
929 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
930 801, 858, 0, 480, 488, 494, 525, 0,
931 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
932 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
933 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
934 /* 52 - 720x576@200Hz */
935 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
936 796, 864, 0, 576, 581, 586, 625, 0,
937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
938 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
939 /* 53 - 720x576@200Hz */
940 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
941 796, 864, 0, 576, 581, 586, 625, 0,
942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
943 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
944 /* 54 - 720(1440)x576i@200Hz */
945 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
946 795, 864, 0, 576, 580, 586, 625, 0,
947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
948 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
949 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
950 /* 55 - 720(1440)x576i@200Hz */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
955 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
956 /* 56 - 720x480@240Hz */
957 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
958 798, 858, 0, 480, 489, 495, 525, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
960 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
961 /* 57 - 720x480@240Hz */
962 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
963 798, 858, 0, 480, 489, 495, 525, 0,
964 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
965 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
966 /* 58 - 720(1440)x480i@240 */
967 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
968 801, 858, 0, 480, 488, 494, 525, 0,
969 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
970 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
971 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
972 /* 59 - 720(1440)x480i@240 */
973 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
974 801, 858, 0, 480, 488, 494, 525, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
978 /* 60 - 1280x720@24Hz */
979 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
980 3080, 3300, 0, 720, 725, 730, 750, 0,
981 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
982 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 61 - 1280x720@25Hz */
984 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
985 3740, 3960, 0, 720, 725, 730, 750, 0,
986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
987 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
988 /* 62 - 1280x720@30Hz */
989 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
990 3080, 3300, 0, 720, 725, 730, 750, 0,
991 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
992 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
993 /* 63 - 1920x1080@120Hz */
994 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
995 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
997 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
998 /* 64 - 1920x1080@100Hz */
999 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1000 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
1001 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1002 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1003 };
1004
1005 /*
1006 * HDMI 1.4 4k modes. Index using the VIC.
1007 */
1008 static const struct drm_display_mode edid_4k_modes[] = {
1009 /* 0 - dummy, VICs start at 1 */
1010 { },
1011 /* 1 - 3840x2160@30Hz */
1012 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1013 3840, 4016, 4104, 4400, 0,
1014 2160, 2168, 2178, 2250, 0,
1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1016 .vrefresh = 30, },
1017 /* 2 - 3840x2160@25Hz */
1018 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1019 3840, 4896, 4984, 5280, 0,
1020 2160, 2168, 2178, 2250, 0,
1021 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1022 .vrefresh = 25, },
1023 /* 3 - 3840x2160@24Hz */
1024 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1025 3840, 5116, 5204, 5500, 0,
1026 2160, 2168, 2178, 2250, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 24, },
1029 /* 4 - 4096x2160@24Hz (SMPTE) */
1030 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1031 4096, 5116, 5204, 5500, 0,
1032 2160, 2168, 2178, 2250, 0,
1033 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1034 .vrefresh = 24, },
1035 };
1036
1037 /*** DDC fetch and block validation ***/
1038
1039 static const u8 edid_header[] = {
1040 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1041 };
1042
1043 /**
1044 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1045 * @raw_edid: pointer to raw base EDID block
1046 *
1047 * Sanity check the header of the base EDID block.
1048 *
1049 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1050 */
1051 int drm_edid_header_is_valid(const u8 *raw_edid)
1052 {
1053 int i, score = 0;
1054
1055 for (i = 0; i < sizeof(edid_header); i++)
1056 if (raw_edid[i] == edid_header[i])
1057 score++;
1058
1059 return score;
1060 }
1061 EXPORT_SYMBOL(drm_edid_header_is_valid);
1062
1063 static int edid_fixup __read_mostly = 6;
1064 module_param_named(edid_fixup, edid_fixup, int, 0400);
1065 MODULE_PARM_DESC(edid_fixup,
1066 "Minimum number of valid EDID header bytes (0-8, default 6)");
1067
1068 static void drm_get_displayid(struct drm_connector *connector,
1069 struct edid *edid);
1070
1071 static int drm_edid_block_checksum(const u8 *raw_edid)
1072 {
1073 int i;
1074 u8 csum = 0;
1075 for (i = 0; i < EDID_LENGTH; i++)
1076 csum += raw_edid[i];
1077
1078 return csum;
1079 }
1080
1081 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1082 {
1083 if (memchr_inv(in_edid, 0, length))
1084 return false;
1085
1086 return true;
1087 }
1088
1089 /**
1090 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1091 * @raw_edid: pointer to raw EDID block
1092 * @block: type of block to validate (0 for base, extension otherwise)
1093 * @print_bad_edid: if true, dump bad EDID blocks to the console
1094 * @edid_corrupt: if true, the header or checksum is invalid
1095 *
1096 * Validate a base or extension EDID block and optionally dump bad blocks to
1097 * the console.
1098 *
1099 * Return: True if the block is valid, false otherwise.
1100 */
1101 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1102 bool *edid_corrupt)
1103 {
1104 u8 csum;
1105 struct edid *edid = (struct edid *)raw_edid;
1106
1107 if (WARN_ON(!raw_edid))
1108 return false;
1109
1110 if (edid_fixup > 8 || edid_fixup < 0)
1111 edid_fixup = 6;
1112
1113 if (block == 0) {
1114 int score = drm_edid_header_is_valid(raw_edid);
1115 if (score == 8) {
1116 if (edid_corrupt)
1117 *edid_corrupt = false;
1118 } else if (score >= edid_fixup) {
1119 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1120 * The corrupt flag needs to be set here otherwise, the
1121 * fix-up code here will correct the problem, the
1122 * checksum is correct and the test fails
1123 */
1124 if (edid_corrupt)
1125 *edid_corrupt = true;
1126 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1127 memcpy(raw_edid, edid_header, sizeof(edid_header));
1128 } else {
1129 if (edid_corrupt)
1130 *edid_corrupt = true;
1131 goto bad;
1132 }
1133 }
1134
1135 csum = drm_edid_block_checksum(raw_edid);
1136 if (csum) {
1137 if (print_bad_edid) {
1138 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1139 }
1140
1141 if (edid_corrupt)
1142 *edid_corrupt = true;
1143
1144 /* allow CEA to slide through, switches mangle this */
1145 if (raw_edid[0] != 0x02)
1146 goto bad;
1147 }
1148
1149 /* per-block-type checks */
1150 switch (raw_edid[0]) {
1151 case 0: /* base */
1152 if (edid->version != 1) {
1153 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1154 goto bad;
1155 }
1156
1157 if (edid->revision > 4)
1158 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1159 break;
1160
1161 default:
1162 break;
1163 }
1164
1165 return true;
1166
1167 bad:
1168 if (print_bad_edid) {
1169 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1170 printk(KERN_ERR "EDID block is all zeroes\n");
1171 } else {
1172 printk(KERN_ERR "Raw EDID:\n");
1173 for (int i = 0; i < EDID_LENGTH; ) {
1174 kprintf("%02x", raw_edid[i]);
1175 i++;
1176 if (i % 16 == 0 || i == EDID_LENGTH)
1177 kprintf("\n");
1178 else if (i % 8 == 0)
1179 kprintf(" ");
1180 else
1181 kprintf(" ");
1182 }
1183 }
1184 }
1185 return false;
1186 }
1187 EXPORT_SYMBOL(drm_edid_block_valid);
1188
1189 /**
1190 * drm_edid_is_valid - sanity check EDID data
1191 * @edid: EDID data
1192 *
1193 * Sanity-check an entire EDID record (including extensions)
1194 *
1195 * Return: True if the EDID data is valid, false otherwise.
1196 */
1197 bool drm_edid_is_valid(struct edid *edid)
1198 {
1199 int i;
1200 u8 *raw = (u8 *)edid;
1201
1202 if (!edid)
1203 return false;
1204
1205 for (i = 0; i <= edid->extensions; i++)
1206 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1207 return false;
1208
1209 return true;
1210 }
1211 EXPORT_SYMBOL(drm_edid_is_valid);
1212
1213 #define DDC_SEGMENT_ADDR 0x30
1214 /**
1215 * drm_do_probe_ddc_edid() - get EDID information via I2C
1216 * @data: I2C device adapter
1217 * @buf: EDID data buffer to be filled
1218 * @block: 128 byte EDID block to start fetching from
1219 * @len: EDID data buffer length to fetch
1220 *
1221 * Try to fetch EDID information by calling I2C driver functions.
1222 *
1223 * Return: 0 on success or -1 on failure.
1224 */
1225 static int
1226 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1227 {
1228 struct i2c_adapter *adapter = data;
1229 unsigned char start = block * EDID_LENGTH;
1230 unsigned char segment = block >> 1;
1231 unsigned char xfers = segment ? 3 : 2;
1232 int ret, retries = 5;
1233
1234 /*
1235 * The core I2C driver will automatically retry the transfer if the
1236 * adapter reports EAGAIN. However, we find that bit-banging transfers
1237 * are susceptible to errors under a heavily loaded machine and
1238 * generate spurious NAKs and timeouts. Retrying the transfer
1239 * of the individual block a few times seems to overcome this.
1240 */
1241 do {
1242 struct i2c_msg msgs[] = {
1243 {
1244 .addr = DDC_SEGMENT_ADDR,
1245 .flags = 0,
1246 .len = 1,
1247 .buf = &segment,
1248 }, {
1249 .addr = DDC_ADDR,
1250 .flags = 0,
1251 .len = 1,
1252 .buf = &start,
1253 }, {
1254 .addr = DDC_ADDR,
1255 .flags = I2C_M_RD,
1256 .len = len,
1257 .buf = buf,
1258 }
1259 };
1260
1261 /*
1262 * Avoid sending the segment addr to not upset non-compliant
1263 * DDC monitors.
1264 */
1265 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1266
1267 if (ret == -ENXIO) {
1268 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1269 adapter->name);
1270 break;
1271 }
1272 } while (ret != xfers && --retries);
1273
1274 return ret == xfers ? 0 : -1;
1275 }
1276
1277 /*
1278 * Old version of drm_do_probe_ddc_edid, still using
1279 * the FreeBSD/DragonFly iic API
1280 */
1281 static int
1282 drm_do_probe_ddc_edid_iic(void *data, u8 *buf, unsigned int block, size_t len)
1283 {
1284 device_t adapter = data;
1285 unsigned char start = block * EDID_LENGTH;
1286 unsigned char segment = block >> 1;
1287 unsigned char xfers = segment ? 3 : 2;
1288 int ret, retries = 5;
1289
1290 /*
1291 * The core I2C driver will automatically retry the transfer if the
1292 * adapter reports EAGAIN. However, we find that bit-banging transfers
1293 * are susceptible to errors under a heavily loaded machine and
1294 * generate spurious NAKs and timeouts. Retrying the transfer
1295 * of the individual block a few times seems to overcome this.
1296 */
1297 do {
1298 struct iic_msg msgs[] = {
1299 {
1300 .slave = DDC_SEGMENT_ADDR << 1,
1301 .flags = 0,
1302 .len = 1,
1303 .buf = &segment,
1304 }, {
1305 .slave = DDC_ADDR << 1,
1306 .flags = 0,
1307 .len = 1,
1308 .buf = &start,
1309 }, {
1310 .slave = DDC_ADDR << 1,
1311 .flags = I2C_M_RD,
1312 .len = len,
1313 .buf = buf,
1314 }
1315 };
1316
1317 /*
1318 * Avoid sending the segment addr to not upset non-compliant
1319 * DDC monitors.
1320 */
1321 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers);
1322 if (ret != 0)
1323 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n",
1324 retries, ret);
1325 } while (ret != 0 && --retries);
1326
1327 return (ret == 0 ? 0 : -1);
1328 }
1329
1330 /*
1331 * Old version of drm_probe_ddc(), still using
1332 * the FreeBSD/DragonFly iic API
1333 */
1334 static bool
1335 drm_probe_ddc_iic(device_t adapter)
1336 {
1337 unsigned char out;
1338
1339 return (drm_do_probe_ddc_edid_iic(adapter, &out, 0, 1) == 0);
1340 }
1341
1342 /*
1343 * Old version of drm_get_edid(), still using
1344 * the FreeBSD/DragonFly iic API
1345 */
1346 struct edid *drm_get_edid_iic(struct drm_connector *connector,
1347 device_t adapter)
1348 {
1349 if (!drm_probe_ddc_iic(adapter))
1350 return NULL;
1351
1352 return drm_do_get_edid(connector, drm_do_probe_ddc_edid_iic, adapter);
1353 }
1354
1355 /**
1356 * drm_do_get_edid - get EDID data using a custom EDID block read function
1357 * @connector: connector we're probing
1358 * @get_edid_block: EDID block read function
1359 * @data: private data passed to the block read function
1360 *
1361 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1362 * exposes a different interface to read EDID blocks this function can be used
1363 * to get EDID data using a custom block read function.
1364 *
1365 * As in the general case the DDC bus is accessible by the kernel at the I2C
1366 * level, drivers must make all reasonable efforts to expose it as an I2C
1367 * adapter and use drm_get_edid() instead of abusing this function.
1368 *
1369 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1370 */
1371 struct edid *drm_do_get_edid(struct drm_connector *connector,
1372 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1373 size_t len),
1374 void *data)
1375 {
1376 int i, j = 0, valid_extensions = 0;
1377 u8 *block, *new;
1378 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1379
1380 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL)
1381 return NULL;
1382
1383 /* base block fetch */
1384 for (i = 0; i < 4; i++) {
1385 if (get_edid_block(data, block, 0, EDID_LENGTH))
1386 goto out;
1387 if (drm_edid_block_valid(block, 0, print_bad_edid,
1388 &connector->edid_corrupt))
1389 break;
1390 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1391 connector->null_edid_counter++;
1392 goto carp;
1393 }
1394 }
1395 if (i == 4)
1396 goto carp;
1397
1398 /* if there's no extensions, we're done */
1399 if (block[0x7e] == 0)
1400 return (struct edid *)block;
1401
1402 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK);
1403 if (!new)
1404 goto out;
1405 block = new;
1406
1407 for (j = 1; j <= block[0x7e]; j++) {
1408 for (i = 0; i < 4; i++) {
1409 if (get_edid_block(data,
1410 block + (valid_extensions + 1) * EDID_LENGTH,
1411 j, EDID_LENGTH))
1412 goto out;
1413 if (drm_edid_block_valid(block + (valid_extensions + 1)
1414 * EDID_LENGTH, j,
1415 print_bad_edid,
1416 NULL)) {
1417 valid_extensions++;
1418 break;
1419 }
1420 }
1421
1422 if (i == 4 && print_bad_edid) {
1423 dev_warn(connector->dev->dev,
1424 "%s: Ignoring invalid EDID block %d.\n",
1425 connector->name, j);
1426
1427 connector->bad_edid_counter++;
1428 }
1429 }
1430
1431 if (valid_extensions != block[0x7e]) {
1432 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1433 block[0x7e] = valid_extensions;
1434 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK);
1435 if (!new)
1436 goto out;
1437 block = new;
1438 }
1439
1440 return (struct edid *)block;
1441
1442 carp:
1443 if (print_bad_edid) {
1444 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1445 connector->name, j);
1446 }
1447 connector->bad_edid_counter++;
1448
1449 out:
1450 kfree(block);
1451 return NULL;
1452 }
1453
1454 /**
1455 * drm_probe_ddc() - probe DDC presence
1456 * @adapter: I2C adapter to probe
1457 *
1458 * Return: True on success, false on failure.
1459 */
1460 bool
1461 drm_probe_ddc(struct i2c_adapter *adapter)
1462 {
1463 unsigned char out;
1464
1465 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1466 }
1467 EXPORT_SYMBOL(drm_probe_ddc);
1468
1469 /**
1470 * drm_get_edid - get EDID data, if available
1471 * @connector: connector we're probing
1472 * @adapter: I2C adapter to use for DDC
1473 *
1474 * Poke the given I2C channel to grab EDID data if possible. If found,
1475 * attach it to the connector.
1476 *
1477 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1478 */
1479 struct edid *drm_get_edid(struct drm_connector *connector,
1480 struct i2c_adapter *adapter)
1481 {
1482 struct edid *edid;
1483
1484 if (!drm_probe_ddc(adapter))
1485 return NULL;
1486
1487 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1488 if (edid)
1489 drm_get_displayid(connector, edid);
1490 return edid;
1491 }
1492 EXPORT_SYMBOL(drm_get_edid);
1493
1494 /**
1495 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1496 * @connector: connector we're probing
1497 * @adapter: I2C adapter to use for DDC
1498 *
1499 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1500 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1501 * switch DDC to the GPU which is retrieving EDID.
1502 *
1503 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1504 */
1505 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1506 struct i2c_adapter *adapter)
1507 {
1508 struct pci_dev *pdev = connector->dev->pdev;
1509 struct edid *edid;
1510
1511 vga_switcheroo_lock_ddc(pdev);
1512 edid = drm_get_edid(connector, adapter);
1513 vga_switcheroo_unlock_ddc(pdev);
1514
1515 return edid;
1516 }
1517 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1518
1519 /**
1520 * drm_edid_duplicate - duplicate an EDID and the extensions
1521 * @edid: EDID to duplicate
1522 *
1523 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1524 */
1525 struct edid *drm_edid_duplicate(const struct edid *edid)
1526 {
1527 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1528 }
1529 EXPORT_SYMBOL(drm_edid_duplicate);
1530
1531 /*** EDID parsing ***/
1532
1533 /**
1534 * edid_vendor - match a string against EDID's obfuscated vendor field
1535 * @edid: EDID to match
1536 * @vendor: vendor string
1537 *
1538 * Returns true if @vendor is in @edid, false otherwise
1539 */
1540 static bool edid_vendor(struct edid *edid, char *vendor)
1541 {
1542 char edid_vendor[3];
1543
1544 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1545 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1546 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1547 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1548
1549 return !strncmp(edid_vendor, vendor, 3);
1550 }
1551
1552 /**
1553 * edid_get_quirks - return quirk flags for a given EDID
1554 * @edid: EDID to process
1555 *
1556 * This tells subsequent routines what fixes they need to apply.
1557 */
1558 static u32 edid_get_quirks(struct edid *edid)
1559 {
1560 struct edid_quirk *quirk;
1561 int i;
1562
1563 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1564 quirk = &edid_quirk_list[i];
1565
1566 if (edid_vendor(edid, quirk->vendor) &&
1567 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1568 return quirk->quirks;
1569 }
1570
1571 return 0;
1572 }
1573
1574 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1575 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1576
1577 /**
1578 * edid_fixup_preferred - set preferred modes based on quirk list
1579 * @connector: has mode list to fix up
1580 * @quirks: quirks list
1581 *
1582 * Walk the mode list for @connector, clearing the preferred status
1583 * on existing modes and setting it anew for the right mode ala @quirks.
1584 */
1585 static void edid_fixup_preferred(struct drm_connector *connector,
1586 u32 quirks)
1587 {
1588 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1589 int target_refresh = 0;
1590 int cur_vrefresh, preferred_vrefresh;
1591
1592 if (list_empty(&connector->probed_modes))
1593 return;
1594
1595 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1596 target_refresh = 60;
1597 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1598 target_refresh = 75;
1599
1600 preferred_mode = list_first_entry(&connector->probed_modes,
1601 struct drm_display_mode, head);
1602
1603 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1604 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1605
1606 if (cur_mode == preferred_mode)
1607 continue;
1608
1609 /* Largest mode is preferred */
1610 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1611 preferred_mode = cur_mode;
1612
1613 cur_vrefresh = cur_mode->vrefresh ?
1614 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1615 preferred_vrefresh = preferred_mode->vrefresh ?
1616 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1617 /* At a given size, try to get closest to target refresh */
1618 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1619 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1620 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1621 preferred_mode = cur_mode;
1622 }
1623 }
1624
1625 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1626 }
1627
1628 static bool
1629 mode_is_rb(const struct drm_display_mode *mode)
1630 {
1631 return (mode->htotal - mode->hdisplay == 160) &&
1632 (mode->hsync_end - mode->hdisplay == 80) &&
1633 (mode->hsync_end - mode->hsync_start == 32) &&
1634 (mode->vsync_start - mode->vdisplay == 3);
1635 }
1636
1637 /*
1638 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1639 * @dev: Device to duplicate against
1640 * @hsize: Mode width
1641 * @vsize: Mode height
1642 * @fresh: Mode refresh rate
1643 * @rb: Mode reduced-blanking-ness
1644 *
1645 * Walk the DMT mode list looking for a match for the given parameters.
1646 *
1647 * Return: A newly allocated copy of the mode, or NULL if not found.
1648 */
1649 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1650 int hsize, int vsize, int fresh,
1651 bool rb)
1652 {
1653 int i;
1654
1655 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1656 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1657 if (hsize != ptr->hdisplay)
1658 continue;
1659 if (vsize != ptr->vdisplay)
1660 continue;
1661 if (fresh != drm_mode_vrefresh(ptr))
1662 continue;
1663 if (rb != mode_is_rb(ptr))
1664 continue;
1665
1666 return drm_mode_duplicate(dev, ptr);
1667 }
1668
1669 return NULL;
1670 }
1671 EXPORT_SYMBOL(drm_mode_find_dmt);
1672
1673 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1674
1675 static void
1676 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1677 {
1678 int i, n = 0;
1679 u8 d = ext[0x02];
1680 u8 *det_base = ext + d;
1681
1682 n = (127 - d) / 18;
1683 for (i = 0; i < n; i++)
1684 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1685 }
1686
1687 static void
1688 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1689 {
1690 unsigned int i, n = min((int)ext[0x02], 6);
1691 u8 *det_base = ext + 5;
1692
1693 if (ext[0x01] != 1)
1694 return; /* unknown version */
1695
1696 for (i = 0; i < n; i++)
1697 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1698 }
1699
1700 static void
1701 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1702 {
1703 int i;
1704 struct edid *edid = (struct edid *)raw_edid;
1705
1706 if (edid == NULL)
1707 return;
1708
1709 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1710 cb(&(edid->detailed_timings[i]), closure);
1711
1712 for (i = 1; i <= raw_edid[0x7e]; i++) {
1713 u8 *ext = raw_edid + (i * EDID_LENGTH);
1714 switch (*ext) {
1715 case CEA_EXT:
1716 cea_for_each_detailed_block(ext, cb, closure);
1717 break;
1718 case VTB_EXT:
1719 vtb_for_each_detailed_block(ext, cb, closure);
1720 break;
1721 default:
1722 break;
1723 }
1724 }
1725 }
1726
1727 static void
1728 is_rb(struct detailed_timing *t, void *data)
1729 {
1730 u8 *r = (u8 *)t;
1731 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1732 if (r[15] & 0x10)
1733 *(bool *)data = true;
1734 }
1735
1736 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1737 static bool
1738 drm_monitor_supports_rb(struct edid *edid)
1739 {
1740 if (edid->revision >= 4) {
1741 bool ret = false;
1742 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1743 return ret;
1744 }
1745
1746 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1747 }
1748
1749 static void
1750 find_gtf2(struct detailed_timing *t, void *data)
1751 {
1752 u8 *r = (u8 *)t;
1753 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1754 *(u8 **)data = r;
1755 }
1756
1757 /* Secondary GTF curve kicks in above some break frequency */
1758 static int
1759 drm_gtf2_hbreak(struct edid *edid)
1760 {
1761 u8 *r = NULL;
1762 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1763 return r ? (r[12] * 2) : 0;
1764 }
1765
1766 static int
1767 drm_gtf2_2c(struct edid *edid)
1768 {
1769 u8 *r = NULL;
1770 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1771 return r ? r[13] : 0;
1772 }
1773
1774 static int
1775 drm_gtf2_m(struct edid *edid)
1776 {
1777 u8 *r = NULL;
1778 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1779 return r ? (r[15] << 8) + r[14] : 0;
1780 }
1781
1782 static int
1783 drm_gtf2_k(struct edid *edid)
1784 {
1785 u8 *r = NULL;
1786 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1787 return r ? r[16] : 0;
1788 }
1789
1790 static int
1791 drm_gtf2_2j(struct edid *edid)
1792 {
1793 u8 *r = NULL;
1794 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1795 return r ? r[17] : 0;
1796 }
1797
1798 /**
1799 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1800 * @edid: EDID block to scan
1801 */
1802 static int standard_timing_level(struct edid *edid)
1803 {
1804 if (edid->revision >= 2) {
1805 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1806 return LEVEL_CVT;
1807 if (drm_gtf2_hbreak(edid))
1808 return LEVEL_GTF2;
1809 return LEVEL_GTF;
1810 }
1811 return LEVEL_DMT;
1812 }
1813
1814 /*
1815 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1816 * monitors fill with ascii space (0x20) instead.
1817 */
1818 static int
1819 bad_std_timing(u8 a, u8 b)
1820 {
1821 return (a == 0x00 && b == 0x00) ||
1822 (a == 0x01 && b == 0x01) ||
1823 (a == 0x20 && b == 0x20);
1824 }
1825
1826 /**
1827 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1828 * @connector: connector of for the EDID block
1829 * @edid: EDID block to scan
1830 * @t: standard timing params
1831 *
1832 * Take the standard timing params (in this case width, aspect, and refresh)
1833 * and convert them into a real mode using CVT/GTF/DMT.
1834 */
1835 static struct drm_display_mode *
1836 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1837 struct std_timing *t)
1838 {
1839 struct drm_device *dev = connector->dev;
1840 struct drm_display_mode *m, *mode = NULL;
1841 int hsize, vsize;
1842 int vrefresh_rate;
1843 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1844 >> EDID_TIMING_ASPECT_SHIFT;
1845 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1846 >> EDID_TIMING_VFREQ_SHIFT;
1847 int timing_level = standard_timing_level(edid);
1848
1849 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1850 return NULL;
1851
1852 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1853 hsize = t->hsize * 8 + 248;
1854 /* vrefresh_rate = vfreq + 60 */
1855 vrefresh_rate = vfreq + 60;
1856 /* the vdisplay is calculated based on the aspect ratio */
1857 if (aspect_ratio == 0) {
1858 if (edid->revision < 3)
1859 vsize = hsize;
1860 else
1861 vsize = (hsize * 10) / 16;
1862 } else if (aspect_ratio == 1)
1863 vsize = (hsize * 3) / 4;
1864 else if (aspect_ratio == 2)
1865 vsize = (hsize * 4) / 5;
1866 else
1867 vsize = (hsize * 9) / 16;
1868
1869 /* HDTV hack, part 1 */
1870 if (vrefresh_rate == 60 &&
1871 ((hsize == 1360 && vsize == 765) ||
1872 (hsize == 1368 && vsize == 769))) {
1873 hsize = 1366;
1874 vsize = 768;
1875 }
1876
1877 /*
1878 * If this connector already has a mode for this size and refresh
1879 * rate (because it came from detailed or CVT info), use that
1880 * instead. This way we don't have to guess at interlace or
1881 * reduced blanking.
1882 */
1883 list_for_each_entry(m, &connector->probed_modes, head)
1884 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1885 drm_mode_vrefresh(m) == vrefresh_rate)
1886 return NULL;
1887
1888 /* HDTV hack, part 2 */
1889 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1890 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1891 false);
1892 mode->hdisplay = 1366;
1893 mode->hsync_start = mode->hsync_start - 1;
1894 mode->hsync_end = mode->hsync_end - 1;
1895 return mode;
1896 }
1897
1898 /* check whether it can be found in default mode table */
1899 if (drm_monitor_supports_rb(edid)) {
1900 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1901 true);
1902 if (mode)
1903 return mode;
1904 }
1905 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1906 if (mode)
1907 return mode;
1908
1909 /* okay, generate it */
1910 switch (timing_level) {
1911 case LEVEL_DMT:
1912 break;
1913 case LEVEL_GTF:
1914 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1915 break;
1916 case LEVEL_GTF2:
1917 /*
1918 * This is potentially wrong if there's ever a monitor with
1919 * more than one ranges section, each claiming a different
1920 * secondary GTF curve. Please don't do that.
1921 */
1922 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1923 if (!mode)
1924 return NULL;
1925 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1926 drm_mode_destroy(dev, mode);
1927 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1928 vrefresh_rate, 0, 0,
1929 drm_gtf2_m(edid),
1930 drm_gtf2_2c(edid),
1931 drm_gtf2_k(edid),
1932 drm_gtf2_2j(edid));
1933 }
1934 break;
1935 case LEVEL_CVT:
1936 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1937 false);
1938 break;
1939 }
1940 return mode;
1941 }
1942
1943 /*
1944 * EDID is delightfully ambiguous about how interlaced modes are to be
1945 * encoded. Our internal representation is of frame height, but some
1946 * HDTV detailed timings are encoded as field height.
1947 *
1948 * The format list here is from CEA, in frame size. Technically we
1949 * should be checking refresh rate too. Whatever.
1950 */
1951 static void
1952 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1953 struct detailed_pixel_timing *pt)
1954 {
1955 int i;
1956 static const struct {
1957 int w, h;
1958 } cea_interlaced[] = {
1959 { 1920, 1080 },
1960 { 720, 480 },
1961 { 1440, 480 },
1962 { 2880, 480 },
1963 { 720, 576 },
1964 { 1440, 576 },
1965 { 2880, 576 },
1966 };
1967
1968 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1969 return;
1970
1971 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1972 if ((mode->hdisplay == cea_interlaced[i].w) &&
1973 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1974 mode->vdisplay *= 2;
1975 mode->vsync_start *= 2;
1976 mode->vsync_end *= 2;
1977 mode->vtotal *= 2;
1978 mode->vtotal |= 1;
1979 }
1980 }
1981
1982 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1983 }
1984
1985 /**
1986 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1987 * @dev: DRM device (needed to create new mode)
1988 * @edid: EDID block
1989 * @timing: EDID detailed timing info
1990 * @quirks: quirks to apply
1991 *
1992 * An EDID detailed timing block contains enough info for us to create and
1993 * return a new struct drm_display_mode.
1994 */
1995 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1996 struct edid *edid,
1997 struct detailed_timing *timing,
1998 u32 quirks)
1999 {
2000 struct drm_display_mode *mode;
2001 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2002 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2003 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2004 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2005 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2006 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2007 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2008 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2009 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2010
2011 /* ignore tiny modes */
2012 if (hactive < 64 || vactive < 64)
2013 return NULL;
2014
2015 if (pt->misc & DRM_EDID_PT_STEREO) {
2016 DRM_DEBUG_KMS("stereo mode not supported\n");
2017 return NULL;
2018 }
2019 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2020 DRM_DEBUG_KMS("composite sync not supported\n");
2021 }
2022
2023 /* it is incorrect if hsync/vsync width is zero */
2024 if (!hsync_pulse_width || !vsync_pulse_width) {
2025 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2026 "Wrong Hsync/Vsync pulse width\n");
2027 return NULL;
2028 }
2029
2030 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2031 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2032 if (!mode)
2033 return NULL;
2034
2035 goto set_size;
2036 }
2037
2038 mode = drm_mode_create(dev);
2039 if (!mode)
2040 return NULL;
2041
2042 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2043 timing->pixel_clock = cpu_to_le16(1088);
2044
2045 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2046
2047 mode->hdisplay = hactive;
2048 mode->hsync_start = mode->hdisplay + hsync_offset;
2049 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2050 mode->htotal = mode->hdisplay + hblank;
2051
2052 mode->vdisplay = vactive;
2053 mode->vsync_start = mode->vdisplay + vsync_offset;
2054 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2055 mode->vtotal = mode->vdisplay + vblank;
2056
2057 /* Some EDIDs have bogus h/vtotal values */
2058 if (mode->hsync_end > mode->htotal)
2059 mode->htotal = mode->hsync_end + 1;
2060 if (mode->vsync_end > mode->vtotal)
2061 mode->vtotal = mode->vsync_end + 1;
2062
2063 drm_mode_do_interlace_quirk(mode, pt);
2064
2065 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2066 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2067 }
2068
2069 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2070 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2071 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2072 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2073
2074 set_size:
2075 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2076 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2077
2078 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2079 mode->width_mm *= 10;
2080 mode->height_mm *= 10;
2081 }
2082
2083 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2084 mode->width_mm = edid->width_cm * 10;
2085 mode->height_mm = edid->height_cm * 10;
2086 }
2087
2088 mode->type = DRM_MODE_TYPE_DRIVER;
2089 mode->vrefresh = drm_mode_vrefresh(mode);
2090 drm_mode_set_name(mode);
2091
2092 return mode;
2093 }
2094
2095 static bool
2096 mode_in_hsync_range(const struct drm_display_mode *mode,
2097 struct edid *edid, u8 *t)
2098 {
2099 int hsync, hmin, hmax;
2100
2101 hmin = t[7];
2102 if (edid->revision >= 4)
2103 hmin += ((t[4] & 0x04) ? 255 : 0);
2104 hmax = t[8];
2105 if (edid->revision >= 4)
2106 hmax += ((t[4] & 0x08) ? 255 : 0);
2107 hsync = drm_mode_hsync(mode);
2108
2109 return (hsync <= hmax && hsync >= hmin);
2110 }
2111
2112 static bool
2113 mode_in_vsync_range(const struct drm_display_mode *mode,
2114 struct edid *edid, u8 *t)
2115 {
2116 int vsync, vmin, vmax;
2117
2118 vmin = t[5];
2119 if (edid->revision >= 4)
2120 vmin += ((t[4] & 0x01) ? 255 : 0);
2121 vmax = t[6];
2122 if (edid->revision >= 4)
2123 vmax += ((t[4] & 0x02) ? 255 : 0);
2124 vsync = drm_mode_vrefresh(mode);
2125
2126 return (vsync <= vmax && vsync >= vmin);
2127 }
2128
2129 static u32
2130 range_pixel_clock(struct edid *edid, u8 *t)
2131 {
2132 /* unspecified */
2133 if (t[9] == 0 || t[9] == 255)
2134 return 0;
2135
2136 /* 1.4 with CVT support gives us real precision, yay */
2137 if (edid->revision >= 4 && t[10] == 0x04)
2138 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2139
2140 /* 1.3 is pathetic, so fuzz up a bit */
2141 return t[9] * 10000 + 5001;
2142 }
2143
2144 static bool
2145 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2146 struct detailed_timing *timing)
2147 {
2148 u32 max_clock;
2149 u8 *t = (u8 *)timing;
2150
2151 if (!mode_in_hsync_range(mode, edid, t))
2152 return false;
2153
2154 if (!mode_in_vsync_range(mode, edid, t))
2155 return false;
2156
2157 if ((max_clock = range_pixel_clock(edid, t)))
2158 if (mode->clock > max_clock)
2159 return false;
2160
2161 /* 1.4 max horizontal check */
2162 if (edid->revision >= 4 && t[10] == 0x04)
2163 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2164 return false;
2165
2166 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2167 return false;
2168
2169 return true;
2170 }
2171
2172 static bool valid_inferred_mode(const struct drm_connector *connector,
2173 const struct drm_display_mode *mode)
2174 {
2175 struct drm_display_mode *m;
2176 bool ok = false;
2177
2178 list_for_each_entry(m, &connector->probed_modes, head) {
2179 if (mode->hdisplay == m->hdisplay &&
2180 mode->vdisplay == m->vdisplay &&
2181 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2182 return false; /* duplicated */
2183 if (mode->hdisplay <= m->hdisplay &&
2184 mode->vdisplay <= m->vdisplay)
2185 ok = true;
2186 }
2187 return ok;
2188 }
2189
2190 static int
2191 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2192 struct detailed_timing *timing)
2193 {
2194 int i, modes = 0;
2195 struct drm_display_mode *newmode;
2196 struct drm_device *dev = connector->dev;
2197
2198 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2199 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2200 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2201 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2202 if (newmode) {
2203 drm_mode_probed_add(connector, newmode);
2204 modes++;
2205 }
2206 }
2207 }
2208
2209 return modes;
2210 }
2211
2212 /* fix up 1366x768 mode from 1368x768;
2213 * GFT/CVT can't express 1366 width which isn't dividable by 8
2214 */
2215 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2216 {
2217 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2218 mode->hdisplay = 1366;
2219 mode->hsync_start--;
2220 mode->hsync_end--;
2221 drm_mode_set_name(mode);
2222 }
2223 }
2224
2225 static int
2226 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2227 struct detailed_timing *timing)
2228 {
2229 int i, modes = 0;
2230 struct drm_display_mode *newmode;
2231 struct drm_device *dev = connector->dev;
2232
2233 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2234 const struct minimode *m = &extra_modes[i];
2235 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2236 if (!newmode)
2237 return modes;
2238
2239 fixup_mode_1366x768(newmode);
2240 if (!mode_in_range(newmode, edid, timing) ||
2241 !valid_inferred_mode(connector, newmode)) {
2242 drm_mode_destroy(dev, newmode);
2243 continue;
2244 }
2245
2246 drm_mode_probed_add(connector, newmode);
2247 modes++;
2248 }
2249
2250 return modes;
2251 }
2252
2253 static int
2254 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2255 struct detailed_timing *timing)
2256 {
2257 int i, modes = 0;
2258 struct drm_display_mode *newmode;
2259 struct drm_device *dev = connector->dev;
2260 bool rb = drm_monitor_supports_rb(edid);
2261
2262 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2263 const struct minimode *m = &extra_modes[i];
2264 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2265 if (!newmode)
2266 return modes;
2267
2268 fixup_mode_1366x768(newmode);
2269 if (!mode_in_range(newmode, edid, timing) ||
2270 !valid_inferred_mode(connector, newmode)) {
2271 drm_mode_destroy(dev, newmode);
2272 continue;
2273 }
2274
2275 drm_mode_probed_add(connector, newmode);
2276 modes++;
2277 }
2278
2279 return modes;
2280 }
2281
2282 static void
2283 do_inferred_modes(struct detailed_timing *timing, void *c)
2284 {
2285 struct detailed_mode_closure *closure = c;
2286 struct detailed_non_pixel *data = &timing->data.other_data;
2287 struct detailed_data_monitor_range *range = &data->data.range;
2288
2289 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2290 return;
2291
2292 closure->modes += drm_dmt_modes_for_range(closure->connector,
2293 closure->edid,
2294 timing);
2295
2296 if (!version_greater(closure->edid, 1, 1))
2297 return; /* GTF not defined yet */
2298
2299 switch (range->flags) {
2300 case 0x02: /* secondary gtf, XXX could do more */
2301 case 0x00: /* default gtf */
2302 closure->modes += drm_gtf_modes_for_range(closure->connector,
2303 closure->edid,
2304 timing);
2305 break;
2306 case 0x04: /* cvt, only in 1.4+ */
2307 if (!version_greater(closure->edid, 1, 3))
2308 break;
2309
2310 closure->modes += drm_cvt_modes_for_range(closure->connector,
2311 closure->edid,
2312 timing);
2313 break;
2314 case 0x01: /* just the ranges, no formula */
2315 default:
2316 break;
2317 }
2318 }
2319
2320 static int
2321 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2322 {
2323 struct detailed_mode_closure closure = {
2324 .connector = connector,
2325 .edid = edid,
2326 };
2327
2328 if (version_greater(edid, 1, 0))
2329 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2330 &closure);
2331
2332 return closure.modes;
2333 }
2334
2335 static int
2336 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2337 {
2338 int i, j, m, modes = 0;
2339 struct drm_display_mode *mode;
2340 u8 *est = ((u8 *)timing) + 6;
2341
2342 for (i = 0; i < 6; i++) {
2343 for (j = 7; j >= 0; j--) {
2344 m = (i * 8) + (7 - j);
2345 if (m >= ARRAY_SIZE(est3_modes))
2346 break;
2347 if (est[i] & (1 << j)) {
2348 mode = drm_mode_find_dmt(connector->dev,
2349 est3_modes[m].w,
2350 est3_modes[m].h,
2351 est3_modes[m].r,
2352 est3_modes[m].rb);
2353 if (mode) {
2354 drm_mode_probed_add(connector, mode);
2355 modes++;
2356 }
2357 }
2358 }
2359 }
2360
2361 return modes;
2362 }
2363
2364 static void
2365 do_established_modes(struct detailed_timing *timing, void *c)
2366 {
2367 struct detailed_mode_closure *closure = c;
2368 struct detailed_non_pixel *data = &timing->data.other_data;
2369
2370 if (data->type == EDID_DETAIL_EST_TIMINGS)
2371 closure->modes += drm_est3_modes(closure->connector, timing);
2372 }
2373
2374 /**
2375 * add_established_modes - get est. modes from EDID and add them
2376 * @connector: connector to add mode(s) to
2377 * @edid: EDID block to scan
2378 *
2379 * Each EDID block contains a bitmap of the supported "established modes" list
2380 * (defined above). Tease them out and add them to the global modes list.
2381 */
2382 static int
2383 add_established_modes(struct drm_connector *connector, struct edid *edid)
2384 {
2385 struct drm_device *dev = connector->dev;
2386 unsigned long est_bits = edid->established_timings.t1 |
2387 (edid->established_timings.t2 << 8) |
2388 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2389 int i, modes = 0;
2390 struct detailed_mode_closure closure = {
2391 .connector = connector,
2392 .edid = edid,
2393 };
2394
2395 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2396 if (est_bits & (1<<i)) {
2397 struct drm_display_mode *newmode;
2398 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2399 if (newmode) {
2400 drm_mode_probed_add(connector, newmode);
2401 modes++;
2402 }
2403 }
2404 }
2405
2406 if (version_greater(edid, 1, 0))
2407 drm_for_each_detailed_block((u8 *)edid,
2408 do_established_modes, &closure);
2409
2410 return modes + closure.modes;
2411 }
2412
2413 static void
2414 do_standard_modes(struct detailed_timing *timing, void *c)
2415 {
2416 struct detailed_mode_closure *closure = c;
2417 struct detailed_non_pixel *data = &timing->data.other_data;
2418 struct drm_connector *connector = closure->connector;
2419 struct edid *edid = closure->edid;
2420
2421 if (data->type == EDID_DETAIL_STD_MODES) {
2422 int i;
2423 for (i = 0; i < 6; i++) {
2424 struct std_timing *std;
2425 struct drm_display_mode *newmode;
2426
2427 std = &data->data.timings[i];
2428 newmode = drm_mode_std(connector, edid, std);
2429 if (newmode) {
2430 drm_mode_probed_add(connector, newmode);
2431 closure->modes++;
2432 }
2433 }
2434 }
2435 }
2436
2437 /**
2438 * add_standard_modes - get std. modes from EDID and add them
2439 * @connector: connector to add mode(s) to
2440 * @edid: EDID block to scan
2441 *
2442 * Standard modes can be calculated using the appropriate standard (DMT,
2443 * GTF or CVT. Grab them from @edid and add them to the list.
2444 */
2445 static int
2446 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2447 {
2448 int i, modes = 0;
2449 struct detailed_mode_closure closure = {
2450 .connector = connector,
2451 .edid = edid,
2452 };
2453
2454 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2455 struct drm_display_mode *newmode;
2456
2457 newmode = drm_mode_std(connector, edid,
2458 &edid->standard_timings[i]);
2459 if (newmode) {
2460 drm_mode_probed_add(connector, newmode);
2461 modes++;
2462 }
2463 }
2464
2465 if (version_greater(edid, 1, 0))
2466 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2467 &closure);
2468
2469 /* XXX should also look for standard codes in VTB blocks */
2470
2471 return modes + closure.modes;
2472 }
2473
2474 static int drm_cvt_modes(struct drm_connector *connector,
2475 struct detailed_timing *timing)
2476 {
2477 int i, j, modes = 0;
2478 struct drm_display_mode *newmode;
2479 struct drm_device *dev = connector->dev;
2480 struct cvt_timing *cvt;
2481 const int rates[] = { 60, 85, 75, 60, 50 };
2482 const u8 empty[3] = { 0, 0, 0 };
2483
2484 for (i = 0; i < 4; i++) {
2485 int width = 0, height;
2486 cvt = &(timing->data.other_data.data.cvt[i]);
2487
2488 if (!memcmp(cvt->code, empty, 3))
2489 continue;
2490
2491 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2492 switch (cvt->code[1] & 0x0c) {
2493 case 0x00:
2494 width = height * 4 / 3;
2495 break;
2496 case 0x04:
2497 width = height * 16 / 9;
2498 break;
2499 case 0x08:
2500 width = height * 16 / 10;
2501 break;
2502 case 0x0c:
2503 width = height * 15 / 9;
2504 break;
2505 }
2506
2507 for (j = 1; j < 5; j++) {
2508 if (cvt->code[2] & (1 << j)) {
2509 newmode = drm_cvt_mode(dev, width, height,
2510 rates[j], j == 0,
2511 false, false);
2512 if (newmode) {
2513 drm_mode_probed_add(connector, newmode);
2514 modes++;
2515 }
2516 }
2517 }
2518 }
2519
2520 return modes;
2521 }
2522
2523 static void
2524 do_cvt_mode(struct detailed_timing *timing, void *c)
2525 {
2526 struct detailed_mode_closure *closure = c;
2527 struct detailed_non_pixel *data = &timing->data.other_data;
2528
2529 if (data->type == EDID_DETAIL_CVT_3BYTE)
2530 closure->modes += drm_cvt_modes(closure->connector, timing);
2531 }
2532
2533 static int
2534 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2535 {
2536 struct detailed_mode_closure closure = {
2537 .connector = connector,
2538 .edid = edid,
2539 };
2540
2541 if (version_greater(edid, 1, 2))
2542 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2543
2544 /* XXX should also look for CVT codes in VTB blocks */
2545
2546 return closure.modes;
2547 }
2548
2549 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2550
2551 static void
2552 do_detailed_mode(struct detailed_timing *timing, void *c)
2553 {
2554 struct detailed_mode_closure *closure = c;
2555 struct drm_display_mode *newmode;
2556
2557 if (timing->pixel_clock) {
2558 newmode = drm_mode_detailed(closure->connector->dev,
2559 closure->edid, timing,
2560 closure->quirks);
2561 if (!newmode)
2562 return;
2563
2564 if (closure->preferred)
2565 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2566
2567 /*
2568 * Detailed modes are limited to 10kHz pixel clock resolution,
2569 * so fix up anything that looks like CEA/HDMI mode, but the clock
2570 * is just slightly off.
2571 */
2572 fixup_detailed_cea_mode_clock(newmode);
2573
2574 drm_mode_probed_add(closure->connector, newmode);
2575 closure->modes++;
2576 closure->preferred = 0;
2577 }
2578 }
2579
2580 /*
2581 * add_detailed_modes - Add modes from detailed timings
2582 * @connector: attached connector
2583 * @edid: EDID block to scan
2584 * @quirks: quirks to apply
2585 */
2586 static int
2587 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2588 u32 quirks)
2589 {
2590 struct detailed_mode_closure closure = {
2591 .connector = connector,
2592 .edid = edid,
2593 .preferred = 1,
2594 .quirks = quirks,
2595 };
2596
2597 if (closure.preferred && !version_greater(edid, 1, 3))
2598 closure.preferred =
2599 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2600
2601 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2602
2603 return closure.modes;
2604 }
2605
2606 #define AUDIO_BLOCK 0x01
2607 #define VIDEO_BLOCK 0x02
2608 #define VENDOR_BLOCK 0x03
2609 #define SPEAKER_BLOCK 0x04
2610 #define VIDEO_CAPABILITY_BLOCK 0x07
2611 #define EDID_BASIC_AUDIO (1 << 6)
2612 #define EDID_CEA_YCRCB444 (1 << 5)
2613 #define EDID_CEA_YCRCB422 (1 << 4)
2614 #define EDID_CEA_VCDB_QS (1 << 6)
2615
2616 /*
2617 * Search EDID for CEA extension block.
2618 */
2619 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2620 {
2621 u8 *edid_ext = NULL;
2622 int i;
2623
2624 /* No EDID or EDID extensions */
2625 if (edid == NULL || edid->extensions == 0)
2626 return NULL;
2627
2628 /* Find CEA extension */
2629 for (i = 0; i < edid->extensions; i++) {
2630 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2631 if (edid_ext[0] == ext_id)
2632 break;
2633 }
2634
2635 if (i == edid->extensions)
2636 return NULL;
2637
2638 return edid_ext;
2639 }
2640
2641 static u8 *drm_find_cea_extension(struct edid *edid)
2642 {
2643 return drm_find_edid_extension(edid, CEA_EXT);
2644 }
2645
2646 static u8 *drm_find_displayid_extension(struct edid *edid)
2647 {
2648 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2649 }
2650
2651 /*
2652 * Calculate the alternate clock for the CEA mode
2653 * (60Hz vs. 59.94Hz etc.)
2654 */
2655 static unsigned int
2656 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2657 {
2658 unsigned int clock = cea_mode->clock;
2659
2660 if (cea_mode->vrefresh % 6 != 0)
2661 return clock;
2662
2663 /*
2664 * edid_cea_modes contains the 59.94Hz
2665 * variant for 240 and 480 line modes,
2666 * and the 60Hz variant otherwise.
2667 */
2668 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2669 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2670 else
2671 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2672
2673 return clock;
2674 }
2675
2676 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2677 unsigned int clock_tolerance)
2678 {
2679 u8 vic;
2680
2681 if (!to_match->clock)
2682 return 0;
2683
2684 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2685 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2686 unsigned int clock1, clock2;
2687
2688 /* Check both 60Hz and 59.94Hz */
2689 clock1 = cea_mode->clock;
2690 clock2 = cea_mode_alternate_clock(cea_mode);
2691
2692 if (abs(to_match->clock - clock1) > clock_tolerance &&
2693 abs(to_match->clock - clock2) > clock_tolerance)
2694 continue;
2695
2696 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2697 return vic;
2698 }
2699
2700 return 0;
2701 }
2702
2703 /**
2704 * drm_match_cea_mode - look for a CEA mode matching given mode
2705 * @to_match: display mode
2706 *
2707 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2708 * mode.
2709 */
2710 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2711 {
2712 u8 vic;
2713
2714 if (!to_match->clock)
2715 return 0;
2716
2717 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2718 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2719 unsigned int clock1, clock2;
2720
2721 /* Check both 60Hz and 59.94Hz */
2722 clock1 = cea_mode->clock;
2723 clock2 = cea_mode_alternate_clock(cea_mode);
2724
2725 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2726 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2727 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2728 return vic;
2729 }
2730 return 0;
2731 }
2732 EXPORT_SYMBOL(drm_match_cea_mode);
2733
2734 static bool drm_valid_cea_vic(u8 vic)
2735 {
2736 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2737 }
2738
2739 /**
2740 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2741 * the input VIC from the CEA mode list
2742 * @video_code: ID given to each of the CEA modes
2743 *
2744 * Returns picture aspect ratio
2745 */
2746 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2747 {
2748 return edid_cea_modes[video_code].picture_aspect_ratio;
2749 }
2750 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2751
2752 /*
2753 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2754 * specific block).
2755 *
2756 * It's almost like cea_mode_alternate_clock(), we just need to add an
2757 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2758 * one.
2759 */
2760 static unsigned int
2761 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2762 {
2763 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2764 return hdmi_mode->clock;
2765
2766 return cea_mode_alternate_clock(hdmi_mode);
2767 }
2768
2769 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2770 unsigned int clock_tolerance)
2771 {
2772 u8 vic;
2773
2774 if (!to_match->clock)
2775 return 0;
2776
2777 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2778 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2779 unsigned int clock1, clock2;
2780
2781 /* Make sure to also match alternate clocks */
2782 clock1 = hdmi_mode->clock;
2783 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2784
2785 if (abs(to_match->clock - clock1) > clock_tolerance &&
2786 abs(to_match->clock - clock2) > clock_tolerance)
2787 continue;
2788
2789 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2790 return vic;
2791 }
2792
2793 return 0;
2794 }
2795
2796 /*
2797 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2798 * @to_match: display mode
2799 *
2800 * An HDMI mode is one defined in the HDMI vendor specific block.
2801 *
2802 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2803 */
2804 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2805 {
2806 u8 vic;
2807
2808 if (!to_match->clock)
2809 return 0;
2810
2811 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2812 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2813 unsigned int clock1, clock2;
2814
2815 /* Make sure to also match alternate clocks */
2816 clock1 = hdmi_mode->clock;
2817 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2818
2819 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2820 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2821 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2822 return vic;
2823 }
2824 return 0;
2825 }
2826
2827 static bool drm_valid_hdmi_vic(u8 vic)
2828 {
2829 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2830 }
2831
2832 static int
2833 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2834 {
2835 struct drm_device *dev = connector->dev;
2836 struct drm_display_mode *mode, *tmp;
2837 LINUX_LIST_HEAD(list);
2838 int modes = 0;
2839
2840 /* Don't add CEA modes if the CEA extension block is missing */
2841 if (!drm_find_cea_extension(edid))
2842 return 0;
2843
2844 /*
2845 * Go through all probed modes and create a new mode
2846 * with the alternate clock for certain CEA modes.
2847 */
2848 list_for_each_entry(mode, &connector->probed_modes, head) {
2849 const struct drm_display_mode *cea_mode = NULL;
2850 struct drm_display_mode *newmode;
2851 u8 vic = drm_match_cea_mode(mode);
2852 unsigned int clock1, clock2;
2853
2854 if (drm_valid_cea_vic(vic)) {
2855 cea_mode = &edid_cea_modes[vic];
2856 clock2 = cea_mode_alternate_clock(cea_mode);
2857 } else {
2858 vic = drm_match_hdmi_mode(mode);
2859 if (drm_valid_hdmi_vic(vic)) {
2860 cea_mode = &edid_4k_modes[vic];
2861 clock2 = hdmi_mode_alternate_clock(cea_mode);
2862 }
2863 }
2864
2865 if (!cea_mode)
2866 continue;
2867
2868 clock1 = cea_mode->clock;
2869
2870 if (clock1 == clock2)
2871 continue;
2872
2873 if (mode->clock != clock1 && mode->clock != clock2)
2874 continue;
2875
2876 newmode = drm_mode_duplicate(dev, cea_mode);
2877 if (!newmode)
2878 continue;
2879
2880 /* Carry over the stereo flags */
2881 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2882
2883 /*
2884 * The current mode could be either variant. Make
2885 * sure to pick the "other" clock for the new mode.
2886 */
2887 if (mode->clock != clock1)
2888 newmode->clock = clock1;
2889 else
2890 newmode->clock = clock2;
2891
2892 list_add_tail(&newmode->head, &list);
2893 }
2894
2895 list_for_each_entry_safe(mode, tmp, &list, head) {
2896 list_del(&mode->head);
2897 drm_mode_probed_add(connector, mode);
2898 modes++;
2899 }
2900
2901 return modes;
2902 }
2903
2904 static struct drm_display_mode *
2905 drm_display_mode_from_vic_index(struct drm_connector *connector,
2906 const u8 *video_db, u8 video_len,
2907 u8 video_index)
2908 {
2909 struct drm_device *dev = connector->dev;
2910 struct drm_display_mode *newmode;
2911 u8 vic;
2912
2913 if (video_db == NULL || video_index >= video_len)
2914 return NULL;
2915
2916 /* CEA modes are numbered 1..127 */
2917 vic = (video_db[video_index] & 127);
2918 if (!drm_valid_cea_vic(vic))
2919 return NULL;
2920
2921 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2922 if (!newmode)
2923 return NULL;
2924
2925 newmode->vrefresh = 0;
2926
2927 return newmode;
2928 }
2929
2930 static int
2931 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2932 {
2933 int i, modes = 0;
2934
2935 for (i = 0; i < len; i++) {
2936 struct drm_display_mode *mode;
2937 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2938 if (mode) {
2939 drm_mode_probed_add(connector, mode);
2940 modes++;
2941 }
2942 }
2943
2944 return modes;
2945 }
2946
2947 struct stereo_mandatory_mode {
2948 int width, height, vrefresh;
2949 unsigned int flags;
2950 };
2951
2952 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2953 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2954 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2955 { 1920, 1080, 50,
2956 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2957 { 1920, 1080, 60,
2958 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2959 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2960 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2961 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2962 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2963 };
2964
2965 static bool
2966 stereo_match_mandatory(const struct drm_display_mode *mode,
2967 const struct stereo_mandatory_mode *stereo_mode)
2968 {
2969 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2970
2971 return mode->hdisplay == stereo_mode->width &&
2972 mode->vdisplay == stereo_mode->height &&
2973 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2974 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2975 }
2976
2977 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2978 {
2979 struct drm_device *dev = connector->dev;
2980 struct drm_display_mode *mode;
2981 struct list_head stereo_modes;
2982 int modes = 0, i;
2983
2984 INIT_LIST_HEAD(&stereo_modes);
2985
2986 list_for_each_entry(mode, &connector->probed_modes, head) {
2987 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2988 const struct stereo_mandatory_mode *mandatory;
2989 struct drm_display_mode *new_mode;
2990
2991 if (!stereo_match_mandatory(mode,
2992 &stereo_mandatory_modes[i]))
2993 continue;
2994
2995 mandatory = &stereo_mandatory_modes[i];
2996 new_mode = drm_mode_duplicate(dev, mode);
2997 if (!new_mode)
2998 continue;
2999
3000 new_mode->flags |= mandatory->flags;
3001 list_add_tail(&new_mode->head, &stereo_modes);
3002 modes++;
3003 }
3004 }
3005
3006 list_splice_tail(&stereo_modes, &connector->probed_modes);
3007
3008 return modes;
3009 }
3010
3011 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3012 {
3013 struct drm_device *dev = connector->dev;
3014 struct drm_display_mode *newmode;
3015
3016 if (!drm_valid_hdmi_vic(vic)) {
3017 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3018 return 0;
3019 }
3020
3021 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3022 if (!newmode)
3023 return 0;
3024
3025 drm_mode_probed_add(connector, newmode);
3026
3027 return 1;
3028 }
3029
3030 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3031 const u8 *video_db, u8 video_len, u8 video_index)
3032 {
3033 struct drm_display_mode *newmode;
3034 int modes = 0;
3035
3036 if (structure & (1 << 0)) {
3037 newmode = drm_display_mode_from_vic_index(connector, video_db,
3038 video_len,
3039 video_index);
3040 if (newmode) {
3041 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3042 drm_mode_probed_add(connector, newmode);
3043 modes++;
3044 }
3045 }
3046 if (structure & (1 << 6)) {
3047 newmode = drm_display_mode_from_vic_index(connector, video_db,
3048 video_len,
3049 video_index);
3050 if (newmode) {
3051 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3052 drm_mode_probed_add(connector, newmode);
3053 modes++;
3054 }
3055 }
3056 if (structure & (1 << 8)) {
3057 newmode = drm_display_mode_from_vic_index(connector, video_db,
3058 video_len,
3059 video_index);
3060 if (newmode) {
3061 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3062 drm_mode_probed_add(connector, newmode);
3063 modes++;
3064 }
3065 }
3066
3067 return modes;
3068 }
3069
3070 /*
3071 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3072 * @connector: connector corresponding to the HDMI sink
3073 * @db: start of the CEA vendor specific block
3074 * @len: length of the CEA block payload, ie. one can access up to db[len]
3075 *
3076 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3077 * also adds the stereo 3d modes when applicable.
3078 */
3079 static int
3080 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3081 const u8 *video_db, u8 video_len)
3082 {
3083 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3084 u8 vic_len, hdmi_3d_len = 0;
3085 u16 mask;
3086 u16 structure_all;
3087
3088 if (len < 8)
3089 goto out;
3090
3091 /* no HDMI_Video_Present */
3092 if (!(db[8] & (1 << 5)))
3093 goto out;
3094
3095 /* Latency_Fields_Present */
3096 if (db[8] & (1 << 7))
3097 offset += 2;
3098
3099 /* I_Latency_Fields_Present */
3100 if (db[8] & (1 << 6))
3101 offset += 2;
3102
3103 /* the declared length is not long enough for the 2 first bytes
3104 * of additional video format capabilities */
3105 if (len < (8 + offset + 2))
3106 goto out;
3107
3108 /* 3D_Present */
3109 offset++;
3110 if (db[8 + offset] & (1 << 7)) {
3111 modes += add_hdmi_mandatory_stereo_modes(connector);
3112
3113 /* 3D_Multi_present */
3114 multi_present = (db[8 + offset] & 0x60) >> 5;
3115 }
3116
3117 offset++;
3118 vic_len = db[8 + offset] >> 5;
3119 hdmi_3d_len = db[8 + offset] & 0x1f;
3120
3121 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3122 u8 vic;
3123
3124 vic = db[9 + offset + i];
3125 modes += add_hdmi_mode(connector, vic);
3126 }
3127 offset += 1 + vic_len;
3128
3129 if (multi_present == 1)
3130 multi_len = 2;
3131 else if (multi_present == 2)
3132 multi_len = 4;
3133 else
3134 multi_len = 0;
3135
3136 if (len < (8 + offset + hdmi_3d_len - 1))
3137 goto out;
3138
3139 if (hdmi_3d_len < multi_len)
3140 goto out;
3141
3142 if (multi_present == 1 || multi_present == 2) {
3143 /* 3D_Structure_ALL */
3144 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3145
3146 /* check if 3D_MASK is present */
3147 if (multi_present == 2)
3148 mask = (db[10 + offset] << 8) | db[11 + offset];
3149 else
3150 mask = 0xffff;
3151
3152 for (i = 0; i < 16; i++) {
3153 if (mask & (1 << i))
3154 modes += add_3d_struct_modes(connector,
3155 structure_all,
3156 video_db,
3157 video_len, i);
3158 }
3159 }
3160
3161 offset += multi_len;
3162
3163 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3164 int vic_index;
3165 struct drm_display_mode *newmode = NULL;
3166 unsigned int newflag = 0;
3167 bool detail_present;
3168
3169 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3170
3171 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3172 break;
3173
3174 /* 2D_VIC_order_X */
3175 vic_index = db[8 + offset + i] >> 4;
3176
3177 /* 3D_Structure_X */
3178 switch (db[8 + offset + i] & 0x0f) {
3179 case 0:
3180 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3181 break;
3182 case 6:
3183 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3184 break;
3185 case 8:
3186 /* 3D_Detail_X */
3187 if ((db[9 + offset + i] >> 4) == 1)
3188 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3189 break;
3190 }
3191
3192 if (newflag != 0) {
3193 newmode = drm_display_mode_from_vic_index(connector,
3194 video_db,
3195 video_len,
3196 vic_index);
3197
3198 if (newmode) {
3199 newmode->flags |= newflag;
3200 drm_mode_probed_add(connector, newmode);
3201 modes++;
3202 }
3203 }
3204
3205 if (detail_present)
3206 i++;
3207 }
3208
3209 out:
3210 return modes;
3211 }
3212
3213 static int
3214 cea_db_payload_len(const u8 *db)
3215 {
3216 return db[0] & 0x1f;
3217 }
3218
3219 static int
3220 cea_db_tag(const u8 *db)
3221 {
3222 return db[0] >> 5;
3223 }
3224
3225 static int
3226 cea_revision(const u8 *cea)
3227 {
3228 return cea[1];
3229 }
3230
3231 static int
3232 cea_db_offsets(const u8 *cea, int *start, int *end)
3233 {
3234 /* Data block offset in CEA extension block */
3235 *start = 4;
3236 *end = cea[2];
3237 if (*end == 0)
3238 *end = 127;
3239 if (*end < 4 || *end > 127)
3240 return -ERANGE;
3241 return 0;
3242 }
3243
3244 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3245 {
3246 int hdmi_id;
3247
3248 if (cea_db_tag(db) != VENDOR_BLOCK)
3249 return false;
3250
3251 if (cea_db_payload_len(db) < 5)
3252 return false;
3253
3254 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3255
3256 return hdmi_id == HDMI_IEEE_OUI;
3257 }
3258
3259 #define for_each_cea_db(cea, i, start, end) \
3260 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3261
3262 static int
3263 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3264 {
3265 const u8 *cea = drm_find_cea_extension(edid);
3266 const u8 *db, *hdmi = NULL, *video = NULL;
3267 u8 dbl, hdmi_len, video_len = 0;
3268 int modes = 0;
3269
3270 if (cea && cea_revision(cea) >= 3) {
3271 int i, start, end;
3272
3273 if (cea_db_offsets(cea, &start, &end))
3274 return 0;
3275
3276 for_each_cea_db(cea, i, start, end) {
3277 db = &cea[i];
3278 dbl = cea_db_payload_len(db);
3279
3280 if (cea_db_tag(db) == VIDEO_BLOCK) {
3281 video = db + 1;
3282 video_len = dbl;
3283 modes += do_cea_modes(connector, video, dbl);
3284 }
3285 else if (cea_db_is_hdmi_vsdb(db)) {
3286 hdmi = db;
3287 hdmi_len = dbl;
3288 }
3289 }
3290 }
3291
3292 /*
3293 * We parse the HDMI VSDB after having added the cea modes as we will
3294 * be patching their flags when the sink supports stereo 3D.
3295 */
3296 if (hdmi)
3297 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3298 video_len);
3299
3300 return modes;
3301 }
3302
3303 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3304 {
3305 const struct drm_display_mode *cea_mode;
3306 int clock1, clock2, clock;
3307 u8 vic;
3308 const char *type;
3309
3310 /*
3311 * allow 5kHz clock difference either way to account for
3312 * the 10kHz clock resolution limit of detailed timings.
3313 */
3314 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3315 if (drm_valid_cea_vic(vic)) {
3316 type = "CEA";
3317 cea_mode = &edid_cea_modes[vic];
3318 clock1 = cea_mode->clock;
3319 clock2 = cea_mode_alternate_clock(cea_mode);
3320 } else {
3321 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3322 if (drm_valid_hdmi_vic(vic)) {
3323 type = "HDMI";
3324 cea_mode = &edid_4k_modes[vic];
3325 clock1 = cea_mode->clock;
3326 clock2 = hdmi_mode_alternate_clock(cea_mode);
3327 } else {
3328 return;
3329 }
3330 }
3331
3332 /* pick whichever is closest */
3333 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3334 clock = clock1;
3335 else
3336 clock = clock2;
3337
3338 if (mode->clock == clock)
3339 return;
3340
3341 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3342 type, vic, mode->clock, clock);
3343 mode->clock = clock;
3344 }
3345
3346 static void
3347 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3348 {
3349 u8 len = cea_db_payload_len(db);
3350
3351 if (len >= 6) {
3352 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3353 connector->dvi_dual = db[6] & 1;
3354 }
3355 if (len >= 7)
3356 connector->max_tmds_clock = db[7] * 5;
3357 if (len >= 8) {
3358 connector->latency_present[0] = db[8] >> 7;
3359 connector->latency_present[1] = (db[8] >> 6) & 1;
3360 }
3361 if (len >= 9)
3362 connector->video_latency[0] = db[9];
3363 if (len >= 10)
3364 connector->audio_latency[0] = db[10];
3365 if (len >= 11)
3366 connector->video_latency[1] = db[11];
3367 if (len >= 12)
3368 connector->audio_latency[1] = db[12];
3369
3370 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3371 "max TMDS clock %d, "
3372 "latency present %d %d, "
3373 "video latency %d %d, "
3374 "audio latency %d %d\n",
3375 connector->dvi_dual,
3376 connector->max_tmds_clock,
3377 (int) connector->latency_present[0],
3378 (int) connector->latency_present[1],
3379 connector->video_latency[0],
3380 connector->video_latency[1],
3381 connector->audio_latency[0],
3382 connector->audio_latency[1]);
3383 }
3384
3385 static void
3386 monitor_name(struct detailed_timing *t, void *data)
3387 {
3388 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3389 *(u8 **)data = t->data.other_data.data.str.str;
3390 }
3391
3392 static int get_monitor_name(struct edid *edid, char name[13])
3393 {
3394 char *edid_name = NULL;
3395 int mnl;
3396
3397 if (!edid || !name)
3398 return 0;
3399
3400 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3401 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3402 if (edid_name[mnl] == 0x0a)
3403 break;
3404
3405 name[mnl] = edid_name[mnl];
3406 }
3407
3408 return mnl;
3409 }
3410
3411 /**
3412 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3413 * @edid: monitor EDID information
3414 * @name: pointer to a character array to hold the name of the monitor
3415 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3416 *
3417 */
3418 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3419 {
3420 int name_length;
3421 char buf[13];
3422
3423 if (bufsize <= 0)
3424 return;
3425
3426 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3427 memcpy(name, buf, name_length);
3428 name[name_length] = '\0';
3429 }
3430 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3431
3432 /**
3433 * drm_edid_to_eld - build ELD from EDID
3434 * @connector: connector corresponding to the HDMI/DP sink
3435 * @edid: EDID to parse
3436 *
3437 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3438 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3439 * fill in.
3440 */
3441 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3442 {
3443 uint8_t *eld = connector->eld;
3444 u8 *cea;
3445 u8 *db;
3446 int total_sad_count = 0;
3447 int mnl;
3448 int dbl;
3449
3450 memset(eld, 0, sizeof(connector->eld));
3451
3452 cea = drm_find_cea_extension(edid);
3453 if (!cea) {
3454 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3455 return;
3456 }
3457
3458 mnl = get_monitor_name(edid, eld + 20);
3459
3460 eld[4] = (cea[1] << 5) | mnl;
3461 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3462
3463 eld[0] = 2 << 3; /* ELD version: 2 */
3464
3465 eld[16] = edid->mfg_id[0];
3466 eld[17] = edid->mfg_id[1];
3467 eld[18] = edid->prod_code[0];
3468 eld[19] = edid->prod_code[1];
3469
3470 if (cea_revision(cea) >= 3) {
3471 int i, start, end;
3472
3473 if (cea_db_offsets(cea, &start, &end)) {
3474 start = 0;
3475 end = 0;
3476 }
3477
3478 for_each_cea_db(cea, i, start, end) {
3479 db = &cea[i];
3480 dbl = cea_db_payload_len(db);
3481
3482 switch (cea_db_tag(db)) {
3483 int sad_count;
3484
3485 case AUDIO_BLOCK:
3486 /* Audio Data Block, contains SADs */
3487 sad_count = min(dbl / 3, 15 - total_sad_count);
3488 if (sad_count >= 1)
3489 memcpy(eld + 20 + mnl + total_sad_count * 3,
3490 &db[1], sad_count * 3);
3491 total_sad_count += sad_count;
3492 break;
3493 case SPEAKER_BLOCK:
3494 /* Speaker Allocation Data Block */
3495 if (dbl >= 1)
3496 eld[7] = db[1];
3497 break;
3498 case VENDOR_BLOCK:
3499 /* HDMI Vendor-Specific Data Block */
3500 if (cea_db_is_hdmi_vsdb(db))
3501 parse_hdmi_vsdb(connector, db);
3502 break;
3503 default:
3504 break;
3505 }
3506 }
3507 }
3508 eld[5] |= total_sad_count << 4;
3509
3510 eld[DRM_ELD_BASELINE_ELD_LEN] =
3511 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3512
3513 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3514 drm_eld_size(eld), total_sad_count);
3515 }
3516 EXPORT_SYMBOL(drm_edid_to_eld);
3517
3518 /**
3519 * drm_edid_to_sad - extracts SADs from EDID
3520 * @edid: EDID to parse
3521 * @sads: pointer that will be set to the extracted SADs
3522 *
3523 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3524 *
3525 * Note: The returned pointer needs to be freed using kfree().
3526 *
3527 * Return: The number of found SADs or negative number on error.
3528 */
3529 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3530 {
3531 int count = 0;
3532 int i, start, end, dbl;
3533 u8 *cea;
3534
3535 cea = drm_find_cea_extension(edid);
3536 if (!cea) {
3537 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3538 return -ENOENT;
3539 }
3540
3541 if (cea_revision(cea) < 3) {
3542 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3543 return -EOPNOTSUPP;
3544 }
3545
3546 if (cea_db_offsets(cea, &start, &end)) {
3547 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3548 return -EPROTO;
3549 }
3550
3551 for_each_cea_db(cea, i, start, end) {
3552 u8 *db = &cea[i];
3553
3554 if (cea_db_tag(db) == AUDIO_BLOCK) {
3555 int j;
3556 dbl = cea_db_payload_len(db);
3557
3558 count = dbl / 3; /* SAD is 3B */
3559 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3560 if (!*sads)
3561 return -ENOMEM;
3562 for (j = 0; j < count; j++) {
3563 u8 *sad = &db[1 + j * 3];
3564
3565 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3566 (*sads)[j].channels = sad[0] & 0x7;
3567 (*sads)[j].freq = sad[1] & 0x7F;
3568 (*sads)[j].byte2 = sad[2];
3569 }
3570 break;
3571 }
3572 }
3573
3574 return count;
3575 }
3576 EXPORT_SYMBOL(drm_edid_to_sad);
3577
3578 /**
3579 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3580 * @edid: EDID to parse
3581 * @sadb: pointer to the speaker block
3582 *
3583 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3584 *
3585 * Note: The returned pointer needs to be freed using kfree().
3586 *
3587 * Return: The number of found Speaker Allocation Blocks or negative number on
3588 * error.
3589 */
3590 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3591 {
3592 int count = 0;
3593 int i, start, end, dbl;
3594 const u8 *cea;
3595
3596 cea = drm_find_cea_extension(edid);
3597 if (!cea) {
3598 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3599 return -ENOENT;
3600 }
3601
3602 if (cea_revision(cea) < 3) {
3603 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3604 return -ENOTSUPP;
3605 }
3606
3607 if (cea_db_offsets(cea, &start, &end)) {
3608 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3609 return -EPROTO;
3610 }
3611
3612 for_each_cea_db(cea, i, start, end) {
3613 const u8 *db = &cea[i];
3614
3615 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3616 dbl = cea_db_payload_len(db);
3617
3618 /* Speaker Allocation Data Block */
3619 if (dbl == 3) {
3620 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3621 if (!*sadb)
3622 return -ENOMEM;
3623 count = dbl;
3624 break;
3625 }
3626 }
3627 }
3628
3629 return count;
3630 }
3631 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3632
3633 /**
3634 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3635 * @connector: connector associated with the HDMI/DP sink
3636 * @mode: the display mode
3637 *
3638 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3639 * the sink doesn't support audio or video.
3640 */
3641 int drm_av_sync_delay(struct drm_connector *connector,
3642 const struct drm_display_mode *mode)
3643 {
3644 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3645 int a, v;
3646
3647 if (!connector->latency_present[0])
3648 return 0;
3649 if (!connector->latency_present[1])
3650 i = 0;
3651
3652 a = connector->audio_latency[i];
3653 v = connector->video_latency[i];
3654
3655 /*
3656 * HDMI/DP sink doesn't support audio or video?
3657 */
3658 if (a == 255 || v == 255)
3659 return 0;
3660
3661 /*
3662 * Convert raw EDID values to millisecond.
3663 * Treat unknown latency as 0ms.
3664 */
3665 if (a)
3666 a = min(2 * (a - 1), 500);
3667 if (v)
3668 v = min(2 * (v - 1), 500);
3669
3670 return max(v - a, 0);
3671 }
3672 EXPORT_SYMBOL(drm_av_sync_delay);
3673
3674 /**
3675 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3676 * @encoder: the encoder just changed display mode
3677 *
3678 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3679 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3680 *
3681 * Return: The connector associated with the first HDMI/DP sink that has ELD
3682 * attached to it.
3683 */
3684 struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3685 {
3686 struct drm_connector *connector;
3687 struct drm_device *dev = encoder->dev;
3688
3689 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3690 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3691
3692 drm_for_each_connector(connector, dev)
3693 if (connector->encoder == encoder && connector->eld[0])
3694 return connector;
3695
3696 return NULL;
3697 }
3698 EXPORT_SYMBOL(drm_select_eld);
3699
3700 /**
3701 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3702 * @edid: monitor EDID information
3703 *
3704 * Parse the CEA extension according to CEA-861-B.
3705 *
3706 * Return: True if the monitor is HDMI, false if not or unknown.
3707 */
3708 bool drm_detect_hdmi_monitor(struct edid *edid)
3709 {
3710 u8 *edid_ext;
3711 int i;
3712 int start_offset, end_offset;
3713
3714 edid_ext = drm_find_cea_extension(edid);
3715 if (!edid_ext)
3716 return false;
3717
3718 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3719 return false;
3720
3721 /*
3722 * Because HDMI identifier is in Vendor Specific Block,
3723 * search it from all data blocks of CEA extension.
3724 */
3725 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3726 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3727 return true;
3728 }
3729
3730 return false;
3731 }
3732 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3733
3734 /**
3735 * drm_detect_monitor_audio - check monitor audio capability
3736 * @edid: EDID block to scan
3737 *
3738 * Monitor should have CEA extension block.
3739 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3740 * audio' only. If there is any audio extension block and supported
3741 * audio format, assume at least 'basic audio' support, even if 'basic
3742 * audio' is not defined in EDID.
3743 *
3744 * Return: True if the monitor supports audio, false otherwise.
3745 */
3746 bool drm_detect_monitor_audio(struct edid *edid)
3747 {
3748 u8 *edid_ext;
3749 int i, j;
3750 bool has_audio = false;
3751 int start_offset, end_offset;
3752
3753 edid_ext = drm_find_cea_extension(edid);
3754 if (!edid_ext)
3755 goto end;
3756
3757 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3758
3759 if (has_audio) {
3760 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3761 goto end;
3762 }
3763
3764 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3765 goto end;
3766
3767 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3768 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3769 has_audio = true;
3770 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3771 DRM_DEBUG_KMS("CEA audio format %d\n",
3772 (edid_ext[i + j] >> 3) & 0xf);
3773 goto end;
3774 }
3775 }
3776 end:
3777 return has_audio;
3778 }
3779 EXPORT_SYMBOL(drm_detect_monitor_audio);
3780
3781 /**
3782 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3783 * @edid: EDID block to scan
3784 *
3785 * Check whether the monitor reports the RGB quantization range selection
3786 * as supported. The AVI infoframe can then be used to inform the monitor
3787 * which quantization range (full or limited) is used.
3788 *
3789 * Return: True if the RGB quantization range is selectable, false otherwise.
3790 */
3791 bool drm_rgb_quant_range_selectable(struct edid *edid)
3792 {
3793 u8 *edid_ext;
3794 int i, start, end;
3795
3796 edid_ext = drm_find_cea_extension(edid);
3797 if (!edid_ext)
3798 return false;
3799
3800 if (cea_db_offsets(edid_ext, &start, &end))
3801 return false;
3802
3803 for_each_cea_db(edid_ext, i, start, end) {
3804 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3805 cea_db_payload_len(&edid_ext[i]) == 2) {
3806 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3807 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3808 }
3809 }
3810
3811 return false;
3812 }
3813 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3814
3815 /**
3816 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3817 * hdmi deep color modes and update drm_display_info if so.
3818 * @edid: monitor EDID information
3819 * @info: Updated with maximum supported deep color bpc and color format
3820 * if deep color supported.
3821 * @connector: DRM connector, used only for debug output
3822 *
3823 * Parse the CEA extension according to CEA-861-B.
3824 * Return true if HDMI deep color supported, false if not or unknown.
3825 */
3826 static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3827 struct drm_display_info *info,
3828 struct drm_connector *connector)
3829 {
3830 u8 *edid_ext, *hdmi;
3831 int i;
3832 int start_offset, end_offset;
3833 unsigned int dc_bpc = 0;
3834
3835 edid_ext = drm_find_cea_extension(edid);
3836 if (!edid_ext)
3837 return false;
3838
3839 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3840 return false;
3841
3842 /*
3843 * Because HDMI identifier is in Vendor Specific Block,
3844 * search it from all data blocks of CEA extension.
3845 */
3846 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3847 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3848 /* HDMI supports at least 8 bpc */
3849 info->bpc = 8;
3850
3851 hdmi = &edid_ext[i];
3852 if (cea_db_payload_len(hdmi) < 6)
3853 return false;
3854
3855 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3856 dc_bpc = 10;
3857 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3858 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3859 connector->name);
3860 }
3861
3862 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3863 dc_bpc = 12;
3864 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3865 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3866 connector->name);
3867 }
3868
3869 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3870 dc_bpc = 16;
3871 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3872 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3873 connector->name);
3874 }
3875
3876 if (dc_bpc > 0) {
3877 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3878 connector->name, dc_bpc);
3879 info->bpc = dc_bpc;
3880
3881 /*
3882 * Deep color support mandates RGB444 support for all video
3883 * modes and forbids YCRCB422 support for all video modes per
3884 * HDMI 1.3 spec.
3885 */
3886 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3887
3888 /* YCRCB444 is optional according to spec. */
3889 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3890 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3891 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3892 connector->name);
3893 }
3894
3895 /*
3896 * Spec says that if any deep color mode is supported at all,
3897 * then deep color 36 bit must be supported.
3898 */
3899 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3900 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3901 connector->name);
3902 }
3903
3904 return true;
3905 }
3906 else {
3907 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3908 connector->name);
3909 }
3910 }
3911 }
3912
3913 return false;
3914 }
3915
3916 /**
3917 * drm_add_display_info - pull display info out if present
3918 * @edid: EDID data
3919 * @info: display info (attached to connector)
3920 * @connector: connector whose edid is used to build display info
3921 *
3922 * Grab any available display info and stuff it into the drm_display_info
3923 * structure that's part of the connector. Useful for tracking bpp and
3924 * color spaces.
3925 */
3926 static void drm_add_display_info(struct edid *edid,
3927 struct drm_display_info *info,
3928 struct drm_connector *connector)
3929 {
3930 u8 *edid_ext;
3931
3932 info->width_mm = edid->width_cm * 10;
3933 info->height_mm = edid->height_cm * 10;
3934
3935 /* driver figures it out in this case */
3936 info->bpc = 0;
3937 info->color_formats = 0;
3938
3939 if (edid->revision < 3)
3940 return;
3941
3942 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3943 return;
3944
3945 /* Get data from CEA blocks if present */
3946 edid_ext = drm_find_cea_extension(edid);
3947 if (edid_ext) {
3948 info->cea_rev = edid_ext[1];
3949
3950 /* The existence of a CEA block should imply RGB support */
3951 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3952 if (edid_ext[3] & EDID_CEA_YCRCB444)
3953 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3954 if (edid_ext[3] & EDID_CEA_YCRCB422)
3955 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3956 }
3957
3958 /* HDMI deep color modes supported? Assign to info, if so */
3959 drm_assign_hdmi_deep_color_info(edid, info, connector);
3960
3961 /* Only defined for 1.4 with digital displays */
3962 if (edid->revision < 4)
3963 return;
3964
3965 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3966 case DRM_EDID_DIGITAL_DEPTH_6:
3967 info->bpc = 6;
3968 break;
3969 case DRM_EDID_DIGITAL_DEPTH_8:
3970 info->bpc = 8;
3971 break;
3972 case DRM_EDID_DIGITAL_DEPTH_10:
3973 info->bpc = 10;
3974 break;
3975 case DRM_EDID_DIGITAL_DEPTH_12:
3976 info->bpc = 12;
3977 break;
3978 case DRM_EDID_DIGITAL_DEPTH_14:
3979 info->bpc = 14;
3980 break;
3981 case DRM_EDID_DIGITAL_DEPTH_16:
3982 info->bpc = 16;
3983 break;
3984 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3985 default:
3986 info->bpc = 0;
3987 break;
3988 }
3989
3990 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3991 connector->name, info->bpc);
3992
3993 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3994 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3995 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3996 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3997 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3998 }
3999
4000 static int validate_displayid(u8 *displayid, int length, int idx)
4001 {
4002 int i;
4003 u8 csum = 0;
4004 struct displayid_hdr *base;
4005
4006 base = (struct displayid_hdr *)&displayid[idx];
4007
4008 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4009 base->rev, base->bytes, base->prod_id, base->ext_count);
4010
4011 if (base->bytes + 5 > length - idx)
4012 return -EINVAL;
4013 for (i = idx; i <= base->bytes + 5; i++) {
4014 csum += displayid[i];
4015 }
4016 if (csum) {
4017 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum);
4018 return -EINVAL;
4019 }
4020 return 0;
4021 }
4022
4023 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4024 struct displayid_detailed_timings_1 *timings)
4025 {
4026 struct drm_display_mode *mode;
4027 unsigned pixel_clock = (timings->pixel_clock[0] |
4028 (timings->pixel_clock[1] << 8) |
4029 (timings->pixel_clock[2] << 16));
4030 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4031 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4032 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4033 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4034 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4035 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4036 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4037 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4038 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4039 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4040 mode = drm_mode_create(dev);
4041 if (!mode)
4042 return NULL;
4043
4044 mode->clock = pixel_clock * 10;
4045 mode->hdisplay = hactive;
4046 mode->hsync_start = mode->hdisplay + hsync;
4047 mode->hsync_end = mode->hsync_start + hsync_width;
4048 mode->htotal = mode->hdisplay + hblank;
4049
4050 mode->vdisplay = vactive;
4051 mode->vsync_start = mode->vdisplay + vsync;
4052 mode->vsync_end = mode->vsync_start + vsync_width;
4053 mode->vtotal = mode->vdisplay + vblank;
4054
4055 mode->flags = 0;
4056 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4057 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4058 mode->type = DRM_MODE_TYPE_DRIVER;
4059
4060 if (timings->flags & 0x80)
4061 mode->type |= DRM_MODE_TYPE_PREFERRED;
4062 mode->vrefresh = drm_mode_vrefresh(mode);
4063 drm_mode_set_name(mode);
4064
4065 return mode;
4066 }
4067
4068 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4069 struct displayid_block *block)
4070 {
4071 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4072 int i;
4073 int num_timings;
4074 struct drm_display_mode *newmode;
4075 int num_modes = 0;
4076 /* blocks must be multiple of 20 bytes length */
4077 if (block->num_bytes % 20)
4078 return 0;
4079
4080 num_timings = block->num_bytes / 20;
4081 for (i = 0; i < num_timings; i++) {
4082 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4083
4084 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4085 if (!newmode)
4086 continue;
4087
4088 drm_mode_probed_add(connector, newmode);
4089 num_modes++;
4090 }
4091 return num_modes;
4092 }
4093
4094 static int add_displayid_detailed_modes(struct drm_connector *connector,
4095 struct edid *edid)
4096 {
4097 u8 *displayid;
4098 int ret;
4099 int idx = 1;
4100 int length = EDID_LENGTH;
4101 struct displayid_block *block;
4102 int num_modes = 0;
4103
4104 displayid = drm_find_displayid_extension(edid);
4105 if (!displayid)
4106 return 0;
4107
4108 ret = validate_displayid(displayid, length, idx);
4109 if (ret)
4110 return 0;
4111
4112 idx += sizeof(struct displayid_hdr);
4113 while (block = (struct displayid_block *)&displayid[idx],
4114 idx + sizeof(struct displayid_block) <= length &&
4115 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4116 block->num_bytes > 0) {
4117 idx += block->num_bytes + sizeof(struct displayid_block);
4118 switch (block->tag) {
4119 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4120 num_modes += add_displayid_detailed_1_modes(connector, block);
4121 break;
4122 }
4123 }
4124 return num_modes;
4125 }
4126
4127 /**
4128 * drm_add_edid_modes - add modes from EDID data, if available
4129 * @connector: connector we're probing
4130 * @edid: EDID data
4131 *
4132 * Add the specified modes to the connector's mode list.
4133 *
4134 * Return: The number of modes added or 0 if we couldn't find any.
4135 */
4136 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4137 {
4138 int num_modes = 0;
4139 u32 quirks;
4140
4141 if (edid == NULL) {
4142 return 0;
4143 }
4144 if (!drm_edid_is_valid(edid)) {
4145 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4146 connector->name);
4147 return 0;
4148 }
4149
4150 quirks = edid_get_quirks(edid);
4151
4152 /*
4153 * EDID spec says modes should be preferred in this order:
4154 * - preferred detailed mode
4155 * - other detailed modes from base block
4156 * - detailed modes from extension blocks
4157 * - CVT 3-byte code modes
4158 * - standard timing codes
4159 * - established timing codes
4160 * - modes inferred from GTF or CVT range information
4161 *
4162 * We get this pretty much right.
4163 *
4164 * XXX order for additional mode types in extension blocks?
4165 */
4166 num_modes += add_detailed_modes(connector, edid, quirks);
4167 num_modes += add_cvt_modes(connector, edid);
4168 num_modes += add_standard_modes(connector, edid);
4169 num_modes += add_established_modes(connector, edid);
4170 num_modes += add_cea_modes(connector, edid);
4171 num_modes += add_alternate_cea_modes(connector, edid);
4172 num_modes += add_displayid_detailed_modes(connector, edid);
4173 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4174 num_modes += add_inferred_modes(connector, edid);
4175
4176 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4177 edid_fixup_preferred(connector, quirks);
4178
4179 drm_add_display_info(edid, &connector->display_info, connector);
4180
4181 if (quirks & EDID_QUIRK_FORCE_6BPC)
4182 connector->display_info.bpc = 6;
4183
4184 if (quirks & EDID_QUIRK_FORCE_8BPC)
4185 connector->display_info.bpc = 8;
4186
4187 if (quirks & EDID_QUIRK_FORCE_12BPC)
4188 connector->display_info.bpc = 12;
4189
4190 return num_modes;
4191 }
4192 EXPORT_SYMBOL(drm_add_edid_modes);
4193
4194 /**
4195 * drm_add_modes_noedid - add modes for the connectors without EDID
4196 * @connector: connector we're probing
4197 * @hdisplay: the horizontal display limit
4198 * @vdisplay: the vertical display limit
4199 *
4200 * Add the specified modes to the connector's mode list. Only when the
4201 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4202 *
4203 * Return: The number of modes added or 0 if we couldn't find any.
4204 */
4205 int drm_add_modes_noedid(struct drm_connector *connector,
4206 int hdisplay, int vdisplay)
4207 {
4208 int i, count, num_modes = 0;
4209 struct drm_display_mode *mode;
4210 struct drm_device *dev = connector->dev;
4211
4212 count = ARRAY_SIZE(drm_dmt_modes);
4213 if (hdisplay < 0)
4214 hdisplay = 0;
4215 if (vdisplay < 0)
4216 vdisplay = 0;
4217
4218 for (i = 0; i < count; i++) {
4219 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4220 if (hdisplay && vdisplay) {
4221 /*
4222 * Only when two are valid, they will be used to check
4223 * whether the mode should be added to the mode list of
4224 * the connector.
4225 */
4226 if (ptr->hdisplay > hdisplay ||
4227 ptr->vdisplay > vdisplay)
4228 continue;
4229 }
4230 if (drm_mode_vrefresh(ptr) > 61)
4231 continue;
4232 mode = drm_mode_duplicate(dev, ptr);
4233 if (mode) {
4234 drm_mode_probed_add(connector, mode);
4235 num_modes++;
4236 }
4237 }
4238 return num_modes;
4239 }
4240 EXPORT_SYMBOL(drm_add_modes_noedid);
4241
4242 /**
4243 * drm_set_preferred_mode - Sets the preferred mode of a connector
4244 * @connector: connector whose mode list should be processed
4245 * @hpref: horizontal resolution of preferred mode
4246 * @vpref: vertical resolution of preferred mode
4247 *
4248 * Marks a mode as preferred if it matches the resolution specified by @hpref
4249 * and @vpref.
4250 */
4251 void drm_set_preferred_mode(struct drm_connector *connector,
4252 int hpref, int vpref)
4253 {
4254 struct drm_display_mode *mode;
4255
4256 list_for_each_entry(mode, &connector->probed_modes, head) {
4257 if (mode->hdisplay == hpref &&
4258 mode->vdisplay == vpref)
4259 mode->type |= DRM_MODE_TYPE_PREFERRED;
4260 }
4261 }
4262 EXPORT_SYMBOL(drm_set_preferred_mode);
4263
4264 /**
4265 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4266 * data from a DRM display mode
4267 * @frame: HDMI AVI infoframe
4268 * @mode: DRM display mode
4269 *
4270 * Return: 0 on success or a negative error code on failure.
4271 */
4272 int
4273 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4274 const struct drm_display_mode *mode)
4275 {
4276 int err;
4277
4278 if (!frame || !mode)
4279 return -EINVAL;
4280
4281 err = hdmi_avi_infoframe_init(frame);
4282 if (err < 0)
4283 return err;
4284
4285 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4286 frame->pixel_repeat = 1;
4287
4288 frame->video_code = drm_match_cea_mode(mode);
4289
4290 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4291
4292 /*
4293 * Populate picture aspect ratio from either
4294 * user input (if specified) or from the CEA mode list.
4295 */
4296 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4297 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4298 frame->picture_aspect = mode->picture_aspect_ratio;
4299 else if (frame->video_code > 0)
4300 frame->picture_aspect = drm_get_cea_aspect_ratio(
4301 frame->video_code);
4302
4303 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4304 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4305
4306 return 0;
4307 }
4308 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4309
4310 static enum hdmi_3d_structure
4311 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4312 {
4313 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4314
4315 switch (layout) {
4316 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4317 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4318 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4319 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4320 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4321 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4322 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4323 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4324 case DRM_MODE_FLAG_3D_L_DEPTH:
4325 return HDMI_3D_STRUCTURE_L_DEPTH;
4326 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4327 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4328 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4329 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4330 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4331 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4332 default:
4333 return HDMI_3D_STRUCTURE_INVALID;
4334 }
4335 }
4336
4337 /**
4338 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4339 * data from a DRM display mode
4340 * @frame: HDMI vendor infoframe
4341 * @mode: DRM display mode
4342 *
4343 * Note that there's is a need to send HDMI vendor infoframes only when using a
4344 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4345 * function will return -EINVAL, error that can be safely ignored.
4346 *
4347 * Return: 0 on success or a negative error code on failure.
4348 */
4349 int
4350 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4351 const struct drm_display_mode *mode)
4352 {
4353 int err;
4354 u32 s3d_flags;
4355 u8 vic;
4356
4357 if (!frame || !mode)
4358 return -EINVAL;
4359
4360 vic = drm_match_hdmi_mode(mode);
4361 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4362
4363 if (!vic && !s3d_flags)
4364 return -EINVAL;
4365
4366 if (vic && s3d_flags)
4367 return -EINVAL;
4368
4369 err = hdmi_vendor_infoframe_init(frame);
4370 if (err < 0)
4371 return err;
4372
4373 if (vic)
4374 frame->vic = vic;
4375 else
4376 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4377
4378 return 0;
4379 }
4380 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4381
4382 static int drm_parse_tiled_block(struct drm_connector *connector,
4383 struct displayid_block *block)
4384 {
4385 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4386 u16 w, h;
4387 u8 tile_v_loc, tile_h_loc;
4388 u8 num_v_tile, num_h_tile;
4389 struct drm_tile_group *tg;
4390
4391 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4392 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4393
4394 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4395 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4396 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4397 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4398
4399 connector->has_tile = true;
4400 if (tile->tile_cap & 0x80)
4401 connector->tile_is_single_monitor = true;
4402
4403 connector->num_h_tile = num_h_tile + 1;
4404 connector->num_v_tile = num_v_tile + 1;
4405 connector->tile_h_loc = tile_h_loc;
4406 connector->tile_v_loc = tile_v_loc;
4407 connector->tile_h_size = w + 1;
4408 connector->tile_v_size = h + 1;
4409
4410 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4411 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4412 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4413 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4414 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4415
4416 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4417 if (!tg) {
4418 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4419 }
4420 if (!tg)
4421 return -ENOMEM;
4422
4423 if (connector->tile_group != tg) {
4424 /* if we haven't got a pointer,
4425 take the reference, drop ref to old tile group */
4426 if (connector->tile_group) {
4427 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4428 }
4429 connector->tile_group = tg;
4430 } else
4431 /* if same tile group, then release the ref we just took. */
4432 drm_mode_put_tile_group(connector->dev, tg);
4433 return 0;
4434 }
4435
4436 static int drm_parse_display_id(struct drm_connector *connector,
4437 u8 *displayid, int length,
4438 bool is_edid_extension)
4439 {
4440 /* if this is an EDID extension the first byte will be 0x70 */
4441 int idx = 0;
4442 struct displayid_block *block;
4443 int ret;
4444
4445 if (is_edid_extension)
4446 idx = 1;
4447
4448 ret = validate_displayid(displayid, length, idx);
4449 if (ret)
4450 return ret;
4451
4452 idx += sizeof(struct displayid_hdr);
4453 while (block = (struct displayid_block *)&displayid[idx],
4454 idx + sizeof(struct displayid_block) <= length &&
4455 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4456 block->num_bytes > 0) {
4457 idx += block->num_bytes + sizeof(struct displayid_block);
4458 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
4459 block->tag, block->rev, block->num_bytes);
4460
4461 switch (block->tag) {
4462 case DATA_BLOCK_TILED_DISPLAY:
4463 ret = drm_parse_tiled_block(connector, block);
4464 if (ret)
4465 return ret;
4466 break;
4467 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4468 /* handled in mode gathering code. */
4469 break;
4470 default:
4471 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
4472 break;
4473 }
4474 }
4475 return 0;
4476 }
4477
4478 static void drm_get_displayid(struct drm_connector *connector,
4479 struct edid *edid)
4480 {
4481 void *displayid = NULL;
4482 int ret;
4483 connector->has_tile = false;
4484 displayid = drm_find_displayid_extension(edid);
4485 if (!displayid) {
4486 /* drop reference to any tile group we had */
4487 goto out_drop_ref;
4488 }
4489
4490 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
4491 if (ret < 0)
4492 goto out_drop_ref;
4493 if (!connector->has_tile)
4494 goto out_drop_ref;
4495 return;
4496 out_drop_ref:
4497 if (connector->tile_group) {
4498 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4499 connector->tile_group = NULL;
4500 }
4501 return;
4502 }
DragonFly BSD