?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
inet6: require RTF_ANNOUNCE to proxy NS
[dragonfly.git] / sys / dev / drm / drm_edid.c
blobc2d6ec66b05eb7f5e4850cfc653ee22362004829
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31 #ifdef __DragonFly__
32 #include "opt_drm.h"
33 #endif
34
35 #include <linux/kernel.h>
36 #include <linux/slab.h>
37 #include <linux/hdmi.h>
38 #include <linux/i2c.h>
39 #include <linux/module.h>
40 #include <linux/vga_switcheroo.h>
41 #include <drm/drmP.h>
42 #include <drm/drm_edid.h>
43 #include <drm/drm_encoder.h>
44 #include <drm/drm_displayid.h>
45 #include <drm/drm_scdc_helper.h>
46
47 #include "drm_crtc_internal.h"
48
49 #define version_greater(edid, maj, min) \
50 (((edid)->version > (maj)) || \
51 ((edid)->version == (maj) && (edid)->revision > (min)))
52
53 #define EDID_EST_TIMINGS 16
54 #define EDID_STD_TIMINGS 8
55 #define EDID_DETAILED_TIMINGS 4
56
57 /*
58 * EDID blocks out in the wild have a variety of bugs, try to collect
59 * them here (note that userspace may work around broken monitors first,
60 * but fixes should make their way here so that the kernel "just works"
61 * on as many displays as possible).
62 */
63
64 /* First detailed mode wrong, use largest 60Hz mode */
65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
66 /* Reported 135MHz pixel clock is too high, needs adjustment */
67 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
68 /* Prefer the largest mode at 75 Hz */
69 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
70 /* Detail timing is in cm not mm */
71 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
72 /* Detailed timing descriptors have bogus size values, so just take the
73 * maximum size and use that.
74 */
75 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
76 /* Monitor forgot to set the first detailed is preferred bit. */
77 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
78 /* use +hsync +vsync for detailed mode */
79 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
80 /* Force reduced-blanking timings for detailed modes */
81 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
82 /* Force 8bpc */
83 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
84 /* Force 12bpc */
85 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
86 /* Force 6bpc */
87 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
88 /* Force 10bpc */
89 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
90 /* Non desktop display (i.e. HMD) */
91 #define EDID_QUIRK_NON_DESKTOP (1 << 12)
92
93 struct detailed_mode_closure {
94 struct drm_connector *connector;
95 struct edid *edid;
96 bool preferred;
97 u32 quirks;
98 int modes;
99 };
100
101 #define LEVEL_DMT 0
102 #define LEVEL_GTF 1
103 #define LEVEL_GTF2 2
104 #define LEVEL_CVT 3
105
106 static const struct edid_quirk {
107 char vendor[4];
108 int product_id;
109 u32 quirks;
110 } edid_quirk_list[] = {
111 /* Acer AL1706 */
112 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
113 /* Acer F51 */
114 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
115 /* Unknown Acer */
116 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
117
118 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
119 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
120
121 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
122 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
123
124 /* Belinea 10 15 55 */
125 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
126 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
127
128 /* Envision Peripherals, Inc. EN-7100e */
129 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
130 /* Envision EN2028 */
131 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
132
133 /* Funai Electronics PM36B */
134 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
135 EDID_QUIRK_DETAILED_IN_CM },
136
137 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
138 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
139
140 /* LG Philips LCD LP154W01-A5 */
141 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
142 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
143
144 /* Philips 107p5 CRT */
145 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
146
147 /* Proview AY765C */
148 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
149
150 /* Samsung SyncMaster 205BW. Note: irony */
151 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
152 /* Samsung SyncMaster 22[5-6]BW */
153 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
154 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
155
156 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
157 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
158
159 /* ViewSonic VA2026w */
160 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
161
162 /* Medion MD 30217 PG */
163 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
164
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
170
171 /* HTC Vive VR Headset */
172 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
173 };
174
175 /*
176 * Autogenerated from the DMT spec.
177 * This table is copied from xfree86/modes/xf86EdidModes.c.
178 */
179 static const struct drm_display_mode drm_dmt_modes[] = {
180 /* 0x01 - 640x350@85Hz */
181 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
182 736, 832, 0, 350, 382, 385, 445, 0,
183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
184 /* 0x02 - 640x400@85Hz */
185 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
186 736, 832, 0, 400, 401, 404, 445, 0,
187 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
188 /* 0x03 - 720x400@85Hz */
189 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
190 828, 936, 0, 400, 401, 404, 446, 0,
191 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
192 /* 0x04 - 640x480@60Hz */
193 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
194 752, 800, 0, 480, 490, 492, 525, 0,
195 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
196 /* 0x05 - 640x480@72Hz */
197 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
198 704, 832, 0, 480, 489, 492, 520, 0,
199 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
200 /* 0x06 - 640x480@75Hz */
201 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
202 720, 840, 0, 480, 481, 484, 500, 0,
203 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
204 /* 0x07 - 640x480@85Hz */
205 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
206 752, 832, 0, 480, 481, 484, 509, 0,
207 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
208 /* 0x08 - 800x600@56Hz */
209 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
210 896, 1024, 0, 600, 601, 603, 625, 0,
211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
212 /* 0x09 - 800x600@60Hz */
213 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
214 968, 1056, 0, 600, 601, 605, 628, 0,
215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
216 /* 0x0a - 800x600@72Hz */
217 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
218 976, 1040, 0, 600, 637, 643, 666, 0,
219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
220 /* 0x0b - 800x600@75Hz */
221 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
222 896, 1056, 0, 600, 601, 604, 625, 0,
223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
224 /* 0x0c - 800x600@85Hz */
225 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
226 896, 1048, 0, 600, 601, 604, 631, 0,
227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
228 /* 0x0d - 800x600@120Hz RB */
229 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
230 880, 960, 0, 600, 603, 607, 636, 0,
231 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
232 /* 0x0e - 848x480@60Hz */
233 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
234 976, 1088, 0, 480, 486, 494, 517, 0,
235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
236 /* 0x0f - 1024x768@43Hz, interlace */
237 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
238 1208, 1264, 0, 768, 768, 776, 817, 0,
239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
240 DRM_MODE_FLAG_INTERLACE) },
241 /* 0x10 - 1024x768@60Hz */
242 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
243 1184, 1344, 0, 768, 771, 777, 806, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x11 - 1024x768@70Hz */
246 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
247 1184, 1328, 0, 768, 771, 777, 806, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x12 - 1024x768@75Hz */
250 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
251 1136, 1312, 0, 768, 769, 772, 800, 0,
252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x13 - 1024x768@85Hz */
254 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
255 1168, 1376, 0, 768, 769, 772, 808, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x14 - 1024x768@120Hz RB */
258 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
259 1104, 1184, 0, 768, 771, 775, 813, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x15 - 1152x864@75Hz */
262 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
263 1344, 1600, 0, 864, 865, 868, 900, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x55 - 1280x720@60Hz */
266 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
267 1430, 1650, 0, 720, 725, 730, 750, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x16 - 1280x768@60Hz RB */
270 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
271 1360, 1440, 0, 768, 771, 778, 790, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
273 /* 0x17 - 1280x768@60Hz */
274 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
275 1472, 1664, 0, 768, 771, 778, 798, 0,
276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x18 - 1280x768@75Hz */
278 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
279 1488, 1696, 0, 768, 771, 778, 805, 0,
280 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x19 - 1280x768@85Hz */
282 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
283 1496, 1712, 0, 768, 771, 778, 809, 0,
284 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x1a - 1280x768@120Hz RB */
286 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
287 1360, 1440, 0, 768, 771, 778, 813, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
289 /* 0x1b - 1280x800@60Hz RB */
290 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
291 1360, 1440, 0, 800, 803, 809, 823, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x1c - 1280x800@60Hz */
294 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
295 1480, 1680, 0, 800, 803, 809, 831, 0,
296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x1d - 1280x800@75Hz */
298 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
299 1488, 1696, 0, 800, 803, 809, 838, 0,
300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x1e - 1280x800@85Hz */
302 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
303 1496, 1712, 0, 800, 803, 809, 843, 0,
304 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 0x1f - 1280x800@120Hz RB */
306 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
307 1360, 1440, 0, 800, 803, 809, 847, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 0x20 - 1280x960@60Hz */
310 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
311 1488, 1800, 0, 960, 961, 964, 1000, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 0x21 - 1280x960@85Hz */
314 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
315 1504, 1728, 0, 960, 961, 964, 1011, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
317 /* 0x22 - 1280x960@120Hz RB */
318 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
319 1360, 1440, 0, 960, 963, 967, 1017, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
321 /* 0x23 - 1280x1024@60Hz */
322 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
323 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x24 - 1280x1024@75Hz */
326 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
327 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
329 /* 0x25 - 1280x1024@85Hz */
330 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
331 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x26 - 1280x1024@120Hz RB */
334 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
335 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
337 /* 0x27 - 1360x768@60Hz */
338 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
339 1536, 1792, 0, 768, 771, 777, 795, 0,
340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x28 - 1360x768@120Hz RB */
342 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
343 1440, 1520, 0, 768, 771, 776, 813, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
345 /* 0x51 - 1366x768@60Hz */
346 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
347 1579, 1792, 0, 768, 771, 774, 798, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
349 /* 0x56 - 1366x768@60Hz */
350 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
351 1436, 1500, 0, 768, 769, 772, 800, 0,
352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x29 - 1400x1050@60Hz RB */
354 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
355 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
356 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
357 /* 0x2a - 1400x1050@60Hz */
358 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
359 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x2b - 1400x1050@75Hz */
362 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
363 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
364 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
365 /* 0x2c - 1400x1050@85Hz */
366 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
367 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
368 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x2d - 1400x1050@120Hz RB */
370 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
371 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
373 /* 0x2e - 1440x900@60Hz RB */
374 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
375 1520, 1600, 0, 900, 903, 909, 926, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
377 /* 0x2f - 1440x900@60Hz */
378 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
379 1672, 1904, 0, 900, 903, 909, 934, 0,
380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x30 - 1440x900@75Hz */
382 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
383 1688, 1936, 0, 900, 903, 909, 942, 0,
384 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x31 - 1440x900@85Hz */
386 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
387 1696, 1952, 0, 900, 903, 909, 948, 0,
388 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x32 - 1440x900@120Hz RB */
390 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
391 1520, 1600, 0, 900, 903, 909, 953, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
393 /* 0x53 - 1600x900@60Hz */
394 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
395 1704, 1800, 0, 900, 901, 904, 1000, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
397 /* 0x33 - 1600x1200@60Hz */
398 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
399 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x34 - 1600x1200@65Hz */
402 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
403 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x35 - 1600x1200@70Hz */
406 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
407 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x36 - 1600x1200@75Hz */
410 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
411 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
413 /* 0x37 - 1600x1200@85Hz */
414 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
415 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x38 - 1600x1200@120Hz RB */
418 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
419 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
421 /* 0x39 - 1680x1050@60Hz RB */
422 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
423 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
425 /* 0x3a - 1680x1050@60Hz */
426 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
427 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x3b - 1680x1050@75Hz */
430 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
431 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x3c - 1680x1050@85Hz */
434 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
435 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
437 /* 0x3d - 1680x1050@120Hz RB */
438 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
439 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 0x3e - 1792x1344@60Hz */
442 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
443 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
445 /* 0x3f - 1792x1344@75Hz */
446 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
447 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x40 - 1792x1344@120Hz RB */
450 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
451 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
453 /* 0x41 - 1856x1392@60Hz */
454 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
455 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x42 - 1856x1392@75Hz */
458 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
459 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
461 /* 0x43 - 1856x1392@120Hz RB */
462 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
463 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
465 /* 0x52 - 1920x1080@60Hz */
466 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
467 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
469 /* 0x44 - 1920x1200@60Hz RB */
470 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
471 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
473 /* 0x45 - 1920x1200@60Hz */
474 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
475 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
476 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x46 - 1920x1200@75Hz */
478 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
479 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
481 /* 0x47 - 1920x1200@85Hz */
482 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
483 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x48 - 1920x1200@120Hz RB */
486 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
487 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
489 /* 0x49 - 1920x1440@60Hz */
490 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
491 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x4a - 1920x1440@75Hz */
494 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
495 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
497 /* 0x4b - 1920x1440@120Hz RB */
498 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
499 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x54 - 2048x1152@60Hz */
502 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
503 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
505 /* 0x4c - 2560x1600@60Hz RB */
506 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
507 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
509 /* 0x4d - 2560x1600@60Hz */
510 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
511 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
513 /* 0x4e - 2560x1600@75Hz */
514 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
515 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
516 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
517 /* 0x4f - 2560x1600@85Hz */
518 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
519 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
521 /* 0x50 - 2560x1600@120Hz RB */
522 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
523 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
525 /* 0x57 - 4096x2160@60Hz RB */
526 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
527 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
529 /* 0x58 - 4096x2160@59.94Hz RB */
530 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
531 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
533 };
534
535 /*
536 * These more or less come from the DMT spec. The 720x400 modes are
537 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
538 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
539 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
540 * mode.
541 *
542 * The DMT modes have been fact-checked; the rest are mild guesses.
543 */
544 static const struct drm_display_mode edid_est_modes[] = {
545 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
546 968, 1056, 0, 600, 601, 605, 628, 0,
547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
548 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
549 896, 1024, 0, 600, 601, 603, 625, 0,
550 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
551 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
552 720, 840, 0, 480, 481, 484, 500, 0,
553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
554 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
555 704, 832, 0, 480, 489, 492, 520, 0,
556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
557 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
558 768, 864, 0, 480, 483, 486, 525, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
560 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
561 752, 800, 0, 480, 490, 492, 525, 0,
562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
563 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
564 846, 900, 0, 400, 421, 423, 449, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
566 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
567 846, 900, 0, 400, 412, 414, 449, 0,
568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
569 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
570 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
572 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
573 1136, 1312, 0, 768, 769, 772, 800, 0,
574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
575 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
576 1184, 1328, 0, 768, 771, 777, 806, 0,
577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
578 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
579 1184, 1344, 0, 768, 771, 777, 806, 0,
580 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
581 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
582 1208, 1264, 0, 768, 768, 776, 817, 0,
583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
584 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
585 928, 1152, 0, 624, 625, 628, 667, 0,
586 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
587 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
588 896, 1056, 0, 600, 601, 604, 625, 0,
589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
591 976, 1040, 0, 600, 637, 643, 666, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
593 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
594 1344, 1600, 0, 864, 865, 868, 900, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
596 };
597
598 struct minimode {
599 short w;
600 short h;
601 short r;
602 short rb;
603 };
604
605 static const struct minimode est3_modes[] = {
606 /* byte 6 */
607 { 640, 350, 85, 0 },
608 { 640, 400, 85, 0 },
609 { 720, 400, 85, 0 },
610 { 640, 480, 85, 0 },
611 { 848, 480, 60, 0 },
612 { 800, 600, 85, 0 },
613 { 1024, 768, 85, 0 },
614 { 1152, 864, 75, 0 },
615 /* byte 7 */
616 { 1280, 768, 60, 1 },
617 { 1280, 768, 60, 0 },
618 { 1280, 768, 75, 0 },
619 { 1280, 768, 85, 0 },
620 { 1280, 960, 60, 0 },
621 { 1280, 960, 85, 0 },
622 { 1280, 1024, 60, 0 },
623 { 1280, 1024, 85, 0 },
624 /* byte 8 */
625 { 1360, 768, 60, 0 },
626 { 1440, 900, 60, 1 },
627 { 1440, 900, 60, 0 },
628 { 1440, 900, 75, 0 },
629 { 1440, 900, 85, 0 },
630 { 1400, 1050, 60, 1 },
631 { 1400, 1050, 60, 0 },
632 { 1400, 1050, 75, 0 },
633 /* byte 9 */
634 { 1400, 1050, 85, 0 },
635 { 1680, 1050, 60, 1 },
636 { 1680, 1050, 60, 0 },
637 { 1680, 1050, 75, 0 },
638 { 1680, 1050, 85, 0 },
639 { 1600, 1200, 60, 0 },
640 { 1600, 1200, 65, 0 },
641 { 1600, 1200, 70, 0 },
642 /* byte 10 */
643 { 1600, 1200, 75, 0 },
644 { 1600, 1200, 85, 0 },
645 { 1792, 1344, 60, 0 },
646 { 1792, 1344, 75, 0 },
647 { 1856, 1392, 60, 0 },
648 { 1856, 1392, 75, 0 },
649 { 1920, 1200, 60, 1 },
650 { 1920, 1200, 60, 0 },
651 /* byte 11 */
652 { 1920, 1200, 75, 0 },
653 { 1920, 1200, 85, 0 },
654 { 1920, 1440, 60, 0 },
655 { 1920, 1440, 75, 0 },
656 };
657
658 static const struct minimode extra_modes[] = {
659 { 1024, 576, 60, 0 },
660 { 1366, 768, 60, 0 },
661 { 1600, 900, 60, 0 },
662 { 1680, 945, 60, 0 },
663 { 1920, 1080, 60, 0 },
664 { 2048, 1152, 60, 0 },
665 { 2048, 1536, 60, 0 },
666 };
667
668 /*
669 * Probably taken from CEA-861 spec.
670 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
671 *
672 * Index using the VIC.
673 */
674 static const struct drm_display_mode edid_cea_modes[] = {
675 /* 0 - dummy, VICs start at 1 */
676 { },
677 /* 1 - 640x480@60Hz */
678 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
679 752, 800, 0, 480, 490, 492, 525, 0,
680 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
681 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
682 /* 2 - 720x480@60Hz */
683 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
684 798, 858, 0, 480, 489, 495, 525, 0,
685 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
687 /* 3 - 720x480@60Hz */
688 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
689 798, 858, 0, 480, 489, 495, 525, 0,
690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
691 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
692 /* 4 - 1280x720@60Hz */
693 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
694 1430, 1650, 0, 720, 725, 730, 750, 0,
695 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
696 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
697 /* 5 - 1920x1080i@60Hz */
698 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
699 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
700 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
701 DRM_MODE_FLAG_INTERLACE),
702 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
703 /* 6 - 720(1440)x480i@60Hz */
704 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
705 801, 858, 0, 480, 488, 494, 525, 0,
706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
707 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
708 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
709 /* 7 - 720(1440)x480i@60Hz */
710 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
711 801, 858, 0, 480, 488, 494, 525, 0,
712 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
713 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
714 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
715 /* 8 - 720(1440)x240@60Hz */
716 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
717 801, 858, 0, 240, 244, 247, 262, 0,
718 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
719 DRM_MODE_FLAG_DBLCLK),
720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
721 /* 9 - 720(1440)x240@60Hz */
722 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
723 801, 858, 0, 240, 244, 247, 262, 0,
724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
725 DRM_MODE_FLAG_DBLCLK),
726 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
727 /* 10 - 2880x480i@60Hz */
728 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
729 3204, 3432, 0, 480, 488, 494, 525, 0,
730 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
731 DRM_MODE_FLAG_INTERLACE),
732 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
733 /* 11 - 2880x480i@60Hz */
734 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
735 3204, 3432, 0, 480, 488, 494, 525, 0,
736 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
737 DRM_MODE_FLAG_INTERLACE),
738 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
739 /* 12 - 2880x240@60Hz */
740 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
741 3204, 3432, 0, 240, 244, 247, 262, 0,
742 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
743 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
744 /* 13 - 2880x240@60Hz */
745 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
746 3204, 3432, 0, 240, 244, 247, 262, 0,
747 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
748 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
749 /* 14 - 1440x480@60Hz */
750 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
751 1596, 1716, 0, 480, 489, 495, 525, 0,
752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
753 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
754 /* 15 - 1440x480@60Hz */
755 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
756 1596, 1716, 0, 480, 489, 495, 525, 0,
757 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
758 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
759 /* 16 - 1920x1080@60Hz */
760 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
761 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
762 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
763 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
764 /* 17 - 720x576@50Hz */
765 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
766 796, 864, 0, 576, 581, 586, 625, 0,
767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
769 /* 18 - 720x576@50Hz */
770 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
771 796, 864, 0, 576, 581, 586, 625, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
773 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
774 /* 19 - 1280x720@50Hz */
775 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
776 1760, 1980, 0, 720, 725, 730, 750, 0,
777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
778 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 20 - 1920x1080i@50Hz */
780 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
781 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
782 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
783 DRM_MODE_FLAG_INTERLACE),
784 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
785 /* 21 - 720(1440)x576i@50Hz */
786 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
787 795, 864, 0, 576, 580, 586, 625, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
790 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
791 /* 22 - 720(1440)x576i@50Hz */
792 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
793 795, 864, 0, 576, 580, 586, 625, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
796 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
797 /* 23 - 720(1440)x288@50Hz */
798 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
799 795, 864, 0, 288, 290, 293, 312, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
801 DRM_MODE_FLAG_DBLCLK),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
803 /* 24 - 720(1440)x288@50Hz */
804 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
805 795, 864, 0, 288, 290, 293, 312, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
807 DRM_MODE_FLAG_DBLCLK),
808 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
809 /* 25 - 2880x576i@50Hz */
810 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
811 3180, 3456, 0, 576, 580, 586, 625, 0,
812 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
813 DRM_MODE_FLAG_INTERLACE),
814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
815 /* 26 - 2880x576i@50Hz */
816 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
817 3180, 3456, 0, 576, 580, 586, 625, 0,
818 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
819 DRM_MODE_FLAG_INTERLACE),
820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 27 - 2880x288@50Hz */
822 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
823 3180, 3456, 0, 288, 290, 293, 312, 0,
824 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
825 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
826 /* 28 - 2880x288@50Hz */
827 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
828 3180, 3456, 0, 288, 290, 293, 312, 0,
829 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
830 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
831 /* 29 - 1440x576@50Hz */
832 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
833 1592, 1728, 0, 576, 581, 586, 625, 0,
834 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
835 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
836 /* 30 - 1440x576@50Hz */
837 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
838 1592, 1728, 0, 576, 581, 586, 625, 0,
839 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
840 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
841 /* 31 - 1920x1080@50Hz */
842 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
843 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
845 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
846 /* 32 - 1920x1080@24Hz */
847 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
848 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
850 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 33 - 1920x1080@25Hz */
852 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
853 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
855 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
856 /* 34 - 1920x1080@30Hz */
857 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
858 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
859 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
860 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
861 /* 35 - 2880x480@60Hz */
862 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
863 3192, 3432, 0, 480, 489, 495, 525, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
865 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
866 /* 36 - 2880x480@60Hz */
867 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
868 3192, 3432, 0, 480, 489, 495, 525, 0,
869 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
870 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
871 /* 37 - 2880x576@50Hz */
872 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
873 3184, 3456, 0, 576, 581, 586, 625, 0,
874 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
875 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
876 /* 38 - 2880x576@50Hz */
877 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
878 3184, 3456, 0, 576, 581, 586, 625, 0,
879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
880 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
881 /* 39 - 1920x1080i@50Hz */
882 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
883 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
884 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
885 DRM_MODE_FLAG_INTERLACE),
886 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
887 /* 40 - 1920x1080i@100Hz */
888 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
889 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
890 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
891 DRM_MODE_FLAG_INTERLACE),
892 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 41 - 1280x720@100Hz */
894 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
895 1760, 1980, 0, 720, 725, 730, 750, 0,
896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
897 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 42 - 720x576@100Hz */
899 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
900 796, 864, 0, 576, 581, 586, 625, 0,
901 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
902 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
903 /* 43 - 720x576@100Hz */
904 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
905 796, 864, 0, 576, 581, 586, 625, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
907 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
908 /* 44 - 720(1440)x576i@100Hz */
909 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
910 795, 864, 0, 576, 580, 586, 625, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
912 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
913 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
914 /* 45 - 720(1440)x576i@100Hz */
915 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
916 795, 864, 0, 576, 580, 586, 625, 0,
917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
918 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
919 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 46 - 1920x1080i@120Hz */
921 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
922 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
924 DRM_MODE_FLAG_INTERLACE),
925 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
926 /* 47 - 1280x720@120Hz */
927 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
928 1430, 1650, 0, 720, 725, 730, 750, 0,
929 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
930 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
931 /* 48 - 720x480@120Hz */
932 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
933 798, 858, 0, 480, 489, 495, 525, 0,
934 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
935 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
936 /* 49 - 720x480@120Hz */
937 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
938 798, 858, 0, 480, 489, 495, 525, 0,
939 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
940 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
941 /* 50 - 720(1440)x480i@120Hz */
942 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
943 801, 858, 0, 480, 488, 494, 525, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
946 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
947 /* 51 - 720(1440)x480i@120Hz */
948 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
949 801, 858, 0, 480, 488, 494, 525, 0,
950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
951 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
952 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
953 /* 52 - 720x576@200Hz */
954 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
955 796, 864, 0, 576, 581, 586, 625, 0,
956 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
957 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
958 /* 53 - 720x576@200Hz */
959 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
960 796, 864, 0, 576, 581, 586, 625, 0,
961 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
962 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
963 /* 54 - 720(1440)x576i@200Hz */
964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
965 795, 864, 0, 576, 580, 586, 625, 0,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
968 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
969 /* 55 - 720(1440)x576i@200Hz */
970 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
971 795, 864, 0, 576, 580, 586, 625, 0,
972 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
973 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
974 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
975 /* 56 - 720x480@240Hz */
976 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
977 798, 858, 0, 480, 489, 495, 525, 0,
978 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
979 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
980 /* 57 - 720x480@240Hz */
981 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
982 798, 858, 0, 480, 489, 495, 525, 0,
983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
984 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
985 /* 58 - 720(1440)x480i@240Hz */
986 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
987 801, 858, 0, 480, 488, 494, 525, 0,
988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
989 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
990 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
991 /* 59 - 720(1440)x480i@240Hz */
992 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
993 801, 858, 0, 480, 488, 494, 525, 0,
994 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
995 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
996 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
997 /* 60 - 1280x720@24Hz */
998 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
999 3080, 3300, 0, 720, 725, 730, 750, 0,
1000 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1001 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1002 /* 61 - 1280x720@25Hz */
1003 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1004 3740, 3960, 0, 720, 725, 730, 750, 0,
1005 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1006 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1007 /* 62 - 1280x720@30Hz */
1008 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1009 3080, 3300, 0, 720, 725, 730, 750, 0,
1010 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1011 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1012 /* 63 - 1920x1080@120Hz */
1013 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1014 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1015 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1016 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 64 - 1920x1080@100Hz */
1018 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1019 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1020 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1021 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1022 /* 65 - 1280x720@24Hz */
1023 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1024 3080, 3300, 0, 720, 725, 730, 750, 0,
1025 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1026 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1027 /* 66 - 1280x720@25Hz */
1028 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1029 3740, 3960, 0, 720, 725, 730, 750, 0,
1030 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1031 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1032 /* 67 - 1280x720@30Hz */
1033 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1034 3080, 3300, 0, 720, 725, 730, 750, 0,
1035 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1036 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1037 /* 68 - 1280x720@50Hz */
1038 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1039 1760, 1980, 0, 720, 725, 730, 750, 0,
1040 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1041 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1042 /* 69 - 1280x720@60Hz */
1043 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1044 1430, 1650, 0, 720, 725, 730, 750, 0,
1045 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1046 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1047 /* 70 - 1280x720@100Hz */
1048 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1049 1760, 1980, 0, 720, 725, 730, 750, 0,
1050 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1051 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1052 /* 71 - 1280x720@120Hz */
1053 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1054 1430, 1650, 0, 720, 725, 730, 750, 0,
1055 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1056 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1057 /* 72 - 1920x1080@24Hz */
1058 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1059 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1060 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1061 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1062 /* 73 - 1920x1080@25Hz */
1063 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1064 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1065 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1066 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1067 /* 74 - 1920x1080@30Hz */
1068 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1069 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1070 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1071 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1072 /* 75 - 1920x1080@50Hz */
1073 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1074 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1075 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1076 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1077 /* 76 - 1920x1080@60Hz */
1078 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1079 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1081 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1082 /* 77 - 1920x1080@100Hz */
1083 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1084 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1085 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1086 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1087 /* 78 - 1920x1080@120Hz */
1088 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1089 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1090 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1091 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1092 /* 79 - 1680x720@24Hz */
1093 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1094 3080, 3300, 0, 720, 725, 730, 750, 0,
1095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1096 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1097 /* 80 - 1680x720@25Hz */
1098 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1099 2948, 3168, 0, 720, 725, 730, 750, 0,
1100 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1101 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1102 /* 81 - 1680x720@30Hz */
1103 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1104 2420, 2640, 0, 720, 725, 730, 750, 0,
1105 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1106 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1107 /* 82 - 1680x720@50Hz */
1108 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1109 1980, 2200, 0, 720, 725, 730, 750, 0,
1110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1111 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1112 /* 83 - 1680x720@60Hz */
1113 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1114 1980, 2200, 0, 720, 725, 730, 750, 0,
1115 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1116 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1117 /* 84 - 1680x720@100Hz */
1118 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1119 1780, 2000, 0, 720, 725, 730, 825, 0,
1120 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1121 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1122 /* 85 - 1680x720@120Hz */
1123 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1124 1780, 2000, 0, 720, 725, 730, 825, 0,
1125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1126 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1127 /* 86 - 2560x1080@24Hz */
1128 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1129 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1130 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1131 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1132 /* 87 - 2560x1080@25Hz */
1133 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1134 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1135 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1136 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1137 /* 88 - 2560x1080@30Hz */
1138 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1139 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1140 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1141 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1142 /* 89 - 2560x1080@50Hz */
1143 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1144 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1145 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1146 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1147 /* 90 - 2560x1080@60Hz */
1148 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1149 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1150 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1151 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1152 /* 91 - 2560x1080@100Hz */
1153 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1154 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1156 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1157 /* 92 - 2560x1080@120Hz */
1158 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1159 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1160 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1161 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1162 /* 93 - 3840x2160p@24Hz 16:9 */
1163 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1164 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1165 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1166 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1167 /* 94 - 3840x2160p@25Hz 16:9 */
1168 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1169 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1170 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1171 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1172 /* 95 - 3840x2160p@30Hz 16:9 */
1173 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1174 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1175 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1176 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1177 /* 96 - 3840x2160p@50Hz 16:9 */
1178 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1179 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1181 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1182 /* 97 - 3840x2160p@60Hz 16:9 */
1183 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1184 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1186 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1187 /* 98 - 4096x2160p@24Hz 256:135 */
1188 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1189 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1190 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1191 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1192 /* 99 - 4096x2160p@25Hz 256:135 */
1193 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1194 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1196 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1197 /* 100 - 4096x2160p@30Hz 256:135 */
1198 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1199 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1200 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1201 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1202 /* 101 - 4096x2160p@50Hz 256:135 */
1203 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1204 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1206 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1207 /* 102 - 4096x2160p@60Hz 256:135 */
1208 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1209 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1210 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1211 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1212 /* 103 - 3840x2160p@24Hz 64:27 */
1213 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1214 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1215 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1216 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1217 /* 104 - 3840x2160p@25Hz 64:27 */
1218 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1219 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1221 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1222 /* 105 - 3840x2160p@30Hz 64:27 */
1223 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1224 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1226 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1227 /* 106 - 3840x2160p@50Hz 64:27 */
1228 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1229 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1231 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1232 /* 107 - 3840x2160p@60Hz 64:27 */
1233 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1234 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1236 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1237 };
1238
1239 /*
1240 * HDMI 1.4 4k modes. Index using the VIC.
1241 */
1242 static const struct drm_display_mode edid_4k_modes[] = {
1243 /* 0 - dummy, VICs start at 1 */
1244 { },
1245 /* 1 - 3840x2160@30Hz */
1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1247 3840, 4016, 4104, 4400, 0,
1248 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .vrefresh = 30, },
1251 /* 2 - 3840x2160@25Hz */
1252 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1253 3840, 4896, 4984, 5280, 0,
1254 2160, 2168, 2178, 2250, 0,
1255 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1256 .vrefresh = 25, },
1257 /* 3 - 3840x2160@24Hz */
1258 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1259 3840, 5116, 5204, 5500, 0,
1260 2160, 2168, 2178, 2250, 0,
1261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1262 .vrefresh = 24, },
1263 /* 4 - 4096x2160@24Hz (SMPTE) */
1264 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1265 4096, 5116, 5204, 5500, 0,
1266 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .vrefresh = 24, },
1269 };
1270
1271 /*** DDC fetch and block validation ***/
1272
1273 static const u8 edid_header[] = {
1274 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1275 };
1276
1277 /**
1278 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1279 * @raw_edid: pointer to raw base EDID block
1280 *
1281 * Sanity check the header of the base EDID block.
1282 *
1283 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1284 */
1285 int drm_edid_header_is_valid(const u8 *raw_edid)
1286 {
1287 int i, score = 0;
1288
1289 for (i = 0; i < sizeof(edid_header); i++)
1290 if (raw_edid[i] == edid_header[i])
1291 score++;
1292
1293 return score;
1294 }
1295 EXPORT_SYMBOL(drm_edid_header_is_valid);
1296
1297 static int edid_fixup __read_mostly = 6;
1298 module_param_named(edid_fixup, edid_fixup, int, 0400);
1299 MODULE_PARM_DESC(edid_fixup,
1300 "Minimum number of valid EDID header bytes (0-8, default 6)");
1301
1302 static void drm_get_displayid(struct drm_connector *connector,
1303 struct edid *edid);
1304
1305 static int drm_edid_block_checksum(const u8 *raw_edid)
1306 {
1307 int i;
1308 u8 csum = 0;
1309 for (i = 0; i < EDID_LENGTH; i++)
1310 csum += raw_edid[i];
1311
1312 return csum;
1313 }
1314
1315 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1316 {
1317 if (memchr_inv(in_edid, 0, length))
1318 return false;
1319
1320 return true;
1321 }
1322
1323 /**
1324 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1325 * @raw_edid: pointer to raw EDID block
1326 * @block: type of block to validate (0 for base, extension otherwise)
1327 * @print_bad_edid: if true, dump bad EDID blocks to the console
1328 * @edid_corrupt: if true, the header or checksum is invalid
1329 *
1330 * Validate a base or extension EDID block and optionally dump bad blocks to
1331 * the console.
1332 *
1333 * Return: True if the block is valid, false otherwise.
1334 */
1335 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1336 bool *edid_corrupt)
1337 {
1338 u8 csum;
1339 struct edid *edid = (struct edid *)raw_edid;
1340
1341 if (WARN_ON(!raw_edid))
1342 return false;
1343
1344 if (edid_fixup > 8 || edid_fixup < 0)
1345 edid_fixup = 6;
1346
1347 if (block == 0) {
1348 int score = drm_edid_header_is_valid(raw_edid);
1349 if (score == 8) {
1350 if (edid_corrupt)
1351 *edid_corrupt = false;
1352 } else if (score >= edid_fixup) {
1353 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1354 * The corrupt flag needs to be set here otherwise, the
1355 * fix-up code here will correct the problem, the
1356 * checksum is correct and the test fails
1357 */
1358 if (edid_corrupt)
1359 *edid_corrupt = true;
1360 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1361 memcpy(raw_edid, edid_header, sizeof(edid_header));
1362 } else {
1363 if (edid_corrupt)
1364 *edid_corrupt = true;
1365 goto bad;
1366 }
1367 }
1368
1369 csum = drm_edid_block_checksum(raw_edid);
1370 if (csum) {
1371 if (edid_corrupt)
1372 *edid_corrupt = true;
1373
1374 /* allow CEA to slide through, switches mangle this */
1375 if (raw_edid[0] == CEA_EXT) {
1376 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1377 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1378 } else {
1379 if (print_bad_edid)
1380 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1381
1382 goto bad;
1383 }
1384 }
1385
1386 /* per-block-type checks */
1387 switch (raw_edid[0]) {
1388 case 0: /* base */
1389 if (edid->version != 1) {
1390 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1391 goto bad;
1392 }
1393
1394 if (edid->revision > 4)
1395 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1396 break;
1397
1398 default:
1399 break;
1400 }
1401
1402 return true;
1403
1404 bad:
1405 if (print_bad_edid) {
1406 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1407 pr_notice("EDID block is all zeroes\n");
1408 } else {
1409 pr_notice("Raw EDID:\n");
1410 print_hex_dump(KERN_NOTICE,
1411 " \t", DUMP_PREFIX_NONE, 16, 1,
1412 raw_edid, EDID_LENGTH, false);
1413 }
1414 }
1415 return false;
1416 }
1417 EXPORT_SYMBOL(drm_edid_block_valid);
1418
1419 /**
1420 * drm_edid_is_valid - sanity check EDID data
1421 * @edid: EDID data
1422 *
1423 * Sanity-check an entire EDID record (including extensions)
1424 *
1425 * Return: True if the EDID data is valid, false otherwise.
1426 */
1427 bool drm_edid_is_valid(struct edid *edid)
1428 {
1429 int i;
1430 u8 *raw = (u8 *)edid;
1431
1432 if (!edid)
1433 return false;
1434
1435 for (i = 0; i <= edid->extensions; i++)
1436 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1437 return false;
1438
1439 return true;
1440 }
1441 EXPORT_SYMBOL(drm_edid_is_valid);
1442
1443 #define DDC_SEGMENT_ADDR 0x30
1444 /**
1445 * drm_do_probe_ddc_edid() - get EDID information via I2C
1446 * @data: I2C device adapter
1447 * @buf: EDID data buffer to be filled
1448 * @block: 128 byte EDID block to start fetching from
1449 * @len: EDID data buffer length to fetch
1450 *
1451 * Try to fetch EDID information by calling I2C driver functions.
1452 *
1453 * Return: 0 on success or -1 on failure.
1454 */
1455 static int
1456 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1457 {
1458 struct i2c_adapter *adapter = data;
1459 unsigned char start = block * EDID_LENGTH;
1460 unsigned char segment = block >> 1;
1461 unsigned char xfers = segment ? 3 : 2;
1462 int ret, retries = 5;
1463
1464 /*
1465 * The core I2C driver will automatically retry the transfer if the
1466 * adapter reports EAGAIN. However, we find that bit-banging transfers
1467 * are susceptible to errors under a heavily loaded machine and
1468 * generate spurious NAKs and timeouts. Retrying the transfer
1469 * of the individual block a few times seems to overcome this.
1470 */
1471 do {
1472 struct i2c_msg msgs[] = {
1473 {
1474 .addr = DDC_SEGMENT_ADDR,
1475 .flags = 0,
1476 .len = 1,
1477 .buf = &segment,
1478 }, {
1479 .addr = DDC_ADDR,
1480 .flags = 0,
1481 .len = 1,
1482 .buf = &start,
1483 }, {
1484 .addr = DDC_ADDR,
1485 .flags = I2C_M_RD,
1486 .len = len,
1487 .buf = buf,
1488 }
1489 };
1490
1491 /*
1492 * Avoid sending the segment addr to not upset non-compliant
1493 * DDC monitors.
1494 */
1495 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1496
1497 if (ret == -ENXIO) {
1498 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1499 adapter->name);
1500 break;
1501 }
1502 } while (ret != xfers && --retries);
1503
1504 return ret == xfers ? 0 : -1;
1505 }
1506
1507 static void connector_bad_edid(struct drm_connector *connector,
1508 u8 *edid, int num_blocks)
1509 {
1510 int i;
1511
1512 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1513 return;
1514
1515 dev_warn(connector->dev->dev,
1516 "%s: EDID is invalid:\n",
1517 connector->name);
1518 for (i = 0; i < num_blocks; i++) {
1519 u8 *block = edid + i * EDID_LENGTH;
1520 char prefix[20];
1521
1522 if (drm_edid_is_zero(block, EDID_LENGTH))
1523 ksprintf(prefix, "\t[%02x] ZERO ", i);
1524 else if (!drm_edid_block_valid(block, i, false, NULL))
1525 ksprintf(prefix, "\t[%02x] BAD ", i);
1526 else
1527 ksprintf(prefix, "\t[%02x] GOOD ", i);
1528
1529 print_hex_dump(KERN_WARNING,
1530 prefix, DUMP_PREFIX_NONE, 16, 1,
1531 block, EDID_LENGTH, false);
1532 }
1533 }
1534
1535 /**
1536 * drm_do_get_edid - get EDID data using a custom EDID block read function
1537 * @connector: connector we're probing
1538 * @get_edid_block: EDID block read function
1539 * @data: private data passed to the block read function
1540 *
1541 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1542 * exposes a different interface to read EDID blocks this function can be used
1543 * to get EDID data using a custom block read function.
1544 *
1545 * As in the general case the DDC bus is accessible by the kernel at the I2C
1546 * level, drivers must make all reasonable efforts to expose it as an I2C
1547 * adapter and use drm_get_edid() instead of abusing this function.
1548 *
1549 * The EDID may be overridden using debugfs override_edid or firmare EDID
1550 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1551 * order. Having either of them bypasses actual EDID reads.
1552 *
1553 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1554 */
1555 struct edid *drm_do_get_edid(struct drm_connector *connector,
1556 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1557 size_t len),
1558 void *data)
1559 {
1560 int i, j = 0, valid_extensions = 0;
1561 u8 *edid, *new;
1562 struct edid *override = NULL;
1563
1564 if (connector->override_edid)
1565 override = drm_edid_duplicate((const struct edid *)
1566 connector->edid_blob_ptr->data);
1567
1568 if (!override)
1569 override = drm_load_edid_firmware(connector);
1570
1571 if (!IS_ERR_OR_NULL(override))
1572 return override;
1573
1574 if ((edid = kmalloc(EDID_LENGTH, M_DRM, GFP_KERNEL)) == NULL)
1575 return NULL;
1576
1577 /* base block fetch */
1578 for (i = 0; i < 4; i++) {
1579 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1580 goto out;
1581 if (drm_edid_block_valid(edid, 0, false,
1582 &connector->edid_corrupt))
1583 break;
1584 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1585 connector->null_edid_counter++;
1586 goto carp;
1587 }
1588 }
1589 if (i == 4)
1590 goto carp;
1591
1592 /* if there's no extensions, we're done */
1593 valid_extensions = edid[0x7e];
1594 if (valid_extensions == 0)
1595 return (struct edid *)edid;
1596
1597 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, M_DRM,
1598 GFP_KERNEL);
1599 if (!new)
1600 goto out;
1601 edid = new;
1602
1603 for (j = 1; j <= edid[0x7e]; j++) {
1604 u8 *block = edid + j * EDID_LENGTH;
1605
1606 for (i = 0; i < 4; i++) {
1607 if (get_edid_block(data, block, j, EDID_LENGTH))
1608 goto out;
1609 if (drm_edid_block_valid(block, j, false, NULL))
1610 break;
1611 }
1612
1613 if (i == 4)
1614 valid_extensions--;
1615 }
1616
1617 if (valid_extensions != edid[0x7e]) {
1618 u8 *base;
1619
1620 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1621
1622 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1623 edid[0x7e] = valid_extensions;
1624
1625 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, M_DRM,
1626 GFP_KERNEL);
1627 if (!new)
1628 goto out;
1629
1630 base = new;
1631 for (i = 0; i <= edid[0x7e]; i++) {
1632 u8 *block = edid + i * EDID_LENGTH;
1633
1634 if (!drm_edid_block_valid(block, i, false, NULL))
1635 continue;
1636
1637 memcpy(base, block, EDID_LENGTH);
1638 base += EDID_LENGTH;
1639 }
1640
1641 kfree(edid);
1642 edid = new;
1643 }
1644
1645 return (struct edid *)edid;
1646
1647 carp:
1648 connector_bad_edid(connector, edid, 1);
1649 out:
1650 kfree(edid);
1651 return NULL;
1652 }
1653
1654 /**
1655 * drm_probe_ddc() - probe DDC presence
1656 * @adapter: I2C adapter to probe
1657 *
1658 * Return: True on success, false on failure.
1659 */
1660 bool
1661 drm_probe_ddc(struct i2c_adapter *adapter)
1662 {
1663 unsigned char out;
1664
1665 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1666 }
1667 EXPORT_SYMBOL(drm_probe_ddc);
1668
1669 /**
1670 * drm_get_edid - get EDID data, if available
1671 * @connector: connector we're probing
1672 * @adapter: I2C adapter to use for DDC
1673 *
1674 * Poke the given I2C channel to grab EDID data if possible. If found,
1675 * attach it to the connector.
1676 *
1677 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1678 */
1679 struct edid *drm_get_edid(struct drm_connector *connector,
1680 struct i2c_adapter *adapter)
1681 {
1682 struct edid *edid;
1683
1684 if (connector->force == DRM_FORCE_OFF)
1685 return NULL;
1686
1687 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1688 return NULL;
1689
1690 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1691 if (edid)
1692 drm_get_displayid(connector, edid);
1693 return edid;
1694 }
1695 EXPORT_SYMBOL(drm_get_edid);
1696
1697 /**
1698 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1699 * @connector: connector we're probing
1700 * @adapter: I2C adapter to use for DDC
1701 *
1702 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1703 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1704 * switch DDC to the GPU which is retrieving EDID.
1705 *
1706 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1707 */
1708 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1709 struct i2c_adapter *adapter)
1710 {
1711 struct pci_dev *pdev = connector->dev->pdev;
1712 struct edid *edid;
1713
1714 vga_switcheroo_lock_ddc(pdev);
1715 edid = drm_get_edid(connector, adapter);
1716 vga_switcheroo_unlock_ddc(pdev);
1717
1718 return edid;
1719 }
1720 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1721
1722 /**
1723 * drm_edid_duplicate - duplicate an EDID and the extensions
1724 * @edid: EDID to duplicate
1725 *
1726 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1727 */
1728 struct edid *drm_edid_duplicate(const struct edid *edid)
1729 {
1730 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1731 }
1732 EXPORT_SYMBOL(drm_edid_duplicate);
1733
1734 /*** EDID parsing ***/
1735
1736 /**
1737 * edid_vendor - match a string against EDID's obfuscated vendor field
1738 * @edid: EDID to match
1739 * @vendor: vendor string
1740 *
1741 * Returns true if @vendor is in @edid, false otherwise
1742 */
1743 static bool edid_vendor(const struct edid *edid, const char *vendor)
1744 {
1745 char edid_vendor[3];
1746
1747 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1748 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1749 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1750 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1751
1752 return !strncmp(edid_vendor, vendor, 3);
1753 }
1754
1755 /**
1756 * edid_get_quirks - return quirk flags for a given EDID
1757 * @edid: EDID to process
1758 *
1759 * This tells subsequent routines what fixes they need to apply.
1760 */
1761 static u32 edid_get_quirks(const struct edid *edid)
1762 {
1763 const struct edid_quirk *quirk;
1764 int i;
1765
1766 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1767 quirk = &edid_quirk_list[i];
1768
1769 if (edid_vendor(edid, quirk->vendor) &&
1770 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1771 return quirk->quirks;
1772 }
1773
1774 return 0;
1775 }
1776
1777 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1778 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1779
1780 /**
1781 * edid_fixup_preferred - set preferred modes based on quirk list
1782 * @connector: has mode list to fix up
1783 * @quirks: quirks list
1784 *
1785 * Walk the mode list for @connector, clearing the preferred status
1786 * on existing modes and setting it anew for the right mode ala @quirks.
1787 */
1788 static void edid_fixup_preferred(struct drm_connector *connector,
1789 u32 quirks)
1790 {
1791 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1792 int target_refresh = 0;
1793 int cur_vrefresh, preferred_vrefresh;
1794
1795 if (list_empty(&connector->probed_modes))
1796 return;
1797
1798 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1799 target_refresh = 60;
1800 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1801 target_refresh = 75;
1802
1803 preferred_mode = list_first_entry(&connector->probed_modes,
1804 struct drm_display_mode, head);
1805
1806 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1807 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1808
1809 if (cur_mode == preferred_mode)
1810 continue;
1811
1812 /* Largest mode is preferred */
1813 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1814 preferred_mode = cur_mode;
1815
1816 cur_vrefresh = cur_mode->vrefresh ?
1817 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1818 preferred_vrefresh = preferred_mode->vrefresh ?
1819 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1820 /* At a given size, try to get closest to target refresh */
1821 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1822 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1823 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1824 preferred_mode = cur_mode;
1825 }
1826 }
1827
1828 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1829 }
1830
1831 static bool
1832 mode_is_rb(const struct drm_display_mode *mode)
1833 {
1834 return (mode->htotal - mode->hdisplay == 160) &&
1835 (mode->hsync_end - mode->hdisplay == 80) &&
1836 (mode->hsync_end - mode->hsync_start == 32) &&
1837 (mode->vsync_start - mode->vdisplay == 3);
1838 }
1839
1840 /*
1841 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1842 * @dev: Device to duplicate against
1843 * @hsize: Mode width
1844 * @vsize: Mode height
1845 * @fresh: Mode refresh rate
1846 * @rb: Mode reduced-blanking-ness
1847 *
1848 * Walk the DMT mode list looking for a match for the given parameters.
1849 *
1850 * Return: A newly allocated copy of the mode, or NULL if not found.
1851 */
1852 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1853 int hsize, int vsize, int fresh,
1854 bool rb)
1855 {
1856 int i;
1857
1858 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1859 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1860 if (hsize != ptr->hdisplay)
1861 continue;
1862 if (vsize != ptr->vdisplay)
1863 continue;
1864 if (fresh != drm_mode_vrefresh(ptr))
1865 continue;
1866 if (rb != mode_is_rb(ptr))
1867 continue;
1868
1869 return drm_mode_duplicate(dev, ptr);
1870 }
1871
1872 return NULL;
1873 }
1874 EXPORT_SYMBOL(drm_mode_find_dmt);
1875
1876 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1877
1878 static void
1879 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1880 {
1881 int i, n = 0;
1882 u8 d = ext[0x02];
1883 u8 *det_base = ext + d;
1884
1885 n = (127 - d) / 18;
1886 for (i = 0; i < n; i++)
1887 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1888 }
1889
1890 static void
1891 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1892 {
1893 unsigned int i, n = min((int)ext[0x02], 6);
1894 u8 *det_base = ext + 5;
1895
1896 if (ext[0x01] != 1)
1897 return; /* unknown version */
1898
1899 for (i = 0; i < n; i++)
1900 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1901 }
1902
1903 static void
1904 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1905 {
1906 int i;
1907 struct edid *edid = (struct edid *)raw_edid;
1908
1909 if (edid == NULL)
1910 return;
1911
1912 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1913 cb(&(edid->detailed_timings[i]), closure);
1914
1915 for (i = 1; i <= raw_edid[0x7e]; i++) {
1916 u8 *ext = raw_edid + (i * EDID_LENGTH);
1917 switch (*ext) {
1918 case CEA_EXT:
1919 cea_for_each_detailed_block(ext, cb, closure);
1920 break;
1921 case VTB_EXT:
1922 vtb_for_each_detailed_block(ext, cb, closure);
1923 break;
1924 default:
1925 break;
1926 }
1927 }
1928 }
1929
1930 static void
1931 is_rb(struct detailed_timing *t, void *data)
1932 {
1933 u8 *r = (u8 *)t;
1934 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1935 if (r[15] & 0x10)
1936 *(bool *)data = true;
1937 }
1938
1939 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1940 static bool
1941 drm_monitor_supports_rb(struct edid *edid)
1942 {
1943 if (edid->revision >= 4) {
1944 bool ret = false;
1945 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1946 return ret;
1947 }
1948
1949 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1950 }
1951
1952 static void
1953 find_gtf2(struct detailed_timing *t, void *data)
1954 {
1955 u8 *r = (u8 *)t;
1956 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1957 *(u8 **)data = r;
1958 }
1959
1960 /* Secondary GTF curve kicks in above some break frequency */
1961 static int
1962 drm_gtf2_hbreak(struct edid *edid)
1963 {
1964 u8 *r = NULL;
1965 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1966 return r ? (r[12] * 2) : 0;
1967 }
1968
1969 static int
1970 drm_gtf2_2c(struct edid *edid)
1971 {
1972 u8 *r = NULL;
1973 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1974 return r ? r[13] : 0;
1975 }
1976
1977 static int
1978 drm_gtf2_m(struct edid *edid)
1979 {
1980 u8 *r = NULL;
1981 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1982 return r ? (r[15] << 8) + r[14] : 0;
1983 }
1984
1985 static int
1986 drm_gtf2_k(struct edid *edid)
1987 {
1988 u8 *r = NULL;
1989 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1990 return r ? r[16] : 0;
1991 }
1992
1993 static int
1994 drm_gtf2_2j(struct edid *edid)
1995 {
1996 u8 *r = NULL;
1997 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1998 return r ? r[17] : 0;
1999 }
2000
2001 /**
2002 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2003 * @edid: EDID block to scan
2004 */
2005 static int standard_timing_level(struct edid *edid)
2006 {
2007 if (edid->revision >= 2) {
2008 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2009 return LEVEL_CVT;
2010 if (drm_gtf2_hbreak(edid))
2011 return LEVEL_GTF2;
2012 return LEVEL_GTF;
2013 }
2014 return LEVEL_DMT;
2015 }
2016
2017 /*
2018 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2019 * monitors fill with ascii space (0x20) instead.
2020 */
2021 static int
2022 bad_std_timing(u8 a, u8 b)
2023 {
2024 return (a == 0x00 && b == 0x00) ||
2025 (a == 0x01 && b == 0x01) ||
2026 (a == 0x20 && b == 0x20);
2027 }
2028
2029 /**
2030 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2031 * @connector: connector of for the EDID block
2032 * @edid: EDID block to scan
2033 * @t: standard timing params
2034 *
2035 * Take the standard timing params (in this case width, aspect, and refresh)
2036 * and convert them into a real mode using CVT/GTF/DMT.
2037 */
2038 static struct drm_display_mode *
2039 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2040 struct std_timing *t)
2041 {
2042 struct drm_device *dev = connector->dev;
2043 struct drm_display_mode *m, *mode = NULL;
2044 int hsize, vsize;
2045 int vrefresh_rate;
2046 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2047 >> EDID_TIMING_ASPECT_SHIFT;
2048 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2049 >> EDID_TIMING_VFREQ_SHIFT;
2050 int timing_level = standard_timing_level(edid);
2051
2052 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2053 return NULL;
2054
2055 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2056 hsize = t->hsize * 8 + 248;
2057 /* vrefresh_rate = vfreq + 60 */
2058 vrefresh_rate = vfreq + 60;
2059 /* the vdisplay is calculated based on the aspect ratio */
2060 if (aspect_ratio == 0) {
2061 if (edid->revision < 3)
2062 vsize = hsize;
2063 else
2064 vsize = (hsize * 10) / 16;
2065 } else if (aspect_ratio == 1)
2066 vsize = (hsize * 3) / 4;
2067 else if (aspect_ratio == 2)
2068 vsize = (hsize * 4) / 5;
2069 else
2070 vsize = (hsize * 9) / 16;
2071
2072 /* HDTV hack, part 1 */
2073 if (vrefresh_rate == 60 &&
2074 ((hsize == 1360 && vsize == 765) ||
2075 (hsize == 1368 && vsize == 769))) {
2076 hsize = 1366;
2077 vsize = 768;
2078 }
2079
2080 /*
2081 * If this connector already has a mode for this size and refresh
2082 * rate (because it came from detailed or CVT info), use that
2083 * instead. This way we don't have to guess at interlace or
2084 * reduced blanking.
2085 */
2086 list_for_each_entry(m, &connector->probed_modes, head)
2087 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2088 drm_mode_vrefresh(m) == vrefresh_rate)
2089 return NULL;
2090
2091 /* HDTV hack, part 2 */
2092 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2093 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2094 false);
2095 mode->hdisplay = 1366;
2096 mode->hsync_start = mode->hsync_start - 1;
2097 mode->hsync_end = mode->hsync_end - 1;
2098 return mode;
2099 }
2100
2101 /* check whether it can be found in default mode table */
2102 if (drm_monitor_supports_rb(edid)) {
2103 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2104 true);
2105 if (mode)
2106 return mode;
2107 }
2108 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2109 if (mode)
2110 return mode;
2111
2112 /* okay, generate it */
2113 switch (timing_level) {
2114 case LEVEL_DMT:
2115 break;
2116 case LEVEL_GTF:
2117 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2118 break;
2119 case LEVEL_GTF2:
2120 /*
2121 * This is potentially wrong if there's ever a monitor with
2122 * more than one ranges section, each claiming a different
2123 * secondary GTF curve. Please don't do that.
2124 */
2125 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2126 if (!mode)
2127 return NULL;
2128 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2129 drm_mode_destroy(dev, mode);
2130 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2131 vrefresh_rate, 0, 0,
2132 drm_gtf2_m(edid),
2133 drm_gtf2_2c(edid),
2134 drm_gtf2_k(edid),
2135 drm_gtf2_2j(edid));
2136 }
2137 break;
2138 case LEVEL_CVT:
2139 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2140 false);
2141 break;
2142 }
2143 return mode;
2144 }
2145
2146 /*
2147 * EDID is delightfully ambiguous about how interlaced modes are to be
2148 * encoded. Our internal representation is of frame height, but some
2149 * HDTV detailed timings are encoded as field height.
2150 *
2151 * The format list here is from CEA, in frame size. Technically we
2152 * should be checking refresh rate too. Whatever.
2153 */
2154 static void
2155 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2156 struct detailed_pixel_timing *pt)
2157 {
2158 int i;
2159 static const struct {
2160 int w, h;
2161 } cea_interlaced[] = {
2162 { 1920, 1080 },
2163 { 720, 480 },
2164 { 1440, 480 },
2165 { 2880, 480 },
2166 { 720, 576 },
2167 { 1440, 576 },
2168 { 2880, 576 },
2169 };
2170
2171 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2172 return;
2173
2174 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2175 if ((mode->hdisplay == cea_interlaced[i].w) &&
2176 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2177 mode->vdisplay *= 2;
2178 mode->vsync_start *= 2;
2179 mode->vsync_end *= 2;
2180 mode->vtotal *= 2;
2181 mode->vtotal |= 1;
2182 }
2183 }
2184
2185 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2186 }
2187
2188 /**
2189 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2190 * @dev: DRM device (needed to create new mode)
2191 * @edid: EDID block
2192 * @timing: EDID detailed timing info
2193 * @quirks: quirks to apply
2194 *
2195 * An EDID detailed timing block contains enough info for us to create and
2196 * return a new struct drm_display_mode.
2197 */
2198 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2199 struct edid *edid,
2200 struct detailed_timing *timing,
2201 u32 quirks)
2202 {
2203 struct drm_display_mode *mode;
2204 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2205 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2206 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2207 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2208 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2209 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2210 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2211 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2212 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2213
2214 /* ignore tiny modes */
2215 if (hactive < 64 || vactive < 64)
2216 return NULL;
2217
2218 if (pt->misc & DRM_EDID_PT_STEREO) {
2219 DRM_DEBUG_KMS("stereo mode not supported\n");
2220 return NULL;
2221 }
2222 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2223 DRM_DEBUG_KMS("composite sync not supported\n");
2224 }
2225
2226 /* it is incorrect if hsync/vsync width is zero */
2227 if (!hsync_pulse_width || !vsync_pulse_width) {
2228 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2229 "Wrong Hsync/Vsync pulse width\n");
2230 return NULL;
2231 }
2232
2233 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2234 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2235 if (!mode)
2236 return NULL;
2237
2238 goto set_size;
2239 }
2240
2241 mode = drm_mode_create(dev);
2242 if (!mode)
2243 return NULL;
2244
2245 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2246 timing->pixel_clock = cpu_to_le16(1088);
2247
2248 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2249
2250 mode->hdisplay = hactive;
2251 mode->hsync_start = mode->hdisplay + hsync_offset;
2252 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2253 mode->htotal = mode->hdisplay + hblank;
2254
2255 mode->vdisplay = vactive;
2256 mode->vsync_start = mode->vdisplay + vsync_offset;
2257 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2258 mode->vtotal = mode->vdisplay + vblank;
2259
2260 /* Some EDIDs have bogus h/vtotal values */
2261 if (mode->hsync_end > mode->htotal)
2262 mode->htotal = mode->hsync_end + 1;
2263 if (mode->vsync_end > mode->vtotal)
2264 mode->vtotal = mode->vsync_end + 1;
2265
2266 drm_mode_do_interlace_quirk(mode, pt);
2267
2268 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2269 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2270 }
2271
2272 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2273 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2274 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2275 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2276
2277 set_size:
2278 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2279 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2280
2281 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2282 mode->width_mm *= 10;
2283 mode->height_mm *= 10;
2284 }
2285
2286 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2287 mode->width_mm = edid->width_cm * 10;
2288 mode->height_mm = edid->height_cm * 10;
2289 }
2290
2291 mode->type = DRM_MODE_TYPE_DRIVER;
2292 mode->vrefresh = drm_mode_vrefresh(mode);
2293 drm_mode_set_name(mode);
2294
2295 return mode;
2296 }
2297
2298 static bool
2299 mode_in_hsync_range(const struct drm_display_mode *mode,
2300 struct edid *edid, u8 *t)
2301 {
2302 int hsync, hmin, hmax;
2303
2304 hmin = t[7];
2305 if (edid->revision >= 4)
2306 hmin += ((t[4] & 0x04) ? 255 : 0);
2307 hmax = t[8];
2308 if (edid->revision >= 4)
2309 hmax += ((t[4] & 0x08) ? 255 : 0);
2310 hsync = drm_mode_hsync(mode);
2311
2312 return (hsync <= hmax && hsync >= hmin);
2313 }
2314
2315 static bool
2316 mode_in_vsync_range(const struct drm_display_mode *mode,
2317 struct edid *edid, u8 *t)
2318 {
2319 int vsync, vmin, vmax;
2320
2321 vmin = t[5];
2322 if (edid->revision >= 4)
2323 vmin += ((t[4] & 0x01) ? 255 : 0);
2324 vmax = t[6];
2325 if (edid->revision >= 4)
2326 vmax += ((t[4] & 0x02) ? 255 : 0);
2327 vsync = drm_mode_vrefresh(mode);
2328
2329 return (vsync <= vmax && vsync >= vmin);
2330 }
2331
2332 static u32
2333 range_pixel_clock(struct edid *edid, u8 *t)
2334 {
2335 /* unspecified */
2336 if (t[9] == 0 || t[9] == 255)
2337 return 0;
2338
2339 /* 1.4 with CVT support gives us real precision, yay */
2340 if (edid->revision >= 4 && t[10] == 0x04)
2341 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2342
2343 /* 1.3 is pathetic, so fuzz up a bit */
2344 return t[9] * 10000 + 5001;
2345 }
2346
2347 static bool
2348 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2349 struct detailed_timing *timing)
2350 {
2351 u32 max_clock;
2352 u8 *t = (u8 *)timing;
2353
2354 if (!mode_in_hsync_range(mode, edid, t))
2355 return false;
2356
2357 if (!mode_in_vsync_range(mode, edid, t))
2358 return false;
2359
2360 if ((max_clock = range_pixel_clock(edid, t)))
2361 if (mode->clock > max_clock)
2362 return false;
2363
2364 /* 1.4 max horizontal check */
2365 if (edid->revision >= 4 && t[10] == 0x04)
2366 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2367 return false;
2368
2369 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2370 return false;
2371
2372 return true;
2373 }
2374
2375 static bool valid_inferred_mode(const struct drm_connector *connector,
2376 const struct drm_display_mode *mode)
2377 {
2378 const struct drm_display_mode *m;
2379 bool ok = false;
2380
2381 list_for_each_entry(m, &connector->probed_modes, head) {
2382 if (mode->hdisplay == m->hdisplay &&
2383 mode->vdisplay == m->vdisplay &&
2384 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2385 return false; /* duplicated */
2386 if (mode->hdisplay <= m->hdisplay &&
2387 mode->vdisplay <= m->vdisplay)
2388 ok = true;
2389 }
2390 return ok;
2391 }
2392
2393 static int
2394 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2395 struct detailed_timing *timing)
2396 {
2397 int i, modes = 0;
2398 struct drm_display_mode *newmode;
2399 struct drm_device *dev = connector->dev;
2400
2401 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2402 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2403 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2404 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2405 if (newmode) {
2406 drm_mode_probed_add(connector, newmode);
2407 modes++;
2408 }
2409 }
2410 }
2411
2412 return modes;
2413 }
2414
2415 /* fix up 1366x768 mode from 1368x768;
2416 * GFT/CVT can't express 1366 width which isn't dividable by 8
2417 */
2418 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2419 {
2420 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2421 mode->hdisplay = 1366;
2422 mode->hsync_start--;
2423 mode->hsync_end--;
2424 drm_mode_set_name(mode);
2425 }
2426 }
2427
2428 static int
2429 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2430 struct detailed_timing *timing)
2431 {
2432 int i, modes = 0;
2433 struct drm_display_mode *newmode;
2434 struct drm_device *dev = connector->dev;
2435
2436 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2437 const struct minimode *m = &extra_modes[i];
2438 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2439 if (!newmode)
2440 return modes;
2441
2442 drm_mode_fixup_1366x768(newmode);
2443 if (!mode_in_range(newmode, edid, timing) ||
2444 !valid_inferred_mode(connector, newmode)) {
2445 drm_mode_destroy(dev, newmode);
2446 continue;
2447 }
2448
2449 drm_mode_probed_add(connector, newmode);
2450 modes++;
2451 }
2452
2453 return modes;
2454 }
2455
2456 static int
2457 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2458 struct detailed_timing *timing)
2459 {
2460 int i, modes = 0;
2461 struct drm_display_mode *newmode;
2462 struct drm_device *dev = connector->dev;
2463 bool rb = drm_monitor_supports_rb(edid);
2464
2465 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2466 const struct minimode *m = &extra_modes[i];
2467 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2468 if (!newmode)
2469 return modes;
2470
2471 drm_mode_fixup_1366x768(newmode);
2472 if (!mode_in_range(newmode, edid, timing) ||
2473 !valid_inferred_mode(connector, newmode)) {
2474 drm_mode_destroy(dev, newmode);
2475 continue;
2476 }
2477
2478 drm_mode_probed_add(connector, newmode);
2479 modes++;
2480 }
2481
2482 return modes;
2483 }
2484
2485 static void
2486 do_inferred_modes(struct detailed_timing *timing, void *c)
2487 {
2488 struct detailed_mode_closure *closure = c;
2489 struct detailed_non_pixel *data = &timing->data.other_data;
2490 struct detailed_data_monitor_range *range = &data->data.range;
2491
2492 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2493 return;
2494
2495 closure->modes += drm_dmt_modes_for_range(closure->connector,
2496 closure->edid,
2497 timing);
2498
2499 if (!version_greater(closure->edid, 1, 1))
2500 return; /* GTF not defined yet */
2501
2502 switch (range->flags) {
2503 case 0x02: /* secondary gtf, XXX could do more */
2504 case 0x00: /* default gtf */
2505 closure->modes += drm_gtf_modes_for_range(closure->connector,
2506 closure->edid,
2507 timing);
2508 break;
2509 case 0x04: /* cvt, only in 1.4+ */
2510 if (!version_greater(closure->edid, 1, 3))
2511 break;
2512
2513 closure->modes += drm_cvt_modes_for_range(closure->connector,
2514 closure->edid,
2515 timing);
2516 break;
2517 case 0x01: /* just the ranges, no formula */
2518 default:
2519 break;
2520 }
2521 }
2522
2523 static int
2524 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2525 {
2526 struct detailed_mode_closure closure = {
2527 .connector = connector,
2528 .edid = edid,
2529 };
2530
2531 if (version_greater(edid, 1, 0))
2532 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2533 &closure);
2534
2535 return closure.modes;
2536 }
2537
2538 static int
2539 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2540 {
2541 int i, j, m, modes = 0;
2542 struct drm_display_mode *mode;
2543 u8 *est = ((u8 *)timing) + 6;
2544
2545 for (i = 0; i < 6; i++) {
2546 for (j = 7; j >= 0; j--) {
2547 m = (i * 8) + (7 - j);
2548 if (m >= ARRAY_SIZE(est3_modes))
2549 break;
2550 if (est[i] & (1 << j)) {
2551 mode = drm_mode_find_dmt(connector->dev,
2552 est3_modes[m].w,
2553 est3_modes[m].h,
2554 est3_modes[m].r,
2555 est3_modes[m].rb);
2556 if (mode) {
2557 drm_mode_probed_add(connector, mode);
2558 modes++;
2559 }
2560 }
2561 }
2562 }
2563
2564 return modes;
2565 }
2566
2567 static void
2568 do_established_modes(struct detailed_timing *timing, void *c)
2569 {
2570 struct detailed_mode_closure *closure = c;
2571 struct detailed_non_pixel *data = &timing->data.other_data;
2572
2573 if (data->type == EDID_DETAIL_EST_TIMINGS)
2574 closure->modes += drm_est3_modes(closure->connector, timing);
2575 }
2576
2577 /**
2578 * add_established_modes - get est. modes from EDID and add them
2579 * @connector: connector to add mode(s) to
2580 * @edid: EDID block to scan
2581 *
2582 * Each EDID block contains a bitmap of the supported "established modes" list
2583 * (defined above). Tease them out and add them to the global modes list.
2584 */
2585 static int
2586 add_established_modes(struct drm_connector *connector, struct edid *edid)
2587 {
2588 struct drm_device *dev = connector->dev;
2589 unsigned long est_bits = edid->established_timings.t1 |
2590 (edid->established_timings.t2 << 8) |
2591 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2592 int i, modes = 0;
2593 struct detailed_mode_closure closure = {
2594 .connector = connector,
2595 .edid = edid,
2596 };
2597
2598 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2599 if (est_bits & (1<<i)) {
2600 struct drm_display_mode *newmode;
2601 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2602 if (newmode) {
2603 drm_mode_probed_add(connector, newmode);
2604 modes++;
2605 }
2606 }
2607 }
2608
2609 if (version_greater(edid, 1, 0))
2610 drm_for_each_detailed_block((u8 *)edid,
2611 do_established_modes, &closure);
2612
2613 return modes + closure.modes;
2614 }
2615
2616 static void
2617 do_standard_modes(struct detailed_timing *timing, void *c)
2618 {
2619 struct detailed_mode_closure *closure = c;
2620 struct detailed_non_pixel *data = &timing->data.other_data;
2621 struct drm_connector *connector = closure->connector;
2622 struct edid *edid = closure->edid;
2623
2624 if (data->type == EDID_DETAIL_STD_MODES) {
2625 int i;
2626 for (i = 0; i < 6; i++) {
2627 struct std_timing *std;
2628 struct drm_display_mode *newmode;
2629
2630 std = &data->data.timings[i];
2631 newmode = drm_mode_std(connector, edid, std);
2632 if (newmode) {
2633 drm_mode_probed_add(connector, newmode);
2634 closure->modes++;
2635 }
2636 }
2637 }
2638 }
2639
2640 /**
2641 * add_standard_modes - get std. modes from EDID and add them
2642 * @connector: connector to add mode(s) to
2643 * @edid: EDID block to scan
2644 *
2645 * Standard modes can be calculated using the appropriate standard (DMT,
2646 * GTF or CVT. Grab them from @edid and add them to the list.
2647 */
2648 static int
2649 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2650 {
2651 int i, modes = 0;
2652 struct detailed_mode_closure closure = {
2653 .connector = connector,
2654 .edid = edid,
2655 };
2656
2657 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2658 struct drm_display_mode *newmode;
2659
2660 newmode = drm_mode_std(connector, edid,
2661 &edid->standard_timings[i]);
2662 if (newmode) {
2663 drm_mode_probed_add(connector, newmode);
2664 modes++;
2665 }
2666 }
2667
2668 if (version_greater(edid, 1, 0))
2669 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2670 &closure);
2671
2672 /* XXX should also look for standard codes in VTB blocks */
2673
2674 return modes + closure.modes;
2675 }
2676
2677 static int drm_cvt_modes(struct drm_connector *connector,
2678 struct detailed_timing *timing)
2679 {
2680 int i, j, modes = 0;
2681 struct drm_display_mode *newmode;
2682 struct drm_device *dev = connector->dev;
2683 struct cvt_timing *cvt;
2684 const int rates[] = { 60, 85, 75, 60, 50 };
2685 const u8 empty[3] = { 0, 0, 0 };
2686
2687 for (i = 0; i < 4; i++) {
2688 int width = 0, height;
2689 cvt = &(timing->data.other_data.data.cvt[i]);
2690
2691 if (!memcmp(cvt->code, empty, 3))
2692 continue;
2693
2694 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2695 switch (cvt->code[1] & 0x0c) {
2696 case 0x00:
2697 width = height * 4 / 3;
2698 break;
2699 case 0x04:
2700 width = height * 16 / 9;
2701 break;
2702 case 0x08:
2703 width = height * 16 / 10;
2704 break;
2705 case 0x0c:
2706 width = height * 15 / 9;
2707 break;
2708 }
2709
2710 for (j = 1; j < 5; j++) {
2711 if (cvt->code[2] & (1 << j)) {
2712 newmode = drm_cvt_mode(dev, width, height,
2713 rates[j], j == 0,
2714 false, false);
2715 if (newmode) {
2716 drm_mode_probed_add(connector, newmode);
2717 modes++;
2718 }
2719 }
2720 }
2721 }
2722
2723 return modes;
2724 }
2725
2726 static void
2727 do_cvt_mode(struct detailed_timing *timing, void *c)
2728 {
2729 struct detailed_mode_closure *closure = c;
2730 struct detailed_non_pixel *data = &timing->data.other_data;
2731
2732 if (data->type == EDID_DETAIL_CVT_3BYTE)
2733 closure->modes += drm_cvt_modes(closure->connector, timing);
2734 }
2735
2736 static int
2737 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2738 {
2739 struct detailed_mode_closure closure = {
2740 .connector = connector,
2741 .edid = edid,
2742 };
2743
2744 if (version_greater(edid, 1, 2))
2745 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2746
2747 /* XXX should also look for CVT codes in VTB blocks */
2748
2749 return closure.modes;
2750 }
2751
2752 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2753
2754 static void
2755 do_detailed_mode(struct detailed_timing *timing, void *c)
2756 {
2757 struct detailed_mode_closure *closure = c;
2758 struct drm_display_mode *newmode;
2759
2760 if (timing->pixel_clock) {
2761 newmode = drm_mode_detailed(closure->connector->dev,
2762 closure->edid, timing,
2763 closure->quirks);
2764 if (!newmode)
2765 return;
2766
2767 if (closure->preferred)
2768 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2769
2770 /*
2771 * Detailed modes are limited to 10kHz pixel clock resolution,
2772 * so fix up anything that looks like CEA/HDMI mode, but the clock
2773 * is just slightly off.
2774 */
2775 fixup_detailed_cea_mode_clock(newmode);
2776
2777 drm_mode_probed_add(closure->connector, newmode);
2778 closure->modes++;
2779 closure->preferred = 0;
2780 }
2781 }
2782
2783 /*
2784 * add_detailed_modes - Add modes from detailed timings
2785 * @connector: attached connector
2786 * @edid: EDID block to scan
2787 * @quirks: quirks to apply
2788 */
2789 static int
2790 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2791 u32 quirks)
2792 {
2793 struct detailed_mode_closure closure = {
2794 .connector = connector,
2795 .edid = edid,
2796 .preferred = 1,
2797 .quirks = quirks,
2798 };
2799
2800 if (closure.preferred && !version_greater(edid, 1, 3))
2801 closure.preferred =
2802 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2803
2804 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2805
2806 return closure.modes;
2807 }
2808
2809 #define AUDIO_BLOCK 0x01
2810 #define VIDEO_BLOCK 0x02
2811 #define VENDOR_BLOCK 0x03
2812 #define SPEAKER_BLOCK 0x04
2813 #define USE_EXTENDED_TAG 0x07
2814 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2815 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2816 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2817 #define EDID_BASIC_AUDIO (1 << 6)
2818 #define EDID_CEA_YCRCB444 (1 << 5)
2819 #define EDID_CEA_YCRCB422 (1 << 4)
2820 #define EDID_CEA_VCDB_QS (1 << 6)
2821
2822 /*
2823 * Search EDID for CEA extension block.
2824 */
2825 static u8 *drm_find_edid_extension(const struct edid *edid, int ext_id)
2826 {
2827 u8 *edid_ext = NULL;
2828 int i;
2829
2830 /* No EDID or EDID extensions */
2831 if (edid == NULL || edid->extensions == 0)
2832 return NULL;
2833
2834 /* Find CEA extension */
2835 for (i = 0; i < edid->extensions; i++) {
2836 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2837 if (edid_ext[0] == ext_id)
2838 break;
2839 }
2840
2841 if (i == edid->extensions)
2842 return NULL;
2843
2844 return edid_ext;
2845 }
2846
2847 static u8 *drm_find_cea_extension(const struct edid *edid)
2848 {
2849 return drm_find_edid_extension(edid, CEA_EXT);
2850 }
2851
2852 static u8 *drm_find_displayid_extension(const struct edid *edid)
2853 {
2854 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2855 }
2856
2857 /*
2858 * Calculate the alternate clock for the CEA mode
2859 * (60Hz vs. 59.94Hz etc.)
2860 */
2861 static unsigned int
2862 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2863 {
2864 unsigned int clock = cea_mode->clock;
2865
2866 if (cea_mode->vrefresh % 6 != 0)
2867 return clock;
2868
2869 /*
2870 * edid_cea_modes contains the 59.94Hz
2871 * variant for 240 and 480 line modes,
2872 * and the 60Hz variant otherwise.
2873 */
2874 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2875 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2876 else
2877 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2878
2879 return clock;
2880 }
2881
2882 static bool
2883 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2884 {
2885 /*
2886 * For certain VICs the spec allows the vertical
2887 * front porch to vary by one or two lines.
2888 *
2889 * cea_modes[] stores the variant with the shortest
2890 * vertical front porch. We can adjust the mode to
2891 * get the other variants by simply increasing the
2892 * vertical front porch length.
2893 */
2894 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2895 edid_cea_modes[9].vtotal != 262 ||
2896 edid_cea_modes[12].vtotal != 262 ||
2897 edid_cea_modes[13].vtotal != 262 ||
2898 edid_cea_modes[23].vtotal != 312 ||
2899 edid_cea_modes[24].vtotal != 312 ||
2900 edid_cea_modes[27].vtotal != 312 ||
2901 edid_cea_modes[28].vtotal != 312);
2902
2903 if (((vic == 8 || vic == 9 ||
2904 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2905 ((vic == 23 || vic == 24 ||
2906 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2907 mode->vsync_start++;
2908 mode->vsync_end++;
2909 mode->vtotal++;
2910
2911 return true;
2912 }
2913
2914 return false;
2915 }
2916
2917 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2918 unsigned int clock_tolerance)
2919 {
2920 u8 vic;
2921
2922 if (!to_match->clock)
2923 return 0;
2924
2925 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2926 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2927 unsigned int clock1, clock2;
2928
2929 /* Check both 60Hz and 59.94Hz */
2930 clock1 = cea_mode.clock;
2931 clock2 = cea_mode_alternate_clock(&cea_mode);
2932
2933 if (abs(to_match->clock - clock1) > clock_tolerance &&
2934 abs(to_match->clock - clock2) > clock_tolerance)
2935 continue;
2936
2937 do {
2938 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2939 return vic;
2940 } while (cea_mode_alternate_timings(vic, &cea_mode));
2941 }
2942
2943 return 0;
2944 }
2945
2946 /**
2947 * drm_match_cea_mode - look for a CEA mode matching given mode
2948 * @to_match: display mode
2949 *
2950 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2951 * mode.
2952 */
2953 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2954 {
2955 u8 vic;
2956
2957 if (!to_match->clock)
2958 return 0;
2959
2960 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2961 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2962 unsigned int clock1, clock2;
2963
2964 /* Check both 60Hz and 59.94Hz */
2965 clock1 = cea_mode.clock;
2966 clock2 = cea_mode_alternate_clock(&cea_mode);
2967
2968 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2969 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2970 continue;
2971
2972 do {
2973 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2974 return vic;
2975 } while (cea_mode_alternate_timings(vic, &cea_mode));
2976 }
2977
2978 return 0;
2979 }
2980 EXPORT_SYMBOL(drm_match_cea_mode);
2981
2982 static bool drm_valid_cea_vic(u8 vic)
2983 {
2984 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2985 }
2986
2987 /**
2988 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2989 * the input VIC from the CEA mode list
2990 * @video_code: ID given to each of the CEA modes
2991 *
2992 * Returns picture aspect ratio
2993 */
2994 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2995 {
2996 return edid_cea_modes[video_code].picture_aspect_ratio;
2997 }
2998 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2999
3000 /*
3001 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3002 * specific block).
3003 *
3004 * It's almost like cea_mode_alternate_clock(), we just need to add an
3005 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
3006 * one.
3007 */
3008 static unsigned int
3009 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3010 {
3011 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
3012 return hdmi_mode->clock;
3013
3014 return cea_mode_alternate_clock(hdmi_mode);
3015 }
3016
3017 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3018 unsigned int clock_tolerance)
3019 {
3020 u8 vic;
3021
3022 if (!to_match->clock)
3023 return 0;
3024
3025 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3026 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3027 unsigned int clock1, clock2;
3028
3029 /* Make sure to also match alternate clocks */
3030 clock1 = hdmi_mode->clock;
3031 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3032
3033 if (abs(to_match->clock - clock1) > clock_tolerance &&
3034 abs(to_match->clock - clock2) > clock_tolerance)
3035 continue;
3036
3037 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3038 return vic;
3039 }
3040
3041 return 0;
3042 }
3043
3044 /*
3045 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3046 * @to_match: display mode
3047 *
3048 * An HDMI mode is one defined in the HDMI vendor specific block.
3049 *
3050 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3051 */
3052 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3053 {
3054 u8 vic;
3055
3056 if (!to_match->clock)
3057 return 0;
3058
3059 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3060 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3061 unsigned int clock1, clock2;
3062
3063 /* Make sure to also match alternate clocks */
3064 clock1 = hdmi_mode->clock;
3065 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3066
3067 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3068 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3069 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3070 return vic;
3071 }
3072 return 0;
3073 }
3074
3075 static bool drm_valid_hdmi_vic(u8 vic)
3076 {
3077 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3078 }
3079
3080 static int
3081 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3082 {
3083 struct drm_device *dev = connector->dev;
3084 struct drm_display_mode *mode, *tmp;
3085 LINUX_LIST_HEAD(list);
3086 int modes = 0;
3087
3088 /* Don't add CEA modes if the CEA extension block is missing */
3089 if (!drm_find_cea_extension(edid))
3090 return 0;
3091
3092 /*
3093 * Go through all probed modes and create a new mode
3094 * with the alternate clock for certain CEA modes.
3095 */
3096 list_for_each_entry(mode, &connector->probed_modes, head) {
3097 const struct drm_display_mode *cea_mode = NULL;
3098 struct drm_display_mode *newmode;
3099 u8 vic = drm_match_cea_mode(mode);
3100 unsigned int clock1, clock2;
3101
3102 if (drm_valid_cea_vic(vic)) {
3103 cea_mode = &edid_cea_modes[vic];
3104 clock2 = cea_mode_alternate_clock(cea_mode);
3105 } else {
3106 vic = drm_match_hdmi_mode(mode);
3107 if (drm_valid_hdmi_vic(vic)) {
3108 cea_mode = &edid_4k_modes[vic];
3109 clock2 = hdmi_mode_alternate_clock(cea_mode);
3110 }
3111 }
3112
3113 if (!cea_mode)
3114 continue;
3115
3116 clock1 = cea_mode->clock;
3117
3118 if (clock1 == clock2)
3119 continue;
3120
3121 if (mode->clock != clock1 && mode->clock != clock2)
3122 continue;
3123
3124 newmode = drm_mode_duplicate(dev, cea_mode);
3125 if (!newmode)
3126 continue;
3127
3128 /* Carry over the stereo flags */
3129 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3130
3131 /*
3132 * The current mode could be either variant. Make
3133 * sure to pick the "other" clock for the new mode.
3134 */
3135 if (mode->clock != clock1)
3136 newmode->clock = clock1;
3137 else
3138 newmode->clock = clock2;
3139
3140 list_add_tail(&newmode->head, &list);
3141 }
3142
3143 list_for_each_entry_safe(mode, tmp, &list, head) {
3144 list_del(&mode->head);
3145 drm_mode_probed_add(connector, mode);
3146 modes++;
3147 }
3148
3149 return modes;
3150 }
3151
3152 static u8 svd_to_vic(u8 svd)
3153 {
3154 /* 0-6 bit vic, 7th bit native mode indicator */
3155 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3156 return svd & 127;
3157
3158 return svd;
3159 }
3160
3161 static struct drm_display_mode *
3162 drm_display_mode_from_vic_index(struct drm_connector *connector,
3163 const u8 *video_db, u8 video_len,
3164 u8 video_index)
3165 {
3166 struct drm_device *dev = connector->dev;
3167 struct drm_display_mode *newmode;
3168 u8 vic;
3169
3170 if (video_db == NULL || video_index >= video_len)
3171 return NULL;
3172
3173 /* CEA modes are numbered 1..127 */
3174 vic = svd_to_vic(video_db[video_index]);
3175 if (!drm_valid_cea_vic(vic))
3176 return NULL;
3177
3178 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3179 if (!newmode)
3180 return NULL;
3181
3182 newmode->vrefresh = 0;
3183
3184 return newmode;
3185 }
3186
3187 /*
3188 * do_y420vdb_modes - Parse YCBCR 420 only modes
3189 * @connector: connector corresponding to the HDMI sink
3190 * @svds: start of the data block of CEA YCBCR 420 VDB
3191 * @len: length of the CEA YCBCR 420 VDB
3192 *
3193 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3194 * which contains modes which can be supported in YCBCR 420
3195 * output format only.
3196 */
3197 static int do_y420vdb_modes(struct drm_connector *connector,
3198 const u8 *svds, u8 svds_len)
3199 {
3200 int modes = 0, i;
3201 struct drm_device *dev = connector->dev;
3202 struct drm_display_info *info = &connector->display_info;
3203 struct drm_hdmi_info *hdmi = &info->hdmi;
3204
3205 for (i = 0; i < svds_len; i++) {
3206 u8 vic = svd_to_vic(svds[i]);
3207 struct drm_display_mode *newmode;
3208
3209 if (!drm_valid_cea_vic(vic))
3210 continue;
3211
3212 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3213 if (!newmode)
3214 break;
3215 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3216 drm_mode_probed_add(connector, newmode);
3217 modes++;
3218 }
3219
3220 if (modes > 0)
3221 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3222 return modes;
3223 }
3224
3225 /*
3226 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3227 * @connector: connector corresponding to the HDMI sink
3228 * @vic: CEA vic for the video mode to be added in the map
3229 *
3230 * Makes an entry for a videomode in the YCBCR 420 bitmap
3231 */
3232 static void
3233 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3234 {
3235 u8 vic = svd_to_vic(svd);
3236 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3237
3238 if (!drm_valid_cea_vic(vic))
3239 return;
3240
3241 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3242 }
3243
3244 static int
3245 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3246 {
3247 int i, modes = 0;
3248 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3249
3250 for (i = 0; i < len; i++) {
3251 struct drm_display_mode *mode;
3252 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3253 if (mode) {
3254 /*
3255 * YCBCR420 capability block contains a bitmap which
3256 * gives the index of CEA modes from CEA VDB, which
3257 * can support YCBCR 420 sampling output also (apart
3258 * from RGB/YCBCR444 etc).
3259 * For example, if the bit 0 in bitmap is set,
3260 * first mode in VDB can support YCBCR420 output too.
3261 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3262 */
3263 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3264 drm_add_cmdb_modes(connector, db[i]);
3265
3266 drm_mode_probed_add(connector, mode);
3267 modes++;
3268 }
3269 }
3270
3271 return modes;
3272 }
3273
3274 struct stereo_mandatory_mode {
3275 int width, height, vrefresh;
3276 unsigned int flags;
3277 };
3278
3279 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3280 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3281 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3282 { 1920, 1080, 50,
3283 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3284 { 1920, 1080, 60,
3285 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3286 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3287 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3288 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3289 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3290 };
3291
3292 static bool
3293 stereo_match_mandatory(const struct drm_display_mode *mode,
3294 const struct stereo_mandatory_mode *stereo_mode)
3295 {
3296 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3297
3298 return mode->hdisplay == stereo_mode->width &&
3299 mode->vdisplay == stereo_mode->height &&
3300 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3301 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3302 }
3303
3304 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3305 {
3306 struct drm_device *dev = connector->dev;
3307 const struct drm_display_mode *mode;
3308 struct list_head stereo_modes;
3309 int modes = 0, i;
3310
3311 INIT_LIST_HEAD(&stereo_modes);
3312
3313 list_for_each_entry(mode, &connector->probed_modes, head) {
3314 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3315 const struct stereo_mandatory_mode *mandatory;
3316 struct drm_display_mode *new_mode;
3317
3318 if (!stereo_match_mandatory(mode,
3319 &stereo_mandatory_modes[i]))
3320 continue;
3321
3322 mandatory = &stereo_mandatory_modes[i];
3323 new_mode = drm_mode_duplicate(dev, mode);
3324 if (!new_mode)
3325 continue;
3326
3327 new_mode->flags |= mandatory->flags;
3328 list_add_tail(&new_mode->head, &stereo_modes);
3329 modes++;
3330 }
3331 }
3332
3333 list_splice_tail(&stereo_modes, &connector->probed_modes);
3334
3335 return modes;
3336 }
3337
3338 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3339 {
3340 struct drm_device *dev = connector->dev;
3341 struct drm_display_mode *newmode;
3342
3343 if (!drm_valid_hdmi_vic(vic)) {
3344 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3345 return 0;
3346 }
3347
3348 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3349 if (!newmode)
3350 return 0;
3351
3352 drm_mode_probed_add(connector, newmode);
3353
3354 return 1;
3355 }
3356
3357 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3358 const u8 *video_db, u8 video_len, u8 video_index)
3359 {
3360 struct drm_display_mode *newmode;
3361 int modes = 0;
3362
3363 if (structure & (1 << 0)) {
3364 newmode = drm_display_mode_from_vic_index(connector, video_db,
3365 video_len,
3366 video_index);
3367 if (newmode) {
3368 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3369 drm_mode_probed_add(connector, newmode);
3370 modes++;
3371 }
3372 }
3373 if (structure & (1 << 6)) {
3374 newmode = drm_display_mode_from_vic_index(connector, video_db,
3375 video_len,
3376 video_index);
3377 if (newmode) {
3378 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3379 drm_mode_probed_add(connector, newmode);
3380 modes++;
3381 }
3382 }
3383 if (structure & (1 << 8)) {
3384 newmode = drm_display_mode_from_vic_index(connector, video_db,
3385 video_len,
3386 video_index);
3387 if (newmode) {
3388 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3389 drm_mode_probed_add(connector, newmode);
3390 modes++;
3391 }
3392 }
3393
3394 return modes;
3395 }
3396
3397 /*
3398 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3399 * @connector: connector corresponding to the HDMI sink
3400 * @db: start of the CEA vendor specific block
3401 * @len: length of the CEA block payload, ie. one can access up to db[len]
3402 *
3403 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3404 * also adds the stereo 3d modes when applicable.
3405 */
3406 static int
3407 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3408 const u8 *video_db, u8 video_len)
3409 {
3410 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3411 u8 vic_len, hdmi_3d_len = 0;
3412 u16 mask;
3413 u16 structure_all;
3414
3415 if (len < 8)
3416 goto out;
3417
3418 /* no HDMI_Video_Present */
3419 if (!(db[8] & (1 << 5)))
3420 goto out;
3421
3422 /* Latency_Fields_Present */
3423 if (db[8] & (1 << 7))
3424 offset += 2;
3425
3426 /* I_Latency_Fields_Present */
3427 if (db[8] & (1 << 6))
3428 offset += 2;
3429
3430 /* the declared length is not long enough for the 2 first bytes
3431 * of additional video format capabilities */
3432 if (len < (8 + offset + 2))
3433 goto out;
3434
3435 /* 3D_Present */
3436 offset++;
3437 if (db[8 + offset] & (1 << 7)) {
3438 modes += add_hdmi_mandatory_stereo_modes(connector);
3439
3440 /* 3D_Multi_present */
3441 multi_present = (db[8 + offset] & 0x60) >> 5;
3442 }
3443
3444 offset++;
3445 vic_len = db[8 + offset] >> 5;
3446 hdmi_3d_len = db[8 + offset] & 0x1f;
3447
3448 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3449 u8 vic;
3450
3451 vic = db[9 + offset + i];
3452 modes += add_hdmi_mode(connector, vic);
3453 }
3454 offset += 1 + vic_len;
3455
3456 if (multi_present == 1)
3457 multi_len = 2;
3458 else if (multi_present == 2)
3459 multi_len = 4;
3460 else
3461 multi_len = 0;
3462
3463 if (len < (8 + offset + hdmi_3d_len - 1))
3464 goto out;
3465
3466 if (hdmi_3d_len < multi_len)
3467 goto out;
3468
3469 if (multi_present == 1 || multi_present == 2) {
3470 /* 3D_Structure_ALL */
3471 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3472
3473 /* check if 3D_MASK is present */
3474 if (multi_present == 2)
3475 mask = (db[10 + offset] << 8) | db[11 + offset];
3476 else
3477 mask = 0xffff;
3478
3479 for (i = 0; i < 16; i++) {
3480 if (mask & (1 << i))
3481 modes += add_3d_struct_modes(connector,
3482 structure_all,
3483 video_db,
3484 video_len, i);
3485 }
3486 }
3487
3488 offset += multi_len;
3489
3490 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3491 int vic_index;
3492 struct drm_display_mode *newmode = NULL;
3493 unsigned int newflag = 0;
3494 bool detail_present;
3495
3496 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3497
3498 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3499 break;
3500
3501 /* 2D_VIC_order_X */
3502 vic_index = db[8 + offset + i] >> 4;
3503
3504 /* 3D_Structure_X */
3505 switch (db[8 + offset + i] & 0x0f) {
3506 case 0:
3507 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3508 break;
3509 case 6:
3510 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3511 break;
3512 case 8:
3513 /* 3D_Detail_X */
3514 if ((db[9 + offset + i] >> 4) == 1)
3515 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3516 break;
3517 }
3518
3519 if (newflag != 0) {
3520 newmode = drm_display_mode_from_vic_index(connector,
3521 video_db,
3522 video_len,
3523 vic_index);
3524
3525 if (newmode) {
3526 newmode->flags |= newflag;
3527 drm_mode_probed_add(connector, newmode);
3528 modes++;
3529 }
3530 }
3531
3532 if (detail_present)
3533 i++;
3534 }
3535
3536 out:
3537 return modes;
3538 }
3539
3540 static int
3541 cea_db_payload_len(const u8 *db)
3542 {
3543 return db[0] & 0x1f;
3544 }
3545
3546 static int
3547 cea_db_extended_tag(const u8 *db)
3548 {
3549 return db[1];
3550 }
3551
3552 static int
3553 cea_db_tag(const u8 *db)
3554 {
3555 return db[0] >> 5;
3556 }
3557
3558 static int
3559 cea_revision(const u8 *cea)
3560 {
3561 return cea[1];
3562 }
3563
3564 static int
3565 cea_db_offsets(const u8 *cea, int *start, int *end)
3566 {
3567 /* Data block offset in CEA extension block */
3568 *start = 4;
3569 *end = cea[2];
3570 if (*end == 0)
3571 *end = 127;
3572 if (*end < 4 || *end > 127)
3573 return -ERANGE;
3574 return 0;
3575 }
3576
3577 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3578 {
3579 int hdmi_id;
3580
3581 if (cea_db_tag(db) != VENDOR_BLOCK)
3582 return false;
3583
3584 if (cea_db_payload_len(db) < 5)
3585 return false;
3586
3587 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3588
3589 return hdmi_id == HDMI_IEEE_OUI;
3590 }
3591
3592 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3593 {
3594 unsigned int oui;
3595
3596 if (cea_db_tag(db) != VENDOR_BLOCK)
3597 return false;
3598
3599 if (cea_db_payload_len(db) < 7)
3600 return false;
3601
3602 oui = db[3] << 16 | db[2] << 8 | db[1];
3603
3604 return oui == HDMI_FORUM_IEEE_OUI;
3605 }
3606
3607 static bool cea_db_is_y420cmdb(const u8 *db)
3608 {
3609 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3610 return false;
3611
3612 if (!cea_db_payload_len(db))
3613 return false;
3614
3615 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3616 return false;
3617
3618 return true;
3619 }
3620
3621 static bool cea_db_is_y420vdb(const u8 *db)
3622 {
3623 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3624 return false;
3625
3626 if (!cea_db_payload_len(db))
3627 return false;
3628
3629 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3630 return false;
3631
3632 return true;
3633 }
3634
3635 #define for_each_cea_db(cea, i, start, end) \
3636 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3637
3638 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3639 const u8 *db)
3640 {
3641 struct drm_display_info *info = &connector->display_info;
3642 struct drm_hdmi_info *hdmi = &info->hdmi;
3643 u8 map_len = cea_db_payload_len(db) - 1;
3644 u8 count;
3645 u64 map = 0;
3646
3647 if (map_len == 0) {
3648 /* All CEA modes support ycbcr420 sampling also.*/
3649 hdmi->y420_cmdb_map = U64_MAX;
3650 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3651 return;
3652 }
3653
3654 /*
3655 * This map indicates which of the existing CEA block modes
3656 * from VDB can support YCBCR420 output too. So if bit=0 is
3657 * set, first mode from VDB can support YCBCR420 output too.
3658 * We will parse and keep this map, before parsing VDB itself
3659 * to avoid going through the same block again and again.
3660 *
3661 * Spec is not clear about max possible size of this block.
3662 * Clamping max bitmap block size at 8 bytes. Every byte can
3663 * address 8 CEA modes, in this way this map can address
3664 * 8*8 = first 64 SVDs.
3665 */
3666 if (WARN_ON_ONCE(map_len > 8))
3667 map_len = 8;
3668
3669 for (count = 0; count < map_len; count++)
3670 map |= (u64)db[2 + count] << (8 * count);
3671
3672 if (map)
3673 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3674
3675 hdmi->y420_cmdb_map = map;
3676 }
3677
3678 static int
3679 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3680 {
3681 const u8 *cea = drm_find_cea_extension(edid);
3682 const u8 *db, *hdmi = NULL, *video = NULL;
3683 u8 dbl, hdmi_len, video_len = 0;
3684 int modes = 0;
3685
3686 if (cea && cea_revision(cea) >= 3) {
3687 int i, start, end;
3688
3689 if (cea_db_offsets(cea, &start, &end))
3690 return 0;
3691
3692 for_each_cea_db(cea, i, start, end) {
3693 db = &cea[i];
3694 dbl = cea_db_payload_len(db);
3695
3696 if (cea_db_tag(db) == VIDEO_BLOCK) {
3697 video = db + 1;
3698 video_len = dbl;
3699 modes += do_cea_modes(connector, video, dbl);
3700 } else if (cea_db_is_hdmi_vsdb(db)) {
3701 hdmi = db;
3702 hdmi_len = dbl;
3703 } else if (cea_db_is_y420vdb(db)) {
3704 const u8 *vdb420 = &db[2];
3705
3706 /* Add 4:2:0(only) modes present in EDID */
3707 modes += do_y420vdb_modes(connector,
3708 vdb420,
3709 dbl - 1);
3710 }
3711 }
3712 }
3713
3714 /*
3715 * We parse the HDMI VSDB after having added the cea modes as we will
3716 * be patching their flags when the sink supports stereo 3D.
3717 */
3718 if (hdmi)
3719 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3720 video_len);
3721
3722 return modes;
3723 }
3724
3725 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3726 {
3727 const struct drm_display_mode *cea_mode;
3728 int clock1, clock2, clock;
3729 u8 vic;
3730 const char *type;
3731
3732 /*
3733 * allow 5kHz clock difference either way to account for
3734 * the 10kHz clock resolution limit of detailed timings.
3735 */
3736 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3737 if (drm_valid_cea_vic(vic)) {
3738 type = "CEA";
3739 cea_mode = &edid_cea_modes[vic];
3740 clock1 = cea_mode->clock;
3741 clock2 = cea_mode_alternate_clock(cea_mode);
3742 } else {
3743 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3744 if (drm_valid_hdmi_vic(vic)) {
3745 type = "HDMI";
3746 cea_mode = &edid_4k_modes[vic];
3747 clock1 = cea_mode->clock;
3748 clock2 = hdmi_mode_alternate_clock(cea_mode);
3749 } else {
3750 return;
3751 }
3752 }
3753
3754 /* pick whichever is closest */
3755 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3756 clock = clock1;
3757 else
3758 clock = clock2;
3759
3760 if (mode->clock == clock)
3761 return;
3762
3763 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3764 type, vic, mode->clock, clock);
3765 mode->clock = clock;
3766 }
3767
3768 static void
3769 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3770 {
3771 u8 len = cea_db_payload_len(db);
3772
3773 if (len >= 6)
3774 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3775 if (len >= 8) {
3776 connector->latency_present[0] = db[8] >> 7;
3777 connector->latency_present[1] = (db[8] >> 6) & 1;
3778 }
3779 if (len >= 9)
3780 connector->video_latency[0] = db[9];
3781 if (len >= 10)
3782 connector->audio_latency[0] = db[10];
3783 if (len >= 11)
3784 connector->video_latency[1] = db[11];
3785 if (len >= 12)
3786 connector->audio_latency[1] = db[12];
3787
3788 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3789 "video latency %d %d, "
3790 "audio latency %d %d\n",
3791 connector->latency_present[0],
3792 connector->latency_present[1],
3793 connector->video_latency[0],
3794 connector->video_latency[1],
3795 connector->audio_latency[0],
3796 connector->audio_latency[1]);
3797 }
3798
3799 static void
3800 monitor_name(struct detailed_timing *t, void *data)
3801 {
3802 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3803 *(u8 **)data = t->data.other_data.data.str.str;
3804 }
3805
3806 static int get_monitor_name(struct edid *edid, char name[13])
3807 {
3808 char *edid_name = NULL;
3809 int mnl;
3810
3811 if (!edid || !name)
3812 return 0;
3813
3814 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3815 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3816 if (edid_name[mnl] == 0x0a)
3817 break;
3818
3819 name[mnl] = edid_name[mnl];
3820 }
3821
3822 return mnl;
3823 }
3824
3825 /**
3826 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3827 * @edid: monitor EDID information
3828 * @name: pointer to a character array to hold the name of the monitor
3829 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3830 *
3831 */
3832 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3833 {
3834 int name_length;
3835 char buf[13];
3836
3837 if (bufsize <= 0)
3838 return;
3839
3840 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3841 memcpy(name, buf, name_length);
3842 name[name_length] = '\0';
3843 }
3844 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3845
3846 /**
3847 * drm_edid_to_eld - build ELD from EDID
3848 * @connector: connector corresponding to the HDMI/DP sink
3849 * @edid: EDID to parse
3850 *
3851 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3852 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3853 */
3854 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3855 {
3856 uint8_t *eld = connector->eld;
3857 u8 *cea;
3858 u8 *db;
3859 int total_sad_count = 0;
3860 int mnl;
3861 int dbl;
3862
3863 memset(eld, 0, sizeof(connector->eld));
3864
3865 connector->latency_present[0] = false;
3866 connector->latency_present[1] = false;
3867 connector->video_latency[0] = 0;
3868 connector->audio_latency[0] = 0;
3869 connector->video_latency[1] = 0;
3870 connector->audio_latency[1] = 0;
3871
3872 if (!edid)
3873 return;
3874
3875 cea = drm_find_cea_extension(edid);
3876 if (!cea) {
3877 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3878 return;
3879 }
3880
3881 mnl = get_monitor_name(edid, eld + 20);
3882
3883 eld[4] = (cea[1] << 5) | mnl;
3884 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3885
3886 eld[0] = 2 << 3; /* ELD version: 2 */
3887
3888 eld[16] = edid->mfg_id[0];
3889 eld[17] = edid->mfg_id[1];
3890 eld[18] = edid->prod_code[0];
3891 eld[19] = edid->prod_code[1];
3892
3893 if (cea_revision(cea) >= 3) {
3894 int i, start, end;
3895
3896 if (cea_db_offsets(cea, &start, &end)) {
3897 start = 0;
3898 end = 0;
3899 }
3900
3901 for_each_cea_db(cea, i, start, end) {
3902 db = &cea[i];
3903 dbl = cea_db_payload_len(db);
3904
3905 switch (cea_db_tag(db)) {
3906 int sad_count;
3907
3908 case AUDIO_BLOCK:
3909 /* Audio Data Block, contains SADs */
3910 sad_count = min(dbl / 3, 15 - total_sad_count);
3911 if (sad_count >= 1)
3912 memcpy(eld + 20 + mnl + total_sad_count * 3,
3913 &db[1], sad_count * 3);
3914 total_sad_count += sad_count;
3915 break;
3916 case SPEAKER_BLOCK:
3917 /* Speaker Allocation Data Block */
3918 if (dbl >= 1)
3919 eld[7] = db[1];
3920 break;
3921 case VENDOR_BLOCK:
3922 /* HDMI Vendor-Specific Data Block */
3923 if (cea_db_is_hdmi_vsdb(db))
3924 drm_parse_hdmi_vsdb_audio(connector, db);
3925 break;
3926 default:
3927 break;
3928 }
3929 }
3930 }
3931 eld[5] |= total_sad_count << 4;
3932
3933 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3934 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3935 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3936 else
3937 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3938
3939 eld[DRM_ELD_BASELINE_ELD_LEN] =
3940 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3941
3942 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3943 drm_eld_size(eld), total_sad_count);
3944 }
3945 EXPORT_SYMBOL(drm_edid_to_eld);
3946
3947 /**
3948 * drm_edid_to_sad - extracts SADs from EDID
3949 * @edid: EDID to parse
3950 * @sads: pointer that will be set to the extracted SADs
3951 *
3952 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3953 *
3954 * Note: The returned pointer needs to be freed using kfree().
3955 *
3956 * Return: The number of found SADs or negative number on error.
3957 */
3958 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3959 {
3960 int count = 0;
3961 int i, start, end, dbl;
3962 u8 *cea;
3963
3964 cea = drm_find_cea_extension(edid);
3965 if (!cea) {
3966 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3967 return -ENOENT;
3968 }
3969
3970 if (cea_revision(cea) < 3) {
3971 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3972 return -ENOTSUPP;
3973 }
3974
3975 if (cea_db_offsets(cea, &start, &end)) {
3976 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3977 return -EPROTO;
3978 }
3979
3980 for_each_cea_db(cea, i, start, end) {
3981 u8 *db = &cea[i];
3982
3983 if (cea_db_tag(db) == AUDIO_BLOCK) {
3984 int j;
3985 dbl = cea_db_payload_len(db);
3986
3987 count = dbl / 3; /* SAD is 3B */
3988 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3989 if (!*sads)
3990 return -ENOMEM;
3991 for (j = 0; j < count; j++) {
3992 u8 *sad = &db[1 + j * 3];
3993
3994 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3995 (*sads)[j].channels = sad[0] & 0x7;
3996 (*sads)[j].freq = sad[1] & 0x7F;
3997 (*sads)[j].byte2 = sad[2];
3998 }
3999 break;
4000 }
4001 }
4002
4003 return count;
4004 }
4005 EXPORT_SYMBOL(drm_edid_to_sad);
4006
4007 /**
4008 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4009 * @edid: EDID to parse
4010 * @sadb: pointer to the speaker block
4011 *
4012 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4013 *
4014 * Note: The returned pointer needs to be freed using kfree().
4015 *
4016 * Return: The number of found Speaker Allocation Blocks or negative number on
4017 * error.
4018 */
4019 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4020 {
4021 int count = 0;
4022 int i, start, end, dbl;
4023 const u8 *cea;
4024
4025 cea = drm_find_cea_extension(edid);
4026 if (!cea) {
4027 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4028 return -ENOENT;
4029 }
4030
4031 if (cea_revision(cea) < 3) {
4032 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4033 return -ENOTSUPP;
4034 }
4035
4036 if (cea_db_offsets(cea, &start, &end)) {
4037 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4038 return -EPROTO;
4039 }
4040
4041 for_each_cea_db(cea, i, start, end) {
4042 const u8 *db = &cea[i];
4043
4044 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4045 dbl = cea_db_payload_len(db);
4046
4047 /* Speaker Allocation Data Block */
4048 if (dbl == 3) {
4049 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4050 if (!*sadb)
4051 return -ENOMEM;
4052 count = dbl;
4053 break;
4054 }
4055 }
4056 }
4057
4058 return count;
4059 }
4060 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4061
4062 /**
4063 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4064 * @connector: connector associated with the HDMI/DP sink
4065 * @mode: the display mode
4066 *
4067 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4068 * the sink doesn't support audio or video.
4069 */
4070 int drm_av_sync_delay(struct drm_connector *connector,
4071 const struct drm_display_mode *mode)
4072 {
4073 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4074 int a, v;
4075
4076 if (!connector->latency_present[0])
4077 return 0;
4078 if (!connector->latency_present[1])
4079 i = 0;
4080
4081 a = connector->audio_latency[i];
4082 v = connector->video_latency[i];
4083
4084 /*
4085 * HDMI/DP sink doesn't support audio or video?
4086 */
4087 if (a == 255 || v == 255)
4088 return 0;
4089
4090 /*
4091 * Convert raw EDID values to millisecond.
4092 * Treat unknown latency as 0ms.
4093 */
4094 if (a)
4095 a = min(2 * (a - 1), 500);
4096 if (v)
4097 v = min(2 * (v - 1), 500);
4098
4099 return max(v - a, 0);
4100 }
4101 EXPORT_SYMBOL(drm_av_sync_delay);
4102
4103 /**
4104 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4105 * @edid: monitor EDID information
4106 *
4107 * Parse the CEA extension according to CEA-861-B.
4108 *
4109 * Return: True if the monitor is HDMI, false if not or unknown.
4110 */
4111 bool drm_detect_hdmi_monitor(struct edid *edid)
4112 {
4113 u8 *edid_ext;
4114 int i;
4115 int start_offset, end_offset;
4116
4117 edid_ext = drm_find_cea_extension(edid);
4118 if (!edid_ext)
4119 return false;
4120
4121 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4122 return false;
4123
4124 /*
4125 * Because HDMI identifier is in Vendor Specific Block,
4126 * search it from all data blocks of CEA extension.
4127 */
4128 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4129 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4130 return true;
4131 }
4132
4133 return false;
4134 }
4135 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4136
4137 /**
4138 * drm_detect_monitor_audio - check monitor audio capability
4139 * @edid: EDID block to scan
4140 *
4141 * Monitor should have CEA extension block.
4142 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4143 * audio' only. If there is any audio extension block and supported
4144 * audio format, assume at least 'basic audio' support, even if 'basic
4145 * audio' is not defined in EDID.
4146 *
4147 * Return: True if the monitor supports audio, false otherwise.
4148 */
4149 bool drm_detect_monitor_audio(struct edid *edid)
4150 {
4151 u8 *edid_ext;
4152 int i, j;
4153 bool has_audio = false;
4154 int start_offset, end_offset;
4155
4156 edid_ext = drm_find_cea_extension(edid);
4157 if (!edid_ext)
4158 goto end;
4159
4160 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4161
4162 if (has_audio) {
4163 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4164 goto end;
4165 }
4166
4167 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4168 goto end;
4169
4170 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4171 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4172 has_audio = true;
4173 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4174 DRM_DEBUG_KMS("CEA audio format %d\n",
4175 (edid_ext[i + j] >> 3) & 0xf);
4176 goto end;
4177 }
4178 }
4179 end:
4180 return has_audio;
4181 }
4182 EXPORT_SYMBOL(drm_detect_monitor_audio);
4183
4184 /**
4185 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4186 * @edid: EDID block to scan
4187 *
4188 * Check whether the monitor reports the RGB quantization range selection
4189 * as supported. The AVI infoframe can then be used to inform the monitor
4190 * which quantization range (full or limited) is used.
4191 *
4192 * Return: True if the RGB quantization range is selectable, false otherwise.
4193 */
4194 bool drm_rgb_quant_range_selectable(struct edid *edid)
4195 {
4196 u8 *edid_ext;
4197 int i, start, end;
4198
4199 edid_ext = drm_find_cea_extension(edid);
4200 if (!edid_ext)
4201 return false;
4202
4203 if (cea_db_offsets(edid_ext, &start, &end))
4204 return false;
4205
4206 for_each_cea_db(edid_ext, i, start, end) {
4207 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4208 cea_db_payload_len(&edid_ext[i]) == 2 &&
4209 cea_db_extended_tag(&edid_ext[i]) ==
4210 EXT_VIDEO_CAPABILITY_BLOCK) {
4211 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4212 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4213 }
4214 }
4215
4216 return false;
4217 }
4218 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4219
4220 /**
4221 * drm_default_rgb_quant_range - default RGB quantization range
4222 * @mode: display mode
4223 *
4224 * Determine the default RGB quantization range for the mode,
4225 * as specified in CEA-861.
4226 *
4227 * Return: The default RGB quantization range for the mode
4228 */
4229 enum hdmi_quantization_range
4230 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4231 {
4232 /* All CEA modes other than VIC 1 use limited quantization range. */
4233 return drm_match_cea_mode(mode) > 1 ?
4234 HDMI_QUANTIZATION_RANGE_LIMITED :
4235 HDMI_QUANTIZATION_RANGE_FULL;
4236 }
4237 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4238
4239 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4240 const u8 *db)
4241 {
4242 u8 dc_mask;
4243 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4244
4245 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4246 hdmi->y420_dc_modes |= dc_mask;
4247 }
4248
4249 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4250 const u8 *hf_vsdb)
4251 {
4252 struct drm_display_info *display = &connector->display_info;
4253 struct drm_hdmi_info *hdmi = &display->hdmi;
4254
4255 if (hf_vsdb[6] & 0x80) {
4256 hdmi->scdc.supported = true;
4257 if (hf_vsdb[6] & 0x40)
4258 hdmi->scdc.read_request = true;
4259 }
4260
4261 /*
4262 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4263 * And as per the spec, three factors confirm this:
4264 * * Availability of a HF-VSDB block in EDID (check)
4265 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4266 * * SCDC support available (let's check)
4267 * Lets check it out.
4268 */
4269
4270 if (hf_vsdb[5]) {
4271 /* max clock is 5000 KHz times block value */
4272 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4273 struct drm_scdc *scdc = &hdmi->scdc;
4274
4275 if (max_tmds_clock > 340000) {
4276 display->max_tmds_clock = max_tmds_clock;
4277 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4278 display->max_tmds_clock);
4279 }
4280
4281 if (scdc->supported) {
4282 scdc->scrambling.supported = true;
4283
4284 /* Few sinks support scrambling for cloks < 340M */
4285 if ((hf_vsdb[6] & 0x8))
4286 scdc->scrambling.low_rates = true;
4287 }
4288 }
4289
4290 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4291 }
4292
4293 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4294 const u8 *hdmi)
4295 {
4296 struct drm_display_info *info = &connector->display_info;
4297 unsigned int dc_bpc = 0;
4298
4299 /* HDMI supports at least 8 bpc */
4300 info->bpc = 8;
4301
4302 if (cea_db_payload_len(hdmi) < 6)
4303 return;
4304
4305 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4306 dc_bpc = 10;
4307 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4308 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4309 connector->name);
4310 }
4311
4312 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4313 dc_bpc = 12;
4314 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4315 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4316 connector->name);
4317 }
4318
4319 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4320 dc_bpc = 16;
4321 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4322 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4323 connector->name);
4324 }
4325
4326 if (dc_bpc == 0) {
4327 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4328 connector->name);
4329 return;
4330 }
4331
4332 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4333 connector->name, dc_bpc);
4334 info->bpc = dc_bpc;
4335
4336 /*
4337 * Deep color support mandates RGB444 support for all video
4338 * modes and forbids YCRCB422 support for all video modes per
4339 * HDMI 1.3 spec.
4340 */
4341 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4342
4343 /* YCRCB444 is optional according to spec. */
4344 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4345 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4346 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4347 connector->name);
4348 }
4349
4350 /*
4351 * Spec says that if any deep color mode is supported at all,
4352 * then deep color 36 bit must be supported.
4353 */
4354 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4355 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4356 connector->name);
4357 }
4358 }
4359
4360 static void
4361 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4362 {
4363 struct drm_display_info *info = &connector->display_info;
4364 u8 len = cea_db_payload_len(db);
4365
4366 if (len >= 6)
4367 info->dvi_dual = db[6] & 1;
4368 if (len >= 7)
4369 info->max_tmds_clock = db[7] * 5000;
4370
4371 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4372 "max TMDS clock %d kHz\n",
4373 info->dvi_dual,
4374 info->max_tmds_clock);
4375
4376 drm_parse_hdmi_deep_color_info(connector, db);
4377 }
4378
4379 static void drm_parse_cea_ext(struct drm_connector *connector,
4380 const struct edid *edid)
4381 {
4382 struct drm_display_info *info = &connector->display_info;
4383 const u8 *edid_ext;
4384 int i, start, end;
4385
4386 edid_ext = drm_find_cea_extension(edid);
4387 if (!edid_ext)
4388 return;
4389
4390 info->cea_rev = edid_ext[1];
4391
4392 /* The existence of a CEA block should imply RGB support */
4393 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4394 if (edid_ext[3] & EDID_CEA_YCRCB444)
4395 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4396 if (edid_ext[3] & EDID_CEA_YCRCB422)
4397 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4398
4399 if (cea_db_offsets(edid_ext, &start, &end))
4400 return;
4401
4402 for_each_cea_db(edid_ext, i, start, end) {
4403 const u8 *db = &edid_ext[i];
4404
4405 if (cea_db_is_hdmi_vsdb(db))
4406 drm_parse_hdmi_vsdb_video(connector, db);
4407 if (cea_db_is_hdmi_forum_vsdb(db))
4408 drm_parse_hdmi_forum_vsdb(connector, db);
4409 if (cea_db_is_y420cmdb(db))
4410 drm_parse_y420cmdb_bitmap(connector, db);
4411 }
4412 }
4413
4414 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
4415 * all of the values which would have been set from EDID
4416 */
4417 void
4418 drm_reset_display_info(struct drm_connector *connector)
4419 {
4420 struct drm_display_info *info = &connector->display_info;
4421
4422 info->width_mm = 0;
4423 info->height_mm = 0;
4424
4425 info->bpc = 0;
4426 info->color_formats = 0;
4427 info->cea_rev = 0;
4428 info->max_tmds_clock = 0;
4429 info->dvi_dual = false;
4430
4431 info->non_desktop = 0;
4432 }
4433 EXPORT_SYMBOL_GPL(drm_reset_display_info);
4434
4435 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
4436 {
4437 struct drm_display_info *info = &connector->display_info;
4438
4439 u32 quirks = edid_get_quirks(edid);
4440
4441 info->width_mm = edid->width_cm * 10;
4442 info->height_mm = edid->height_cm * 10;
4443
4444 /* driver figures it out in this case */
4445 info->bpc = 0;
4446 info->color_formats = 0;
4447 info->cea_rev = 0;
4448 info->max_tmds_clock = 0;
4449 info->dvi_dual = false;
4450
4451 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
4452
4453 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
4454
4455 if (edid->revision < 3)
4456 return quirks;
4457
4458 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4459 return quirks;
4460
4461 drm_parse_cea_ext(connector, edid);
4462
4463 /*
4464 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4465 *
4466 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4467 * tells us to assume 8 bpc color depth if the EDID doesn't have
4468 * extensions which tell otherwise.
4469 */
4470 if ((info->bpc == 0) && (edid->revision < 4) &&
4471 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4472 info->bpc = 8;
4473 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4474 connector->name, info->bpc);
4475 }
4476
4477 /* Only defined for 1.4 with digital displays */
4478 if (edid->revision < 4)
4479 return quirks;
4480
4481 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4482 case DRM_EDID_DIGITAL_DEPTH_6:
4483 info->bpc = 6;
4484 break;
4485 case DRM_EDID_DIGITAL_DEPTH_8:
4486 info->bpc = 8;
4487 break;
4488 case DRM_EDID_DIGITAL_DEPTH_10:
4489 info->bpc = 10;
4490 break;
4491 case DRM_EDID_DIGITAL_DEPTH_12:
4492 info->bpc = 12;
4493 break;
4494 case DRM_EDID_DIGITAL_DEPTH_14:
4495 info->bpc = 14;
4496 break;
4497 case DRM_EDID_DIGITAL_DEPTH_16:
4498 info->bpc = 16;
4499 break;
4500 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4501 default:
4502 info->bpc = 0;
4503 break;
4504 }
4505
4506 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4507 connector->name, info->bpc);
4508
4509 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4510 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4511 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4512 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4513 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4514 return quirks;
4515 }
4516 EXPORT_SYMBOL_GPL(drm_add_display_info);
4517
4518 static int validate_displayid(u8 *displayid, int length, int idx)
4519 {
4520 int i;
4521 u8 csum = 0;
4522 struct displayid_hdr *base;
4523
4524 base = (struct displayid_hdr *)&displayid[idx];
4525
4526 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4527 base->rev, base->bytes, base->prod_id, base->ext_count);
4528
4529 if (base->bytes + 5 > length - idx)
4530 return -EINVAL;
4531 for (i = idx; i <= base->bytes + 5; i++) {
4532 csum += displayid[i];
4533 }
4534 if (csum) {
4535 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4536 return -EINVAL;
4537 }
4538 return 0;
4539 }
4540
4541 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4542 struct displayid_detailed_timings_1 *timings)
4543 {
4544 struct drm_display_mode *mode;
4545 unsigned pixel_clock = (timings->pixel_clock[0] |
4546 (timings->pixel_clock[1] << 8) |
4547 (timings->pixel_clock[2] << 16));
4548 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4549 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4550 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4551 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4552 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4553 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4554 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4555 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4556 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4557 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4558 mode = drm_mode_create(dev);
4559 if (!mode)
4560 return NULL;
4561
4562 mode->clock = pixel_clock * 10;
4563 mode->hdisplay = hactive;
4564 mode->hsync_start = mode->hdisplay + hsync;
4565 mode->hsync_end = mode->hsync_start + hsync_width;
4566 mode->htotal = mode->hdisplay + hblank;
4567
4568 mode->vdisplay = vactive;
4569 mode->vsync_start = mode->vdisplay + vsync;
4570 mode->vsync_end = mode->vsync_start + vsync_width;
4571 mode->vtotal = mode->vdisplay + vblank;
4572
4573 mode->flags = 0;
4574 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4575 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4576 mode->type = DRM_MODE_TYPE_DRIVER;
4577
4578 if (timings->flags & 0x80)
4579 mode->type |= DRM_MODE_TYPE_PREFERRED;
4580 mode->vrefresh = drm_mode_vrefresh(mode);
4581 drm_mode_set_name(mode);
4582
4583 return mode;
4584 }
4585
4586 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4587 struct displayid_block *block)
4588 {
4589 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4590 int i;
4591 int num_timings;
4592 struct drm_display_mode *newmode;
4593 int num_modes = 0;
4594 /* blocks must be multiple of 20 bytes length */
4595 if (block->num_bytes % 20)
4596 return 0;
4597
4598 num_timings = block->num_bytes / 20;
4599 for (i = 0; i < num_timings; i++) {
4600 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4601
4602 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4603 if (!newmode)
4604 continue;
4605
4606 drm_mode_probed_add(connector, newmode);
4607 num_modes++;
4608 }
4609 return num_modes;
4610 }
4611
4612 static int add_displayid_detailed_modes(struct drm_connector *connector,
4613 struct edid *edid)
4614 {
4615 u8 *displayid;
4616 int ret;
4617 int idx = 1;
4618 int length = EDID_LENGTH;
4619 struct displayid_block *block;
4620 int num_modes = 0;
4621
4622 displayid = drm_find_displayid_extension(edid);
4623 if (!displayid)
4624 return 0;
4625
4626 ret = validate_displayid(displayid, length, idx);
4627 if (ret)
4628 return 0;
4629
4630 idx += sizeof(struct displayid_hdr);
4631 while (block = (struct displayid_block *)&displayid[idx],
4632 idx + sizeof(struct displayid_block) <= length &&
4633 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4634 block->num_bytes > 0) {
4635 idx += block->num_bytes + sizeof(struct displayid_block);
4636 switch (block->tag) {
4637 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4638 num_modes += add_displayid_detailed_1_modes(connector, block);
4639 break;
4640 }
4641 }
4642 return num_modes;
4643 }
4644
4645 /**
4646 * drm_add_edid_modes - add modes from EDID data, if available
4647 * @connector: connector we're probing
4648 * @edid: EDID data
4649 *
4650 * Add the specified modes to the connector's mode list. Also fills out the
4651 * &drm_display_info structure in @connector with any information which can be
4652 * derived from the edid.
4653 *
4654 * Return: The number of modes added or 0 if we couldn't find any.
4655 */
4656 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4657 {
4658 int num_modes = 0;
4659 u32 quirks;
4660
4661 if (edid == NULL) {
4662 return 0;
4663 }
4664 if (!drm_edid_is_valid(edid)) {
4665 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4666 connector->name);
4667 return 0;
4668 }
4669
4670 /*
4671 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4672 * To avoid multiple parsing of same block, lets parse that map
4673 * from sink info, before parsing CEA modes.
4674 */
4675 quirks = drm_add_display_info(connector, edid);
4676
4677 /*
4678 * EDID spec says modes should be preferred in this order:
4679 * - preferred detailed mode
4680 * - other detailed modes from base block
4681 * - detailed modes from extension blocks
4682 * - CVT 3-byte code modes
4683 * - standard timing codes
4684 * - established timing codes
4685 * - modes inferred from GTF or CVT range information
4686 *
4687 * We get this pretty much right.
4688 *
4689 * XXX order for additional mode types in extension blocks?
4690 */
4691 num_modes += add_detailed_modes(connector, edid, quirks);
4692 num_modes += add_cvt_modes(connector, edid);
4693 num_modes += add_standard_modes(connector, edid);
4694 num_modes += add_established_modes(connector, edid);
4695 num_modes += add_cea_modes(connector, edid);
4696 num_modes += add_alternate_cea_modes(connector, edid);
4697 num_modes += add_displayid_detailed_modes(connector, edid);
4698 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4699 num_modes += add_inferred_modes(connector, edid);
4700
4701 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4702 edid_fixup_preferred(connector, quirks);
4703
4704 if (quirks & EDID_QUIRK_FORCE_6BPC)
4705 connector->display_info.bpc = 6;
4706
4707 if (quirks & EDID_QUIRK_FORCE_8BPC)
4708 connector->display_info.bpc = 8;
4709
4710 if (quirks & EDID_QUIRK_FORCE_10BPC)
4711 connector->display_info.bpc = 10;
4712
4713 if (quirks & EDID_QUIRK_FORCE_12BPC)
4714 connector->display_info.bpc = 12;
4715
4716 return num_modes;
4717 }
4718 EXPORT_SYMBOL(drm_add_edid_modes);
4719
4720 /**
4721 * drm_add_modes_noedid - add modes for the connectors without EDID
4722 * @connector: connector we're probing
4723 * @hdisplay: the horizontal display limit
4724 * @vdisplay: the vertical display limit
4725 *
4726 * Add the specified modes to the connector's mode list. Only when the
4727 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4728 *
4729 * Return: The number of modes added or 0 if we couldn't find any.
4730 */
4731 int drm_add_modes_noedid(struct drm_connector *connector,
4732 int hdisplay, int vdisplay)
4733 {
4734 int i, count, num_modes = 0;
4735 struct drm_display_mode *mode;
4736 struct drm_device *dev = connector->dev;
4737
4738 count = ARRAY_SIZE(drm_dmt_modes);
4739 if (hdisplay < 0)
4740 hdisplay = 0;
4741 if (vdisplay < 0)
4742 vdisplay = 0;
4743
4744 for (i = 0; i < count; i++) {
4745 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4746 if (hdisplay && vdisplay) {
4747 /*
4748 * Only when two are valid, they will be used to check
4749 * whether the mode should be added to the mode list of
4750 * the connector.
4751 */
4752 if (ptr->hdisplay > hdisplay ||
4753 ptr->vdisplay > vdisplay)
4754 continue;
4755 }
4756 if (drm_mode_vrefresh(ptr) > 61)
4757 continue;
4758 mode = drm_mode_duplicate(dev, ptr);
4759 if (mode) {
4760 drm_mode_probed_add(connector, mode);
4761 num_modes++;
4762 }
4763 }
4764 return num_modes;
4765 }
4766 EXPORT_SYMBOL(drm_add_modes_noedid);
4767
4768 /**
4769 * drm_set_preferred_mode - Sets the preferred mode of a connector
4770 * @connector: connector whose mode list should be processed
4771 * @hpref: horizontal resolution of preferred mode
4772 * @vpref: vertical resolution of preferred mode
4773 *
4774 * Marks a mode as preferred if it matches the resolution specified by @hpref
4775 * and @vpref.
4776 */
4777 void drm_set_preferred_mode(struct drm_connector *connector,
4778 int hpref, int vpref)
4779 {
4780 struct drm_display_mode *mode;
4781
4782 list_for_each_entry(mode, &connector->probed_modes, head) {
4783 if (mode->hdisplay == hpref &&
4784 mode->vdisplay == vpref)
4785 mode->type |= DRM_MODE_TYPE_PREFERRED;
4786 }
4787 }
4788 EXPORT_SYMBOL(drm_set_preferred_mode);
4789
4790 /**
4791 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4792 * data from a DRM display mode
4793 * @frame: HDMI AVI infoframe
4794 * @mode: DRM display mode
4795 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4796 *
4797 * Return: 0 on success or a negative error code on failure.
4798 */
4799 int
4800 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4801 const struct drm_display_mode *mode,
4802 bool is_hdmi2_sink)
4803 {
4804 int err;
4805
4806 if (!frame || !mode)
4807 return -EINVAL;
4808
4809 err = hdmi_avi_infoframe_init(frame);
4810 if (err < 0)
4811 return err;
4812
4813 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4814 frame->pixel_repeat = 1;
4815
4816 frame->video_code = drm_match_cea_mode(mode);
4817
4818 /*
4819 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4820 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4821 * have to make sure we dont break HDMI 1.4 sinks.
4822 */
4823 if (!is_hdmi2_sink && frame->video_code > 64)
4824 frame->video_code = 0;
4825
4826 /*
4827 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4828 * we should send its VIC in vendor infoframes, else send the
4829 * VIC in AVI infoframes. Lets check if this mode is present in
4830 * HDMI 1.4b 4K modes
4831 */
4832 if (frame->video_code) {
4833 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4834 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4835
4836 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4837 frame->video_code = 0;
4838 }
4839
4840 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4841
4842 /*
4843 * Populate picture aspect ratio from either
4844 * user input (if specified) or from the CEA mode list.
4845 */
4846 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4847 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4848 frame->picture_aspect = mode->picture_aspect_ratio;
4849 else if (frame->video_code > 0)
4850 frame->picture_aspect = drm_get_cea_aspect_ratio(
4851 frame->video_code);
4852
4853 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4854 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4855
4856 return 0;
4857 }
4858 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4859
4860 /**
4861 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4862 * quantization range information
4863 * @frame: HDMI AVI infoframe
4864 * @mode: DRM display mode
4865 * @rgb_quant_range: RGB quantization range (Q)
4866 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4867 */
4868 void
4869 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4870 const struct drm_display_mode *mode,
4871 enum hdmi_quantization_range rgb_quant_range,
4872 bool rgb_quant_range_selectable,
4873 bool is_hdmi2_sink)
4874 {
4875 /*
4876 * CEA-861:
4877 * "A Source shall not send a non-zero Q value that does not correspond
4878 * to the default RGB Quantization Range for the transmitted Picture
4879 * unless the Sink indicates support for the Q bit in a Video
4880 * Capabilities Data Block."
4881 *
4882 * HDMI 2.0 recommends sending non-zero Q when it does match the
4883 * default RGB quantization range for the mode, even when QS=0.
4884 */
4885 if (rgb_quant_range_selectable ||
4886 rgb_quant_range == drm_default_rgb_quant_range(mode))
4887 frame->quantization_range = rgb_quant_range;
4888 else
4889 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4890
4891 /*
4892 * CEA-861-F:
4893 * "When transmitting any RGB colorimetry, the Source should set the
4894 * YQ-field to match the RGB Quantization Range being transmitted
4895 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4896 * set YQ=1) and the Sink shall ignore the YQ-field."
4897 *
4898 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4899 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4900 * good way to tell which version of CEA-861 the sink supports, so
4901 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4902 * on on CEA-861-F.
4903 */
4904 if (!is_hdmi2_sink ||
4905 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4906 frame->ycc_quantization_range =
4907 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4908 else
4909 frame->ycc_quantization_range =
4910 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4911 }
4912 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4913
4914 static enum hdmi_3d_structure
4915 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4916 {
4917 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4918
4919 switch (layout) {
4920 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4921 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4922 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4923 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4924 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4925 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4926 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4927 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4928 case DRM_MODE_FLAG_3D_L_DEPTH:
4929 return HDMI_3D_STRUCTURE_L_DEPTH;
4930 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4931 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4932 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4933 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4934 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4935 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4936 default:
4937 return HDMI_3D_STRUCTURE_INVALID;
4938 }
4939 }
4940
4941 /**
4942 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4943 * data from a DRM display mode
4944 * @frame: HDMI vendor infoframe
4945 * @mode: DRM display mode
4946 *
4947 * Note that there's is a need to send HDMI vendor infoframes only when using a
4948 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4949 * function will return -EINVAL, error that can be safely ignored.
4950 *
4951 * Return: 0 on success or a negative error code on failure.
4952 */
4953 int
4954 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4955 const struct drm_display_mode *mode)
4956 {
4957 int err;
4958 u32 s3d_flags;
4959 u8 vic;
4960
4961 if (!frame || !mode)
4962 return -EINVAL;
4963
4964 vic = drm_match_hdmi_mode(mode);
4965 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4966
4967 if (!vic && !s3d_flags)
4968 return -EINVAL;
4969
4970 if (vic && s3d_flags)
4971 return -EINVAL;
4972
4973 err = hdmi_vendor_infoframe_init(frame);
4974 if (err < 0)
4975 return err;
4976
4977 if (vic)
4978 frame->vic = vic;
4979 else
4980 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4981
4982 return 0;
4983 }
4984 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4985
4986 static int drm_parse_tiled_block(struct drm_connector *connector,
4987 struct displayid_block *block)
4988 {
4989 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4990 u16 w, h;
4991 u8 tile_v_loc, tile_h_loc;
4992 u8 num_v_tile, num_h_tile;
4993 struct drm_tile_group *tg;
4994
4995 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4996 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4997
4998 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4999 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5000 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5001 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5002
5003 connector->has_tile = true;
5004 if (tile->tile_cap & 0x80)
5005 connector->tile_is_single_monitor = true;
5006
5007 connector->num_h_tile = num_h_tile + 1;
5008 connector->num_v_tile = num_v_tile + 1;
5009 connector->tile_h_loc = tile_h_loc;
5010 connector->tile_v_loc = tile_v_loc;
5011 connector->tile_h_size = w + 1;
5012 connector->tile_v_size = h + 1;
5013
5014 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5015 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5016 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5017 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5018 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5019
5020 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5021 if (!tg) {
5022 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5023 }
5024 if (!tg)
5025 return -ENOMEM;
5026
5027 if (connector->tile_group != tg) {
5028 /* if we haven't got a pointer,
5029 take the reference, drop ref to old tile group */
5030 if (connector->tile_group) {
5031 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5032 }
5033 connector->tile_group = tg;
5034 } else
5035 /* if same tile group, then release the ref we just took. */
5036 drm_mode_put_tile_group(connector->dev, tg);
5037 return 0;
5038 }
5039
5040 static int drm_parse_display_id(struct drm_connector *connector,
5041 u8 *displayid, int length,
5042 bool is_edid_extension)
5043 {
5044 /* if this is an EDID extension the first byte will be 0x70 */
5045 int idx = 0;
5046 struct displayid_block *block;
5047 int ret;
5048
5049 if (is_edid_extension)
5050 idx = 1;
5051
5052 ret = validate_displayid(displayid, length, idx);
5053 if (ret)
5054 return ret;
5055
5056 idx += sizeof(struct displayid_hdr);
5057 while (block = (struct displayid_block *)&displayid[idx],
5058 idx + sizeof(struct displayid_block) <= length &&
5059 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5060 block->num_bytes > 0) {
5061 idx += block->num_bytes + sizeof(struct displayid_block);
5062 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5063 block->tag, block->rev, block->num_bytes);
5064
5065 switch (block->tag) {
5066 case DATA_BLOCK_TILED_DISPLAY:
5067 ret = drm_parse_tiled_block(connector, block);
5068 if (ret)
5069 return ret;
5070 break;
5071 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5072 /* handled in mode gathering code. */
5073 break;
5074 default:
5075 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5076 break;
5077 }
5078 }
5079 return 0;
5080 }
5081
5082 static void drm_get_displayid(struct drm_connector *connector,
5083 struct edid *edid)
5084 {
5085 void *displayid = NULL;
5086 int ret;
5087 connector->has_tile = false;
5088 displayid = drm_find_displayid_extension(edid);
5089 if (!displayid) {
5090 /* drop reference to any tile group we had */
5091 goto out_drop_ref;
5092 }
5093
5094 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5095 if (ret < 0)
5096 goto out_drop_ref;
5097 if (!connector->has_tile)
5098 goto out_drop_ref;
5099 return;
5100 out_drop_ref:
5101 if (connector->tile_group) {
5102 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5103 connector->tile_group = NULL;
5104 }
5105 return;
5106 }
DragonFly BSD