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drm/linux: Implement tasklets
[dragonfly.git] / sys / dev / drm / drm_edid.c
blobe642656c80167abaf9cad117839ae85423a69a5c
1 /*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30 #include <linux/kernel.h>
31 #include <linux/hdmi.h>
32 #include <linux/i2c.h>
33 #include <linux/module.h>
34 #include <drm/drmP.h>
35 #include <drm/drm_edid.h>
36 #include <linux/string.h>
37
38 #include <bus/iicbus/iic.h>
39 #include <bus/iicbus/iiconf.h>
40 #include "iicbus_if.h"
41
42 #define version_greater(edid, maj, min) \
43 (((edid)->version > (maj)) || \
44 ((edid)->version == (maj) && (edid)->revision > (min)))
45
46 #define EDID_EST_TIMINGS 16
47 #define EDID_STD_TIMINGS 8
48 #define EDID_DETAILED_TIMINGS 4
49
50 /*
51 * EDID blocks out in the wild have a variety of bugs, try to collect
52 * them here (note that userspace may work around broken monitors first,
53 * but fixes should make their way here so that the kernel "just works"
54 * on as many displays as possible).
55 */
56
57 /* First detailed mode wrong, use largest 60Hz mode */
58 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
59 /* Reported 135MHz pixel clock is too high, needs adjustment */
60 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
61 /* Prefer the largest mode at 75 Hz */
62 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
63 /* Detail timing is in cm not mm */
64 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
65 /* Detailed timing descriptors have bogus size values, so just take the
66 * maximum size and use that.
67 */
68 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
69 /* Monitor forgot to set the first detailed is preferred bit. */
70 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
71 /* use +hsync +vsync for detailed mode */
72 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
73 /* Force reduced-blanking timings for detailed modes */
74 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
75 /* Force 8bpc */
76 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
77 /* Force 12bpc */
78 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
79
80 struct detailed_mode_closure {
81 struct drm_connector *connector;
82 struct edid *edid;
83 bool preferred;
84 u32 quirks;
85 int modes;
86 };
87
88 #define LEVEL_DMT 0
89 #define LEVEL_GTF 1
90 #define LEVEL_GTF2 2
91 #define LEVEL_CVT 3
92
93 static struct edid_quirk {
94 char vendor[4];
95 int product_id;
96 u32 quirks;
97 } edid_quirk_list[] = {
98 /* Acer AL1706 */
99 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
100 /* Acer F51 */
101 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
102 /* Unknown Acer */
103 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
104
105 /* Belinea 10 15 55 */
106 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
107 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
108
109 /* Envision Peripherals, Inc. EN-7100e */
110 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
111 /* Envision EN2028 */
112 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
113
114 /* Funai Electronics PM36B */
115 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
116 EDID_QUIRK_DETAILED_IN_CM },
117
118 /* LG Philips LCD LP154W01-A5 */
119 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
120 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
121
122 /* Philips 107p5 CRT */
123 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
124
125 /* Proview AY765C */
126 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
127
128 /* Samsung SyncMaster 205BW. Note: irony */
129 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
130 /* Samsung SyncMaster 22[5-6]BW */
131 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
132 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
133
134 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
135 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
136
137 /* ViewSonic VA2026w */
138 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
139
140 /* Medion MD 30217 PG */
141 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
142
143 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
144 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
145 };
146
147 /*
148 * Autogenerated from the DMT spec.
149 * This table is copied from xfree86/modes/xf86EdidModes.c.
150 */
151 static const struct drm_display_mode drm_dmt_modes[] = {
152 /* 0x01 - 640x350@85Hz */
153 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
154 736, 832, 0, 350, 382, 385, 445, 0,
155 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
156 /* 0x02 - 640x400@85Hz */
157 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
158 736, 832, 0, 400, 401, 404, 445, 0,
159 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
160 /* 0x03 - 720x400@85Hz */
161 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
162 828, 936, 0, 400, 401, 404, 446, 0,
163 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
164 /* 0x04 - 640x480@60Hz */
165 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
166 752, 800, 0, 480, 490, 492, 525, 0,
167 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
168 /* 0x05 - 640x480@72Hz */
169 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
170 704, 832, 0, 480, 489, 492, 520, 0,
171 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
172 /* 0x06 - 640x480@75Hz */
173 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
174 720, 840, 0, 480, 481, 484, 500, 0,
175 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
176 /* 0x07 - 640x480@85Hz */
177 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
178 752, 832, 0, 480, 481, 484, 509, 0,
179 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
180 /* 0x08 - 800x600@56Hz */
181 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
182 896, 1024, 0, 600, 601, 603, 625, 0,
183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
184 /* 0x09 - 800x600@60Hz */
185 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
186 968, 1056, 0, 600, 601, 605, 628, 0,
187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
188 /* 0x0a - 800x600@72Hz */
189 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
190 976, 1040, 0, 600, 637, 643, 666, 0,
191 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
192 /* 0x0b - 800x600@75Hz */
193 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
194 896, 1056, 0, 600, 601, 604, 625, 0,
195 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
196 /* 0x0c - 800x600@85Hz */
197 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
198 896, 1048, 0, 600, 601, 604, 631, 0,
199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
200 /* 0x0d - 800x600@120Hz RB */
201 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
202 880, 960, 0, 600, 603, 607, 636, 0,
203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
204 /* 0x0e - 848x480@60Hz */
205 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
206 976, 1088, 0, 480, 486, 494, 517, 0,
207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
208 /* 0x0f - 1024x768@43Hz, interlace */
209 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
210 1208, 1264, 0, 768, 768, 776, 817, 0,
211 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
212 DRM_MODE_FLAG_INTERLACE) },
213 /* 0x10 - 1024x768@60Hz */
214 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
215 1184, 1344, 0, 768, 771, 777, 806, 0,
216 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
217 /* 0x11 - 1024x768@70Hz */
218 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
219 1184, 1328, 0, 768, 771, 777, 806, 0,
220 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
221 /* 0x12 - 1024x768@75Hz */
222 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
223 1136, 1312, 0, 768, 769, 772, 800, 0,
224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
225 /* 0x13 - 1024x768@85Hz */
226 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
227 1168, 1376, 0, 768, 769, 772, 808, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
229 /* 0x14 - 1024x768@120Hz RB */
230 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
231 1104, 1184, 0, 768, 771, 775, 813, 0,
232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
233 /* 0x15 - 1152x864@75Hz */
234 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
235 1344, 1600, 0, 864, 865, 868, 900, 0,
236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x55 - 1280x720@60Hz */
238 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
239 1430, 1650, 0, 720, 725, 730, 750, 0,
240 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
241 /* 0x16 - 1280x768@60Hz RB */
242 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
243 1360, 1440, 0, 768, 771, 778, 790, 0,
244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x17 - 1280x768@60Hz */
246 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
247 1472, 1664, 0, 768, 771, 778, 798, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
249 /* 0x18 - 1280x768@75Hz */
250 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
251 1488, 1696, 0, 768, 771, 778, 805, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
253 /* 0x19 - 1280x768@85Hz */
254 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
255 1496, 1712, 0, 768, 771, 778, 809, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x1a - 1280x768@120Hz RB */
258 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
259 1360, 1440, 0, 768, 771, 778, 813, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
261 /* 0x1b - 1280x800@60Hz RB */
262 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
263 1360, 1440, 0, 800, 803, 809, 823, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
265 /* 0x1c - 1280x800@60Hz */
266 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
267 1480, 1680, 0, 800, 803, 809, 831, 0,
268 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x1d - 1280x800@75Hz */
270 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
271 1488, 1696, 0, 800, 803, 809, 838, 0,
272 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x1e - 1280x800@85Hz */
274 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
275 1496, 1712, 0, 800, 803, 809, 843, 0,
276 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
277 /* 0x1f - 1280x800@120Hz RB */
278 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
279 1360, 1440, 0, 800, 803, 809, 847, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
281 /* 0x20 - 1280x960@60Hz */
282 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
283 1488, 1800, 0, 960, 961, 964, 1000, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
285 /* 0x21 - 1280x960@85Hz */
286 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
287 1504, 1728, 0, 960, 961, 964, 1011, 0,
288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
289 /* 0x22 - 1280x960@120Hz RB */
290 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
291 1360, 1440, 0, 960, 963, 967, 1017, 0,
292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
293 /* 0x23 - 1280x1024@60Hz */
294 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
295 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
296 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
297 /* 0x24 - 1280x1024@75Hz */
298 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
299 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
300 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
301 /* 0x25 - 1280x1024@85Hz */
302 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
303 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
305 /* 0x26 - 1280x1024@120Hz RB */
306 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
307 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
309 /* 0x27 - 1360x768@60Hz */
310 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
311 1536, 1792, 0, 768, 771, 777, 795, 0,
312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
313 /* 0x28 - 1360x768@120Hz RB */
314 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
315 1440, 1520, 0, 768, 771, 776, 813, 0,
316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
317 /* 0x51 - 1366x768@60Hz */
318 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
319 1579, 1792, 0, 768, 771, 774, 798, 0,
320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
321 /* 0x56 - 1366x768@60Hz */
322 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
323 1436, 1500, 0, 768, 769, 772, 800, 0,
324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
325 /* 0x29 - 1400x1050@60Hz RB */
326 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
327 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
329 /* 0x2a - 1400x1050@60Hz */
330 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
331 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
333 /* 0x2b - 1400x1050@75Hz */
334 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
335 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
337 /* 0x2c - 1400x1050@85Hz */
338 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
339 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
340 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
341 /* 0x2d - 1400x1050@120Hz RB */
342 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
343 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
345 /* 0x2e - 1440x900@60Hz RB */
346 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
347 1520, 1600, 0, 900, 903, 909, 926, 0,
348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
349 /* 0x2f - 1440x900@60Hz */
350 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
351 1672, 1904, 0, 900, 903, 909, 934, 0,
352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
353 /* 0x30 - 1440x900@75Hz */
354 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
355 1688, 1936, 0, 900, 903, 909, 942, 0,
356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
357 /* 0x31 - 1440x900@85Hz */
358 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
359 1696, 1952, 0, 900, 903, 909, 948, 0,
360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
361 /* 0x32 - 1440x900@120Hz RB */
362 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
363 1520, 1600, 0, 900, 903, 909, 953, 0,
364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
365 /* 0x53 - 1600x900@60Hz */
366 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
367 1704, 1800, 0, 900, 901, 904, 1000, 0,
368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
369 /* 0x33 - 1600x1200@60Hz */
370 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
371 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
373 /* 0x34 - 1600x1200@65Hz */
374 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
375 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
377 /* 0x35 - 1600x1200@70Hz */
378 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
379 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
381 /* 0x36 - 1600x1200@75Hz */
382 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
383 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
385 /* 0x37 - 1600x1200@85Hz */
386 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
387 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
389 /* 0x38 - 1600x1200@120Hz RB */
390 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
391 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
393 /* 0x39 - 1680x1050@60Hz RB */
394 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
395 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
397 /* 0x3a - 1680x1050@60Hz */
398 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
399 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
400 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
401 /* 0x3b - 1680x1050@75Hz */
402 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
403 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
404 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
405 /* 0x3c - 1680x1050@85Hz */
406 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
407 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
408 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
409 /* 0x3d - 1680x1050@120Hz RB */
410 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
411 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
413 /* 0x3e - 1792x1344@60Hz */
414 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
415 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
417 /* 0x3f - 1792x1344@75Hz */
418 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
419 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
421 /* 0x40 - 1792x1344@120Hz RB */
422 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
423 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
425 /* 0x41 - 1856x1392@60Hz */
426 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
427 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
428 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
429 /* 0x42 - 1856x1392@75Hz */
430 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
431 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
433 /* 0x43 - 1856x1392@120Hz RB */
434 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
435 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
437 /* 0x52 - 1920x1080@60Hz */
438 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
439 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
441 /* 0x44 - 1920x1200@60Hz RB */
442 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
443 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
445 /* 0x45 - 1920x1200@60Hz */
446 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
447 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
448 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
449 /* 0x46 - 1920x1200@75Hz */
450 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
451 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
452 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
453 /* 0x47 - 1920x1200@85Hz */
454 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
455 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
457 /* 0x48 - 1920x1200@120Hz RB */
458 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
459 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
461 /* 0x49 - 1920x1440@60Hz */
462 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
463 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
465 /* 0x4a - 1920x1440@75Hz */
466 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
467 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
468 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
469 /* 0x4b - 1920x1440@120Hz RB */
470 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
471 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
473 /* 0x54 - 2048x1152@60Hz */
474 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
475 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
477 /* 0x4c - 2560x1600@60Hz RB */
478 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
479 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
481 /* 0x4d - 2560x1600@60Hz */
482 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
483 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
485 /* 0x4e - 2560x1600@75Hz */
486 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
487 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
489 /* 0x4f - 2560x1600@85Hz */
490 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
491 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
492 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
493 /* 0x50 - 2560x1600@120Hz RB */
494 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
495 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
497 /* 0x57 - 4096x2160@60Hz RB */
498 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
499 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
501 /* 0x58 - 4096x2160@59.94Hz RB */
502 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
503 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
505 };
506
507 /*
508 * These more or less come from the DMT spec. The 720x400 modes are
509 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
510 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
511 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
512 * mode.
513 *
514 * The DMT modes have been fact-checked; the rest are mild guesses.
515 */
516 static const struct drm_display_mode edid_est_modes[] = {
517 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
518 968, 1056, 0, 600, 601, 605, 628, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
520 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
521 896, 1024, 0, 600, 601, 603, 625, 0,
522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
523 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
524 720, 840, 0, 480, 481, 484, 500, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
526 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
527 704, 832, 0, 480, 489, 492, 520, 0,
528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
529 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
530 768, 864, 0, 480, 483, 486, 525, 0,
531 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
532 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
533 752, 800, 0, 480, 490, 492, 525, 0,
534 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
535 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
536 846, 900, 0, 400, 421, 423, 449, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
538 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
539 846, 900, 0, 400, 412, 414, 449, 0,
540 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
541 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
542 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
543 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
544 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
545 1136, 1312, 0, 768, 769, 772, 800, 0,
546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
547 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
548 1184, 1328, 0, 768, 771, 777, 806, 0,
549 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
550 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
551 1184, 1344, 0, 768, 771, 777, 806, 0,
552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
553 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
554 1208, 1264, 0, 768, 768, 776, 817, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
556 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
557 928, 1152, 0, 624, 625, 628, 667, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
559 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
560 896, 1056, 0, 600, 601, 604, 625, 0,
561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
562 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
563 976, 1040, 0, 600, 637, 643, 666, 0,
564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
565 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
566 1344, 1600, 0, 864, 865, 868, 900, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
568 };
569
570 struct minimode {
571 short w;
572 short h;
573 short r;
574 short rb;
575 };
576
577 static const struct minimode est3_modes[] = {
578 /* byte 6 */
579 { 640, 350, 85, 0 },
580 { 640, 400, 85, 0 },
581 { 720, 400, 85, 0 },
582 { 640, 480, 85, 0 },
583 { 848, 480, 60, 0 },
584 { 800, 600, 85, 0 },
585 { 1024, 768, 85, 0 },
586 { 1152, 864, 75, 0 },
587 /* byte 7 */
588 { 1280, 768, 60, 1 },
589 { 1280, 768, 60, 0 },
590 { 1280, 768, 75, 0 },
591 { 1280, 768, 85, 0 },
592 { 1280, 960, 60, 0 },
593 { 1280, 960, 85, 0 },
594 { 1280, 1024, 60, 0 },
595 { 1280, 1024, 85, 0 },
596 /* byte 8 */
597 { 1360, 768, 60, 0 },
598 { 1440, 900, 60, 1 },
599 { 1440, 900, 60, 0 },
600 { 1440, 900, 75, 0 },
601 { 1440, 900, 85, 0 },
602 { 1400, 1050, 60, 1 },
603 { 1400, 1050, 60, 0 },
604 { 1400, 1050, 75, 0 },
605 /* byte 9 */
606 { 1400, 1050, 85, 0 },
607 { 1680, 1050, 60, 1 },
608 { 1680, 1050, 60, 0 },
609 { 1680, 1050, 75, 0 },
610 { 1680, 1050, 85, 0 },
611 { 1600, 1200, 60, 0 },
612 { 1600, 1200, 65, 0 },
613 { 1600, 1200, 70, 0 },
614 /* byte 10 */
615 { 1600, 1200, 75, 0 },
616 { 1600, 1200, 85, 0 },
617 { 1792, 1344, 60, 0 },
618 { 1792, 1344, 75, 0 },
619 { 1856, 1392, 60, 0 },
620 { 1856, 1392, 75, 0 },
621 { 1920, 1200, 60, 1 },
622 { 1920, 1200, 60, 0 },
623 /* byte 11 */
624 { 1920, 1200, 75, 0 },
625 { 1920, 1200, 85, 0 },
626 { 1920, 1440, 60, 0 },
627 { 1920, 1440, 75, 0 },
628 };
629
630 static const struct minimode extra_modes[] = {
631 { 1024, 576, 60, 0 },
632 { 1366, 768, 60, 0 },
633 { 1600, 900, 60, 0 },
634 { 1680, 945, 60, 0 },
635 { 1920, 1080, 60, 0 },
636 { 2048, 1152, 60, 0 },
637 { 2048, 1536, 60, 0 },
638 };
639
640 /*
641 * Probably taken from CEA-861 spec.
642 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
643 *
644 * Index using the VIC.
645 */
646 static const struct drm_display_mode edid_cea_modes[] = {
647 /* 0 - dummy, VICs start at 1 */
648 { },
649 /* 1 - 640x480@60Hz */
650 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
651 752, 800, 0, 480, 490, 492, 525, 0,
652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
653 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
654 /* 2 - 720x480@60Hz */
655 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
656 798, 858, 0, 480, 489, 495, 525, 0,
657 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
658 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
659 /* 3 - 720x480@60Hz */
660 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
661 798, 858, 0, 480, 489, 495, 525, 0,
662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
663 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
664 /* 4 - 1280x720@60Hz */
665 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
666 1430, 1650, 0, 720, 725, 730, 750, 0,
667 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
668 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
669 /* 5 - 1920x1080i@60Hz */
670 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
671 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
673 DRM_MODE_FLAG_INTERLACE),
674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
675 /* 6 - 720(1440)x480i@60Hz */
676 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
677 801, 858, 0, 480, 488, 494, 525, 0,
678 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
679 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
680 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
681 /* 7 - 720(1440)x480i@60Hz */
682 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
683 801, 858, 0, 480, 488, 494, 525, 0,
684 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
685 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
686 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
687 /* 8 - 720(1440)x240@60Hz */
688 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
689 801, 858, 0, 240, 244, 247, 262, 0,
690 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
691 DRM_MODE_FLAG_DBLCLK),
692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
693 /* 9 - 720(1440)x240@60Hz */
694 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
695 801, 858, 0, 240, 244, 247, 262, 0,
696 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
697 DRM_MODE_FLAG_DBLCLK),
698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
699 /* 10 - 2880x480i@60Hz */
700 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
701 3204, 3432, 0, 480, 488, 494, 525, 0,
702 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
703 DRM_MODE_FLAG_INTERLACE),
704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
705 /* 11 - 2880x480i@60Hz */
706 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
707 3204, 3432, 0, 480, 488, 494, 525, 0,
708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
709 DRM_MODE_FLAG_INTERLACE),
710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
711 /* 12 - 2880x240@60Hz */
712 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
713 3204, 3432, 0, 240, 244, 247, 262, 0,
714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
715 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
716 /* 13 - 2880x240@60Hz */
717 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
718 3204, 3432, 0, 240, 244, 247, 262, 0,
719 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
720 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
721 /* 14 - 1440x480@60Hz */
722 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
723 1596, 1716, 0, 480, 489, 495, 525, 0,
724 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
726 /* 15 - 1440x480@60Hz */
727 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
728 1596, 1716, 0, 480, 489, 495, 525, 0,
729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
731 /* 16 - 1920x1080@60Hz */
732 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
733 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
734 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
736 /* 17 - 720x576@50Hz */
737 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
738 796, 864, 0, 576, 581, 586, 625, 0,
739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
740 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
741 /* 18 - 720x576@50Hz */
742 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
743 796, 864, 0, 576, 581, 586, 625, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
746 /* 19 - 1280x720@50Hz */
747 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
748 1760, 1980, 0, 720, 725, 730, 750, 0,
749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
750 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 20 - 1920x1080i@50Hz */
752 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
753 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
755 DRM_MODE_FLAG_INTERLACE),
756 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 21 - 720(1440)x576i@50Hz */
758 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
759 795, 864, 0, 576, 580, 586, 625, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
761 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
762 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 22 - 720(1440)x576i@50Hz */
764 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
765 795, 864, 0, 576, 580, 586, 625, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
768 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 23 - 720(1440)x288@50Hz */
770 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
771 795, 864, 0, 288, 290, 293, 312, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_DBLCLK),
774 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
775 /* 24 - 720(1440)x288@50Hz */
776 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
777 795, 864, 0, 288, 290, 293, 312, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_DBLCLK),
780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 25 - 2880x576i@50Hz */
782 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
783 3180, 3456, 0, 576, 580, 586, 625, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
785 DRM_MODE_FLAG_INTERLACE),
786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
787 /* 26 - 2880x576i@50Hz */
788 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
789 3180, 3456, 0, 576, 580, 586, 625, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
791 DRM_MODE_FLAG_INTERLACE),
792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
793 /* 27 - 2880x288@50Hz */
794 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
795 3180, 3456, 0, 288, 290, 293, 312, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
797 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
798 /* 28 - 2880x288@50Hz */
799 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
800 3180, 3456, 0, 288, 290, 293, 312, 0,
801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
802 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 29 - 1440x576@50Hz */
804 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
805 1592, 1728, 0, 576, 581, 586, 625, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 30 - 1440x576@50Hz */
809 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
810 1592, 1728, 0, 576, 581, 586, 625, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 31 - 1920x1080@50Hz */
814 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
815 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
818 /* 32 - 1920x1080@24Hz */
819 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
820 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
821 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
822 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 33 - 1920x1080@25Hz */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
825 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 34 - 1920x1080@30Hz */
829 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
830 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
832 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 35 - 2880x480@60Hz */
834 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
835 3192, 3432, 0, 480, 489, 495, 525, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
838 /* 36 - 2880x480@60Hz */
839 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
840 3192, 3432, 0, 480, 489, 495, 525, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
842 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 37 - 2880x576@50Hz */
844 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
845 3184, 3456, 0, 576, 581, 586, 625, 0,
846 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
847 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
848 /* 38 - 2880x576@50Hz */
849 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
850 3184, 3456, 0, 576, 581, 586, 625, 0,
851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
852 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 39 - 1920x1080i@50Hz */
854 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
855 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
857 DRM_MODE_FLAG_INTERLACE),
858 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
859 /* 40 - 1920x1080i@100Hz */
860 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
861 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
862 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
863 DRM_MODE_FLAG_INTERLACE),
864 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
865 /* 41 - 1280x720@100Hz */
866 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
867 1760, 1980, 0, 720, 725, 730, 750, 0,
868 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
869 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
870 /* 42 - 720x576@100Hz */
871 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
872 796, 864, 0, 576, 581, 586, 625, 0,
873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
874 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
875 /* 43 - 720x576@100Hz */
876 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
877 796, 864, 0, 576, 581, 586, 625, 0,
878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
879 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
880 /* 44 - 720(1440)x576i@100Hz */
881 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
882 795, 864, 0, 576, 580, 586, 625, 0,
883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
884 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
886 /* 45 - 720(1440)x576i@100Hz */
887 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
888 795, 864, 0, 576, 580, 586, 625, 0,
889 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
890 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
891 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
892 /* 46 - 1920x1080i@120Hz */
893 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
894 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
895 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
896 DRM_MODE_FLAG_INTERLACE),
897 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 47 - 1280x720@120Hz */
899 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
900 1430, 1650, 0, 720, 725, 730, 750, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
902 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 48 - 720x480@120Hz */
904 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
905 798, 858, 0, 480, 489, 495, 525, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
907 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
908 /* 49 - 720x480@120Hz */
909 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
910 798, 858, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 50 - 720(1440)x480i@120Hz */
914 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
915 801, 858, 0, 480, 488, 494, 525, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
917 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
919 /* 51 - 720(1440)x480i@120Hz */
920 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
921 801, 858, 0, 480, 488, 494, 525, 0,
922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
923 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
924 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 52 - 720x576@200Hz */
926 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
927 796, 864, 0, 576, 581, 586, 625, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
930 /* 53 - 720x576@200Hz */
931 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
932 796, 864, 0, 576, 581, 586, 625, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 54 - 720(1440)x576i@200Hz */
936 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
937 795, 864, 0, 576, 580, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
939 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
940 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
941 /* 55 - 720(1440)x576i@200Hz */
942 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
943 795, 864, 0, 576, 580, 586, 625, 0,
944 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
945 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
946 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
947 /* 56 - 720x480@240Hz */
948 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
949 798, 858, 0, 480, 489, 495, 525, 0,
950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
951 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
952 /* 57 - 720x480@240Hz */
953 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
954 798, 858, 0, 480, 489, 495, 525, 0,
955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
956 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 58 - 720(1440)x480i@240 */
958 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
959 801, 858, 0, 480, 488, 494, 525, 0,
960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
962 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
963 /* 59 - 720(1440)x480i@240 */
964 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
965 801, 858, 0, 480, 488, 494, 525, 0,
966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
968 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
969 /* 60 - 1280x720@24Hz */
970 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
971 3080, 3300, 0, 720, 725, 730, 750, 0,
972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
973 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
974 /* 61 - 1280x720@25Hz */
975 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
976 3740, 3960, 0, 720, 725, 730, 750, 0,
977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
978 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
979 /* 62 - 1280x720@30Hz */
980 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
981 3080, 3300, 0, 720, 725, 730, 750, 0,
982 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
983 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 63 - 1920x1080@120Hz */
985 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
986 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
988 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
989 /* 64 - 1920x1080@100Hz */
990 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
991 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
992 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
993 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
994 };
995
996 /*
997 * HDMI 1.4 4k modes. Index using the VIC.
998 */
999 static const struct drm_display_mode edid_4k_modes[] = {
1000 /* 0 - dummy, VICs start at 1 */
1001 { },
1002 /* 1 - 3840x2160@30Hz */
1003 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1004 3840, 4016, 4104, 4400, 0,
1005 2160, 2168, 2178, 2250, 0,
1006 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1007 .vrefresh = 30, },
1008 /* 2 - 3840x2160@25Hz */
1009 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1010 3840, 4896, 4984, 5280, 0,
1011 2160, 2168, 2178, 2250, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 25, },
1014 /* 3 - 3840x2160@24Hz */
1015 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1016 3840, 5116, 5204, 5500, 0,
1017 2160, 2168, 2178, 2250, 0,
1018 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1019 .vrefresh = 24, },
1020 /* 4 - 4096x2160@24Hz (SMPTE) */
1021 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1022 4096, 5116, 5204, 5500, 0,
1023 2160, 2168, 2178, 2250, 0,
1024 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1025 .vrefresh = 24, },
1026 };
1027
1028 /*** DDC fetch and block validation ***/
1029
1030 static const u8 edid_header[] = {
1031 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1032 };
1033
1034 /**
1035 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1036 * @raw_edid: pointer to raw base EDID block
1037 *
1038 * Sanity check the header of the base EDID block.
1039 *
1040 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1041 */
1042 int drm_edid_header_is_valid(const u8 *raw_edid)
1043 {
1044 int i, score = 0;
1045
1046 for (i = 0; i < sizeof(edid_header); i++)
1047 if (raw_edid[i] == edid_header[i])
1048 score++;
1049
1050 return score;
1051 }
1052 EXPORT_SYMBOL(drm_edid_header_is_valid);
1053
1054 static int edid_fixup __read_mostly = 6;
1055 module_param_named(edid_fixup, edid_fixup, int, 0400);
1056 MODULE_PARM_DESC(edid_fixup,
1057 "Minimum number of valid EDID header bytes (0-8, default 6)");
1058
1059 static int drm_edid_block_checksum(const u8 *raw_edid)
1060 {
1061 int i;
1062 u8 csum = 0;
1063 for (i = 0; i < EDID_LENGTH; i++)
1064 csum += raw_edid[i];
1065
1066 return csum;
1067 }
1068
1069 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1070 {
1071 if (memchr_inv(in_edid, 0, length))
1072 return false;
1073
1074 return true;
1075 }
1076
1077 /**
1078 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1079 * @raw_edid: pointer to raw EDID block
1080 * @block: type of block to validate (0 for base, extension otherwise)
1081 * @print_bad_edid: if true, dump bad EDID blocks to the console
1082 * @edid_corrupt: if true, the header or checksum is invalid
1083 *
1084 * Validate a base or extension EDID block and optionally dump bad blocks to
1085 * the console.
1086 *
1087 * Return: True if the block is valid, false otherwise.
1088 */
1089 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1090 bool *edid_corrupt)
1091 {
1092 int i;
1093 u8 csum;
1094 struct edid *edid = (struct edid *)raw_edid;
1095
1096 if (WARN_ON(!raw_edid))
1097 return false;
1098
1099 if (edid_fixup > 8 || edid_fixup < 0)
1100 edid_fixup = 6;
1101
1102 if (block == 0) {
1103 int score = drm_edid_header_is_valid(raw_edid);
1104 if (score == 8) {
1105 if (edid_corrupt)
1106 *edid_corrupt = false;
1107 } else if (score >= edid_fixup) {
1108 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1109 * The corrupt flag needs to be set here otherwise, the
1110 * fix-up code here will correct the problem, the
1111 * checksum is correct and the test fails
1112 */
1113 if (edid_corrupt)
1114 *edid_corrupt = true;
1115 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1116 memcpy(raw_edid, edid_header, sizeof(edid_header));
1117 } else {
1118 if (edid_corrupt)
1119 *edid_corrupt = true;
1120 goto bad;
1121 }
1122 }
1123
1124 csum = drm_edid_block_checksum(raw_edid);
1125 if (csum) {
1126 if (print_bad_edid) {
1127 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum);
1128 }
1129
1130 if (edid_corrupt)
1131 *edid_corrupt = true;
1132
1133 /* allow CEA to slide through, switches mangle this */
1134 if (raw_edid[0] != 0x02)
1135 goto bad;
1136 }
1137
1138 /* per-block-type checks */
1139 switch (raw_edid[0]) {
1140 case 0: /* base */
1141 if (edid->version != 1) {
1142 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version);
1143 goto bad;
1144 }
1145
1146 if (edid->revision > 4)
1147 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1148 break;
1149
1150 default:
1151 break;
1152 }
1153
1154 return true;
1155
1156 bad:
1157 if (print_bad_edid) {
1158 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1159 printk(KERN_ERR "EDID block is all zeroes\n");
1160 } else {
1161 printk(KERN_ERR "Raw EDID:\n");
1162 for (i = 0; i < EDID_LENGTH; ) {
1163 kprintf("%02x", raw_edid[i]);
1164 i++;
1165 if (i % 16 == 0 || i == EDID_LENGTH)
1166 kprintf("\n");
1167 else if (i % 8 == 0)
1168 kprintf(" ");
1169 else
1170 kprintf(" ");
1171 }
1172 }
1173 }
1174 return false;
1175 }
1176 EXPORT_SYMBOL(drm_edid_block_valid);
1177
1178 /**
1179 * drm_edid_is_valid - sanity check EDID data
1180 * @edid: EDID data
1181 *
1182 * Sanity-check an entire EDID record (including extensions)
1183 *
1184 * Return: True if the EDID data is valid, false otherwise.
1185 */
1186 bool drm_edid_is_valid(struct edid *edid)
1187 {
1188 int i;
1189 u8 *raw = (u8 *)edid;
1190
1191 if (!edid)
1192 return false;
1193
1194 for (i = 0; i <= edid->extensions; i++)
1195 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1196 return false;
1197
1198 return true;
1199 }
1200 EXPORT_SYMBOL(drm_edid_is_valid);
1201
1202 #define DDC_SEGMENT_ADDR 0x30
1203 /**
1204 * drm_do_probe_ddc_edid() - get EDID information via I2C
1205 * @data: I2C device adapter
1206 * @buf: EDID data buffer to be filled
1207 * @block: 128 byte EDID block to start fetching from
1208 * @len: EDID data buffer length to fetch
1209 *
1210 * Try to fetch EDID information by calling I2C driver functions.
1211 *
1212 * Return: 0 on success or -1 on failure.
1213 */
1214 static int
1215 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1216 {
1217 struct i2c_adapter *adapter = data;
1218 unsigned char start = block * EDID_LENGTH;
1219 unsigned char segment = block >> 1;
1220 unsigned char xfers = segment ? 3 : 2;
1221 int ret, retries = 5;
1222
1223 /*
1224 * The core I2C driver will automatically retry the transfer if the
1225 * adapter reports EAGAIN. However, we find that bit-banging transfers
1226 * are susceptible to errors under a heavily loaded machine and
1227 * generate spurious NAKs and timeouts. Retrying the transfer
1228 * of the individual block a few times seems to overcome this.
1229 */
1230 do {
1231 struct i2c_msg msgs[] = {
1232 {
1233 .addr = DDC_SEGMENT_ADDR,
1234 .flags = 0,
1235 .len = 1,
1236 .buf = &segment,
1237 }, {
1238 .addr = DDC_ADDR,
1239 .flags = 0,
1240 .len = 1,
1241 .buf = &start,
1242 }, {
1243 .addr = DDC_ADDR,
1244 .flags = I2C_M_RD,
1245 .len = len,
1246 .buf = buf,
1247 }
1248 };
1249
1250 /*
1251 * Avoid sending the segment addr to not upset non-compliant
1252 * DDC monitors.
1253 */
1254 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1255
1256 if (ret == -ENXIO) {
1257 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1258 adapter->name);
1259 break;
1260 }
1261 } while (ret != xfers && --retries);
1262
1263 return ret == xfers ? 0 : -1;
1264 }
1265
1266 /*
1267 * Old version of drm_do_probe_ddc_edid, still using
1268 * the FreeBSD/DragonFly iic API
1269 */
1270 static int
1271 drm_do_probe_ddc_edid_iic(void *data, u8 *buf, unsigned int block, size_t len)
1272 {
1273 device_t adapter = data;
1274 unsigned char start = block * EDID_LENGTH;
1275 unsigned char segment = block >> 1;
1276 unsigned char xfers = segment ? 3 : 2;
1277 int ret, retries = 5;
1278
1279 /*
1280 * The core I2C driver will automatically retry the transfer if the
1281 * adapter reports EAGAIN. However, we find that bit-banging transfers
1282 * are susceptible to errors under a heavily loaded machine and
1283 * generate spurious NAKs and timeouts. Retrying the transfer
1284 * of the individual block a few times seems to overcome this.
1285 */
1286 do {
1287 struct iic_msg msgs[] = {
1288 {
1289 .slave = DDC_SEGMENT_ADDR << 1,
1290 .flags = 0,
1291 .len = 1,
1292 .buf = &segment,
1293 }, {
1294 .slave = DDC_ADDR << 1,
1295 .flags = 0,
1296 .len = 1,
1297 .buf = &start,
1298 }, {
1299 .slave = DDC_ADDR << 1,
1300 .flags = I2C_M_RD,
1301 .len = len,
1302 .buf = buf,
1303 }
1304 };
1305
1306 /*
1307 * Avoid sending the segment addr to not upset non-compliant
1308 * DDC monitors.
1309 */
1310 ret = iicbus_transfer(adapter, &msgs[3 - xfers], xfers);
1311
1312 if (ret != 0)
1313 DRM_DEBUG_KMS("iicbus_transfer countdown %d error %d\n",
1314 retries, ret);
1315 } while (ret != 0 && --retries);
1316
1317 return (ret == 0 ? 0 : -1);
1318 }
1319
1320 /**
1321 * drm_do_get_edid - get EDID data using a custom EDID block read function
1322 * @connector: connector we're probing
1323 * @get_edid_block: EDID block read function
1324 * @data: private data passed to the block read function
1325 *
1326 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1327 * exposes a different interface to read EDID blocks this function can be used
1328 * to get EDID data using a custom block read function.
1329 *
1330 * As in the general case the DDC bus is accessible by the kernel at the I2C
1331 * level, drivers must make all reasonable efforts to expose it as an I2C
1332 * adapter and use drm_get_edid() instead of abusing this function.
1333 *
1334 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1335 */
1336 struct edid *drm_do_get_edid(struct drm_connector *connector,
1337 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1338 size_t len),
1339 void *data)
1340 {
1341 int i, j = 0, valid_extensions = 0;
1342 u8 *block, *new;
1343 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS);
1344
1345 if ((block = kmalloc(EDID_LENGTH, M_DRM, M_WAITOK)) == NULL)
1346 return NULL;
1347
1348 /* base block fetch */
1349 for (i = 0; i < 4; i++) {
1350 if (get_edid_block(data, block, 0, EDID_LENGTH))
1351 goto out;
1352 if (drm_edid_block_valid(block, 0, print_bad_edid,
1353 &connector->edid_corrupt))
1354 break;
1355 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) {
1356 connector->null_edid_counter++;
1357 goto carp;
1358 }
1359 }
1360 if (i == 4)
1361 goto carp;
1362
1363 /* if there's no extensions, we're done */
1364 if (block[0x7e] == 0)
1365 return (struct edid *)block;
1366
1367 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, M_DRM, M_WAITOK);
1368 if (!new)
1369 goto out;
1370 block = new;
1371
1372 for (j = 1; j <= block[0x7e]; j++) {
1373 for (i = 0; i < 4; i++) {
1374 if (get_edid_block(data,
1375 block + (valid_extensions + 1) * EDID_LENGTH,
1376 j, EDID_LENGTH))
1377 goto out;
1378 if (drm_edid_block_valid(block + (valid_extensions + 1)
1379 * EDID_LENGTH, j,
1380 print_bad_edid,
1381 NULL)) {
1382 valid_extensions++;
1383 break;
1384 }
1385 }
1386
1387 if (i == 4 && print_bad_edid) {
1388 dev_warn(connector->dev->dev,
1389 "%s: Ignoring invalid EDID block %d.\n",
1390 connector->name, j);
1391
1392 connector->bad_edid_counter++;
1393 }
1394 }
1395
1396 if (valid_extensions != block[0x7e]) {
1397 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions;
1398 block[0x7e] = valid_extensions;
1399 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, M_DRM, M_WAITOK);
1400 if (!new)
1401 goto out;
1402 block = new;
1403 }
1404
1405 return (struct edid *)block;
1406
1407 carp:
1408 if (print_bad_edid) {
1409 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n",
1410 connector->name, j);
1411 }
1412 connector->bad_edid_counter++;
1413
1414 out:
1415 kfree(block);
1416 return NULL;
1417 }
1418
1419 /**
1420 * drm_probe_ddc() - probe DDC presence
1421 * @adapter: I2C adapter to probe
1422 *
1423 * Return: True on success, false on failure.
1424 */
1425 bool
1426 drm_probe_ddc(struct i2c_adapter *adapter)
1427 {
1428 unsigned char out;
1429
1430 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1431 }
1432 EXPORT_SYMBOL(drm_probe_ddc);
1433
1434 /*
1435 * Old version of drm_probe_ddc(), still using
1436 * the FreeBSD/DragonFly iic API
1437 */
1438 static bool
1439 drm_probe_ddc_iic(device_t adapter)
1440 {
1441 unsigned char out;
1442
1443 return (drm_do_probe_ddc_edid_iic(adapter, &out, 0, 1) == 0);
1444 }
1445
1446 /**
1447 * drm_get_edid - get EDID data, if available
1448 * @connector: connector we're probing
1449 * @adapter: I2C adapter to use for DDC
1450 *
1451 * Poke the given I2C channel to grab EDID data if possible. If found,
1452 * attach it to the connector.
1453 *
1454 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1455 */
1456 struct edid *drm_get_edid(struct drm_connector *connector,
1457 struct i2c_adapter *adapter)
1458 {
1459 if (!drm_probe_ddc(adapter))
1460 return NULL;
1461
1462 return drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1463 }
1464 EXPORT_SYMBOL(drm_get_edid);
1465
1466 /*
1467 * Old version of drm_get_edid(), still using
1468 * the FreeBSD/DragonFly iic API
1469 */
1470 struct edid *drm_get_edid_iic(struct drm_connector *connector,
1471 device_t adapter)
1472 {
1473 if (!drm_probe_ddc_iic(adapter))
1474 return NULL;
1475
1476 return drm_do_get_edid(connector, drm_do_probe_ddc_edid_iic, adapter);
1477 }
1478
1479 /**
1480 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1481 * @connector: connector we're probing
1482 * @adapter: I2C adapter to use for DDC
1483 *
1484 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1485 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1486 * switch DDC to the GPU which is retrieving EDID.
1487 *
1488 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1489 */
1490 #if 0
1491 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1492 struct i2c_adapter *adapter)
1493 {
1494 struct pci_dev *pdev = connector->dev->pdev;
1495 struct edid *edid;
1496
1497 vga_switcheroo_lock_ddc(pdev);
1498 edid = drm_get_edid(connector, adapter);
1499 vga_switcheroo_unlock_ddc(pdev);
1500
1501 return edid;
1502 }
1503 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1504 #endif
1505
1506 /**
1507 * drm_edid_duplicate - duplicate an EDID and the extensions
1508 * @edid: EDID to duplicate
1509 *
1510 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1511 */
1512 struct edid *drm_edid_duplicate(const struct edid *edid)
1513 {
1514 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1515 }
1516 EXPORT_SYMBOL(drm_edid_duplicate);
1517
1518 /*** EDID parsing ***/
1519
1520 /**
1521 * edid_vendor - match a string against EDID's obfuscated vendor field
1522 * @edid: EDID to match
1523 * @vendor: vendor string
1524 *
1525 * Returns true if @vendor is in @edid, false otherwise
1526 */
1527 static bool edid_vendor(struct edid *edid, char *vendor)
1528 {
1529 char edid_vendor[3];
1530
1531 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1532 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1533 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1534 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1535
1536 return !strncmp(edid_vendor, vendor, 3);
1537 }
1538
1539 /**
1540 * edid_get_quirks - return quirk flags for a given EDID
1541 * @edid: EDID to process
1542 *
1543 * This tells subsequent routines what fixes they need to apply.
1544 */
1545 static u32 edid_get_quirks(struct edid *edid)
1546 {
1547 struct edid_quirk *quirk;
1548 int i;
1549
1550 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1551 quirk = &edid_quirk_list[i];
1552
1553 if (edid_vendor(edid, quirk->vendor) &&
1554 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1555 return quirk->quirks;
1556 }
1557
1558 return 0;
1559 }
1560
1561 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1562 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1563
1564 /**
1565 * edid_fixup_preferred - set preferred modes based on quirk list
1566 * @connector: has mode list to fix up
1567 * @quirks: quirks list
1568 *
1569 * Walk the mode list for @connector, clearing the preferred status
1570 * on existing modes and setting it anew for the right mode ala @quirks.
1571 */
1572 static void edid_fixup_preferred(struct drm_connector *connector,
1573 u32 quirks)
1574 {
1575 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1576 int target_refresh = 0;
1577 int cur_vrefresh, preferred_vrefresh;
1578
1579 if (list_empty(&connector->probed_modes))
1580 return;
1581
1582 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1583 target_refresh = 60;
1584 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1585 target_refresh = 75;
1586
1587 preferred_mode = list_first_entry(&connector->probed_modes,
1588 struct drm_display_mode, head);
1589
1590 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1591 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1592
1593 if (cur_mode == preferred_mode)
1594 continue;
1595
1596 /* Largest mode is preferred */
1597 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1598 preferred_mode = cur_mode;
1599
1600 cur_vrefresh = cur_mode->vrefresh ?
1601 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1602 preferred_vrefresh = preferred_mode->vrefresh ?
1603 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1604 /* At a given size, try to get closest to target refresh */
1605 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1606 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1607 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1608 preferred_mode = cur_mode;
1609 }
1610 }
1611
1612 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1613 }
1614
1615 static bool
1616 mode_is_rb(const struct drm_display_mode *mode)
1617 {
1618 return (mode->htotal - mode->hdisplay == 160) &&
1619 (mode->hsync_end - mode->hdisplay == 80) &&
1620 (mode->hsync_end - mode->hsync_start == 32) &&
1621 (mode->vsync_start - mode->vdisplay == 3);
1622 }
1623
1624 /*
1625 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1626 * @dev: Device to duplicate against
1627 * @hsize: Mode width
1628 * @vsize: Mode height
1629 * @fresh: Mode refresh rate
1630 * @rb: Mode reduced-blanking-ness
1631 *
1632 * Walk the DMT mode list looking for a match for the given parameters.
1633 *
1634 * Return: A newly allocated copy of the mode, or NULL if not found.
1635 */
1636 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1637 int hsize, int vsize, int fresh,
1638 bool rb)
1639 {
1640 int i;
1641
1642 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1643 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1644 if (hsize != ptr->hdisplay)
1645 continue;
1646 if (vsize != ptr->vdisplay)
1647 continue;
1648 if (fresh != drm_mode_vrefresh(ptr))
1649 continue;
1650 if (rb != mode_is_rb(ptr))
1651 continue;
1652
1653 return drm_mode_duplicate(dev, ptr);
1654 }
1655
1656 return NULL;
1657 }
1658 EXPORT_SYMBOL(drm_mode_find_dmt);
1659
1660 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1661
1662 static void
1663 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1664 {
1665 int i, n = 0;
1666 u8 d = ext[0x02];
1667 u8 *det_base = ext + d;
1668
1669 n = (127 - d) / 18;
1670 for (i = 0; i < n; i++)
1671 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1672 }
1673
1674 static void
1675 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1676 {
1677 unsigned int i, n = min((int)ext[0x02], 6);
1678 u8 *det_base = ext + 5;
1679
1680 if (ext[0x01] != 1)
1681 return; /* unknown version */
1682
1683 for (i = 0; i < n; i++)
1684 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1685 }
1686
1687 static void
1688 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1689 {
1690 int i;
1691 struct edid *edid = (struct edid *)raw_edid;
1692
1693 if (edid == NULL)
1694 return;
1695
1696 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1697 cb(&(edid->detailed_timings[i]), closure);
1698
1699 for (i = 1; i <= raw_edid[0x7e]; i++) {
1700 u8 *ext = raw_edid + (i * EDID_LENGTH);
1701 switch (*ext) {
1702 case CEA_EXT:
1703 cea_for_each_detailed_block(ext, cb, closure);
1704 break;
1705 case VTB_EXT:
1706 vtb_for_each_detailed_block(ext, cb, closure);
1707 break;
1708 default:
1709 break;
1710 }
1711 }
1712 }
1713
1714 static void
1715 is_rb(struct detailed_timing *t, void *data)
1716 {
1717 u8 *r = (u8 *)t;
1718 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1719 if (r[15] & 0x10)
1720 *(bool *)data = true;
1721 }
1722
1723 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1724 static bool
1725 drm_monitor_supports_rb(struct edid *edid)
1726 {
1727 if (edid->revision >= 4) {
1728 bool ret = false;
1729 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1730 return ret;
1731 }
1732
1733 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1734 }
1735
1736 static void
1737 find_gtf2(struct detailed_timing *t, void *data)
1738 {
1739 u8 *r = (u8 *)t;
1740 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1741 *(u8 **)data = r;
1742 }
1743
1744 /* Secondary GTF curve kicks in above some break frequency */
1745 static int
1746 drm_gtf2_hbreak(struct edid *edid)
1747 {
1748 u8 *r = NULL;
1749 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1750 return r ? (r[12] * 2) : 0;
1751 }
1752
1753 static int
1754 drm_gtf2_2c(struct edid *edid)
1755 {
1756 u8 *r = NULL;
1757 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1758 return r ? r[13] : 0;
1759 }
1760
1761 static int
1762 drm_gtf2_m(struct edid *edid)
1763 {
1764 u8 *r = NULL;
1765 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1766 return r ? (r[15] << 8) + r[14] : 0;
1767 }
1768
1769 static int
1770 drm_gtf2_k(struct edid *edid)
1771 {
1772 u8 *r = NULL;
1773 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1774 return r ? r[16] : 0;
1775 }
1776
1777 static int
1778 drm_gtf2_2j(struct edid *edid)
1779 {
1780 u8 *r = NULL;
1781 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1782 return r ? r[17] : 0;
1783 }
1784
1785 /**
1786 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1787 * @edid: EDID block to scan
1788 */
1789 static int standard_timing_level(struct edid *edid)
1790 {
1791 if (edid->revision >= 2) {
1792 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1793 return LEVEL_CVT;
1794 if (drm_gtf2_hbreak(edid))
1795 return LEVEL_GTF2;
1796 return LEVEL_GTF;
1797 }
1798 return LEVEL_DMT;
1799 }
1800
1801 /*
1802 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
1803 * monitors fill with ascii space (0x20) instead.
1804 */
1805 static int
1806 bad_std_timing(u8 a, u8 b)
1807 {
1808 return (a == 0x00 && b == 0x00) ||
1809 (a == 0x01 && b == 0x01) ||
1810 (a == 0x20 && b == 0x20);
1811 }
1812
1813 /**
1814 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
1815 * @connector: connector of for the EDID block
1816 * @edid: EDID block to scan
1817 * @t: standard timing params
1818 *
1819 * Take the standard timing params (in this case width, aspect, and refresh)
1820 * and convert them into a real mode using CVT/GTF/DMT.
1821 */
1822 static struct drm_display_mode *
1823 drm_mode_std(struct drm_connector *connector, struct edid *edid,
1824 struct std_timing *t)
1825 {
1826 struct drm_device *dev = connector->dev;
1827 struct drm_display_mode *m, *mode = NULL;
1828 int hsize, vsize;
1829 int vrefresh_rate;
1830 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
1831 >> EDID_TIMING_ASPECT_SHIFT;
1832 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
1833 >> EDID_TIMING_VFREQ_SHIFT;
1834 int timing_level = standard_timing_level(edid);
1835
1836 if (bad_std_timing(t->hsize, t->vfreq_aspect))
1837 return NULL;
1838
1839 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
1840 hsize = t->hsize * 8 + 248;
1841 /* vrefresh_rate = vfreq + 60 */
1842 vrefresh_rate = vfreq + 60;
1843 /* the vdisplay is calculated based on the aspect ratio */
1844 if (aspect_ratio == 0) {
1845 if (edid->revision < 3)
1846 vsize = hsize;
1847 else
1848 vsize = (hsize * 10) / 16;
1849 } else if (aspect_ratio == 1)
1850 vsize = (hsize * 3) / 4;
1851 else if (aspect_ratio == 2)
1852 vsize = (hsize * 4) / 5;
1853 else
1854 vsize = (hsize * 9) / 16;
1855
1856 /* HDTV hack, part 1 */
1857 if (vrefresh_rate == 60 &&
1858 ((hsize == 1360 && vsize == 765) ||
1859 (hsize == 1368 && vsize == 769))) {
1860 hsize = 1366;
1861 vsize = 768;
1862 }
1863
1864 /*
1865 * If this connector already has a mode for this size and refresh
1866 * rate (because it came from detailed or CVT info), use that
1867 * instead. This way we don't have to guess at interlace or
1868 * reduced blanking.
1869 */
1870 list_for_each_entry(m, &connector->probed_modes, head)
1871 if (m->hdisplay == hsize && m->vdisplay == vsize &&
1872 drm_mode_vrefresh(m) == vrefresh_rate)
1873 return NULL;
1874
1875 /* HDTV hack, part 2 */
1876 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
1877 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
1878 false);
1879 mode->hdisplay = 1366;
1880 mode->hsync_start = mode->hsync_start - 1;
1881 mode->hsync_end = mode->hsync_end - 1;
1882 return mode;
1883 }
1884
1885 /* check whether it can be found in default mode table */
1886 if (drm_monitor_supports_rb(edid)) {
1887 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
1888 true);
1889 if (mode)
1890 return mode;
1891 }
1892 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
1893 if (mode)
1894 return mode;
1895
1896 /* okay, generate it */
1897 switch (timing_level) {
1898 case LEVEL_DMT:
1899 break;
1900 case LEVEL_GTF:
1901 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1902 break;
1903 case LEVEL_GTF2:
1904 /*
1905 * This is potentially wrong if there's ever a monitor with
1906 * more than one ranges section, each claiming a different
1907 * secondary GTF curve. Please don't do that.
1908 */
1909 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
1910 if (!mode)
1911 return NULL;
1912 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
1913 drm_mode_destroy(dev, mode);
1914 mode = drm_gtf_mode_complex(dev, hsize, vsize,
1915 vrefresh_rate, 0, 0,
1916 drm_gtf2_m(edid),
1917 drm_gtf2_2c(edid),
1918 drm_gtf2_k(edid),
1919 drm_gtf2_2j(edid));
1920 }
1921 break;
1922 case LEVEL_CVT:
1923 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
1924 false);
1925 break;
1926 }
1927 return mode;
1928 }
1929
1930 /*
1931 * EDID is delightfully ambiguous about how interlaced modes are to be
1932 * encoded. Our internal representation is of frame height, but some
1933 * HDTV detailed timings are encoded as field height.
1934 *
1935 * The format list here is from CEA, in frame size. Technically we
1936 * should be checking refresh rate too. Whatever.
1937 */
1938 static void
1939 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
1940 struct detailed_pixel_timing *pt)
1941 {
1942 int i;
1943 static const struct {
1944 int w, h;
1945 } cea_interlaced[] = {
1946 { 1920, 1080 },
1947 { 720, 480 },
1948 { 1440, 480 },
1949 { 2880, 480 },
1950 { 720, 576 },
1951 { 1440, 576 },
1952 { 2880, 576 },
1953 };
1954
1955 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
1956 return;
1957
1958 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
1959 if ((mode->hdisplay == cea_interlaced[i].w) &&
1960 (mode->vdisplay == cea_interlaced[i].h / 2)) {
1961 mode->vdisplay *= 2;
1962 mode->vsync_start *= 2;
1963 mode->vsync_end *= 2;
1964 mode->vtotal *= 2;
1965 mode->vtotal |= 1;
1966 }
1967 }
1968
1969 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1970 }
1971
1972 /**
1973 * drm_mode_detailed - create a new mode from an EDID detailed timing section
1974 * @dev: DRM device (needed to create new mode)
1975 * @edid: EDID block
1976 * @timing: EDID detailed timing info
1977 * @quirks: quirks to apply
1978 *
1979 * An EDID detailed timing block contains enough info for us to create and
1980 * return a new struct drm_display_mode.
1981 */
1982 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
1983 struct edid *edid,
1984 struct detailed_timing *timing,
1985 u32 quirks)
1986 {
1987 struct drm_display_mode *mode;
1988 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
1989 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
1990 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
1991 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
1992 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
1993 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
1994 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
1995 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
1996 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
1997
1998 /* ignore tiny modes */
1999 if (hactive < 64 || vactive < 64)
2000 return NULL;
2001
2002 if (pt->misc & DRM_EDID_PT_STEREO) {
2003 DRM_DEBUG_KMS("stereo mode not supported\n");
2004 return NULL;
2005 }
2006 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2007 DRM_DEBUG_KMS("composite sync not supported\n");
2008 }
2009
2010 /* it is incorrect if hsync/vsync width is zero */
2011 if (!hsync_pulse_width || !vsync_pulse_width) {
2012 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2013 "Wrong Hsync/Vsync pulse width\n");
2014 return NULL;
2015 }
2016
2017 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2018 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2019 if (!mode)
2020 return NULL;
2021
2022 goto set_size;
2023 }
2024
2025 mode = drm_mode_create(dev);
2026 if (!mode)
2027 return NULL;
2028
2029 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2030 timing->pixel_clock = cpu_to_le16(1088);
2031
2032 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2033
2034 mode->hdisplay = hactive;
2035 mode->hsync_start = mode->hdisplay + hsync_offset;
2036 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2037 mode->htotal = mode->hdisplay + hblank;
2038
2039 mode->vdisplay = vactive;
2040 mode->vsync_start = mode->vdisplay + vsync_offset;
2041 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2042 mode->vtotal = mode->vdisplay + vblank;
2043
2044 /* Some EDIDs have bogus h/vtotal values */
2045 if (mode->hsync_end > mode->htotal)
2046 mode->htotal = mode->hsync_end + 1;
2047 if (mode->vsync_end > mode->vtotal)
2048 mode->vtotal = mode->vsync_end + 1;
2049
2050 drm_mode_do_interlace_quirk(mode, pt);
2051
2052 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2053 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2054 }
2055
2056 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2057 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2058 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2059 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2060
2061 set_size:
2062 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2063 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2064
2065 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2066 mode->width_mm *= 10;
2067 mode->height_mm *= 10;
2068 }
2069
2070 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2071 mode->width_mm = edid->width_cm * 10;
2072 mode->height_mm = edid->height_cm * 10;
2073 }
2074
2075 mode->type = DRM_MODE_TYPE_DRIVER;
2076 mode->vrefresh = drm_mode_vrefresh(mode);
2077 drm_mode_set_name(mode);
2078
2079 return mode;
2080 }
2081
2082 static bool
2083 mode_in_hsync_range(const struct drm_display_mode *mode,
2084 struct edid *edid, u8 *t)
2085 {
2086 int hsync, hmin, hmax;
2087
2088 hmin = t[7];
2089 if (edid->revision >= 4)
2090 hmin += ((t[4] & 0x04) ? 255 : 0);
2091 hmax = t[8];
2092 if (edid->revision >= 4)
2093 hmax += ((t[4] & 0x08) ? 255 : 0);
2094 hsync = drm_mode_hsync(mode);
2095
2096 return (hsync <= hmax && hsync >= hmin);
2097 }
2098
2099 static bool
2100 mode_in_vsync_range(const struct drm_display_mode *mode,
2101 struct edid *edid, u8 *t)
2102 {
2103 int vsync, vmin, vmax;
2104
2105 vmin = t[5];
2106 if (edid->revision >= 4)
2107 vmin += ((t[4] & 0x01) ? 255 : 0);
2108 vmax = t[6];
2109 if (edid->revision >= 4)
2110 vmax += ((t[4] & 0x02) ? 255 : 0);
2111 vsync = drm_mode_vrefresh(mode);
2112
2113 return (vsync <= vmax && vsync >= vmin);
2114 }
2115
2116 static u32
2117 range_pixel_clock(struct edid *edid, u8 *t)
2118 {
2119 /* unspecified */
2120 if (t[9] == 0 || t[9] == 255)
2121 return 0;
2122
2123 /* 1.4 with CVT support gives us real precision, yay */
2124 if (edid->revision >= 4 && t[10] == 0x04)
2125 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2126
2127 /* 1.3 is pathetic, so fuzz up a bit */
2128 return t[9] * 10000 + 5001;
2129 }
2130
2131 static bool
2132 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2133 struct detailed_timing *timing)
2134 {
2135 u32 max_clock;
2136 u8 *t = (u8 *)timing;
2137
2138 if (!mode_in_hsync_range(mode, edid, t))
2139 return false;
2140
2141 if (!mode_in_vsync_range(mode, edid, t))
2142 return false;
2143
2144 if ((max_clock = range_pixel_clock(edid, t)))
2145 if (mode->clock > max_clock)
2146 return false;
2147
2148 /* 1.4 max horizontal check */
2149 if (edid->revision >= 4 && t[10] == 0x04)
2150 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2151 return false;
2152
2153 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2154 return false;
2155
2156 return true;
2157 }
2158
2159 static bool valid_inferred_mode(const struct drm_connector *connector,
2160 const struct drm_display_mode *mode)
2161 {
2162 struct drm_display_mode *m;
2163 bool ok = false;
2164
2165 list_for_each_entry(m, &connector->probed_modes, head) {
2166 if (mode->hdisplay == m->hdisplay &&
2167 mode->vdisplay == m->vdisplay &&
2168 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2169 return false; /* duplicated */
2170 if (mode->hdisplay <= m->hdisplay &&
2171 mode->vdisplay <= m->vdisplay)
2172 ok = true;
2173 }
2174 return ok;
2175 }
2176
2177 static int
2178 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2179 struct detailed_timing *timing)
2180 {
2181 int i, modes = 0;
2182 struct drm_display_mode *newmode;
2183 struct drm_device *dev = connector->dev;
2184
2185 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2186 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2187 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2188 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2189 if (newmode) {
2190 drm_mode_probed_add(connector, newmode);
2191 modes++;
2192 }
2193 }
2194 }
2195
2196 return modes;
2197 }
2198
2199 /* fix up 1366x768 mode from 1368x768;
2200 * GFT/CVT can't express 1366 width which isn't dividable by 8
2201 */
2202 static void fixup_mode_1366x768(struct drm_display_mode *mode)
2203 {
2204 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2205 mode->hdisplay = 1366;
2206 mode->hsync_start--;
2207 mode->hsync_end--;
2208 drm_mode_set_name(mode);
2209 }
2210 }
2211
2212 static int
2213 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2214 struct detailed_timing *timing)
2215 {
2216 int i, modes = 0;
2217 struct drm_display_mode *newmode;
2218 struct drm_device *dev = connector->dev;
2219
2220 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2221 const struct minimode *m = &extra_modes[i];
2222 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2223 if (!newmode)
2224 return modes;
2225
2226 fixup_mode_1366x768(newmode);
2227 if (!mode_in_range(newmode, edid, timing) ||
2228 !valid_inferred_mode(connector, newmode)) {
2229 drm_mode_destroy(dev, newmode);
2230 continue;
2231 }
2232
2233 drm_mode_probed_add(connector, newmode);
2234 modes++;
2235 }
2236
2237 return modes;
2238 }
2239
2240 static int
2241 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2242 struct detailed_timing *timing)
2243 {
2244 int i, modes = 0;
2245 struct drm_display_mode *newmode;
2246 struct drm_device *dev = connector->dev;
2247 bool rb = drm_monitor_supports_rb(edid);
2248
2249 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2250 const struct minimode *m = &extra_modes[i];
2251 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2252 if (!newmode)
2253 return modes;
2254
2255 fixup_mode_1366x768(newmode);
2256 if (!mode_in_range(newmode, edid, timing) ||
2257 !valid_inferred_mode(connector, newmode)) {
2258 drm_mode_destroy(dev, newmode);
2259 continue;
2260 }
2261
2262 drm_mode_probed_add(connector, newmode);
2263 modes++;
2264 }
2265
2266 return modes;
2267 }
2268
2269 static void
2270 do_inferred_modes(struct detailed_timing *timing, void *c)
2271 {
2272 struct detailed_mode_closure *closure = c;
2273 struct detailed_non_pixel *data = &timing->data.other_data;
2274 struct detailed_data_monitor_range *range = &data->data.range;
2275
2276 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2277 return;
2278
2279 closure->modes += drm_dmt_modes_for_range(closure->connector,
2280 closure->edid,
2281 timing);
2282
2283 if (!version_greater(closure->edid, 1, 1))
2284 return; /* GTF not defined yet */
2285
2286 switch (range->flags) {
2287 case 0x02: /* secondary gtf, XXX could do more */
2288 case 0x00: /* default gtf */
2289 closure->modes += drm_gtf_modes_for_range(closure->connector,
2290 closure->edid,
2291 timing);
2292 break;
2293 case 0x04: /* cvt, only in 1.4+ */
2294 if (!version_greater(closure->edid, 1, 3))
2295 break;
2296
2297 closure->modes += drm_cvt_modes_for_range(closure->connector,
2298 closure->edid,
2299 timing);
2300 break;
2301 case 0x01: /* just the ranges, no formula */
2302 default:
2303 break;
2304 }
2305 }
2306
2307 static int
2308 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2309 {
2310 struct detailed_mode_closure closure = {
2311 .connector = connector,
2312 .edid = edid,
2313 };
2314
2315 if (version_greater(edid, 1, 0))
2316 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2317 &closure);
2318
2319 return closure.modes;
2320 }
2321
2322 static int
2323 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2324 {
2325 int i, j, m, modes = 0;
2326 struct drm_display_mode *mode;
2327 u8 *est = ((u8 *)timing) + 6;
2328
2329 for (i = 0; i < 6; i++) {
2330 for (j = 7; j >= 0; j--) {
2331 m = (i * 8) + (7 - j);
2332 if (m >= ARRAY_SIZE(est3_modes))
2333 break;
2334 if (est[i] & (1 << j)) {
2335 mode = drm_mode_find_dmt(connector->dev,
2336 est3_modes[m].w,
2337 est3_modes[m].h,
2338 est3_modes[m].r,
2339 est3_modes[m].rb);
2340 if (mode) {
2341 drm_mode_probed_add(connector, mode);
2342 modes++;
2343 }
2344 }
2345 }
2346 }
2347
2348 return modes;
2349 }
2350
2351 static void
2352 do_established_modes(struct detailed_timing *timing, void *c)
2353 {
2354 struct detailed_mode_closure *closure = c;
2355 struct detailed_non_pixel *data = &timing->data.other_data;
2356
2357 if (data->type == EDID_DETAIL_EST_TIMINGS)
2358 closure->modes += drm_est3_modes(closure->connector, timing);
2359 }
2360
2361 /**
2362 * add_established_modes - get est. modes from EDID and add them
2363 * @connector: connector to add mode(s) to
2364 * @edid: EDID block to scan
2365 *
2366 * Each EDID block contains a bitmap of the supported "established modes" list
2367 * (defined above). Tease them out and add them to the global modes list.
2368 */
2369 static int
2370 add_established_modes(struct drm_connector *connector, struct edid *edid)
2371 {
2372 struct drm_device *dev = connector->dev;
2373 unsigned long est_bits = edid->established_timings.t1 |
2374 (edid->established_timings.t2 << 8) |
2375 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2376 int i, modes = 0;
2377 struct detailed_mode_closure closure = {
2378 .connector = connector,
2379 .edid = edid,
2380 };
2381
2382 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2383 if (est_bits & (1<<i)) {
2384 struct drm_display_mode *newmode;
2385 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2386 if (newmode) {
2387 drm_mode_probed_add(connector, newmode);
2388 modes++;
2389 }
2390 }
2391 }
2392
2393 if (version_greater(edid, 1, 0))
2394 drm_for_each_detailed_block((u8 *)edid,
2395 do_established_modes, &closure);
2396
2397 return modes + closure.modes;
2398 }
2399
2400 static void
2401 do_standard_modes(struct detailed_timing *timing, void *c)
2402 {
2403 struct detailed_mode_closure *closure = c;
2404 struct detailed_non_pixel *data = &timing->data.other_data;
2405 struct drm_connector *connector = closure->connector;
2406 struct edid *edid = closure->edid;
2407
2408 if (data->type == EDID_DETAIL_STD_MODES) {
2409 int i;
2410 for (i = 0; i < 6; i++) {
2411 struct std_timing *std;
2412 struct drm_display_mode *newmode;
2413
2414 std = &data->data.timings[i];
2415 newmode = drm_mode_std(connector, edid, std);
2416 if (newmode) {
2417 drm_mode_probed_add(connector, newmode);
2418 closure->modes++;
2419 }
2420 }
2421 }
2422 }
2423
2424 /**
2425 * add_standard_modes - get std. modes from EDID and add them
2426 * @connector: connector to add mode(s) to
2427 * @edid: EDID block to scan
2428 *
2429 * Standard modes can be calculated using the appropriate standard (DMT,
2430 * GTF or CVT. Grab them from @edid and add them to the list.
2431 */
2432 static int
2433 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2434 {
2435 int i, modes = 0;
2436 struct detailed_mode_closure closure = {
2437 .connector = connector,
2438 .edid = edid,
2439 };
2440
2441 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2442 struct drm_display_mode *newmode;
2443
2444 newmode = drm_mode_std(connector, edid,
2445 &edid->standard_timings[i]);
2446 if (newmode) {
2447 drm_mode_probed_add(connector, newmode);
2448 modes++;
2449 }
2450 }
2451
2452 if (version_greater(edid, 1, 0))
2453 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2454 &closure);
2455
2456 /* XXX should also look for standard codes in VTB blocks */
2457
2458 return modes + closure.modes;
2459 }
2460
2461 static int drm_cvt_modes(struct drm_connector *connector,
2462 struct detailed_timing *timing)
2463 {
2464 int i, j, modes = 0;
2465 struct drm_display_mode *newmode;
2466 struct drm_device *dev = connector->dev;
2467 struct cvt_timing *cvt;
2468 const int rates[] = { 60, 85, 75, 60, 50 };
2469 const u8 empty[3] = { 0, 0, 0 };
2470
2471 for (i = 0; i < 4; i++) {
2472 int width = 0, height;
2473 cvt = &(timing->data.other_data.data.cvt[i]);
2474
2475 if (!memcmp(cvt->code, empty, 3))
2476 continue;
2477
2478 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2479 switch (cvt->code[1] & 0x0c) {
2480 case 0x00:
2481 width = height * 4 / 3;
2482 break;
2483 case 0x04:
2484 width = height * 16 / 9;
2485 break;
2486 case 0x08:
2487 width = height * 16 / 10;
2488 break;
2489 case 0x0c:
2490 width = height * 15 / 9;
2491 break;
2492 }
2493
2494 for (j = 1; j < 5; j++) {
2495 if (cvt->code[2] & (1 << j)) {
2496 newmode = drm_cvt_mode(dev, width, height,
2497 rates[j], j == 0,
2498 false, false);
2499 if (newmode) {
2500 drm_mode_probed_add(connector, newmode);
2501 modes++;
2502 }
2503 }
2504 }
2505 }
2506
2507 return modes;
2508 }
2509
2510 static void
2511 do_cvt_mode(struct detailed_timing *timing, void *c)
2512 {
2513 struct detailed_mode_closure *closure = c;
2514 struct detailed_non_pixel *data = &timing->data.other_data;
2515
2516 if (data->type == EDID_DETAIL_CVT_3BYTE)
2517 closure->modes += drm_cvt_modes(closure->connector, timing);
2518 }
2519
2520 static int
2521 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2522 {
2523 struct detailed_mode_closure closure = {
2524 .connector = connector,
2525 .edid = edid,
2526 };
2527
2528 if (version_greater(edid, 1, 2))
2529 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2530
2531 /* XXX should also look for CVT codes in VTB blocks */
2532
2533 return closure.modes;
2534 }
2535
2536 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2537
2538 static void
2539 do_detailed_mode(struct detailed_timing *timing, void *c)
2540 {
2541 struct detailed_mode_closure *closure = c;
2542 struct drm_display_mode *newmode;
2543
2544 if (timing->pixel_clock) {
2545 newmode = drm_mode_detailed(closure->connector->dev,
2546 closure->edid, timing,
2547 closure->quirks);
2548 if (!newmode)
2549 return;
2550
2551 if (closure->preferred)
2552 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2553
2554 /*
2555 * Detailed modes are limited to 10kHz pixel clock resolution,
2556 * so fix up anything that looks like CEA/HDMI mode, but the clock
2557 * is just slightly off.
2558 */
2559 fixup_detailed_cea_mode_clock(newmode);
2560
2561 drm_mode_probed_add(closure->connector, newmode);
2562 closure->modes++;
2563 closure->preferred = 0;
2564 }
2565 }
2566
2567 /*
2568 * add_detailed_modes - Add modes from detailed timings
2569 * @connector: attached connector
2570 * @edid: EDID block to scan
2571 * @quirks: quirks to apply
2572 */
2573 static int
2574 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2575 u32 quirks)
2576 {
2577 struct detailed_mode_closure closure = {
2578 .connector = connector,
2579 .edid = edid,
2580 .preferred = 1,
2581 .quirks = quirks,
2582 };
2583
2584 if (closure.preferred && !version_greater(edid, 1, 3))
2585 closure.preferred =
2586 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2587
2588 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2589
2590 return closure.modes;
2591 }
2592
2593 #define AUDIO_BLOCK 0x01
2594 #define VIDEO_BLOCK 0x02
2595 #define VENDOR_BLOCK 0x03
2596 #define SPEAKER_BLOCK 0x04
2597 #define VIDEO_CAPABILITY_BLOCK 0x07
2598 #define EDID_BASIC_AUDIO (1 << 6)
2599 #define EDID_CEA_YCRCB444 (1 << 5)
2600 #define EDID_CEA_YCRCB422 (1 << 4)
2601 #define EDID_CEA_VCDB_QS (1 << 6)
2602
2603 /*
2604 * Search EDID for CEA extension block.
2605 */
2606 static u8 *drm_find_cea_extension(struct edid *edid)
2607 {
2608 u8 *edid_ext = NULL;
2609 int i;
2610
2611 /* No EDID or EDID extensions */
2612 if (edid == NULL || edid->extensions == 0)
2613 return NULL;
2614
2615 /* Find CEA extension */
2616 for (i = 0; i < edid->extensions; i++) {
2617 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2618 if (edid_ext[0] == CEA_EXT)
2619 break;
2620 }
2621
2622 if (i == edid->extensions)
2623 return NULL;
2624
2625 return edid_ext;
2626 }
2627
2628 /*
2629 * Calculate the alternate clock for the CEA mode
2630 * (60Hz vs. 59.94Hz etc.)
2631 */
2632 static unsigned int
2633 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2634 {
2635 unsigned int clock = cea_mode->clock;
2636
2637 if (cea_mode->vrefresh % 6 != 0)
2638 return clock;
2639
2640 /*
2641 * edid_cea_modes contains the 59.94Hz
2642 * variant for 240 and 480 line modes,
2643 * and the 60Hz variant otherwise.
2644 */
2645 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2646 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2647 else
2648 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2649
2650 return clock;
2651 }
2652
2653 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2654 unsigned int clock_tolerance)
2655 {
2656 u8 vic;
2657
2658 if (!to_match->clock)
2659 return 0;
2660
2661 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2662 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2663 unsigned int clock1, clock2;
2664
2665 /* Check both 60Hz and 59.94Hz */
2666 clock1 = cea_mode->clock;
2667 clock2 = cea_mode_alternate_clock(cea_mode);
2668
2669 if (abs(to_match->clock - clock1) > clock_tolerance &&
2670 abs(to_match->clock - clock2) > clock_tolerance)
2671 continue;
2672
2673 if (drm_mode_equal_no_clocks(to_match, cea_mode))
2674 return vic;
2675 }
2676
2677 return 0;
2678 }
2679
2680 /**
2681 * drm_match_cea_mode - look for a CEA mode matching given mode
2682 * @to_match: display mode
2683 *
2684 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2685 * mode.
2686 */
2687 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2688 {
2689 u8 vic;
2690
2691 if (!to_match->clock)
2692 return 0;
2693
2694 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2695 const struct drm_display_mode *cea_mode = &edid_cea_modes[vic];
2696 unsigned int clock1, clock2;
2697
2698 /* Check both 60Hz and 59.94Hz */
2699 clock1 = cea_mode->clock;
2700 clock2 = cea_mode_alternate_clock(cea_mode);
2701
2702 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2703 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2704 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode))
2705 return vic;
2706 }
2707 return 0;
2708 }
2709 EXPORT_SYMBOL(drm_match_cea_mode);
2710
2711 static bool drm_valid_cea_vic(u8 vic)
2712 {
2713 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2714 }
2715
2716 /**
2717 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2718 * the input VIC from the CEA mode list
2719 * @video_code: ID given to each of the CEA modes
2720 *
2721 * Returns picture aspect ratio
2722 */
2723 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2724 {
2725 return edid_cea_modes[video_code].picture_aspect_ratio;
2726 }
2727 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2728
2729 /*
2730 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2731 * specific block).
2732 *
2733 * It's almost like cea_mode_alternate_clock(), we just need to add an
2734 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2735 * one.
2736 */
2737 static unsigned int
2738 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2739 {
2740 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2741 return hdmi_mode->clock;
2742
2743 return cea_mode_alternate_clock(hdmi_mode);
2744 }
2745
2746 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
2747 unsigned int clock_tolerance)
2748 {
2749 u8 vic;
2750
2751 if (!to_match->clock)
2752 return 0;
2753
2754 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2755 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2756 unsigned int clock1, clock2;
2757
2758 /* Make sure to also match alternate clocks */
2759 clock1 = hdmi_mode->clock;
2760 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2761
2762 if (abs(to_match->clock - clock1) > clock_tolerance &&
2763 abs(to_match->clock - clock2) > clock_tolerance)
2764 continue;
2765
2766 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
2767 return vic;
2768 }
2769
2770 return 0;
2771 }
2772
2773 /*
2774 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
2775 * @to_match: display mode
2776 *
2777 * An HDMI mode is one defined in the HDMI vendor specific block.
2778 *
2779 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
2780 */
2781 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
2782 {
2783 u8 vic;
2784
2785 if (!to_match->clock)
2786 return 0;
2787
2788 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
2789 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
2790 unsigned int clock1, clock2;
2791
2792 /* Make sure to also match alternate clocks */
2793 clock1 = hdmi_mode->clock;
2794 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
2795
2796 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
2797 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
2798 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
2799 return vic;
2800 }
2801 return 0;
2802 }
2803
2804 static bool drm_valid_hdmi_vic(u8 vic)
2805 {
2806 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
2807 }
2808
2809 static int
2810 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
2811 {
2812 struct drm_device *dev = connector->dev;
2813 struct drm_display_mode *mode, *tmp;
2814 LINUX_LIST_HEAD(list);
2815 int modes = 0;
2816
2817 /* Don't add CEA modes if the CEA extension block is missing */
2818 if (!drm_find_cea_extension(edid))
2819 return 0;
2820
2821 /*
2822 * Go through all probed modes and create a new mode
2823 * with the alternate clock for certain CEA modes.
2824 */
2825 list_for_each_entry(mode, &connector->probed_modes, head) {
2826 const struct drm_display_mode *cea_mode = NULL;
2827 struct drm_display_mode *newmode;
2828 u8 vic = drm_match_cea_mode(mode);
2829 unsigned int clock1, clock2;
2830
2831 if (drm_valid_cea_vic(vic)) {
2832 cea_mode = &edid_cea_modes[vic];
2833 clock2 = cea_mode_alternate_clock(cea_mode);
2834 } else {
2835 vic = drm_match_hdmi_mode(mode);
2836 if (drm_valid_hdmi_vic(vic)) {
2837 cea_mode = &edid_4k_modes[vic];
2838 clock2 = hdmi_mode_alternate_clock(cea_mode);
2839 }
2840 }
2841
2842 if (!cea_mode)
2843 continue;
2844
2845 clock1 = cea_mode->clock;
2846
2847 if (clock1 == clock2)
2848 continue;
2849
2850 if (mode->clock != clock1 && mode->clock != clock2)
2851 continue;
2852
2853 newmode = drm_mode_duplicate(dev, cea_mode);
2854 if (!newmode)
2855 continue;
2856
2857 /* Carry over the stereo flags */
2858 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
2859
2860 /*
2861 * The current mode could be either variant. Make
2862 * sure to pick the "other" clock for the new mode.
2863 */
2864 if (mode->clock != clock1)
2865 newmode->clock = clock1;
2866 else
2867 newmode->clock = clock2;
2868
2869 list_add_tail(&newmode->head, &list);
2870 }
2871
2872 list_for_each_entry_safe(mode, tmp, &list, head) {
2873 list_del(&mode->head);
2874 drm_mode_probed_add(connector, mode);
2875 modes++;
2876 }
2877
2878 return modes;
2879 }
2880
2881 static struct drm_display_mode *
2882 drm_display_mode_from_vic_index(struct drm_connector *connector,
2883 const u8 *video_db, u8 video_len,
2884 u8 video_index)
2885 {
2886 struct drm_device *dev = connector->dev;
2887 struct drm_display_mode *newmode;
2888 u8 vic;
2889
2890 if (video_db == NULL || video_index >= video_len)
2891 return NULL;
2892
2893 /* CEA modes are numbered 1..127 */
2894 vic = (video_db[video_index] & 127);
2895 if (!drm_valid_cea_vic(vic))
2896 return NULL;
2897
2898 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
2899 if (!newmode)
2900 return NULL;
2901
2902 newmode->vrefresh = 0;
2903
2904 return newmode;
2905 }
2906
2907 static int
2908 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
2909 {
2910 int i, modes = 0;
2911
2912 for (i = 0; i < len; i++) {
2913 struct drm_display_mode *mode;
2914 mode = drm_display_mode_from_vic_index(connector, db, len, i);
2915 if (mode) {
2916 drm_mode_probed_add(connector, mode);
2917 modes++;
2918 }
2919 }
2920
2921 return modes;
2922 }
2923
2924 struct stereo_mandatory_mode {
2925 int width, height, vrefresh;
2926 unsigned int flags;
2927 };
2928
2929 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
2930 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2931 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
2932 { 1920, 1080, 50,
2933 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2934 { 1920, 1080, 60,
2935 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
2936 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2937 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
2938 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
2939 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
2940 };
2941
2942 static bool
2943 stereo_match_mandatory(const struct drm_display_mode *mode,
2944 const struct stereo_mandatory_mode *stereo_mode)
2945 {
2946 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
2947
2948 return mode->hdisplay == stereo_mode->width &&
2949 mode->vdisplay == stereo_mode->height &&
2950 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
2951 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
2952 }
2953
2954 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
2955 {
2956 struct drm_device *dev = connector->dev;
2957 struct drm_display_mode *mode;
2958 struct list_head stereo_modes;
2959 int modes = 0, i;
2960
2961 INIT_LIST_HEAD(&stereo_modes);
2962
2963 list_for_each_entry(mode, &connector->probed_modes, head) {
2964 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
2965 const struct stereo_mandatory_mode *mandatory;
2966 struct drm_display_mode *new_mode;
2967
2968 if (!stereo_match_mandatory(mode,
2969 &stereo_mandatory_modes[i]))
2970 continue;
2971
2972 mandatory = &stereo_mandatory_modes[i];
2973 new_mode = drm_mode_duplicate(dev, mode);
2974 if (!new_mode)
2975 continue;
2976
2977 new_mode->flags |= mandatory->flags;
2978 list_add_tail(&new_mode->head, &stereo_modes);
2979 modes++;
2980 }
2981 }
2982
2983 list_splice_tail(&stereo_modes, &connector->probed_modes);
2984
2985 return modes;
2986 }
2987
2988 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
2989 {
2990 struct drm_device *dev = connector->dev;
2991 struct drm_display_mode *newmode;
2992
2993 if (!drm_valid_hdmi_vic(vic)) {
2994 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
2995 return 0;
2996 }
2997
2998 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
2999 if (!newmode)
3000 return 0;
3001
3002 drm_mode_probed_add(connector, newmode);
3003
3004 return 1;
3005 }
3006
3007 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3008 const u8 *video_db, u8 video_len, u8 video_index)
3009 {
3010 struct drm_display_mode *newmode;
3011 int modes = 0;
3012
3013 if (structure & (1 << 0)) {
3014 newmode = drm_display_mode_from_vic_index(connector, video_db,
3015 video_len,
3016 video_index);
3017 if (newmode) {
3018 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3019 drm_mode_probed_add(connector, newmode);
3020 modes++;
3021 }
3022 }
3023 if (structure & (1 << 6)) {
3024 newmode = drm_display_mode_from_vic_index(connector, video_db,
3025 video_len,
3026 video_index);
3027 if (newmode) {
3028 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3029 drm_mode_probed_add(connector, newmode);
3030 modes++;
3031 }
3032 }
3033 if (structure & (1 << 8)) {
3034 newmode = drm_display_mode_from_vic_index(connector, video_db,
3035 video_len,
3036 video_index);
3037 if (newmode) {
3038 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3039 drm_mode_probed_add(connector, newmode);
3040 modes++;
3041 }
3042 }
3043
3044 return modes;
3045 }
3046
3047 /*
3048 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3049 * @connector: connector corresponding to the HDMI sink
3050 * @db: start of the CEA vendor specific block
3051 * @len: length of the CEA block payload, ie. one can access up to db[len]
3052 *
3053 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3054 * also adds the stereo 3d modes when applicable.
3055 */
3056 static int
3057 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3058 const u8 *video_db, u8 video_len)
3059 {
3060 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3061 u8 vic_len, hdmi_3d_len = 0;
3062 u16 mask;
3063 u16 structure_all;
3064
3065 if (len < 8)
3066 goto out;
3067
3068 /* no HDMI_Video_Present */
3069 if (!(db[8] & (1 << 5)))
3070 goto out;
3071
3072 /* Latency_Fields_Present */
3073 if (db[8] & (1 << 7))
3074 offset += 2;
3075
3076 /* I_Latency_Fields_Present */
3077 if (db[8] & (1 << 6))
3078 offset += 2;
3079
3080 /* the declared length is not long enough for the 2 first bytes
3081 * of additional video format capabilities */
3082 if (len < (8 + offset + 2))
3083 goto out;
3084
3085 /* 3D_Present */
3086 offset++;
3087 if (db[8 + offset] & (1 << 7)) {
3088 modes += add_hdmi_mandatory_stereo_modes(connector);
3089
3090 /* 3D_Multi_present */
3091 multi_present = (db[8 + offset] & 0x60) >> 5;
3092 }
3093
3094 offset++;
3095 vic_len = db[8 + offset] >> 5;
3096 hdmi_3d_len = db[8 + offset] & 0x1f;
3097
3098 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3099 u8 vic;
3100
3101 vic = db[9 + offset + i];
3102 modes += add_hdmi_mode(connector, vic);
3103 }
3104 offset += 1 + vic_len;
3105
3106 if (multi_present == 1)
3107 multi_len = 2;
3108 else if (multi_present == 2)
3109 multi_len = 4;
3110 else
3111 multi_len = 0;
3112
3113 if (len < (8 + offset + hdmi_3d_len - 1))
3114 goto out;
3115
3116 if (hdmi_3d_len < multi_len)
3117 goto out;
3118
3119 if (multi_present == 1 || multi_present == 2) {
3120 /* 3D_Structure_ALL */
3121 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3122
3123 /* check if 3D_MASK is present */
3124 if (multi_present == 2)
3125 mask = (db[10 + offset] << 8) | db[11 + offset];
3126 else
3127 mask = 0xffff;
3128
3129 for (i = 0; i < 16; i++) {
3130 if (mask & (1 << i))
3131 modes += add_3d_struct_modes(connector,
3132 structure_all,
3133 video_db,
3134 video_len, i);
3135 }
3136 }
3137
3138 offset += multi_len;
3139
3140 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3141 int vic_index;
3142 struct drm_display_mode *newmode = NULL;
3143 unsigned int newflag = 0;
3144 bool detail_present;
3145
3146 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3147
3148 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3149 break;
3150
3151 /* 2D_VIC_order_X */
3152 vic_index = db[8 + offset + i] >> 4;
3153
3154 /* 3D_Structure_X */
3155 switch (db[8 + offset + i] & 0x0f) {
3156 case 0:
3157 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3158 break;
3159 case 6:
3160 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3161 break;
3162 case 8:
3163 /* 3D_Detail_X */
3164 if ((db[9 + offset + i] >> 4) == 1)
3165 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3166 break;
3167 }
3168
3169 if (newflag != 0) {
3170 newmode = drm_display_mode_from_vic_index(connector,
3171 video_db,
3172 video_len,
3173 vic_index);
3174
3175 if (newmode) {
3176 newmode->flags |= newflag;
3177 drm_mode_probed_add(connector, newmode);
3178 modes++;
3179 }
3180 }
3181
3182 if (detail_present)
3183 i++;
3184 }
3185
3186 out:
3187 return modes;
3188 }
3189
3190 static int
3191 cea_db_payload_len(const u8 *db)
3192 {
3193 return db[0] & 0x1f;
3194 }
3195
3196 static int
3197 cea_db_tag(const u8 *db)
3198 {
3199 return db[0] >> 5;
3200 }
3201
3202 static int
3203 cea_revision(const u8 *cea)
3204 {
3205 return cea[1];
3206 }
3207
3208 static int
3209 cea_db_offsets(const u8 *cea, int *start, int *end)
3210 {
3211 /* Data block offset in CEA extension block */
3212 *start = 4;
3213 *end = cea[2];
3214 if (*end == 0)
3215 *end = 127;
3216 if (*end < 4 || *end > 127)
3217 return -ERANGE;
3218 return 0;
3219 }
3220
3221 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3222 {
3223 int hdmi_id;
3224
3225 if (cea_db_tag(db) != VENDOR_BLOCK)
3226 return false;
3227
3228 if (cea_db_payload_len(db) < 5)
3229 return false;
3230
3231 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3232
3233 return hdmi_id == HDMI_IEEE_OUI;
3234 }
3235
3236 #define for_each_cea_db(cea, i, start, end) \
3237 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3238
3239 static int
3240 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3241 {
3242 const u8 *cea = drm_find_cea_extension(edid);
3243 const u8 *db, *hdmi = NULL, *video = NULL;
3244 u8 dbl, hdmi_len, video_len = 0;
3245 int modes = 0;
3246
3247 if (cea && cea_revision(cea) >= 3) {
3248 int i, start, end;
3249
3250 if (cea_db_offsets(cea, &start, &end))
3251 return 0;
3252
3253 for_each_cea_db(cea, i, start, end) {
3254 db = &cea[i];
3255 dbl = cea_db_payload_len(db);
3256
3257 if (cea_db_tag(db) == VIDEO_BLOCK) {
3258 video = db + 1;
3259 video_len = dbl;
3260 modes += do_cea_modes(connector, video, dbl);
3261 }
3262 else if (cea_db_is_hdmi_vsdb(db)) {
3263 hdmi = db;
3264 hdmi_len = dbl;
3265 }
3266 }
3267 }
3268
3269 /*
3270 * We parse the HDMI VSDB after having added the cea modes as we will
3271 * be patching their flags when the sink supports stereo 3D.
3272 */
3273 if (hdmi)
3274 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3275 video_len);
3276
3277 return modes;
3278 }
3279
3280 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3281 {
3282 const struct drm_display_mode *cea_mode;
3283 int clock1, clock2, clock;
3284 u8 vic;
3285 const char *type;
3286
3287 /*
3288 * allow 5kHz clock difference either way to account for
3289 * the 10kHz clock resolution limit of detailed timings.
3290 */
3291 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3292 if (drm_valid_cea_vic(vic)) {
3293 type = "CEA";
3294 cea_mode = &edid_cea_modes[vic];
3295 clock1 = cea_mode->clock;
3296 clock2 = cea_mode_alternate_clock(cea_mode);
3297 } else {
3298 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3299 if (drm_valid_hdmi_vic(vic)) {
3300 type = "HDMI";
3301 cea_mode = &edid_4k_modes[vic];
3302 clock1 = cea_mode->clock;
3303 clock2 = hdmi_mode_alternate_clock(cea_mode);
3304 } else {
3305 return;
3306 }
3307 }
3308
3309 /* pick whichever is closest */
3310 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3311 clock = clock1;
3312 else
3313 clock = clock2;
3314
3315 if (mode->clock == clock)
3316 return;
3317
3318 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3319 type, vic, mode->clock, clock);
3320 mode->clock = clock;
3321 }
3322
3323 static void
3324 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db)
3325 {
3326 u8 len = cea_db_payload_len(db);
3327
3328 if (len >= 6) {
3329 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3330 connector->dvi_dual = db[6] & 1;
3331 }
3332 if (len >= 7)
3333 connector->max_tmds_clock = db[7] * 5;
3334 if (len >= 8) {
3335 connector->latency_present[0] = db[8] >> 7;
3336 connector->latency_present[1] = (db[8] >> 6) & 1;
3337 }
3338 if (len >= 9)
3339 connector->video_latency[0] = db[9];
3340 if (len >= 10)
3341 connector->audio_latency[0] = db[10];
3342 if (len >= 11)
3343 connector->video_latency[1] = db[11];
3344 if (len >= 12)
3345 connector->audio_latency[1] = db[12];
3346
3347 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
3348 "max TMDS clock %d, "
3349 "latency present %d %d, "
3350 "video latency %d %d, "
3351 "audio latency %d %d\n",
3352 connector->dvi_dual,
3353 connector->max_tmds_clock,
3354 (int) connector->latency_present[0],
3355 (int) connector->latency_present[1],
3356 connector->video_latency[0],
3357 connector->video_latency[1],
3358 connector->audio_latency[0],
3359 connector->audio_latency[1]);
3360 }
3361
3362 static void
3363 monitor_name(struct detailed_timing *t, void *data)
3364 {
3365 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3366 *(u8 **)data = t->data.other_data.data.str.str;
3367 }
3368
3369 /**
3370 * drm_edid_to_eld - build ELD from EDID
3371 * @connector: connector corresponding to the HDMI/DP sink
3372 * @edid: EDID to parse
3373 *
3374 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3375 * Conn_Type, HDCP and Port_ID ELD fields are left for the graphics driver to
3376 * fill in.
3377 */
3378 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3379 {
3380 uint8_t *eld = connector->eld;
3381 u8 *cea;
3382 u8 *name;
3383 u8 *db;
3384 int total_sad_count = 0;
3385 int mnl;
3386 int dbl;
3387
3388 memset(eld, 0, sizeof(connector->eld));
3389
3390 cea = drm_find_cea_extension(edid);
3391 if (!cea) {
3392 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3393 return;
3394 }
3395
3396 name = NULL;
3397 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name);
3398 /* max: 13 bytes EDID, 16 bytes ELD */
3399 for (mnl = 0; name && mnl < 13; mnl++) {
3400 if (name[mnl] == 0x0a)
3401 break;
3402 eld[20 + mnl] = name[mnl];
3403 }
3404 eld[4] = (cea[1] << 5) | mnl;
3405 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3406
3407 eld[0] = 2 << 3; /* ELD version: 2 */
3408
3409 eld[16] = edid->mfg_id[0];
3410 eld[17] = edid->mfg_id[1];
3411 eld[18] = edid->prod_code[0];
3412 eld[19] = edid->prod_code[1];
3413
3414 if (cea_revision(cea) >= 3) {
3415 int i, start, end;
3416
3417 if (cea_db_offsets(cea, &start, &end)) {
3418 start = 0;
3419 end = 0;
3420 }
3421
3422 for_each_cea_db(cea, i, start, end) {
3423 db = &cea[i];
3424 dbl = cea_db_payload_len(db);
3425
3426 switch (cea_db_tag(db)) {
3427 int sad_count;
3428
3429 case AUDIO_BLOCK:
3430 /* Audio Data Block, contains SADs */
3431 sad_count = min(dbl / 3, 15 - total_sad_count);
3432 if (sad_count >= 1)
3433 memcpy(eld + 20 + mnl + total_sad_count * 3,
3434 &db[1], sad_count * 3);
3435 total_sad_count += sad_count;
3436 break;
3437 case SPEAKER_BLOCK:
3438 /* Speaker Allocation Data Block */
3439 if (dbl >= 1)
3440 eld[7] = db[1];
3441 break;
3442 case VENDOR_BLOCK:
3443 /* HDMI Vendor-Specific Data Block */
3444 if (cea_db_is_hdmi_vsdb(db))
3445 parse_hdmi_vsdb(connector, db);
3446 break;
3447 default:
3448 break;
3449 }
3450 }
3451 }
3452 eld[5] |= total_sad_count << 4;
3453
3454 eld[DRM_ELD_BASELINE_ELD_LEN] =
3455 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3456
3457 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3458 drm_eld_size(eld), total_sad_count);
3459 }
3460 EXPORT_SYMBOL(drm_edid_to_eld);
3461
3462 /**
3463 * drm_edid_to_sad - extracts SADs from EDID
3464 * @edid: EDID to parse
3465 * @sads: pointer that will be set to the extracted SADs
3466 *
3467 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3468 *
3469 * Note: The returned pointer needs to be freed using kfree().
3470 *
3471 * Return: The number of found SADs or negative number on error.
3472 */
3473 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3474 {
3475 int count = 0;
3476 int i, start, end, dbl;
3477 u8 *cea;
3478
3479 cea = drm_find_cea_extension(edid);
3480 if (!cea) {
3481 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3482 return -ENOENT;
3483 }
3484
3485 if (cea_revision(cea) < 3) {
3486 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3487 return -EOPNOTSUPP;
3488 }
3489
3490 if (cea_db_offsets(cea, &start, &end)) {
3491 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3492 return -EPROTO;
3493 }
3494
3495 for_each_cea_db(cea, i, start, end) {
3496 u8 *db = &cea[i];
3497
3498 if (cea_db_tag(db) == AUDIO_BLOCK) {
3499 int j;
3500 dbl = cea_db_payload_len(db);
3501
3502 count = dbl / 3; /* SAD is 3B */
3503 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3504 if (!*sads)
3505 return -ENOMEM;
3506 for (j = 0; j < count; j++) {
3507 u8 *sad = &db[1 + j * 3];
3508
3509 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3510 (*sads)[j].channels = sad[0] & 0x7;
3511 (*sads)[j].freq = sad[1] & 0x7F;
3512 (*sads)[j].byte2 = sad[2];
3513 }
3514 break;
3515 }
3516 }
3517
3518 return count;
3519 }
3520 EXPORT_SYMBOL(drm_edid_to_sad);
3521
3522 /**
3523 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3524 * @edid: EDID to parse
3525 * @sadb: pointer to the speaker block
3526 *
3527 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
3528 *
3529 * Note: The returned pointer needs to be freed using kfree().
3530 *
3531 * Return: The number of found Speaker Allocation Blocks or negative number on
3532 * error.
3533 */
3534 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
3535 {
3536 int count = 0;
3537 int i, start, end, dbl;
3538 const u8 *cea;
3539
3540 cea = drm_find_cea_extension(edid);
3541 if (!cea) {
3542 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3543 return -ENOENT;
3544 }
3545
3546 if (cea_revision(cea) < 3) {
3547 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3548 return -ENOTSUPP;
3549 }
3550
3551 if (cea_db_offsets(cea, &start, &end)) {
3552 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3553 return -EPROTO;
3554 }
3555
3556 for_each_cea_db(cea, i, start, end) {
3557 const u8 *db = &cea[i];
3558
3559 if (cea_db_tag(db) == SPEAKER_BLOCK) {
3560 dbl = cea_db_payload_len(db);
3561
3562 /* Speaker Allocation Data Block */
3563 if (dbl == 3) {
3564 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
3565 if (!*sadb)
3566 return -ENOMEM;
3567 count = dbl;
3568 break;
3569 }
3570 }
3571 }
3572
3573 return count;
3574 }
3575 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
3576
3577 /**
3578 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
3579 * @connector: connector associated with the HDMI/DP sink
3580 * @mode: the display mode
3581 *
3582 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
3583 * the sink doesn't support audio or video.
3584 */
3585 int drm_av_sync_delay(struct drm_connector *connector,
3586 const struct drm_display_mode *mode)
3587 {
3588 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
3589 int a, v;
3590
3591 if (!connector->latency_present[0])
3592 return 0;
3593 if (!connector->latency_present[1])
3594 i = 0;
3595
3596 a = connector->audio_latency[i];
3597 v = connector->video_latency[i];
3598
3599 /*
3600 * HDMI/DP sink doesn't support audio or video?
3601 */
3602 if (a == 255 || v == 255)
3603 return 0;
3604
3605 /*
3606 * Convert raw EDID values to millisecond.
3607 * Treat unknown latency as 0ms.
3608 */
3609 if (a)
3610 a = min(2 * (a - 1), 500);
3611 if (v)
3612 v = min(2 * (v - 1), 500);
3613
3614 return max(v - a, 0);
3615 }
3616 EXPORT_SYMBOL(drm_av_sync_delay);
3617
3618 /**
3619 * drm_select_eld - select one ELD from multiple HDMI/DP sinks
3620 * @encoder: the encoder just changed display mode
3621 *
3622 * It's possible for one encoder to be associated with multiple HDMI/DP sinks.
3623 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD.
3624 *
3625 * Return: The connector associated with the first HDMI/DP sink that has ELD
3626 * attached to it.
3627 */
3628 struct drm_connector *drm_select_eld(struct drm_encoder *encoder)
3629 {
3630 struct drm_connector *connector;
3631 struct drm_device *dev = encoder->dev;
3632
3633 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
3634 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3635
3636 drm_for_each_connector(connector, dev)
3637 if (connector->encoder == encoder && connector->eld[0])
3638 return connector;
3639
3640 return NULL;
3641 }
3642 EXPORT_SYMBOL(drm_select_eld);
3643
3644 /**
3645 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
3646 * @edid: monitor EDID information
3647 *
3648 * Parse the CEA extension according to CEA-861-B.
3649 *
3650 * Return: True if the monitor is HDMI, false if not or unknown.
3651 */
3652 bool drm_detect_hdmi_monitor(struct edid *edid)
3653 {
3654 u8 *edid_ext;
3655 int i;
3656 int start_offset, end_offset;
3657
3658 edid_ext = drm_find_cea_extension(edid);
3659 if (!edid_ext)
3660 return false;
3661
3662 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3663 return false;
3664
3665 /*
3666 * Because HDMI identifier is in Vendor Specific Block,
3667 * search it from all data blocks of CEA extension.
3668 */
3669 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3670 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
3671 return true;
3672 }
3673
3674 return false;
3675 }
3676 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
3677
3678 /**
3679 * drm_detect_monitor_audio - check monitor audio capability
3680 * @edid: EDID block to scan
3681 *
3682 * Monitor should have CEA extension block.
3683 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
3684 * audio' only. If there is any audio extension block and supported
3685 * audio format, assume at least 'basic audio' support, even if 'basic
3686 * audio' is not defined in EDID.
3687 *
3688 * Return: True if the monitor supports audio, false otherwise.
3689 */
3690 bool drm_detect_monitor_audio(struct edid *edid)
3691 {
3692 u8 *edid_ext;
3693 int i, j;
3694 bool has_audio = false;
3695 int start_offset, end_offset;
3696
3697 edid_ext = drm_find_cea_extension(edid);
3698 if (!edid_ext)
3699 goto end;
3700
3701 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
3702
3703 if (has_audio) {
3704 DRM_DEBUG_KMS("Monitor has basic audio support\n");
3705 goto end;
3706 }
3707
3708 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3709 goto end;
3710
3711 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3712 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
3713 has_audio = true;
3714 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
3715 DRM_DEBUG_KMS("CEA audio format %d\n",
3716 (edid_ext[i + j] >> 3) & 0xf);
3717 goto end;
3718 }
3719 }
3720 end:
3721 return has_audio;
3722 }
3723 EXPORT_SYMBOL(drm_detect_monitor_audio);
3724
3725 /**
3726 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
3727 * @edid: EDID block to scan
3728 *
3729 * Check whether the monitor reports the RGB quantization range selection
3730 * as supported. The AVI infoframe can then be used to inform the monitor
3731 * which quantization range (full or limited) is used.
3732 *
3733 * Return: True if the RGB quantization range is selectable, false otherwise.
3734 */
3735 bool drm_rgb_quant_range_selectable(struct edid *edid)
3736 {
3737 u8 *edid_ext;
3738 int i, start, end;
3739
3740 edid_ext = drm_find_cea_extension(edid);
3741 if (!edid_ext)
3742 return false;
3743
3744 if (cea_db_offsets(edid_ext, &start, &end))
3745 return false;
3746
3747 for_each_cea_db(edid_ext, i, start, end) {
3748 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK &&
3749 cea_db_payload_len(&edid_ext[i]) == 2) {
3750 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
3751 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
3752 }
3753 }
3754
3755 return false;
3756 }
3757 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
3758
3759 /**
3760 * drm_assign_hdmi_deep_color_info - detect whether monitor supports
3761 * hdmi deep color modes and update drm_display_info if so.
3762 * @edid: monitor EDID information
3763 * @info: Updated with maximum supported deep color bpc and color format
3764 * if deep color supported.
3765 * @connector: DRM connector, used only for debug output
3766 *
3767 * Parse the CEA extension according to CEA-861-B.
3768 * Return true if HDMI deep color supported, false if not or unknown.
3769 */
3770 static bool drm_assign_hdmi_deep_color_info(struct edid *edid,
3771 struct drm_display_info *info,
3772 struct drm_connector *connector)
3773 {
3774 u8 *edid_ext, *hdmi;
3775 int i;
3776 int start_offset, end_offset;
3777 unsigned int dc_bpc = 0;
3778
3779 edid_ext = drm_find_cea_extension(edid);
3780 if (!edid_ext)
3781 return false;
3782
3783 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
3784 return false;
3785
3786 /*
3787 * Because HDMI identifier is in Vendor Specific Block,
3788 * search it from all data blocks of CEA extension.
3789 */
3790 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
3791 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) {
3792 /* HDMI supports at least 8 bpc */
3793 info->bpc = 8;
3794
3795 hdmi = &edid_ext[i];
3796 if (cea_db_payload_len(hdmi) < 6)
3797 return false;
3798
3799 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
3800 dc_bpc = 10;
3801 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
3802 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
3803 connector->name);
3804 }
3805
3806 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
3807 dc_bpc = 12;
3808 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
3809 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
3810 connector->name);
3811 }
3812
3813 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
3814 dc_bpc = 16;
3815 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
3816 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
3817 connector->name);
3818 }
3819
3820 if (dc_bpc > 0) {
3821 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
3822 connector->name, dc_bpc);
3823 info->bpc = dc_bpc;
3824
3825 /*
3826 * Deep color support mandates RGB444 support for all video
3827 * modes and forbids YCRCB422 support for all video modes per
3828 * HDMI 1.3 spec.
3829 */
3830 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3831
3832 /* YCRCB444 is optional according to spec. */
3833 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
3834 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3835 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
3836 connector->name);
3837 }
3838
3839 /*
3840 * Spec says that if any deep color mode is supported at all,
3841 * then deep color 36 bit must be supported.
3842 */
3843 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
3844 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
3845 connector->name);
3846 }
3847
3848 return true;
3849 }
3850 else {
3851 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
3852 connector->name);
3853 }
3854 }
3855 }
3856
3857 return false;
3858 }
3859
3860 /**
3861 * drm_add_display_info - pull display info out if present
3862 * @edid: EDID data
3863 * @info: display info (attached to connector)
3864 * @connector: connector whose edid is used to build display info
3865 *
3866 * Grab any available display info and stuff it into the drm_display_info
3867 * structure that's part of the connector. Useful for tracking bpp and
3868 * color spaces.
3869 */
3870 static void drm_add_display_info(struct edid *edid,
3871 struct drm_display_info *info,
3872 struct drm_connector *connector)
3873 {
3874 u8 *edid_ext;
3875
3876 info->width_mm = edid->width_cm * 10;
3877 info->height_mm = edid->height_cm * 10;
3878
3879 /* driver figures it out in this case */
3880 info->bpc = 0;
3881 info->color_formats = 0;
3882
3883 if (edid->revision < 3)
3884 return;
3885
3886 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
3887 return;
3888
3889 /* Get data from CEA blocks if present */
3890 edid_ext = drm_find_cea_extension(edid);
3891 if (edid_ext) {
3892 info->cea_rev = edid_ext[1];
3893
3894 /* The existence of a CEA block should imply RGB support */
3895 info->color_formats = DRM_COLOR_FORMAT_RGB444;
3896 if (edid_ext[3] & EDID_CEA_YCRCB444)
3897 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3898 if (edid_ext[3] & EDID_CEA_YCRCB422)
3899 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3900 }
3901
3902 /* HDMI deep color modes supported? Assign to info, if so */
3903 drm_assign_hdmi_deep_color_info(edid, info, connector);
3904
3905 /* Only defined for 1.4 with digital displays */
3906 if (edid->revision < 4)
3907 return;
3908
3909 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
3910 case DRM_EDID_DIGITAL_DEPTH_6:
3911 info->bpc = 6;
3912 break;
3913 case DRM_EDID_DIGITAL_DEPTH_8:
3914 info->bpc = 8;
3915 break;
3916 case DRM_EDID_DIGITAL_DEPTH_10:
3917 info->bpc = 10;
3918 break;
3919 case DRM_EDID_DIGITAL_DEPTH_12:
3920 info->bpc = 12;
3921 break;
3922 case DRM_EDID_DIGITAL_DEPTH_14:
3923 info->bpc = 14;
3924 break;
3925 case DRM_EDID_DIGITAL_DEPTH_16:
3926 info->bpc = 16;
3927 break;
3928 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
3929 default:
3930 info->bpc = 0;
3931 break;
3932 }
3933
3934 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
3935 connector->name, info->bpc);
3936
3937 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
3938 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
3939 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
3940 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
3941 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
3942 }
3943
3944 /**
3945 * drm_add_edid_modes - add modes from EDID data, if available
3946 * @connector: connector we're probing
3947 * @edid: EDID data
3948 *
3949 * Add the specified modes to the connector's mode list.
3950 *
3951 * Return: The number of modes added or 0 if we couldn't find any.
3952 */
3953 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
3954 {
3955 int num_modes = 0;
3956 u32 quirks;
3957
3958 if (edid == NULL) {
3959 return 0;
3960 }
3961 if (!drm_edid_is_valid(edid)) {
3962 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
3963 connector->name);
3964 return 0;
3965 }
3966
3967 quirks = edid_get_quirks(edid);
3968
3969 /*
3970 * EDID spec says modes should be preferred in this order:
3971 * - preferred detailed mode
3972 * - other detailed modes from base block
3973 * - detailed modes from extension blocks
3974 * - CVT 3-byte code modes
3975 * - standard timing codes
3976 * - established timing codes
3977 * - modes inferred from GTF or CVT range information
3978 *
3979 * We get this pretty much right.
3980 *
3981 * XXX order for additional mode types in extension blocks?
3982 */
3983 num_modes += add_detailed_modes(connector, edid, quirks);
3984 num_modes += add_cvt_modes(connector, edid);
3985 num_modes += add_standard_modes(connector, edid);
3986 num_modes += add_established_modes(connector, edid);
3987 num_modes += add_cea_modes(connector, edid);
3988 num_modes += add_alternate_cea_modes(connector, edid);
3989 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
3990 num_modes += add_inferred_modes(connector, edid);
3991
3992 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
3993 edid_fixup_preferred(connector, quirks);
3994
3995 drm_add_display_info(edid, &connector->display_info, connector);
3996
3997 if (quirks & EDID_QUIRK_FORCE_8BPC)
3998 connector->display_info.bpc = 8;
3999
4000 if (quirks & EDID_QUIRK_FORCE_12BPC)
4001 connector->display_info.bpc = 12;
4002
4003 return num_modes;
4004 }
4005 EXPORT_SYMBOL(drm_add_edid_modes);
4006
4007 /**
4008 * drm_add_modes_noedid - add modes for the connectors without EDID
4009 * @connector: connector we're probing
4010 * @hdisplay: the horizontal display limit
4011 * @vdisplay: the vertical display limit
4012 *
4013 * Add the specified modes to the connector's mode list. Only when the
4014 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4015 *
4016 * Return: The number of modes added or 0 if we couldn't find any.
4017 */
4018 int drm_add_modes_noedid(struct drm_connector *connector,
4019 int hdisplay, int vdisplay)
4020 {
4021 int i, count, num_modes = 0;
4022 struct drm_display_mode *mode;
4023 struct drm_device *dev = connector->dev;
4024
4025 count = ARRAY_SIZE(drm_dmt_modes);
4026 if (hdisplay < 0)
4027 hdisplay = 0;
4028 if (vdisplay < 0)
4029 vdisplay = 0;
4030
4031 for (i = 0; i < count; i++) {
4032 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4033 if (hdisplay && vdisplay) {
4034 /*
4035 * Only when two are valid, they will be used to check
4036 * whether the mode should be added to the mode list of
4037 * the connector.
4038 */
4039 if (ptr->hdisplay > hdisplay ||
4040 ptr->vdisplay > vdisplay)
4041 continue;
4042 }
4043 if (drm_mode_vrefresh(ptr) > 61)
4044 continue;
4045 mode = drm_mode_duplicate(dev, ptr);
4046 if (mode) {
4047 drm_mode_probed_add(connector, mode);
4048 num_modes++;
4049 }
4050 }
4051 return num_modes;
4052 }
4053 EXPORT_SYMBOL(drm_add_modes_noedid);
4054
4055 /**
4056 * drm_set_preferred_mode - Sets the preferred mode of a connector
4057 * @connector: connector whose mode list should be processed
4058 * @hpref: horizontal resolution of preferred mode
4059 * @vpref: vertical resolution of preferred mode
4060 *
4061 * Marks a mode as preferred if it matches the resolution specified by @hpref
4062 * and @vpref.
4063 */
4064 void drm_set_preferred_mode(struct drm_connector *connector,
4065 int hpref, int vpref)
4066 {
4067 struct drm_display_mode *mode;
4068
4069 list_for_each_entry(mode, &connector->probed_modes, head) {
4070 if (mode->hdisplay == hpref &&
4071 mode->vdisplay == vpref)
4072 mode->type |= DRM_MODE_TYPE_PREFERRED;
4073 }
4074 }
4075 EXPORT_SYMBOL(drm_set_preferred_mode);
4076
4077 /**
4078 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4079 * data from a DRM display mode
4080 * @frame: HDMI AVI infoframe
4081 * @mode: DRM display mode
4082 *
4083 * Return: 0 on success or a negative error code on failure.
4084 */
4085 int
4086 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4087 const struct drm_display_mode *mode)
4088 {
4089 int err;
4090
4091 if (!frame || !mode)
4092 return -EINVAL;
4093
4094 err = hdmi_avi_infoframe_init(frame);
4095 if (err < 0)
4096 return err;
4097
4098 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4099 frame->pixel_repeat = 1;
4100
4101 frame->video_code = drm_match_cea_mode(mode);
4102
4103 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4104
4105 /*
4106 * Populate picture aspect ratio from either
4107 * user input (if specified) or from the CEA mode list.
4108 */
4109 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4110 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4111 frame->picture_aspect = mode->picture_aspect_ratio;
4112 else if (frame->video_code > 0)
4113 frame->picture_aspect = drm_get_cea_aspect_ratio(
4114 frame->video_code);
4115
4116 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4117 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4118
4119 return 0;
4120 }
4121 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4122
4123 static enum hdmi_3d_structure
4124 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4125 {
4126 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4127
4128 switch (layout) {
4129 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4130 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4131 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4132 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4133 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4134 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4135 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4136 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4137 case DRM_MODE_FLAG_3D_L_DEPTH:
4138 return HDMI_3D_STRUCTURE_L_DEPTH;
4139 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4140 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4141 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4142 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4143 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4144 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4145 default:
4146 return HDMI_3D_STRUCTURE_INVALID;
4147 }
4148 }
4149
4150 /**
4151 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4152 * data from a DRM display mode
4153 * @frame: HDMI vendor infoframe
4154 * @mode: DRM display mode
4155 *
4156 * Note that there's is a need to send HDMI vendor infoframes only when using a
4157 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4158 * function will return -EINVAL, error that can be safely ignored.
4159 *
4160 * Return: 0 on success or a negative error code on failure.
4161 */
4162 int
4163 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4164 const struct drm_display_mode *mode)
4165 {
4166 int err;
4167 u32 s3d_flags;
4168 u8 vic;
4169
4170 if (!frame || !mode)
4171 return -EINVAL;
4172
4173 vic = drm_match_hdmi_mode(mode);
4174 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4175
4176 if (!vic && !s3d_flags)
4177 return -EINVAL;
4178
4179 if (vic && s3d_flags)
4180 return -EINVAL;
4181
4182 err = hdmi_vendor_infoframe_init(frame);
4183 if (err < 0)
4184 return err;
4185
4186 if (vic)
4187 frame->vic = vic;
4188 else
4189 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4190
4191 return 0;
4192 }
4193 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
DragonFly BSD