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Use sysctl_ctx in softc
[dfdiff.git] / sys / dev / netif / em / if_em.c
blob559fea3444defb35f3af38df8aade4da81627808
1 /*
2 *
3 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 *
5 * Copyright (c) 2001-2006, Intel Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * 3. Neither the name of the Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 *
35 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 *
37 * This code is derived from software contributed to The DragonFly Project
38 * by Matthew Dillon <dillon@backplane.com>
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * 3. Neither the name of The DragonFly Project nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific, prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
57 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
58 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
59 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
60 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
61 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
62 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
64 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 * SUCH DAMAGE.
66 *
67 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.66 2008/04/02 11:48:30 sephe Exp $
68 * $FreeBSD$
69 */
70 /*
71 * SERIALIZATION API RULES:
72 *
73 * - If the driver uses the same serializer for the interrupt as for the
74 * ifnet, most of the serialization will be done automatically for the
75 * driver.
76 *
77 * - ifmedia entry points will be serialized by the ifmedia code using the
78 * ifnet serializer.
79 *
80 * - if_* entry points except for if_input will be serialized by the IF
81 * and protocol layers.
82 *
83 * - The device driver must be sure to serialize access from timeout code
84 * installed by the device driver.
85 *
86 * - The device driver typically holds the serializer at the time it wishes
87 * to call if_input. If so, it should pass the serializer to if_input and
88 * note that the serializer might be dropped temporarily by if_input
89 * (e.g. in case it has to bridge the packet to another interface).
90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
95
96 #include "opt_polling.h"
97 #include "opt_inet.h"
98
99 #include <sys/param.h>
100 #include <sys/bus.h>
101 #include <sys/endian.h>
102 #include <sys/kernel.h>
103 #include <sys/ktr.h>
104 #include <sys/malloc.h>
105 #include <sys/mbuf.h>
106 #include <sys/module.h>
107 #include <sys/rman.h>
108 #include <sys/serialize.h>
109 #include <sys/socket.h>
110 #include <sys/sockio.h>
111 #include <sys/sysctl.h>
112
113 #include <net/bpf.h>
114 #include <net/ethernet.h>
115 #include <net/if.h>
116 #include <net/if_arp.h>
117 #include <net/if_dl.h>
118 #include <net/if_media.h>
119 #include <net/if_types.h>
120 #include <net/ifq_var.h>
121 #include <net/vlan/if_vlan_var.h>
122 #include <net/vlan/if_vlan_ether.h>
123
124 #ifdef INET
125 #include <netinet/in.h>
126 #include <netinet/in_systm.h>
127 #include <netinet/in_var.h>
128 #include <netinet/ip.h>
129 #include <netinet/tcp.h>
130 #include <netinet/udp.h>
131 #endif
132
133 #include <dev/netif/em/if_em_hw.h>
134 #include <dev/netif/em/if_em.h>
135
136 #define EM_X60_WORKAROUND
137
138 /*********************************************************************
139 * Set this to one to display debug statistics
140 *********************************************************************/
141 int em_display_debug_stats = 0;
142
143 /*********************************************************************
144 * Driver version
145 *********************************************************************/
146
147 char em_driver_version[] = "6.2.9";
148
149
150 /*********************************************************************
151 * PCI Device ID Table
152 *
153 * Used by probe to select devices to load on
154 * Last field stores an index into em_strings
155 * Last entry must be all 0s
156 *
157 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
158 *********************************************************************/
159
160 static em_vendor_info_t em_vendor_info_array[] =
161 {
162 /* Intel(R) PRO/1000 Network Connection */
163 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0},
164 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
165 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0},
166 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
167 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0},
168
169 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0},
170 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0},
171 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
172 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
173 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0},
174 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0},
175 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
176
177 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0},
178
179 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
180 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
181
182 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
183 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
184 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
185 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
186
187 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
188 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
189 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
190 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
191 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
192
193 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
194 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
195 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
196 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
197 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
198 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
199 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0},
200 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
201 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
202 PCI_ANY_ID, PCI_ANY_ID, 0},
203
204 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0},
205 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
206 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0},
207
208 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
209 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
210 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
211 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
212 PCI_ANY_ID, PCI_ANY_ID, 0},
213 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE,
214 PCI_ANY_ID, PCI_ANY_ID, 0},
215
216 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
217 PCI_ANY_ID, PCI_ANY_ID, 0},
218 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
219 PCI_ANY_ID, PCI_ANY_ID, 0},
220 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
221 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
222 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
223 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0},
224
225 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0},
226 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0},
227 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0},
228
229 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
230 PCI_ANY_ID, PCI_ANY_ID, 0},
231 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
232 PCI_ANY_ID, PCI_ANY_ID, 0},
233 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
234 PCI_ANY_ID, PCI_ANY_ID, 0},
235 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
236 PCI_ANY_ID, PCI_ANY_ID, 0},
237
238 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
239 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
240 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
241 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
242 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
243 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
244 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0},
245
246 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
247 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
248 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
249 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
250 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
251
252 { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
253 { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
254 PCI_ANY_ID, PCI_ANY_ID, 0},
255 { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
256 PCI_ANY_ID, PCI_ANY_ID, 0},
257 { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0},
258 { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0},
259 /* required last entry */
260 { 0, 0, 0, 0, 0}
261 };
262
263 /*********************************************************************
264 * Table of branding strings for all supported NICs.
265 *********************************************************************/
266
267 static const char *em_strings[] = {
268 "Intel(R) PRO/1000 Network Connection"
269 };
270
271 /*********************************************************************
272 * Function prototypes
273 *********************************************************************/
274 static int em_probe(device_t);
275 static int em_attach(device_t);
276 static int em_detach(device_t);
277 static int em_shutdown(device_t);
278 static void em_intr(void *);
279 static int em_suspend(device_t);
280 static int em_resume(device_t);
281 static void em_start(struct ifnet *);
282 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
283 static void em_watchdog(struct ifnet *);
284 static void em_init(void *);
285 static void em_stop(void *);
286 static void em_media_status(struct ifnet *, struct ifmediareq *);
287 static int em_media_change(struct ifnet *);
288 static void em_identify_hardware(struct adapter *);
289 static int em_allocate_pci_resources(device_t);
290 static void em_free_pci_resources(device_t);
291 static void em_local_timer(void *);
292 static int em_hardware_init(struct adapter *);
293 static void em_setup_interface(device_t, struct adapter *);
294 static int em_setup_transmit_structures(struct adapter *);
295 static void em_initialize_transmit_unit(struct adapter *);
296 static int em_setup_receive_structures(struct adapter *);
297 static void em_initialize_receive_unit(struct adapter *);
298 static void em_enable_intr(struct adapter *);
299 static void em_disable_intr(struct adapter *);
300 static void em_free_transmit_structures(struct adapter *);
301 static void em_free_receive_structures(struct adapter *);
302 static void em_update_stats_counters(struct adapter *);
303 static void em_txeof(struct adapter *);
304 static int em_allocate_receive_structures(struct adapter *);
305 static void em_rxeof(struct adapter *, int);
306 static void em_receive_checksum(struct adapter *, struct em_rx_desc *,
307 struct mbuf *);
308 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *,
309 uint32_t *, uint32_t *);
310 static void em_set_promisc(struct adapter *);
311 static void em_disable_promisc(struct adapter *);
312 static void em_set_multi(struct adapter *);
313 static void em_print_hw_stats(struct adapter *);
314 static void em_update_link_status(struct adapter *);
315 static int em_get_buf(int i, struct adapter *, struct mbuf *, int how);
316 static void em_enable_vlans(struct adapter *);
317 static void em_disable_vlans(struct adapter *);
318 static int em_encap(struct adapter *, struct mbuf *);
319 static void em_smartspeed(struct adapter *);
320 static int em_82547_fifo_workaround(struct adapter *, int);
321 static void em_82547_update_fifo_head(struct adapter *, int);
322 static int em_82547_tx_fifo_reset(struct adapter *);
323 static void em_82547_move_tail(void *);
324 static void em_82547_move_tail_serialized(struct adapter *);
325 static int em_dma_malloc(struct adapter *, bus_size_t,
326 struct em_dma_alloc *);
327 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
328 static void em_print_debug_info(struct adapter *);
329 static int em_is_valid_ether_addr(uint8_t *);
330 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
331 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
332 static uint32_t em_fill_descriptors(bus_addr_t address, uint32_t length,
333 PDESC_ARRAY desc_array);
334 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
335 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
336 static void em_add_int_delay_sysctl(struct adapter *, const char *,
337 const char *,
338 struct em_int_delay_info *, int, int);
339
340 /*********************************************************************
341 * FreeBSD Device Interface Entry Points
342 *********************************************************************/
343
344 static device_method_t em_methods[] = {
345 /* Device interface */
346 DEVMETHOD(device_probe, em_probe),
347 DEVMETHOD(device_attach, em_attach),
348 DEVMETHOD(device_detach, em_detach),
349 DEVMETHOD(device_shutdown, em_shutdown),
350 DEVMETHOD(device_suspend, em_suspend),
351 DEVMETHOD(device_resume, em_resume),
352 {0, 0}
353 };
354
355 static driver_t em_driver = {
356 "em", em_methods, sizeof(struct adapter),
357 };
358
359 static devclass_t em_devclass;
360
361 DECLARE_DUMMY_MODULE(if_em);
362 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0);
363
364 /*********************************************************************
365 * Tunable default values.
366 *********************************************************************/
367
368 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
369 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
370
371 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV);
372 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR);
373 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV);
374 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV);
375 static int em_int_throttle_ceil = 10000;
376 static int em_rxd = EM_DEFAULT_RXD;
377 static int em_txd = EM_DEFAULT_TXD;
378 static int em_smart_pwr_down = FALSE;
379
380 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt);
381 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt);
382 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt);
383 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt);
384 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
385 TUNABLE_INT("hw.em.rxd", &em_rxd);
386 TUNABLE_INT("hw.em.txd", &em_txd);
387 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
388
389 /*
390 * Kernel trace for characterization of operations
391 */
392 #if !defined(KTR_IF_EM)
393 #define KTR_IF_EM KTR_ALL
394 #endif
395 KTR_INFO_MASTER(if_em);
396 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0);
397 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0);
398 #ifdef DEVICE_POLLING
399 KTR_INFO(KTR_IF_EM, if_em, poll_beg, 2, "poll begin", 0);
400 KTR_INFO(KTR_IF_EM, if_em, poll_end, 3, "poll end", 0);
401 #endif
402 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0);
403 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0);
404 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0);
405 #define logif(name) KTR_LOG(if_em_ ## name)
406
407 /*********************************************************************
408 * Device identification routine
409 *
410 * em_probe determines if the driver should be loaded on
411 * adapter based on PCI vendor/device id of the adapter.
412 *
413 * return 0 on success, positive on failure
414 *********************************************************************/
415
416 static int
417 em_probe(device_t dev)
418 {
419 em_vendor_info_t *ent;
420
421 uint16_t pci_vendor_id = 0;
422 uint16_t pci_device_id = 0;
423 uint16_t pci_subvendor_id = 0;
424 uint16_t pci_subdevice_id = 0;
425 char adapter_name[60];
426
427 INIT_DEBUGOUT("em_probe: begin");
428
429 pci_vendor_id = pci_get_vendor(dev);
430 if (pci_vendor_id != EM_VENDOR_ID)
431 return (ENXIO);
432
433 pci_device_id = pci_get_device(dev);
434 pci_subvendor_id = pci_get_subvendor(dev);
435 pci_subdevice_id = pci_get_subdevice(dev);
436
437 ent = em_vendor_info_array;
438 while (ent->vendor_id != 0) {
439 if ((pci_vendor_id == ent->vendor_id) &&
440 (pci_device_id == ent->device_id) &&
441
442 ((pci_subvendor_id == ent->subvendor_id) ||
443 (ent->subvendor_id == PCI_ANY_ID)) &&
444
445 ((pci_subdevice_id == ent->subdevice_id) ||
446 (ent->subdevice_id == PCI_ANY_ID))) {
447 ksnprintf(adapter_name, sizeof(adapter_name),
448 "%s, Version - %s", em_strings[ent->index],
449 em_driver_version);
450 device_set_desc_copy(dev, adapter_name);
451 device_set_async_attach(dev, TRUE);
452 return (0);
453 }
454 ent++;
455 }
456
457 return (ENXIO);
458 }
459
460 /*********************************************************************
461 * Device initialization routine
462 *
463 * The attach entry point is called when the driver is being loaded.
464 * This routine identifies the type of hardware, allocates all resources
465 * and initializes the hardware.
466 *
467 * return 0 on success, positive on failure
468 *********************************************************************/
469
470 static int
471 em_attach(device_t dev)
472 {
473 struct adapter *adapter;
474 int tsize, rsize;
475 int error = 0;
476
477 INIT_DEBUGOUT("em_attach: begin");
478
479 adapter = device_get_softc(dev);
480
481 callout_init(&adapter->timer);
482 callout_init(&adapter->tx_fifo_timer);
483
484 adapter->dev = dev;
485 adapter->osdep.dev = dev;
486
487 /* SYSCTL stuff */
488 sysctl_ctx_init(&adapter->sysctl_ctx);
489 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
490 SYSCTL_STATIC_CHILDREN(_hw),
491 OID_AUTO,
492 device_get_nameunit(dev),
493 CTLFLAG_RD,
494 0, "");
495
496 if (adapter->sysctl_tree == NULL) {
497 device_printf(dev, "Unable to create sysctl tree\n");
498 return EIO;
499 }
500
501 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
502 SYSCTL_CHILDREN(adapter->sysctl_tree),
503 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW,
504 (void *)adapter, 0,
505 em_sysctl_debug_info, "I", "Debug Information");
506
507 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
508 SYSCTL_CHILDREN(adapter->sysctl_tree),
509 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW,
510 (void *)adapter, 0,
511 em_sysctl_stats, "I", "Statistics");
512
513 /* Determine hardware revision */
514 em_identify_hardware(adapter);
515
516 /* Set up some sysctls for the tunable interrupt delays */
517 em_add_int_delay_sysctl(adapter, "rx_int_delay",
518 "receive interrupt delay in usecs",
519 &adapter->rx_int_delay,
520 E1000_REG_OFFSET(&adapter->hw, RDTR),
521 em_rx_int_delay_dflt);
522 em_add_int_delay_sysctl(adapter, "tx_int_delay",
523 "transmit interrupt delay in usecs",
524 &adapter->tx_int_delay,
525 E1000_REG_OFFSET(&adapter->hw, TIDV),
526 em_tx_int_delay_dflt);
527 if (adapter->hw.mac_type >= em_82540) {
528 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
529 "receive interrupt delay limit in usecs",
530 &adapter->rx_abs_int_delay,
531 E1000_REG_OFFSET(&adapter->hw, RADV),
532 em_rx_abs_int_delay_dflt);
533 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
534 "transmit interrupt delay limit in usecs",
535 &adapter->tx_abs_int_delay,
536 E1000_REG_OFFSET(&adapter->hw, TADV),
537 em_tx_abs_int_delay_dflt);
538 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
539 SYSCTL_CHILDREN(adapter->sysctl_tree),
540 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
541 adapter, 0, em_sysctl_int_throttle, "I", NULL);
542 }
543
544 /*
545 * Validate number of transmit and receive descriptors. It
546 * must not exceed hardware maximum, and must be multiple
547 * of EM_DBA_ALIGN.
548 */
549 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 ||
550 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) ||
551 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) ||
552 (em_txd < EM_MIN_TXD)) {
553 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
554 EM_DEFAULT_TXD, em_txd);
555 adapter->num_tx_desc = EM_DEFAULT_TXD;
556 } else {
557 adapter->num_tx_desc = em_txd;
558 }
559
560 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 ||
561 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) ||
562 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) ||
563 (em_rxd < EM_MIN_RXD)) {
564 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
565 EM_DEFAULT_RXD, em_rxd);
566 adapter->num_rx_desc = EM_DEFAULT_RXD;
567 } else {
568 adapter->num_rx_desc = em_rxd;
569 }
570
571 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
572 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "rxd",
573 CTLFLAG_RD, &adapter->num_rx_desc, 0, NULL);
574 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
575 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "txd",
576 CTLFLAG_RD, &adapter->num_tx_desc, 0, NULL);
577
578 adapter->hw.autoneg = DO_AUTO_NEG;
579 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
580 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
581 adapter->hw.tbi_compatibility_en = TRUE;
582 adapter->rx_buffer_len = EM_RXBUFFER_2048;
583
584 adapter->hw.phy_init_script = 1;
585 adapter->hw.phy_reset_disable = FALSE;
586
587 #ifndef EM_MASTER_SLAVE
588 adapter->hw.master_slave = em_ms_hw_default;
589 #else
590 adapter->hw.master_slave = EM_MASTER_SLAVE;
591 #endif
592
593 /*
594 * Set the max frame size assuming standard ethernet
595 * sized frames.
596 */
597 adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
598
599 adapter->hw.min_frame_size =
600 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
601
602 /*
603 * This controls when hardware reports transmit completion
604 * status.
605 */
606 adapter->hw.report_tx_early = 1;
607
608 error = em_allocate_pci_resources(dev);
609 if (error)
610 goto fail;
611
612 /* Initialize eeprom parameters */
613 em_init_eeprom_params(&adapter->hw);
614
615 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc),
616 EM_DBA_ALIGN);
617
618 /* Allocate Transmit Descriptor ring */
619 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
620 if (error) {
621 device_printf(dev, "Unable to allocate TxDescriptor memory\n");
622 goto fail;
623 }
624 adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr;
625
626 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc),
627 EM_DBA_ALIGN);
628
629 /* Allocate Receive Descriptor ring */
630 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
631 if (error) {
632 device_printf(dev, "Unable to allocate rx_desc memory\n");
633 goto fail;
634 }
635 adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr;
636
637 /* Initialize the hardware */
638 if (em_hardware_init(adapter)) {
639 device_printf(dev, "Unable to initialize the hardware\n");
640 error = EIO;
641 goto fail;
642 }
643
644 /* Copy the permanent MAC address out of the EEPROM */
645 if (em_read_mac_addr(&adapter->hw) < 0) {
646 device_printf(dev,
647 "EEPROM read error while reading MAC address\n");
648 error = EIO;
649 goto fail;
650 }
651
652 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) {
653 device_printf(dev, "Invalid MAC address\n");
654 error = EIO;
655 goto fail;
656 }
657
658 /* Setup OS specific network interface */
659 em_setup_interface(dev, adapter);
660
661 /* Initialize statistics */
662 em_clear_hw_cntrs(&adapter->hw);
663 em_update_stats_counters(adapter);
664 adapter->hw.get_link_status = 1;
665 em_update_link_status(adapter);
666
667 /* Indicate SOL/IDER usage */
668 if (em_check_phy_reset_block(&adapter->hw)) {
669 device_printf(dev, "PHY reset is blocked due to "
670 "SOL/IDER session.\n");
671 }
672
673 /* Identify 82544 on PCIX */
674 em_get_bus_info(&adapter->hw);
675 if (adapter->hw.bus_type == em_bus_type_pcix &&
676 adapter->hw.mac_type == em_82544)
677 adapter->pcix_82544 = TRUE;
678 else
679 adapter->pcix_82544 = FALSE;
680
681 error = bus_setup_intr(dev, adapter->res_interrupt, INTR_NETSAFE,
682 em_intr, adapter,
683 &adapter->int_handler_tag,
684 adapter->interface_data.ac_if.if_serializer);
685 if (error) {
686 device_printf(dev, "Error registering interrupt handler!\n");
687 ether_ifdetach(&adapter->interface_data.ac_if);
688 goto fail;
689 }
690
691 INIT_DEBUGOUT("em_attach: end");
692 return(0);
693
694 fail:
695 em_detach(dev);
696 return(error);
697 }
698
699 /*********************************************************************
700 * Device removal routine
701 *
702 * The detach entry point is called when the driver is being removed.
703 * This routine stops the adapter and deallocates all the resources
704 * that were allocated for driver operation.
705 *
706 * return 0 on success, positive on failure
707 *********************************************************************/
708
709 static int
710 em_detach(device_t dev)
711 {
712 struct adapter *adapter = device_get_softc(dev);
713
714 INIT_DEBUGOUT("em_detach: begin");
715
716 if (device_is_attached(dev)) {
717 struct ifnet *ifp = &adapter->interface_data.ac_if;
718
719 lwkt_serialize_enter(ifp->if_serializer);
720 adapter->in_detach = 1;
721 em_stop(adapter);
722 em_phy_hw_reset(&adapter->hw);
723 bus_teardown_intr(dev, adapter->res_interrupt,
724 adapter->int_handler_tag);
725 lwkt_serialize_exit(ifp->if_serializer);
726
727 ether_ifdetach(ifp);
728 }
729 bus_generic_detach(dev);
730
731 em_free_pci_resources(dev);
732
733 /* Free Transmit Descriptor ring */
734 if (adapter->tx_desc_base != NULL) {
735 em_dma_free(adapter, &adapter->txdma);
736 adapter->tx_desc_base = NULL;
737 }
738
739 /* Free Receive Descriptor ring */
740 if (adapter->rx_desc_base != NULL) {
741 em_dma_free(adapter, &adapter->rxdma);
742 adapter->rx_desc_base = NULL;
743 }
744
745 /* Free sysctl tree */
746 if (adapter->sysctl_tree != NULL) {
747 adapter->sysctl_tree = NULL;
748 sysctl_ctx_free(&adapter->sysctl_ctx);
749 }
750
751 return (0);
752 }
753
754 /*********************************************************************
755 *
756 * Shutdown entry point
757 *
758 **********************************************************************/
759
760 static int
761 em_shutdown(device_t dev)
762 {
763 struct adapter *adapter = device_get_softc(dev);
764 struct ifnet *ifp = &adapter->interface_data.ac_if;
765
766 lwkt_serialize_enter(ifp->if_serializer);
767 em_stop(adapter);
768 lwkt_serialize_exit(ifp->if_serializer);
769
770 return (0);
771 }
772
773 /*
774 * Suspend/resume device methods.
775 */
776 static int
777 em_suspend(device_t dev)
778 {
779 struct adapter *adapter = device_get_softc(dev);
780 struct ifnet *ifp = &adapter->interface_data.ac_if;
781
782 lwkt_serialize_enter(ifp->if_serializer);
783 em_stop(adapter);
784 lwkt_serialize_exit(ifp->if_serializer);
785 return (0);
786 }
787
788 static int
789 em_resume(device_t dev)
790 {
791 struct adapter *adapter = device_get_softc(dev);
792 struct ifnet *ifp = &adapter->interface_data.ac_if;
793
794 lwkt_serialize_enter(ifp->if_serializer);
795 ifp->if_flags &= ~IFF_RUNNING;
796 em_init(adapter);
797 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
798 em_start(ifp);
799 lwkt_serialize_exit(ifp->if_serializer);
800
801 return bus_generic_resume(dev);
802 }
803
804 /*********************************************************************
805 * Transmit entry point
806 *
807 * em_start is called by the stack to initiate a transmit.
808 * The driver will remain in this routine as long as there are
809 * packets to transmit and transmit resources are available.
810 * In case resources are not available stack is notified and
811 * the packet is requeued.
812 **********************************************************************/
813
814 static void
815 em_start(struct ifnet *ifp)
816 {
817 struct mbuf *m_head;
818 struct adapter *adapter = ifp->if_softc;
819
820 ASSERT_SERIALIZED(ifp->if_serializer);
821
822 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
823 return;
824 if (!adapter->link_active)
825 return;
826 while (!ifq_is_empty(&ifp->if_snd)) {
827 m_head = ifq_poll(&ifp->if_snd);
828
829 if (m_head == NULL)
830 break;
831
832 logif(pkt_txqueue);
833 if (em_encap(adapter, m_head)) {
834 ifp->if_flags |= IFF_OACTIVE;
835 break;
836 }
837 ifq_dequeue(&ifp->if_snd, m_head);
838
839 /* Send a copy of the frame to the BPF listener */
840 ETHER_BPF_MTAP(ifp, m_head);
841
842 /* Set timeout in case hardware has problems transmitting. */
843 ifp->if_timer = EM_TX_TIMEOUT;
844 }
845 }
846
847 /*********************************************************************
848 * Ioctl entry point
849 *
850 * em_ioctl is called when the user wants to configure the
851 * interface.
852 *
853 * return 0 on success, positive on failure
854 **********************************************************************/
855
856 static int
857 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
858 {
859 int max_frame_size, mask, error = 0, reinit = 0;
860 struct ifreq *ifr = (struct ifreq *) data;
861 struct adapter *adapter = ifp->if_softc;
862 uint16_t eeprom_data = 0;
863
864 ASSERT_SERIALIZED(ifp->if_serializer);
865
866 if (adapter->in_detach)
867 return 0;
868
869 switch (command) {
870 case SIOCSIFMTU:
871 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
872 switch (adapter->hw.mac_type) {
873 case em_82573:
874 /*
875 * 82573 only supports jumbo frames
876 * if ASPM is disabled.
877 */
878 em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3,
879 1, &eeprom_data);
880 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
881 max_frame_size = ETHER_MAX_LEN;
882 break;
883 }
884 /* Allow Jumbo frames */
885 /* FALLTHROUGH */
886 case em_82571:
887 case em_82572:
888 case em_ich9lan:
889 case em_80003es2lan: /* Limit Jumbo Frame size */
890 max_frame_size = 9234;
891 break;
892 case em_ich8lan:
893 /* ICH8 does not support jumbo frames */
894 max_frame_size = ETHER_MAX_LEN;
895 break;
896 default:
897 max_frame_size = MAX_JUMBO_FRAME_SIZE;
898 break;
899 }
900 if (ifr->ifr_mtu >
901 max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
902 error = EINVAL;
903 } else {
904 ifp->if_mtu = ifr->ifr_mtu;
905 adapter->hw.max_frame_size =
906 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
907 ifp->if_flags &= ~IFF_RUNNING;
908 em_init(adapter);
909 }
910 break;
911 case SIOCSIFFLAGS:
912 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS "
913 "(Set Interface Flags)");
914 if (ifp->if_flags & IFF_UP) {
915 if (!(ifp->if_flags & IFF_RUNNING)) {
916 em_init(adapter);
917 } else if ((ifp->if_flags ^ adapter->if_flags) &
918 IFF_PROMISC) {
919 em_disable_promisc(adapter);
920 em_set_promisc(adapter);
921 }
922 } else {
923 if (ifp->if_flags & IFF_RUNNING)
924 em_stop(adapter);
925 }
926 adapter->if_flags = ifp->if_flags;
927 break;
928 case SIOCADDMULTI:
929 case SIOCDELMULTI:
930 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
931 if (ifp->if_flags & IFF_RUNNING) {
932 em_disable_intr(adapter);
933 em_set_multi(adapter);
934 if (adapter->hw.mac_type == em_82542_rev2_0)
935 em_initialize_receive_unit(adapter);
936 #ifdef DEVICE_POLLING
937 /* Do not enable interrupt if polling(4) is enabled */
938 if ((ifp->if_flags & IFF_POLLING) == 0)
939 #endif
940 em_enable_intr(adapter);
941 }
942 break;
943 case SIOCSIFMEDIA:
944 /* Check SOL/IDER usage */
945 if (em_check_phy_reset_block(&adapter->hw)) {
946 if_printf(ifp, "Media change is blocked due to "
947 "SOL/IDER session.\n");
948 break;
949 }
950 /* FALLTHROUGH */
951 case SIOCGIFMEDIA:
952 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA "
953 "(Get/Set Interface Media)");
954 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
955 break;
956 case SIOCSIFCAP:
957 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
958 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
959 if (mask & IFCAP_HWCSUM) {
960 ifp->if_capenable ^= IFCAP_HWCSUM;
961 reinit = 1;
962 }
963 if (mask & IFCAP_VLAN_HWTAGGING) {
964 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
965 reinit = 1;
966 }
967 if (reinit && (ifp->if_flags & IFF_RUNNING)) {
968 ifp->if_flags &= ~IFF_RUNNING;
969 em_init(adapter);
970 }
971 break;
972 default:
973 error = ether_ioctl(ifp, command, data);
974 break;
975 }
976
977 return (error);
978 }
979
980 /*********************************************************************
981 * Watchdog entry point
982 *
983 * This routine is called whenever hardware quits transmitting.
984 *
985 **********************************************************************/
986
987 static void
988 em_watchdog(struct ifnet *ifp)
989 {
990 struct adapter *adapter = ifp->if_softc;
991
992 /*
993 * If we are in this routine because of pause frames, then
994 * don't reset the hardware.
995 */
996 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) {
997 ifp->if_timer = EM_TX_TIMEOUT;
998 return;
999 }
1000
1001 if (em_check_for_link(&adapter->hw) == 0)
1002 if_printf(ifp, "watchdog timeout -- resetting\n");
1003
1004 ifp->if_flags &= ~IFF_RUNNING;
1005 em_init(adapter);
1006
1007 adapter->watchdog_timeouts++;
1008 }
1009
1010 /*********************************************************************
1011 * Init entry point
1012 *
1013 * This routine is used in two ways. It is used by the stack as
1014 * init entry point in network interface structure. It is also used
1015 * by the driver as a hw/sw initialization routine to get to a
1016 * consistent state.
1017 *
1018 * return 0 on success, positive on failure
1019 **********************************************************************/
1020
1021 static void
1022 em_init(void *arg)
1023 {
1024 struct adapter *adapter = arg;
1025 uint32_t pba;
1026 struct ifnet *ifp = &adapter->interface_data.ac_if;
1027
1028 ASSERT_SERIALIZED(ifp->if_serializer);
1029
1030 INIT_DEBUGOUT("em_init: begin");
1031
1032 if (ifp->if_flags & IFF_RUNNING)
1033 return;
1034
1035 em_stop(adapter);
1036
1037 /*
1038 * Packet Buffer Allocation (PBA)
1039 * Writing PBA sets the receive portion of the buffer
1040 * the remainder is used for the transmit buffer.
1041 *
1042 * Devices before the 82547 had a Packet Buffer of 64K.
1043 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1044 * After the 82547 the buffer was reduced to 40K.
1045 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1046 * Note: default does not leave enough room for Jumbo Frame >10k.
1047 */
1048 switch (adapter->hw.mac_type) {
1049 case em_82547:
1050 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1051 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1052 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1053 else
1054 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1055
1056 adapter->tx_fifo_head = 0;
1057 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1058 adapter->tx_fifo_size =
1059 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1060 break;
1061 /* Total Packet Buffer on these is 48K */
1062 case em_82571:
1063 case em_82572:
1064 case em_80003es2lan:
1065 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1066 break;
1067 case em_82573: /* 82573: Total Packet Buffer is 32K */
1068 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1069 break;
1070 case em_ich8lan:
1071 pba = E1000_PBA_8K;
1072 break;
1073 case em_ich9lan:
1074 #define E1000_PBA_10K 0x000A
1075 pba = E1000_PBA_10K;
1076 break;
1077 default:
1078 /* Devices before 82547 had a Packet Buffer of 64K. */
1079 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1080 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1081 else
1082 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1083 }
1084
1085 INIT_DEBUGOUT1("em_init: pba=%dK",pba);
1086 E1000_WRITE_REG(&adapter->hw, PBA, pba);
1087
1088 /* Get the latest mac address, User can use a LAA */
1089 bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
1090 ETHER_ADDR_LEN);
1091
1092 /* Initialize the hardware */
1093 if (em_hardware_init(adapter)) {
1094 if_printf(ifp, "Unable to initialize the hardware\n");
1095 return;
1096 }
1097 em_update_link_status(adapter);
1098
1099 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1100 em_enable_vlans(adapter);
1101
1102 /* Set hardware offload abilities */
1103 if (adapter->hw.mac_type >= em_82543) {
1104 if (ifp->if_capenable & IFCAP_TXCSUM)
1105 ifp->if_hwassist = EM_CHECKSUM_FEATURES;
1106 else
1107 ifp->if_hwassist = 0;
1108 }
1109
1110 /* Prepare transmit descriptors and buffers */
1111 if (em_setup_transmit_structures(adapter)) {
1112 if_printf(ifp, "Could not setup transmit structures\n");
1113 em_stop(adapter);
1114 return;
1115 }
1116 em_initialize_transmit_unit(adapter);
1117
1118 /* Setup Multicast table */
1119 em_set_multi(adapter);
1120
1121 /* Prepare receive descriptors and buffers */
1122 if (em_setup_receive_structures(adapter)) {
1123 if_printf(ifp, "Could not setup receive structures\n");
1124 em_stop(adapter);
1125 return;
1126 }
1127 em_initialize_receive_unit(adapter);
1128
1129 /* Don't lose promiscuous settings */
1130 em_set_promisc(adapter);
1131
1132 ifp->if_flags |= IFF_RUNNING;
1133 ifp->if_flags &= ~IFF_OACTIVE;
1134
1135 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1136 em_clear_hw_cntrs(&adapter->hw);
1137
1138 #ifdef DEVICE_POLLING
1139 /* Do not enable interrupt if polling(4) is enabled */
1140 if (ifp->if_flags & IFF_POLLING)
1141 em_disable_intr(adapter);
1142 else
1143 #endif
1144 em_enable_intr(adapter);
1145
1146 /* Don't reset the phy next time init gets called */
1147 adapter->hw.phy_reset_disable = TRUE;
1148 }
1149
1150 #ifdef DEVICE_POLLING
1151
1152 static void
1153 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1154 {
1155 struct adapter *adapter = ifp->if_softc;
1156 uint32_t reg_icr;
1157
1158 logif(poll_beg);
1159
1160 ASSERT_SERIALIZED(ifp->if_serializer);
1161
1162 switch(cmd) {
1163 case POLL_REGISTER:
1164 em_disable_intr(adapter);
1165 break;
1166 case POLL_DEREGISTER:
1167 em_enable_intr(adapter);
1168 break;
1169 case POLL_AND_CHECK_STATUS:
1170 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1171 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1172 callout_stop(&adapter->timer);
1173 adapter->hw.get_link_status = 1;
1174 em_check_for_link(&adapter->hw);
1175 em_update_link_status(adapter);
1176 callout_reset(&adapter->timer, hz, em_local_timer,
1177 adapter);
1178 }
1179 /* fall through */
1180 case POLL_ONLY:
1181 if (ifp->if_flags & IFF_RUNNING) {
1182 em_rxeof(adapter, count);
1183 em_txeof(adapter);
1184
1185 if (!ifq_is_empty(&ifp->if_snd))
1186 em_start(ifp);
1187 }
1188 break;
1189 }
1190 logif(poll_end);
1191 }
1192
1193 #endif /* DEVICE_POLLING */
1194
1195 /*********************************************************************
1196 *
1197 * Interrupt Service routine
1198 *
1199 *********************************************************************/
1200 static void
1201 em_intr(void *arg)
1202 {
1203 uint32_t reg_icr;
1204 struct ifnet *ifp;
1205 struct adapter *adapter = arg;
1206
1207 ifp = &adapter->interface_data.ac_if;
1208
1209 logif(intr_beg);
1210 ASSERT_SERIALIZED(ifp->if_serializer);
1211
1212 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1213 if ((adapter->hw.mac_type >= em_82571 &&
1214 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1215 reg_icr == 0) {
1216 logif(intr_end);
1217 return;
1218 }
1219
1220 /*
1221 * XXX: some laptops trigger several spurious interrupts on em(4)
1222 * when in the resume cycle. The ICR register reports all-ones
1223 * value in this case. Processing such interrupts would lead to
1224 * a freeze. I don't know why.
1225 */
1226 if (reg_icr == 0xffffffff) {
1227 logif(intr_end);
1228 return;
1229 }
1230
1231 /*
1232 * note: do not attempt to improve efficiency by looping. This
1233 * only results in unnecessary piecemeal collection of received
1234 * packets and unnecessary piecemeal cleanups of the transmit ring.
1235 */
1236 if (ifp->if_flags & IFF_RUNNING) {
1237 em_rxeof(adapter, -1);
1238 em_txeof(adapter);
1239 }
1240
1241 /* Link status change */
1242 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1243 callout_stop(&adapter->timer);
1244 adapter->hw.get_link_status = 1;
1245 em_check_for_link(&adapter->hw);
1246 em_update_link_status(adapter);
1247 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1248 }
1249
1250 if (reg_icr & E1000_ICR_RXO)
1251 adapter->rx_overruns++;
1252
1253 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1254 em_start(ifp);
1255 logif(intr_end);
1256 }
1257
1258 /*********************************************************************
1259 *
1260 * Media Ioctl callback
1261 *
1262 * This routine is called whenever the user queries the status of
1263 * the interface using ifconfig.
1264 *
1265 **********************************************************************/
1266 static void
1267 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1268 {
1269 struct adapter *adapter = ifp->if_softc;
1270 u_char fiber_type = IFM_1000_SX;
1271
1272 INIT_DEBUGOUT("em_media_status: begin");
1273
1274 ASSERT_SERIALIZED(ifp->if_serializer);
1275
1276 em_check_for_link(&adapter->hw);
1277 em_update_link_status(adapter);
1278
1279 ifmr->ifm_status = IFM_AVALID;
1280 ifmr->ifm_active = IFM_ETHER;
1281
1282 if (!adapter->link_active)
1283 return;
1284
1285 ifmr->ifm_status |= IFM_ACTIVE;
1286
1287 if (adapter->hw.media_type == em_media_type_fiber ||
1288 adapter->hw.media_type == em_media_type_internal_serdes) {
1289 if (adapter->hw.mac_type == em_82545)
1290 fiber_type = IFM_1000_LX;
1291 ifmr->ifm_active |= fiber_type | IFM_FDX;
1292 } else {
1293 switch (adapter->link_speed) {
1294 case 10:
1295 ifmr->ifm_active |= IFM_10_T;
1296 break;
1297 case 100:
1298 ifmr->ifm_active |= IFM_100_TX;
1299 break;
1300 case 1000:
1301 ifmr->ifm_active |= IFM_1000_T;
1302 break;
1303 }
1304 if (adapter->link_duplex == FULL_DUPLEX)
1305 ifmr->ifm_active |= IFM_FDX;
1306 else
1307 ifmr->ifm_active |= IFM_HDX;
1308 }
1309 }
1310
1311 /*********************************************************************
1312 *
1313 * Media Ioctl callback
1314 *
1315 * This routine is called when the user changes speed/duplex using
1316 * media/mediopt option with ifconfig.
1317 *
1318 **********************************************************************/
1319 static int
1320 em_media_change(struct ifnet *ifp)
1321 {
1322 struct adapter *adapter = ifp->if_softc;
1323 struct ifmedia *ifm = &adapter->media;
1324
1325 INIT_DEBUGOUT("em_media_change: begin");
1326
1327 ASSERT_SERIALIZED(ifp->if_serializer);
1328
1329 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1330 return (EINVAL);
1331
1332 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1333 case IFM_AUTO:
1334 adapter->hw.autoneg = DO_AUTO_NEG;
1335 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1336 break;
1337 case IFM_1000_LX:
1338 case IFM_1000_SX:
1339 case IFM_1000_T:
1340 adapter->hw.autoneg = DO_AUTO_NEG;
1341 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
1342 break;
1343 case IFM_100_TX:
1344 adapter->hw.autoneg = FALSE;
1345 adapter->hw.autoneg_advertised = 0;
1346 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1347 adapter->hw.forced_speed_duplex = em_100_full;
1348 else
1349 adapter->hw.forced_speed_duplex = em_100_half;
1350 break;
1351 case IFM_10_T:
1352 adapter->hw.autoneg = FALSE;
1353 adapter->hw.autoneg_advertised = 0;
1354 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1355 adapter->hw.forced_speed_duplex = em_10_full;
1356 else
1357 adapter->hw.forced_speed_duplex = em_10_half;
1358 break;
1359 default:
1360 if_printf(ifp, "Unsupported media type\n");
1361 }
1362 /*
1363 * As the speed/duplex settings may have changed we need to
1364 * reset the PHY.
1365 */
1366 adapter->hw.phy_reset_disable = FALSE;
1367
1368 ifp->if_flags &= ~IFF_RUNNING;
1369 em_init(adapter);
1370
1371 return(0);
1372 }
1373
1374 static void
1375 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize,
1376 int error)
1377 {
1378 struct em_q *q = arg;
1379
1380 if (error)
1381 return;
1382 KASSERT(nsegs <= EM_MAX_SCATTER,
1383 ("Too many DMA segments returned when mapping tx packet"));
1384 q->nsegs = nsegs;
1385 bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
1386 }
1387
1388 /*********************************************************************
1389 *
1390 * This routine maps the mbufs to tx descriptors.
1391 *
1392 * return 0 on success, positive on failure
1393 **********************************************************************/
1394 static int
1395 em_encap(struct adapter *adapter, struct mbuf *m_head)
1396 {
1397 uint32_t txd_upper = 0, txd_lower = 0, txd_used = 0, txd_saved = 0;
1398 int i, j, error, last = 0;
1399
1400 struct em_q q;
1401 struct em_buffer *tx_buffer = NULL, *tx_buffer_first;
1402 bus_dmamap_t map;
1403 struct em_tx_desc *current_tx_desc = NULL;
1404 struct ifnet *ifp = &adapter->interface_data.ac_if;
1405
1406 /*
1407 * Force a cleanup if number of TX descriptors
1408 * available hits the threshold
1409 */
1410 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1411 em_txeof(adapter);
1412 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1413 adapter->no_tx_desc_avail1++;
1414 return (ENOBUFS);
1415 }
1416 }
1417
1418 /*
1419 * Capture the first descriptor index, this descriptor will have
1420 * the index of the EOP which is the only one that now gets a
1421 * DONE bit writeback.
1422 */
1423 tx_buffer_first = &adapter->tx_buffer_area[adapter->next_avail_tx_desc];
1424
1425 /*
1426 * Map the packet for DMA.
1427 */
1428 map = tx_buffer_first->map;
1429 error = bus_dmamap_load_mbuf(adapter->txtag, map, m_head, em_tx_cb,
1430 &q, BUS_DMA_NOWAIT);
1431 if (error != 0) {
1432 adapter->no_tx_dma_setup++;
1433 return (error);
1434 }
1435 KASSERT(q.nsegs != 0, ("em_encap: empty packet"));
1436
1437 if (q.nsegs > (adapter->num_tx_desc_avail - 2)) {
1438 adapter->no_tx_desc_avail2++;
1439 error = ENOBUFS;
1440 goto fail;
1441 }
1442
1443 if (ifp->if_hwassist > 0) {
1444 em_transmit_checksum_setup(adapter, m_head,
1445 &txd_upper, &txd_lower);
1446 }
1447
1448 i = adapter->next_avail_tx_desc;
1449 if (adapter->pcix_82544)
1450 txd_saved = i;
1451
1452 /* Set up our transmit descriptors */
1453 for (j = 0; j < q.nsegs; j++) {
1454 /* If adapter is 82544 and on PCIX bus */
1455 if(adapter->pcix_82544) {
1456 DESC_ARRAY desc_array;
1457 uint32_t array_elements, counter;
1458
1459 /*
1460 * Check the Address and Length combination and
1461 * split the data accordingly
1462 */
1463 array_elements = em_fill_descriptors(q.segs[j].ds_addr,
1464 q.segs[j].ds_len, &desc_array);
1465 for (counter = 0; counter < array_elements; counter++) {
1466 if (txd_used == adapter->num_tx_desc_avail) {
1467 adapter->next_avail_tx_desc = txd_saved;
1468 adapter->no_tx_desc_avail2++;
1469 error = ENOBUFS;
1470 goto fail;
1471 }
1472 tx_buffer = &adapter->tx_buffer_area[i];
1473 current_tx_desc = &adapter->tx_desc_base[i];
1474 current_tx_desc->buffer_addr = htole64(
1475 desc_array.descriptor[counter].address);
1476 current_tx_desc->lower.data = htole32(
1477 adapter->txd_cmd | txd_lower |
1478 (uint16_t)desc_array.descriptor[counter].length);
1479 current_tx_desc->upper.data = htole32(txd_upper);
1480
1481 last = i;
1482 if (++i == adapter->num_tx_desc)
1483 i = 0;
1484
1485 tx_buffer->m_head = NULL;
1486 tx_buffer->next_eop = -1;
1487 txd_used++;
1488 }
1489 } else {
1490 tx_buffer = &adapter->tx_buffer_area[i];
1491 current_tx_desc = &adapter->tx_desc_base[i];
1492
1493 current_tx_desc->buffer_addr = htole64(q.segs[j].ds_addr);
1494 current_tx_desc->lower.data = htole32(
1495 adapter->txd_cmd | txd_lower | q.segs[j].ds_len);
1496 current_tx_desc->upper.data = htole32(txd_upper);
1497
1498 last = i;
1499 if (++i == adapter->num_tx_desc)
1500 i = 0;
1501
1502 tx_buffer->m_head = NULL;
1503 tx_buffer->next_eop = -1;
1504 }
1505 }
1506
1507 adapter->next_avail_tx_desc = i;
1508 if (adapter->pcix_82544)
1509 adapter->num_tx_desc_avail -= txd_used;
1510 else
1511 adapter->num_tx_desc_avail -= q.nsegs;
1512
1513 /* Find out if we are in vlan mode */
1514 if (m_head->m_flags & M_VLANTAG) {
1515 /* Set the vlan id */
1516 current_tx_desc->upper.fields.special =
1517 htole16(m_head->m_pkthdr.ether_vlantag);
1518
1519 /* Tell hardware to add tag */
1520 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);
1521 }
1522
1523 tx_buffer->m_head = m_head;
1524 tx_buffer_first->map = tx_buffer->map;
1525 tx_buffer->map = map;
1526 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1527
1528 /*
1529 * Last Descriptor of Packet needs End Of Packet (EOP)
1530 * and Report Status (RS)
1531 */
1532 current_tx_desc->lower.data |=
1533 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
1534
1535 /*
1536 * Keep track in the first buffer which descriptor will be
1537 * written back.
1538 */
1539 tx_buffer_first->next_eop = last;
1540
1541 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
1542 BUS_DMASYNC_PREWRITE);
1543
1544 /*
1545 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
1546 * that this frame is available to transmit.
1547 */
1548 if (adapter->hw.mac_type == em_82547 &&
1549 adapter->link_duplex == HALF_DUPLEX) {
1550 em_82547_move_tail_serialized(adapter);
1551 } else {
1552 E1000_WRITE_REG(&adapter->hw, TDT, i);
1553 if (adapter->hw.mac_type == em_82547) {
1554 em_82547_update_fifo_head(adapter,
1555 m_head->m_pkthdr.len);
1556 }
1557 }
1558
1559 return (0);
1560 fail:
1561 bus_dmamap_unload(adapter->txtag, map);
1562 return error;
1563 }
1564
1565 /*********************************************************************
1566 *
1567 * 82547 workaround to avoid controller hang in half-duplex environment.
1568 * The workaround is to avoid queuing a large packet that would span
1569 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1570 * in this case. We do that only when FIFO is quiescent.
1571 *
1572 **********************************************************************/
1573 static void
1574 em_82547_move_tail(void *arg)
1575 {
1576 struct adapter *adapter = arg;
1577 struct ifnet *ifp = &adapter->interface_data.ac_if;
1578
1579 lwkt_serialize_enter(ifp->if_serializer);
1580 em_82547_move_tail_serialized(adapter);
1581 lwkt_serialize_exit(ifp->if_serializer);
1582 }
1583
1584 static void
1585 em_82547_move_tail_serialized(struct adapter *adapter)
1586 {
1587 uint16_t hw_tdt;
1588 uint16_t sw_tdt;
1589 struct em_tx_desc *tx_desc;
1590 uint16_t length = 0;
1591 boolean_t eop = 0;
1592
1593 hw_tdt = E1000_READ_REG(&adapter->hw, TDT);
1594 sw_tdt = adapter->next_avail_tx_desc;
1595
1596 while (hw_tdt != sw_tdt) {
1597 tx_desc = &adapter->tx_desc_base[hw_tdt];
1598 length += tx_desc->lower.flags.length;
1599 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1600 if (++hw_tdt == adapter->num_tx_desc)
1601 hw_tdt = 0;
1602
1603 if (eop) {
1604 if (em_82547_fifo_workaround(adapter, length)) {
1605 adapter->tx_fifo_wrk_cnt++;
1606 callout_reset(&adapter->tx_fifo_timer, 1,
1607 em_82547_move_tail, adapter);
1608 break;
1609 }
1610 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt);
1611 em_82547_update_fifo_head(adapter, length);
1612 length = 0;
1613 }
1614 }
1615 }
1616
1617 static int
1618 em_82547_fifo_workaround(struct adapter *adapter, int len)
1619 {
1620 int fifo_space, fifo_pkt_len;
1621
1622 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1623
1624 if (adapter->link_duplex == HALF_DUPLEX) {
1625 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1626
1627 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1628 if (em_82547_tx_fifo_reset(adapter))
1629 return (0);
1630 else
1631 return (1);
1632 }
1633 }
1634
1635 return (0);
1636 }
1637
1638 static void
1639 em_82547_update_fifo_head(struct adapter *adapter, int len)
1640 {
1641 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1642
1643 /* tx_fifo_head is always 16 byte aligned */
1644 adapter->tx_fifo_head += fifo_pkt_len;
1645 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1646 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1647 }
1648
1649 static int
1650 em_82547_tx_fifo_reset(struct adapter *adapter)
1651 {
1652 uint32_t tctl;
1653
1654 if (E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH) &&
1655 E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH) &&
1656 E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS) &&
1657 E1000_READ_REG(&adapter->hw, TDFPC) == 0) {
1658 /* Disable TX unit */
1659 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1660 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
1661
1662 /* Reset FIFO pointers */
1663 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr);
1664 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr);
1665 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
1666 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
1667
1668 /* Re-enable TX unit */
1669 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1670 E1000_WRITE_FLUSH(&adapter->hw);
1671
1672 adapter->tx_fifo_head = 0;
1673 adapter->tx_fifo_reset_cnt++;
1674
1675 return (TRUE);
1676 } else {
1677 return (FALSE);
1678 }
1679 }
1680
1681 static void
1682 em_set_promisc(struct adapter *adapter)
1683 {
1684 uint32_t reg_rctl;
1685 struct ifnet *ifp = &adapter->interface_data.ac_if;
1686
1687 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1688
1689 adapter->em_insert_vlan_header = 0;
1690 if (ifp->if_flags & IFF_PROMISC) {
1691 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1692 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1693
1694 /*
1695 * Disable VLAN stripping in promiscous mode.
1696 * This enables bridging of vlan tagged frames to occur
1697 * and also allows vlan tags to be seen in tcpdump.
1698 */
1699 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1700 em_disable_vlans(adapter);
1701 adapter->em_insert_vlan_header = 1;
1702 } else if (ifp->if_flags & IFF_ALLMULTI) {
1703 reg_rctl |= E1000_RCTL_MPE;
1704 reg_rctl &= ~E1000_RCTL_UPE;
1705 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1706 }
1707 }
1708
1709 static void
1710 em_disable_promisc(struct adapter *adapter)
1711 {
1712 struct ifnet *ifp = &adapter->interface_data.ac_if;
1713
1714 uint32_t reg_rctl;
1715
1716 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1717
1718 reg_rctl &= (~E1000_RCTL_UPE);
1719 reg_rctl &= (~E1000_RCTL_MPE);
1720 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1721
1722 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1723 em_enable_vlans(adapter);
1724 adapter->em_insert_vlan_header = 0;
1725 }
1726
1727 /*********************************************************************
1728 * Multicast Update
1729 *
1730 * This routine is called whenever multicast address list is updated.
1731 *
1732 **********************************************************************/
1733
1734 static void
1735 em_set_multi(struct adapter *adapter)
1736 {
1737 uint32_t reg_rctl = 0;
1738 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
1739 struct ifmultiaddr *ifma;
1740 int mcnt = 0;
1741 struct ifnet *ifp = &adapter->interface_data.ac_if;
1742
1743 IOCTL_DEBUGOUT("em_set_multi: begin");
1744
1745 if (adapter->hw.mac_type == em_82542_rev2_0) {
1746 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1747 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1748 em_pci_clear_mwi(&adapter->hw);
1749 reg_rctl |= E1000_RCTL_RST;
1750 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1751 msec_delay(5);
1752 }
1753
1754 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1755 if (ifma->ifma_addr->sa_family != AF_LINK)
1756 continue;
1757
1758 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1759 break;
1760
1761 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1762 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
1763 mcnt++;
1764 }
1765
1766 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1767 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1768 reg_rctl |= E1000_RCTL_MPE;
1769 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1770 } else {
1771 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1);
1772 }
1773
1774 if (adapter->hw.mac_type == em_82542_rev2_0) {
1775 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1776 reg_rctl &= ~E1000_RCTL_RST;
1777 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1778 msec_delay(5);
1779 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1780 em_pci_set_mwi(&adapter->hw);
1781 }
1782 }
1783
1784 /*********************************************************************
1785 * Timer routine
1786 *
1787 * This routine checks for link status and updates statistics.
1788 *
1789 **********************************************************************/
1790
1791 static void
1792 em_local_timer(void *arg)
1793 {
1794 struct ifnet *ifp;
1795 struct adapter *adapter = arg;
1796 ifp = &adapter->interface_data.ac_if;
1797
1798 lwkt_serialize_enter(ifp->if_serializer);
1799
1800 em_check_for_link(&adapter->hw);
1801 em_update_link_status(adapter);
1802 em_update_stats_counters(adapter);
1803 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING)
1804 em_print_hw_stats(adapter);
1805 em_smartspeed(adapter);
1806
1807 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1808
1809 lwkt_serialize_exit(ifp->if_serializer);
1810 }
1811
1812 static void
1813 em_update_link_status(struct adapter *adapter)
1814 {
1815 struct ifnet *ifp;
1816 ifp = &adapter->interface_data.ac_if;
1817
1818 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
1819 if (adapter->link_active == 0) {
1820 em_get_speed_and_duplex(&adapter->hw,
1821 &adapter->link_speed,
1822 &adapter->link_duplex);
1823 /* Check if we may set SPEED_MODE bit on PCI-E */
1824 if (adapter->link_speed == SPEED_1000 &&
1825 (adapter->hw.mac_type == em_82571 ||
1826 adapter->hw.mac_type == em_82572)) {
1827 int tarc0;
1828
1829 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
1830 tarc0 |= SPEED_MODE_BIT;
1831 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
1832 }
1833 if (bootverbose) {
1834 if_printf(&adapter->interface_data.ac_if,
1835 "Link is up %d Mbps %s\n",
1836 adapter->link_speed,
1837 adapter->link_duplex == FULL_DUPLEX ?
1838 "Full Duplex" : "Half Duplex");
1839 }
1840 adapter->link_active = 1;
1841 adapter->smartspeed = 0;
1842 ifp->if_baudrate = adapter->link_speed * 1000000;
1843 ifp->if_link_state = LINK_STATE_UP;
1844 if_link_state_change(ifp);
1845 }
1846 } else {
1847 if (adapter->link_active == 1) {
1848 ifp->if_baudrate = 0;
1849 adapter->link_speed = 0;
1850 adapter->link_duplex = 0;
1851 if (bootverbose) {
1852 if_printf(&adapter->interface_data.ac_if,
1853 "Link is Down\n");
1854 }
1855 adapter->link_active = 0;
1856 ifp->if_link_state = LINK_STATE_DOWN;
1857 if_link_state_change(ifp);
1858 }
1859 }
1860 }
1861
1862 /*********************************************************************
1863 *
1864 * This routine disables all traffic on the adapter by issuing a
1865 * global reset on the MAC and deallocates TX/RX buffers.
1866 *
1867 **********************************************************************/
1868
1869 static void
1870 em_stop(void *arg)
1871 {
1872 struct ifnet *ifp;
1873 struct adapter * adapter = arg;
1874 ifp = &adapter->interface_data.ac_if;
1875
1876 ASSERT_SERIALIZED(ifp->if_serializer);
1877
1878 INIT_DEBUGOUT("em_stop: begin");
1879 em_disable_intr(adapter);
1880 em_reset_hw(&adapter->hw);
1881 callout_stop(&adapter->timer);
1882 callout_stop(&adapter->tx_fifo_timer);
1883 em_free_transmit_structures(adapter);
1884 em_free_receive_structures(adapter);
1885
1886 /* Tell the stack that the interface is no longer active */
1887 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1888 ifp->if_timer = 0;
1889 }
1890
1891 /*********************************************************************
1892 *
1893 * Determine hardware revision.
1894 *
1895 **********************************************************************/
1896 static void
1897 em_identify_hardware(struct adapter *adapter)
1898 {
1899 device_t dev = adapter->dev;
1900
1901 /* Make sure our PCI config space has the necessary stuff set */
1902 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1903 if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
1904 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) {
1905 device_printf(dev, "Memory Access and/or Bus Master bits "
1906 "were not set!\n");
1907 adapter->hw.pci_cmd_word |= PCIM_CMD_BUSMASTEREN |
1908 PCIM_CMD_MEMEN;
1909 pci_write_config(dev, PCIR_COMMAND,
1910 adapter->hw.pci_cmd_word, 2);
1911 }
1912
1913 /* Save off the information about this board */
1914 adapter->hw.vendor_id = pci_get_vendor(dev);
1915 adapter->hw.device_id = pci_get_device(dev);
1916 adapter->hw.revision_id = pci_get_revid(dev);
1917 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
1918 adapter->hw.subsystem_id = pci_get_subdevice(dev);
1919
1920 /* Identify the MAC */
1921 if (em_set_mac_type(&adapter->hw))
1922 device_printf(dev, "Unknown MAC Type\n");
1923
1924 if (adapter->hw.mac_type == em_82541 ||
1925 adapter->hw.mac_type == em_82541_rev_2 ||
1926 adapter->hw.mac_type == em_82547 ||
1927 adapter->hw.mac_type == em_82547_rev_2)
1928 adapter->hw.phy_init_script = TRUE;
1929 }
1930
1931 static int
1932 em_allocate_pci_resources(device_t dev)
1933 {
1934 struct adapter *adapter = device_get_softc(dev);
1935 int rid;
1936
1937 rid = PCIR_BAR(0);
1938 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1939 &rid, RF_ACTIVE);
1940 if (adapter->res_memory == NULL) {
1941 device_printf(dev, "Unable to allocate bus resource: memory\n");
1942 return ENXIO;
1943 }
1944 adapter->osdep.mem_bus_space_tag =
1945 rman_get_bustag(adapter->res_memory);
1946 adapter->osdep.mem_bus_space_handle =
1947 rman_get_bushandle(adapter->res_memory);
1948 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
1949
1950 if (adapter->hw.mac_type > em_82543) {
1951 /* Figure our where our IO BAR is ? */
1952 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1953 uint32_t val;
1954
1955 val = pci_read_config(dev, rid, 4);
1956 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1957 adapter->io_rid = rid;
1958 break;
1959 }
1960 rid += 4;
1961 /* check for 64bit BAR */
1962 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1963 rid += 4;
1964 }
1965 if (rid >= PCIR_CIS) {
1966 device_printf(dev, "Unable to locate IO BAR\n");
1967 return (ENXIO);
1968 }
1969
1970 adapter->res_ioport = bus_alloc_resource_any(dev,
1971 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1972 if (!(adapter->res_ioport)) {
1973 device_printf(dev, "Unable to allocate bus resource: "
1974 "ioport\n");
1975 return ENXIO;
1976 }
1977 adapter->hw.io_base = 0;
1978 adapter->osdep.io_bus_space_tag =
1979 rman_get_bustag(adapter->res_ioport);
1980 adapter->osdep.io_bus_space_handle =
1981 rman_get_bushandle(adapter->res_ioport);
1982 }
1983
1984 /* For ICH8 we need to find the flash memory. */
1985 if ((adapter->hw.mac_type == em_ich8lan) ||
1986 (adapter->hw.mac_type == em_ich9lan)) {
1987 rid = EM_FLASH;
1988 adapter->flash_mem = bus_alloc_resource_any(dev,
1989 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1990 if (adapter->flash_mem == NULL) {
1991 device_printf(dev, "Unable to allocate bus resource: "
1992 "flash memory\n");
1993 return ENXIO;
1994 }
1995 adapter->osdep.flash_bus_space_tag =
1996 rman_get_bustag(adapter->flash_mem);
1997 adapter->osdep.flash_bus_space_handle =
1998 rman_get_bushandle(adapter->flash_mem);
1999 }
2000
2001 rid = 0x0;
2002 adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ,
2003 &rid, RF_SHAREABLE | RF_ACTIVE);
2004 if (adapter->res_interrupt == NULL) {
2005 device_printf(dev, "Unable to allocate bus resource: "
2006 "interrupt\n");
2007 return ENXIO;
2008 }
2009
2010 adapter->hw.back = &adapter->osdep;
2011
2012 return 0;
2013 }
2014
2015 static void
2016 em_free_pci_resources(device_t dev)
2017 {
2018 struct adapter *adapter = device_get_softc(dev);
2019
2020 if (adapter->res_interrupt != NULL) {
2021 bus_release_resource(dev, SYS_RES_IRQ, 0,
2022 adapter->res_interrupt);
2023 }
2024 if (adapter->res_memory != NULL) {
2025 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2026 adapter->res_memory);
2027 }
2028
2029 if (adapter->res_ioport != NULL) {
2030 bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid,
2031 adapter->res_ioport);
2032 }
2033
2034 if (adapter->flash_mem != NULL) {
2035 bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH,
2036 adapter->flash_mem);
2037 }
2038 }
2039
2040 /*********************************************************************
2041 *
2042 * Initialize the hardware to a configuration as specified by the
2043 * adapter structure. The controller is reset, the EEPROM is
2044 * verified, the MAC address is set, then the shared initialization
2045 * routines are called.
2046 *
2047 **********************************************************************/
2048 static int
2049 em_hardware_init(struct adapter *adapter)
2050 {
2051 uint16_t rx_buffer_size;
2052
2053 INIT_DEBUGOUT("em_hardware_init: begin");
2054 /* Issue a global reset */
2055 em_reset_hw(&adapter->hw);
2056
2057 /* When hardware is reset, fifo_head is also reset */
2058 adapter->tx_fifo_head = 0;
2059
2060 /* Make sure we have a good EEPROM before we read from it */
2061 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2062 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2063 device_printf(adapter->dev,
2064 "The EEPROM Checksum Is Not Valid\n");
2065 return (EIO);
2066 }
2067 }
2068
2069 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) {
2070 device_printf(adapter->dev,
2071 "EEPROM read error while reading part number\n");
2072 return (EIO);
2073 }
2074
2075 /* Set up smart power down as default off on newer adapters. */
2076 if (!em_smart_pwr_down &&
2077 (adapter->hw.mac_type == em_82571 ||
2078 adapter->hw.mac_type == em_82572)) {
2079 uint16_t phy_tmp = 0;
2080
2081 /* Speed up time to link by disabling smart power down. */
2082 em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
2083 &phy_tmp);
2084 phy_tmp &= ~IGP02E1000_PM_SPD;
2085 em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
2086 phy_tmp);
2087 }
2088
2089 /*
2090 * These parameters control the automatic generation (Tx) and
2091 * response (Rx) to Ethernet PAUSE frames.
2092 * - High water mark should allow for at least two frames to be
2093 * received after sending an XOFF.
2094 * - Low water mark works best when it is very near the high water mark.
2095 * This allows the receiver to restart by sending XON when it has
2096 * drained a bit. Here we use an arbitary value of 1500 which will
2097 * restart after one full frame is pulled from the buffer. There
2098 * could be several smaller frames in the buffer and if so they will
2099 * not trigger the XON until their total number reduces the buffer
2100 * by 1500.
2101 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2102 */
2103 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10);
2104
2105 adapter->hw.fc_high_water =
2106 rx_buffer_size - roundup2(adapter->hw.max_frame_size, 1024);
2107 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500;
2108 if (adapter->hw.mac_type == em_80003es2lan)
2109 adapter->hw.fc_pause_time = 0xFFFF;
2110 else
2111 adapter->hw.fc_pause_time = 1000;
2112 adapter->hw.fc_send_xon = TRUE;
2113 adapter->hw.fc = E1000_FC_FULL;
2114
2115 if (em_init_hw(&adapter->hw) < 0) {
2116 device_printf(adapter->dev, "Hardware Initialization Failed");
2117 return (EIO);
2118 }
2119
2120 em_check_for_link(&adapter->hw);
2121
2122 return (0);
2123 }
2124
2125 /*********************************************************************
2126 *
2127 * Setup networking device structure and register an interface.
2128 *
2129 **********************************************************************/
2130 static void
2131 em_setup_interface(device_t dev, struct adapter *adapter)
2132 {
2133 struct ifnet *ifp;
2134 u_char fiber_type = IFM_1000_SX; /* default type */
2135 INIT_DEBUGOUT("em_setup_interface: begin");
2136
2137 ifp = &adapter->interface_data.ac_if;
2138 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2139 ifp->if_mtu = ETHERMTU;
2140 ifp->if_baudrate = 1000000000;
2141 ifp->if_init = em_init;
2142 ifp->if_softc = adapter;
2143 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2144 ifp->if_ioctl = em_ioctl;
2145 ifp->if_start = em_start;
2146 #ifdef DEVICE_POLLING
2147 ifp->if_poll = em_poll;
2148 #endif
2149 ifp->if_watchdog = em_watchdog;
2150 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2151 ifq_set_ready(&ifp->if_snd);
2152
2153 if (adapter->hw.mac_type >= em_82543)
2154 ifp->if_capabilities |= IFCAP_HWCSUM;
2155
2156 ifp->if_capenable = ifp->if_capabilities;
2157
2158 ether_ifattach(ifp, adapter->hw.mac_addr, NULL);
2159
2160 /*
2161 * Tell the upper layer(s) we support long frames.
2162 */
2163 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2164 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2165 #if 0
2166 ifp->if_capenable |= IFCAP_VLAN_MTU;
2167 #endif
2168
2169 /*
2170 * Specify the media types supported by this adapter and register
2171 * callbacks to update media and link information
2172 */
2173 ifmedia_init(&adapter->media, IFM_IMASK, em_media_change,
2174 em_media_status);
2175 if (adapter->hw.media_type == em_media_type_fiber ||
2176 adapter->hw.media_type == em_media_type_internal_serdes) {
2177 if (adapter->hw.mac_type == em_82545)
2178 fiber_type = IFM_1000_LX;
2179 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2180 0, NULL);
2181 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2182 } else {
2183 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2184 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2185 0, NULL);
2186 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2187 0, NULL);
2188 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2189 0, NULL);
2190 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
2191 0, NULL);
2192 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2193 }
2194 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2195 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2196 }
2197
2198 /*********************************************************************
2199 *
2200 * Workaround for SmartSpeed on 82541 and 82547 controllers
2201 *
2202 **********************************************************************/
2203 static void
2204 em_smartspeed(struct adapter *adapter)
2205 {
2206 uint16_t phy_tmp;
2207
2208 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) ||
2209 !adapter->hw.autoneg ||
2210 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
2211 return;
2212
2213 if (adapter->smartspeed == 0) {
2214 /*
2215 * If Master/Slave config fault is asserted twice,
2216 * we assume back-to-back.
2217 */
2218 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2219 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2220 return;
2221 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2222 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2223 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2224 if (phy_tmp & CR_1000T_MS_ENABLE) {
2225 phy_tmp &= ~CR_1000T_MS_ENABLE;
2226 em_write_phy_reg(&adapter->hw,
2227 PHY_1000T_CTRL, phy_tmp);
2228 adapter->smartspeed++;
2229 if (adapter->hw.autoneg &&
2230 !em_phy_setup_autoneg(&adapter->hw) &&
2231 !em_read_phy_reg(&adapter->hw, PHY_CTRL,
2232 &phy_tmp)) {
2233 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2234 MII_CR_RESTART_AUTO_NEG);
2235 em_write_phy_reg(&adapter->hw,
2236 PHY_CTRL, phy_tmp);
2237 }
2238 }
2239 }
2240 return;
2241 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2242 /* If still no link, perhaps using 2/3 pair cable */
2243 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2244 phy_tmp |= CR_1000T_MS_ENABLE;
2245 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2246 if (adapter->hw.autoneg &&
2247 !em_phy_setup_autoneg(&adapter->hw) &&
2248 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) {
2249 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2250 MII_CR_RESTART_AUTO_NEG);
2251 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp);
2252 }
2253 }
2254 /* Restart process after EM_SMARTSPEED_MAX iterations */
2255 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2256 adapter->smartspeed = 0;
2257 }
2258
2259 /*
2260 * Manage DMA'able memory.
2261 */
2262 static void
2263 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2264 {
2265 if (error)
2266 return;
2267 *(bus_addr_t *)arg = segs->ds_addr;
2268 }
2269
2270 static int
2271 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2272 struct em_dma_alloc *dma)
2273 {
2274 device_t dev = adapter->dev;
2275 int error;
2276
2277 error = bus_dma_tag_create(NULL, /* parent */
2278 EM_DBA_ALIGN, 0, /* alignment, bounds */
2279 BUS_SPACE_MAXADDR, /* lowaddr */
2280 BUS_SPACE_MAXADDR, /* highaddr */
2281 NULL, NULL, /* filter, filterarg */
2282 size, /* maxsize */
2283 1, /* nsegments */
2284 size, /* maxsegsize */
2285 0, /* flags */
2286 &dma->dma_tag);
2287 if (error) {
2288 device_printf(dev, "%s: bus_dma_tag_create failed; error %d\n",
2289 __func__, error);
2290 return error;
2291 }
2292
2293 error = bus_dmamem_alloc(dma->dma_tag, (void**)&dma->dma_vaddr,
2294 BUS_DMA_WAITOK, &dma->dma_map);
2295 if (error) {
2296 device_printf(dev, "%s: bus_dmammem_alloc failed; "
2297 "size %llu, error %d\n",
2298 __func__, (uintmax_t)size, error);
2299 goto fail;
2300 }
2301
2302 error = bus_dmamap_load(dma->dma_tag, dma->dma_map,
2303 dma->dma_vaddr, size,
2304 em_dmamap_cb, &dma->dma_paddr,
2305 BUS_DMA_WAITOK);
2306 if (error) {
2307 device_printf(dev, "%s: bus_dmamap_load failed; error %u\n",
2308 __func__, error);
2309 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2310 goto fail;
2311 }
2312
2313 return 0;
2314 fail:
2315 bus_dma_tag_destroy(dma->dma_tag);
2316 dma->dma_tag = NULL;
2317 return error;
2318 }
2319
2320 static void
2321 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2322 {
2323 if (dma->dma_tag != NULL) {
2324 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2325 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2326 bus_dma_tag_destroy(dma->dma_tag);
2327 dma->dma_tag = NULL;
2328 }
2329 }
2330
2331 /*********************************************************************
2332 *
2333 * Allocate and initialize transmit structures.
2334 *
2335 **********************************************************************/
2336 static int
2337 em_setup_transmit_structures(struct adapter *adapter)
2338 {
2339 struct em_buffer *tx_buffer;
2340 bus_size_t size;
2341 int error, i;
2342
2343 /*
2344 * Setup DMA descriptor areas.
2345 */
2346 size = roundup2(adapter->hw.max_frame_size, MCLBYTES);
2347 if (bus_dma_tag_create(NULL, /* parent */
2348 1, 0, /* alignment, bounds */
2349 BUS_SPACE_MAXADDR, /* lowaddr */
2350 BUS_SPACE_MAXADDR, /* highaddr */
2351 NULL, NULL, /* filter, filterarg */
2352 size, /* maxsize */
2353 EM_MAX_SCATTER, /* nsegments */
2354 size, /* maxsegsize */
2355 0, /* flags */
2356 &adapter->txtag)) {
2357 device_printf(adapter->dev, "Unable to allocate TX DMA tag\n");
2358 return(ENOMEM);
2359 }
2360
2361 adapter->tx_buffer_area =
2362 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2363 M_DEVBUF, M_WAITOK | M_ZERO);
2364
2365 bzero(adapter->tx_desc_base,
2366 sizeof(struct em_tx_desc) * adapter->num_tx_desc);
2367 tx_buffer = adapter->tx_buffer_area;
2368 for (i = 0; i < adapter->num_tx_desc; i++) {
2369 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map);
2370 if (error) {
2371 device_printf(adapter->dev,
2372 "Unable to create TX DMA map\n");
2373 goto fail;
2374 }
2375 tx_buffer++;
2376 }
2377
2378 adapter->next_avail_tx_desc = 0;
2379 adapter->next_tx_to_clean = 0;
2380
2381 /* Set number of descriptors available */
2382 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2383
2384 /* Set checksum context */
2385 adapter->active_checksum_context = OFFLOAD_NONE;
2386
2387 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2388 BUS_DMASYNC_PREWRITE);
2389
2390 return (0);
2391 fail:
2392 em_free_transmit_structures(adapter);
2393 return (error);
2394 }
2395
2396 /*********************************************************************
2397 *
2398 * Enable transmit unit.
2399 *
2400 **********************************************************************/
2401 static void
2402 em_initialize_transmit_unit(struct adapter *adapter)
2403 {
2404 uint32_t reg_tctl;
2405 uint32_t reg_tipg = 0;
2406 uint64_t bus_addr;
2407
2408 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2409
2410 /* Setup the Base and Length of the Tx Descriptor Ring */
2411 bus_addr = adapter->txdma.dma_paddr;
2412 E1000_WRITE_REG(&adapter->hw, TDLEN,
2413 adapter->num_tx_desc * sizeof(struct em_tx_desc));
2414 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32));
2415 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr);
2416
2417 /* Setup the HW Tx Head and Tail descriptor pointers */
2418 E1000_WRITE_REG(&adapter->hw, TDT, 0);
2419 E1000_WRITE_REG(&adapter->hw, TDH, 0);
2420
2421 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2422 E1000_READ_REG(&adapter->hw, TDBAL),
2423 E1000_READ_REG(&adapter->hw, TDLEN));
2424
2425 /* Set the default values for the Tx Inter Packet Gap timer */
2426 switch (adapter->hw.mac_type) {
2427 case em_82542_rev2_0:
2428 case em_82542_rev2_1:
2429 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2430 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2431 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2432 break;
2433 case em_80003es2lan:
2434 reg_tipg = DEFAULT_82543_TIPG_IPGR1;
2435 reg_tipg |=
2436 DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2437 break;
2438 default:
2439 if (adapter->hw.media_type == em_media_type_fiber ||
2440 adapter->hw.media_type == em_media_type_internal_serdes)
2441 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2442 else
2443 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2444 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2445 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2446 }
2447
2448 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);
2449 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value);
2450 if (adapter->hw.mac_type >= em_82540) {
2451 E1000_WRITE_REG(&adapter->hw, TADV,
2452 adapter->tx_abs_int_delay.value);
2453 }
2454
2455 /* Program the Transmit Control Register */
2456 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
2457 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2458 if (adapter->hw.mac_type >= em_82571)
2459 reg_tctl |= E1000_TCTL_MULR;
2460 if (adapter->link_duplex == 1)
2461 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2462 else
2463 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2464
2465 /* This write will effectively turn on the transmit unit. */
2466 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);
2467
2468 /* Setup Transmit Descriptor Base Settings */
2469 adapter->txd_cmd = E1000_TXD_CMD_IFCS;
2470
2471 if (adapter->tx_int_delay.value > 0)
2472 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2473 }
2474
2475 /*********************************************************************
2476 *
2477 * Free all transmit related data structures.
2478 *
2479 **********************************************************************/
2480 static void
2481 em_free_transmit_structures(struct adapter *adapter)
2482 {
2483 struct em_buffer *tx_buffer;
2484 int i;
2485
2486 INIT_DEBUGOUT("free_transmit_structures: begin");
2487
2488 if (adapter->tx_buffer_area != NULL) {
2489 tx_buffer = adapter->tx_buffer_area;
2490 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
2491 if (tx_buffer->m_head != NULL) {
2492 bus_dmamap_unload(adapter->txtag,
2493 tx_buffer->map);
2494 m_freem(tx_buffer->m_head);
2495 }
2496
2497 if (tx_buffer->map != NULL) {
2498 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2499 tx_buffer->map = NULL;
2500 }
2501 tx_buffer->m_head = NULL;
2502 }
2503 }
2504 if (adapter->tx_buffer_area != NULL) {
2505 kfree(adapter->tx_buffer_area, M_DEVBUF);
2506 adapter->tx_buffer_area = NULL;
2507 }
2508 if (adapter->txtag != NULL) {
2509 bus_dma_tag_destroy(adapter->txtag);
2510 adapter->txtag = NULL;
2511 }
2512 }
2513
2514 /*********************************************************************
2515 *
2516 * The offload context needs to be set when we transfer the first
2517 * packet of a particular protocol (TCP/UDP). We change the
2518 * context only if the protocol type changes.
2519 *
2520 **********************************************************************/
2521 static void
2522 em_transmit_checksum_setup(struct adapter *adapter,
2523 struct mbuf *mp,
2524 uint32_t *txd_upper,
2525 uint32_t *txd_lower)
2526 {
2527 struct em_context_desc *TXD;
2528 struct em_buffer *tx_buffer;
2529 int curr_txd;
2530
2531 if (mp->m_pkthdr.csum_flags) {
2532 if (mp->m_pkthdr.csum_flags & CSUM_TCP) {
2533 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2534 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2535 if (adapter->active_checksum_context == OFFLOAD_TCP_IP)
2536 return;
2537 else
2538 adapter->active_checksum_context = OFFLOAD_TCP_IP;
2539 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) {
2540 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2541 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2542 if (adapter->active_checksum_context == OFFLOAD_UDP_IP)
2543 return;
2544 else
2545 adapter->active_checksum_context = OFFLOAD_UDP_IP;
2546 } else {
2547 *txd_upper = 0;
2548 *txd_lower = 0;
2549 return;
2550 }
2551 } else {
2552 *txd_upper = 0;
2553 *txd_lower = 0;
2554 return;
2555 }
2556
2557 /*
2558 * If we reach this point, the checksum offload context
2559 * needs to be reset.
2560 */
2561 curr_txd = adapter->next_avail_tx_desc;
2562 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2563 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd];
2564
2565 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
2566 TXD->lower_setup.ip_fields.ipcso =
2567 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
2568 TXD->lower_setup.ip_fields.ipcse =
2569 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1);
2570
2571 TXD->upper_setup.tcp_fields.tucss =
2572 ETHER_HDR_LEN + sizeof(struct ip);
2573 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2574
2575 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) {
2576 TXD->upper_setup.tcp_fields.tucso =
2577 ETHER_HDR_LEN + sizeof(struct ip) +
2578 offsetof(struct tcphdr, th_sum);
2579 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
2580 TXD->upper_setup.tcp_fields.tucso =
2581 ETHER_HDR_LEN + sizeof(struct ip) +
2582 offsetof(struct udphdr, uh_sum);
2583 }
2584
2585 TXD->tcp_seg_setup.data = htole32(0);
2586 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
2587
2588 tx_buffer->m_head = NULL;
2589 tx_buffer->next_eop = -1;
2590
2591 if (++curr_txd == adapter->num_tx_desc)
2592 curr_txd = 0;
2593
2594 adapter->num_tx_desc_avail--;
2595 adapter->next_avail_tx_desc = curr_txd;
2596 }
2597
2598 /**********************************************************************
2599 *
2600 * Examine each tx_buffer in the used queue. If the hardware is done
2601 * processing the packet then free associated resources. The
2602 * tx_buffer is put back on the free queue.
2603 *
2604 **********************************************************************/
2605
2606 static void
2607 em_txeof(struct adapter *adapter)
2608 {
2609 int first, last, done, num_avail;
2610 struct em_buffer *tx_buffer;
2611 struct em_tx_desc *tx_desc, *eop_desc;
2612 struct ifnet *ifp = &adapter->interface_data.ac_if;
2613
2614 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2615 return;
2616
2617 num_avail = adapter->num_tx_desc_avail;
2618 first = adapter->next_tx_to_clean;
2619 tx_desc = &adapter->tx_desc_base[first];
2620 tx_buffer = &adapter->tx_buffer_area[first];
2621 last = tx_buffer->next_eop;
2622 KKASSERT(last >= 0 && last < adapter->num_tx_desc);
2623 eop_desc = &adapter->tx_desc_base[last];
2624
2625 /*
2626 * Now caculate the terminating index for the cleanup loop below
2627 */
2628 if (++last == adapter->num_tx_desc)
2629 last = 0;
2630 done = last;
2631
2632 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2633 BUS_DMASYNC_POSTREAD);
2634
2635 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2636 while (first != done) {
2637 tx_desc->upper.data = 0;
2638 tx_desc->lower.data = 0;
2639 num_avail++;
2640
2641 logif(pkt_txclean);
2642
2643 if (tx_buffer->m_head) {
2644 ifp->if_opackets++;
2645 bus_dmamap_sync(adapter->txtag, tx_buffer->map,
2646 BUS_DMASYNC_POSTWRITE);
2647 bus_dmamap_unload(adapter->txtag,
2648 tx_buffer->map);
2649
2650 m_freem(tx_buffer->m_head);
2651 tx_buffer->m_head = NULL;
2652 }
2653 tx_buffer->next_eop = -1;
2654
2655 if (++first == adapter->num_tx_desc)
2656 first = 0;
2657
2658 tx_buffer = &adapter->tx_buffer_area[first];
2659 tx_desc = &adapter->tx_desc_base[first];
2660 }
2661 /* See if we can continue to the next packet */
2662 last = tx_buffer->next_eop;
2663 if (last != -1) {
2664 KKASSERT(last >= 0 && last < adapter->num_tx_desc);
2665 eop_desc = &adapter->tx_desc_base[last];
2666 if (++last == adapter->num_tx_desc)
2667 last = 0;
2668 done = last;
2669 } else {
2670 break;
2671 }
2672 }
2673
2674 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2675 BUS_DMASYNC_PREWRITE);
2676
2677 adapter->next_tx_to_clean = first;
2678
2679 /*
2680 * If we have enough room, clear IFF_OACTIVE to tell the stack
2681 * that it is OK to send packets.
2682 * If there are no pending descriptors, clear the timeout. Otherwise,
2683 * if some descriptors have been freed, restart the timeout.
2684 */
2685 if (num_avail > EM_TX_CLEANUP_THRESHOLD) {
2686 ifp->if_flags &= ~IFF_OACTIVE;
2687 if (num_avail == adapter->num_tx_desc)
2688 ifp->if_timer = 0;
2689 else if (num_avail == adapter->num_tx_desc_avail)
2690 ifp->if_timer = EM_TX_TIMEOUT;
2691 }
2692 adapter->num_tx_desc_avail = num_avail;
2693 }
2694
2695 /*********************************************************************
2696 *
2697 * Get a buffer from system mbuf buffer pool.
2698 *
2699 **********************************************************************/
2700 static int
2701 em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp, int how)
2702 {
2703 struct mbuf *mp = nmp;
2704 struct em_buffer *rx_buffer;
2705 struct ifnet *ifp;
2706 bus_addr_t paddr;
2707 int error;
2708
2709 ifp = &adapter->interface_data.ac_if;
2710
2711 if (mp == NULL) {
2712 mp = m_getcl(how, MT_DATA, M_PKTHDR);
2713 if (mp == NULL) {
2714 adapter->mbuf_cluster_failed++;
2715 return (ENOBUFS);
2716 }
2717 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2718 } else {
2719 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2720 mp->m_data = mp->m_ext.ext_buf;
2721 mp->m_next = NULL;
2722 }
2723
2724 if (ifp->if_mtu <= ETHERMTU)
2725 m_adj(mp, ETHER_ALIGN);
2726
2727 rx_buffer = &adapter->rx_buffer_area[i];
2728
2729 /*
2730 * Using memory from the mbuf cluster pool, invoke the
2731 * bus_dma machinery to arrange the memory mapping.
2732 */
2733 error = bus_dmamap_load(adapter->rxtag, rx_buffer->map,
2734 mtod(mp, void *), mp->m_len,
2735 em_dmamap_cb, &paddr, 0);
2736 if (error) {
2737 m_freem(mp);
2738 return (error);
2739 }
2740 rx_buffer->m_head = mp;
2741 adapter->rx_desc_base[i].buffer_addr = htole64(paddr);
2742 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD);
2743
2744 return (0);
2745 }
2746
2747 /*********************************************************************
2748 *
2749 * Allocate memory for rx_buffer structures. Since we use one
2750 * rx_buffer per received packet, the maximum number of rx_buffer's
2751 * that we'll need is equal to the number of receive descriptors
2752 * that we've allocated.
2753 *
2754 **********************************************************************/
2755 static int
2756 em_allocate_receive_structures(struct adapter *adapter)
2757 {
2758 int i, error, size;
2759 struct em_buffer *rx_buffer;
2760
2761 size = adapter->num_rx_desc * sizeof(struct em_buffer);
2762 adapter->rx_buffer_area = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
2763
2764 error = bus_dma_tag_create(NULL, /* parent */
2765 1, 0, /* alignment, bounds */
2766 BUS_SPACE_MAXADDR, /* lowaddr */
2767 BUS_SPACE_MAXADDR, /* highaddr */
2768 NULL, NULL, /* filter, filterarg */
2769 MCLBYTES, /* maxsize */
2770 1, /* nsegments */
2771 MCLBYTES, /* maxsegsize */
2772 0, /* flags */
2773 &adapter->rxtag);
2774 if (error) {
2775 device_printf(adapter->dev, "%s: bus_dma_tag_create failed; "
2776 "error %u\n", __func__, error);
2777 goto fail;
2778 }
2779
2780 rx_buffer = adapter->rx_buffer_area;
2781 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2782 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT,
2783 &rx_buffer->map);
2784 if (error) {
2785 device_printf(adapter->dev,
2786 "%s: bus_dmamap_create failed; "
2787 "error %u\n", __func__, error);
2788 goto fail;
2789 }
2790 }
2791
2792 for (i = 0; i < adapter->num_rx_desc; i++) {
2793 error = em_get_buf(i, adapter, NULL, MB_DONTWAIT);
2794 if (error)
2795 goto fail;
2796 }
2797
2798 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2799 BUS_DMASYNC_PREWRITE);
2800
2801 return (0);
2802 fail:
2803 em_free_receive_structures(adapter);
2804 return (error);
2805 }
2806
2807 /*********************************************************************
2808 *
2809 * Allocate and initialize receive structures.
2810 *
2811 **********************************************************************/
2812 static int
2813 em_setup_receive_structures(struct adapter *adapter)
2814 {
2815 int error;
2816
2817 bzero(adapter->rx_desc_base,
2818 sizeof(struct em_rx_desc) * adapter->num_rx_desc);
2819
2820 error = em_allocate_receive_structures(adapter);
2821 if (error)
2822 return (error);
2823
2824 /* Setup our descriptor pointers */
2825 adapter->next_rx_desc_to_check = 0;
2826
2827 return (0);
2828 }
2829
2830 /*********************************************************************
2831 *
2832 * Enable receive unit.
2833 *
2834 **********************************************************************/
2835 static void
2836 em_initialize_receive_unit(struct adapter *adapter)
2837 {
2838 uint32_t reg_rctl;
2839 uint32_t reg_rxcsum;
2840 struct ifnet *ifp;
2841 uint64_t bus_addr;
2842
2843 INIT_DEBUGOUT("em_initialize_receive_unit: begin");
2844
2845 ifp = &adapter->interface_data.ac_if;
2846
2847 /*
2848 * Make sure receives are disabled while setting
2849 * up the descriptor ring
2850 */
2851 E1000_WRITE_REG(&adapter->hw, RCTL, 0);
2852
2853 /* Set the Receive Delay Timer Register */
2854 E1000_WRITE_REG(&adapter->hw, RDTR,
2855 adapter->rx_int_delay.value | E1000_RDT_FPDB);
2856
2857 if(adapter->hw.mac_type >= em_82540) {
2858 E1000_WRITE_REG(&adapter->hw, RADV,
2859 adapter->rx_abs_int_delay.value);
2860
2861 /* Set the interrupt throttling rate in 256ns increments */
2862 if (em_int_throttle_ceil) {
2863 E1000_WRITE_REG(&adapter->hw, ITR,
2864 1000000000 / 256 / em_int_throttle_ceil);
2865 } else {
2866 E1000_WRITE_REG(&adapter->hw, ITR, 0);
2867 }
2868 }
2869
2870 /* Setup the Base and Length of the Rx Descriptor Ring */
2871 bus_addr = adapter->rxdma.dma_paddr;
2872 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc *
2873 sizeof(struct em_rx_desc));
2874 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32));
2875 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr);
2876
2877 /* Setup the Receive Control Register */
2878 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2879 E1000_RCTL_RDMTS_HALF |
2880 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
2881
2882 if (adapter->hw.tbi_compatibility_on == TRUE)
2883 reg_rctl |= E1000_RCTL_SBP;
2884
2885 switch (adapter->rx_buffer_len) {
2886 default:
2887 case EM_RXBUFFER_2048:
2888 reg_rctl |= E1000_RCTL_SZ_2048;
2889 break;
2890 case EM_RXBUFFER_4096:
2891 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX |
2892 E1000_RCTL_LPE;
2893 break;
2894 case EM_RXBUFFER_8192:
2895 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX |
2896 E1000_RCTL_LPE;
2897 break;
2898 case EM_RXBUFFER_16384:
2899 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX |
2900 E1000_RCTL_LPE;
2901 break;
2902 }
2903
2904 if (ifp->if_mtu > ETHERMTU)
2905 reg_rctl |= E1000_RCTL_LPE;
2906
2907 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2908 if ((adapter->hw.mac_type >= em_82543) &&
2909 (ifp->if_capenable & IFCAP_RXCSUM)) {
2910 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
2911 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2912 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum);
2913 }
2914
2915 #ifdef EM_X60_WORKAROUND
2916 if (adapter->hw.mac_type == em_82573)
2917 E1000_WRITE_REG(&adapter->hw, RDTR, 32);
2918 #endif
2919
2920 /* Enable Receives */
2921 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
2922
2923 /* Setup the HW Rx Head and Tail Descriptor Pointers */
2924 E1000_WRITE_REG(&adapter->hw, RDH, 0);
2925 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
2926 }
2927
2928 /*********************************************************************
2929 *
2930 * Free receive related data structures.
2931 *
2932 **********************************************************************/
2933 static void
2934 em_free_receive_structures(struct adapter *adapter)
2935 {
2936 struct em_buffer *rx_buffer;
2937 int i;
2938
2939 INIT_DEBUGOUT("free_receive_structures: begin");
2940
2941 if (adapter->rx_buffer_area != NULL) {
2942 rx_buffer = adapter->rx_buffer_area;
2943 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2944 if (rx_buffer->m_head != NULL) {
2945 bus_dmamap_unload(adapter->rxtag,
2946 rx_buffer->map);
2947 m_freem(rx_buffer->m_head);
2948 rx_buffer->m_head = NULL;
2949 }
2950 if (rx_buffer->map != NULL) {
2951 bus_dmamap_destroy(adapter->rxtag,
2952 rx_buffer->map);
2953 rx_buffer->map = NULL;
2954 }
2955 }
2956 }
2957 if (adapter->rx_buffer_area != NULL) {
2958 kfree(adapter->rx_buffer_area, M_DEVBUF);
2959 adapter->rx_buffer_area = NULL;
2960 }
2961 if (adapter->rxtag != NULL) {
2962 bus_dma_tag_destroy(adapter->rxtag);
2963 adapter->rxtag = NULL;
2964 }
2965 }
2966
2967 /*********************************************************************
2968 *
2969 * This routine executes in interrupt context. It replenishes
2970 * the mbufs in the descriptor and sends data which has been
2971 * dma'ed into host memory to upper layer.
2972 *
2973 * We loop at most count times if count is > 0, or until done if
2974 * count < 0.
2975 *
2976 *********************************************************************/
2977 static void
2978 em_rxeof(struct adapter *adapter, int count)
2979 {
2980 struct ifnet *ifp;
2981 struct mbuf *mp;
2982 uint8_t accept_frame = 0;
2983 uint8_t eop = 0;
2984 uint16_t len, desc_len, prev_len_adj;
2985 int i;
2986
2987 /* Pointer to the receive descriptor being examined. */
2988 struct em_rx_desc *current_desc;
2989
2990 ifp = &adapter->interface_data.ac_if;
2991 i = adapter->next_rx_desc_to_check;
2992 current_desc = &adapter->rx_desc_base[i];
2993
2994 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2995 BUS_DMASYNC_POSTREAD);
2996
2997 if (!(current_desc->status & E1000_RXD_STAT_DD))
2998 return;
2999
3000 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3001 logif(pkt_receive);
3002 mp = adapter->rx_buffer_area[i].m_head;
3003 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3004 BUS_DMASYNC_POSTREAD);
3005 bus_dmamap_unload(adapter->rxtag,
3006 adapter->rx_buffer_area[i].map);
3007
3008 accept_frame = 1;
3009 prev_len_adj = 0;
3010 desc_len = le16toh(current_desc->length);
3011 if (current_desc->status & E1000_RXD_STAT_EOP) {
3012 count--;
3013 eop = 1;
3014 if (desc_len < ETHER_CRC_LEN) {
3015 len = 0;
3016 prev_len_adj = ETHER_CRC_LEN - desc_len;
3017 } else {
3018 len = desc_len - ETHER_CRC_LEN;
3019 }
3020 } else {
3021 eop = 0;
3022 len = desc_len;
3023 }
3024
3025 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3026 uint8_t last_byte;
3027 uint32_t pkt_len = desc_len;
3028
3029 if (adapter->fmp != NULL)
3030 pkt_len += adapter->fmp->m_pkthdr.len;
3031
3032 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3033
3034 if (TBI_ACCEPT(&adapter->hw, current_desc->status,
3035 current_desc->errors,
3036 pkt_len, last_byte)) {
3037 em_tbi_adjust_stats(&adapter->hw,
3038 &adapter->stats,
3039 pkt_len,
3040 adapter->hw.mac_addr);
3041 if (len > 0)
3042 len--;
3043 } else {
3044 accept_frame = 0;
3045 }
3046 }
3047
3048 if (accept_frame) {
3049 if (em_get_buf(i, adapter, NULL, MB_DONTWAIT) == ENOBUFS) {
3050 adapter->dropped_pkts++;
3051 em_get_buf(i, adapter, mp, MB_DONTWAIT);
3052 if (adapter->fmp != NULL)
3053 m_freem(adapter->fmp);
3054 adapter->fmp = NULL;
3055 adapter->lmp = NULL;
3056 goto skip;
3057 }
3058
3059 /* Assign correct length to the current fragment */
3060 mp->m_len = len;
3061
3062 if (adapter->fmp == NULL) {
3063 mp->m_pkthdr.len = len;
3064 adapter->fmp = mp; /* Store the first mbuf */
3065 adapter->lmp = mp;
3066 } else {
3067 /* Chain mbuf's together */
3068 /*
3069 * Adjust length of previous mbuf in chain if
3070 * we received less than 4 bytes in the last
3071 * descriptor.
3072 */
3073 if (prev_len_adj > 0) {
3074 adapter->lmp->m_len -= prev_len_adj;
3075 adapter->fmp->m_pkthdr.len -= prev_len_adj;
3076 }
3077 adapter->lmp->m_next = mp;
3078 adapter->lmp = adapter->lmp->m_next;
3079 adapter->fmp->m_pkthdr.len += len;
3080 }
3081
3082 if (eop) {
3083 adapter->fmp->m_pkthdr.rcvif = ifp;
3084 ifp->if_ipackets++;
3085
3086 em_receive_checksum(adapter, current_desc,
3087 adapter->fmp);
3088 if (current_desc->status & E1000_RXD_STAT_VP) {
3089 VLAN_INPUT_TAG(adapter->fmp,
3090 (current_desc->special &
3091 E1000_RXD_SPC_VLAN_MASK));
3092 } else {
3093 ifp->if_input(ifp, adapter->fmp);
3094 }
3095 adapter->fmp = NULL;
3096 adapter->lmp = NULL;
3097 }
3098 } else {
3099 adapter->dropped_pkts++;
3100 em_get_buf(i, adapter, mp, MB_DONTWAIT);
3101 if (adapter->fmp != NULL)
3102 m_freem(adapter->fmp);
3103 adapter->fmp = NULL;
3104 adapter->lmp = NULL;
3105 }
3106
3107 skip:
3108 /* Zero out the receive descriptors status. */
3109 current_desc->status = 0;
3110
3111 /* Advance our pointers to the next descriptor. */
3112 if (++i == adapter->num_rx_desc) {
3113 i = 0;
3114 current_desc = adapter->rx_desc_base;
3115 } else {
3116 current_desc++;
3117 }
3118 }
3119
3120 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3121 BUS_DMASYNC_PREWRITE);
3122
3123 adapter->next_rx_desc_to_check = i;
3124
3125 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3126 if (--i < 0)
3127 i = adapter->num_rx_desc - 1;
3128
3129 E1000_WRITE_REG(&adapter->hw, RDT, i);
3130 }
3131
3132 /*********************************************************************
3133 *
3134 * Verify that the hardware indicated that the checksum is valid.
3135 * Inform the stack about the status of checksum so that stack
3136 * doesn't spend time verifying the checksum.
3137 *
3138 *********************************************************************/
3139 static void
3140 em_receive_checksum(struct adapter *adapter,
3141 struct em_rx_desc *rx_desc,
3142 struct mbuf *mp)
3143 {
3144 /* 82543 or newer only */
3145 if ((adapter->hw.mac_type < em_82543) ||
3146 /* Ignore Checksum bit is set */
3147 (rx_desc->status & E1000_RXD_STAT_IXSM)) {
3148 mp->m_pkthdr.csum_flags = 0;
3149 return;
3150 }
3151
3152 if (rx_desc->status & E1000_RXD_STAT_IPCS) {
3153 /* Did it pass? */
3154 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3155 /* IP Checksum Good */
3156 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
3157 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3158 } else {
3159 mp->m_pkthdr.csum_flags = 0;
3160 }
3161 }
3162
3163 if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
3164 /* Did it pass? */
3165 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3166 mp->m_pkthdr.csum_flags |=
3167 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR |
3168 CSUM_FRAG_NOT_CHECKED);
3169 mp->m_pkthdr.csum_data = htons(0xffff);
3170 }
3171 }
3172 }
3173
3174
3175 static void
3176 em_enable_vlans(struct adapter *adapter)
3177 {
3178 uint32_t ctrl;
3179
3180 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN);
3181
3182 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3183 ctrl |= E1000_CTRL_VME;
3184 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3185 }
3186
3187 static void
3188 em_disable_vlans(struct adapter *adapter)
3189 {
3190 uint32_t ctrl;
3191
3192 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3193 ctrl &= ~E1000_CTRL_VME;
3194 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3195 }
3196
3197 /*
3198 * note: we must call bus_enable_intr() prior to enabling the hardware
3199 * interrupt and bus_disable_intr() after disabling the hardware interrupt
3200 * in order to avoid handler execution races from scheduled interrupt
3201 * threads.
3202 */
3203 static void
3204 em_enable_intr(struct adapter *adapter)
3205 {
3206 struct ifnet *ifp = &adapter->interface_data.ac_if;
3207
3208 if ((ifp->if_flags & IFF_POLLING) == 0) {
3209 lwkt_serialize_handler_enable(ifp->if_serializer);
3210 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK));
3211 }
3212 }
3213
3214 static void
3215 em_disable_intr(struct adapter *adapter)
3216 {
3217 /*
3218 * The first version of 82542 had an errata where when link was forced
3219 * it would stay up even up even if the cable was disconnected.
3220 * Sequence errors were used to detect the disconnect and then the
3221 * driver would unforce the link. This code in the in the ISR. For
3222 * this to work correctly the Sequence error interrupt had to be
3223 * enabled all the time.
3224 */
3225 if (adapter->hw.mac_type == em_82542_rev2_0) {
3226 E1000_WRITE_REG(&adapter->hw, IMC,
3227 (0xffffffff & ~E1000_IMC_RXSEQ));
3228 } else {
3229 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
3230 }
3231
3232 lwkt_serialize_handler_disable(adapter->interface_data.ac_if.if_serializer);
3233 }
3234
3235 static int
3236 em_is_valid_ether_addr(uint8_t *addr)
3237 {
3238 static const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3239
3240 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3241 return (FALSE);
3242 else
3243 return (TRUE);
3244 }
3245
3246 void
3247 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3248 {
3249 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2);
3250 }
3251
3252 void
3253 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3254 {
3255 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2);
3256 }
3257
3258 void
3259 em_pci_set_mwi(struct em_hw *hw)
3260 {
3261 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3262 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
3263 }
3264
3265 void
3266 em_pci_clear_mwi(struct em_hw *hw)
3267 {
3268 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3269 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
3270 }
3271
3272 uint32_t
3273 em_io_read(struct em_hw *hw, unsigned long port)
3274 {
3275 struct em_osdep *io = hw->back;
3276
3277 return bus_space_read_4(io->io_bus_space_tag,
3278 io->io_bus_space_handle, port);
3279 }
3280
3281 void
3282 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value)
3283 {
3284 struct em_osdep *io = hw->back;
3285
3286 bus_space_write_4(io->io_bus_space_tag,
3287 io->io_bus_space_handle, port, value);
3288 }
3289
3290 /*
3291 * We may eventually really do this, but its unnecessary
3292 * for now so we just return unsupported.
3293 */
3294 int32_t
3295 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3296 {
3297 return (0);
3298 }
3299
3300
3301 /*********************************************************************
3302 * 82544 Coexistence issue workaround.
3303 * There are 2 issues.
3304 * 1. Transmit Hang issue.
3305 * To detect this issue, following equation can be used...
3306 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3307 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3308 *
3309 * 2. DAC issue.
3310 * To detect this issue, following equation can be used...
3311 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3312 * If SUM[3:0] is in between 9 to c, we will have this issue.
3313 *
3314 *
3315 * WORKAROUND:
3316 * Make sure we do not have ending address as 1,2,3,4(Hang) or
3317 * 9,a,b,c (DAC)
3318 *
3319 *************************************************************************/
3320 static uint32_t
3321 em_fill_descriptors(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3322 {
3323 /* Since issue is sensitive to length and address.*/
3324 /* Let us first check the address...*/
3325 uint32_t safe_terminator;
3326 if (length <= 4) {
3327 desc_array->descriptor[0].address = address;
3328 desc_array->descriptor[0].length = length;
3329 desc_array->elements = 1;
3330 return (desc_array->elements);
3331 }
3332 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3333 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3334 if (safe_terminator == 0 ||
3335 (safe_terminator > 4 && safe_terminator < 9) ||
3336 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3337 desc_array->descriptor[0].address = address;
3338 desc_array->descriptor[0].length = length;
3339 desc_array->elements = 1;
3340 return (desc_array->elements);
3341 }
3342
3343 desc_array->descriptor[0].address = address;
3344 desc_array->descriptor[0].length = length - 4;
3345 desc_array->descriptor[1].address = address + (length - 4);
3346 desc_array->descriptor[1].length = 4;
3347 desc_array->elements = 2;
3348 return (desc_array->elements);
3349 }
3350
3351 /**********************************************************************
3352 *
3353 * Update the board statistics counters.
3354 *
3355 **********************************************************************/
3356 static void
3357 em_update_stats_counters(struct adapter *adapter)
3358 {
3359 struct ifnet *ifp;
3360
3361 if (adapter->hw.media_type == em_media_type_copper ||
3362 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
3363 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS);
3364 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC);
3365 }
3366 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS);
3367 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC);
3368 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC);
3369 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL);
3370
3371 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC);
3372 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL);
3373 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC);
3374 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC);
3375 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC);
3376 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC);
3377 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC);
3378 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC);
3379 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC);
3380 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC);
3381 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64);
3382 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127);
3383 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255);
3384 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511);
3385 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023);
3386 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522);
3387 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC);
3388 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC);
3389 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC);
3390 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC);
3391
3392 /* For the 64-bit byte counters the low dword must be read first. */
3393 /* Both registers clear on the read of the high dword */
3394
3395 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL);
3396 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH);
3397 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL);
3398 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH);
3399
3400 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC);
3401 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC);
3402 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC);
3403 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC);
3404 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC);
3405
3406 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL);
3407 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH);
3408 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL);
3409 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH);
3410
3411 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR);
3412 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT);
3413 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64);
3414 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127);
3415 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255);
3416 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511);
3417 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023);
3418 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522);
3419 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC);
3420 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC);
3421
3422 if (adapter->hw.mac_type >= em_82543) {
3423 adapter->stats.algnerrc +=
3424 E1000_READ_REG(&adapter->hw, ALGNERRC);
3425 adapter->stats.rxerrc +=
3426 E1000_READ_REG(&adapter->hw, RXERRC);
3427 adapter->stats.tncrs +=
3428 E1000_READ_REG(&adapter->hw, TNCRS);
3429 adapter->stats.cexterr +=
3430 E1000_READ_REG(&adapter->hw, CEXTERR);
3431 adapter->stats.tsctc +=
3432 E1000_READ_REG(&adapter->hw, TSCTC);
3433 adapter->stats.tsctfc +=
3434 E1000_READ_REG(&adapter->hw, TSCTFC);
3435 }
3436 ifp = &adapter->interface_data.ac_if;
3437
3438 /* Fill out the OS statistics structure */
3439 ifp->if_collisions = adapter->stats.colc;
3440
3441 /* Rx Errors */
3442 ifp->if_ierrors =
3443 adapter->dropped_pkts +
3444 adapter->stats.rxerrc +
3445 adapter->stats.crcerrs +
3446 adapter->stats.algnerrc +
3447 adapter->stats.ruc + adapter->stats.roc +
3448 adapter->stats.mpc + adapter->stats.cexterr +
3449 adapter->rx_overruns;
3450
3451 /* Tx Errors */
3452 ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol +
3453 adapter->watchdog_timeouts;
3454 }
3455
3456
3457 /**********************************************************************
3458 *
3459 * This routine is called only when em_display_debug_stats is enabled.
3460 * This routine provides a way to take a look at important statistics
3461 * maintained by the driver and hardware.
3462 *
3463 **********************************************************************/
3464 static void
3465 em_print_debug_info(struct adapter *adapter)
3466 {
3467 device_t dev= adapter->dev;
3468 uint8_t *hw_addr = adapter->hw.hw_addr;
3469
3470 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3471 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x\n",
3472 E1000_READ_REG(&adapter->hw, CTRL),
3473 E1000_READ_REG(&adapter->hw, RCTL));
3474 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk\n",
3475 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),
3476 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff));
3477 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3478 adapter->hw.fc_high_water, adapter->hw.fc_low_water);
3479 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3480 E1000_READ_REG(&adapter->hw, TIDV),
3481 E1000_READ_REG(&adapter->hw, TADV));
3482 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3483 E1000_READ_REG(&adapter->hw, RDTR),
3484 E1000_READ_REG(&adapter->hw, RADV));
3485 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3486 (long long)adapter->tx_fifo_wrk_cnt,
3487 (long long)adapter->tx_fifo_reset_cnt);
3488 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3489 E1000_READ_REG(&adapter->hw, TDH),
3490 E1000_READ_REG(&adapter->hw, TDT));
3491 device_printf(dev, "Num Tx descriptors avail = %d\n",
3492 adapter->num_tx_desc_avail);
3493 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3494 adapter->no_tx_desc_avail1);
3495 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3496 adapter->no_tx_desc_avail2);
3497 device_printf(dev, "Std mbuf failed = %ld\n",
3498 adapter->mbuf_alloc_failed);
3499 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3500 adapter->mbuf_cluster_failed);
3501 device_printf(dev, "Driver dropped packets = %ld\n",
3502 adapter->dropped_pkts);
3503 }
3504
3505 static void
3506 em_print_hw_stats(struct adapter *adapter)
3507 {
3508 device_t dev= adapter->dev;
3509
3510 device_printf(dev, "Excessive collisions = %lld\n",
3511 (long long)adapter->stats.ecol);
3512 device_printf(dev, "Symbol errors = %lld\n",
3513 (long long)adapter->stats.symerrs);
3514 device_printf(dev, "Sequence errors = %lld\n",
3515 (long long)adapter->stats.sec);
3516 device_printf(dev, "Defer count = %lld\n",
3517 (long long)adapter->stats.dc);
3518
3519 device_printf(dev, "Missed Packets = %lld\n",
3520 (long long)adapter->stats.mpc);
3521 device_printf(dev, "Receive No Buffers = %lld\n",
3522 (long long)adapter->stats.rnbc);
3523 /* RLEC is inaccurate on some hardware, calculate our own. */
3524 device_printf(dev, "Receive Length errors = %lld\n",
3525 (long long)adapter->stats.roc +
3526 (long long)adapter->stats.ruc);
3527 device_printf(dev, "Receive errors = %lld\n",
3528 (long long)adapter->stats.rxerrc);
3529 device_printf(dev, "Crc errors = %lld\n",
3530 (long long)adapter->stats.crcerrs);
3531 device_printf(dev, "Alignment errors = %lld\n",
3532 (long long)adapter->stats.algnerrc);
3533 device_printf(dev, "Carrier extension errors = %lld\n",
3534 (long long)adapter->stats.cexterr);
3535 device_printf(dev, "RX overruns = %lu\n", adapter->rx_overruns);
3536 device_printf(dev, "Watchdog timeouts = %lu\n",
3537 adapter->watchdog_timeouts);
3538
3539 device_printf(dev, "XON Rcvd = %lld\n",
3540 (long long)adapter->stats.xonrxc);
3541 device_printf(dev, "XON Xmtd = %lld\n",
3542 (long long)adapter->stats.xontxc);
3543 device_printf(dev, "XOFF Rcvd = %lld\n",
3544 (long long)adapter->stats.xoffrxc);
3545 device_printf(dev, "XOFF Xmtd = %lld\n",
3546 (long long)adapter->stats.xofftxc);
3547
3548 device_printf(dev, "Good Packets Rcvd = %lld\n",
3549 (long long)adapter->stats.gprc);
3550 device_printf(dev, "Good Packets Xmtd = %lld\n",
3551 (long long)adapter->stats.gptc);
3552 }
3553
3554 static int
3555 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3556 {
3557 int error;
3558 int result;
3559 struct adapter *adapter;
3560
3561 result = -1;
3562 error = sysctl_handle_int(oidp, &result, 0, req);
3563
3564 if (error || !req->newptr)
3565 return (error);
3566
3567 if (result == 1) {
3568 adapter = (struct adapter *)arg1;
3569 em_print_debug_info(adapter);
3570 }
3571
3572 return (error);
3573 }
3574
3575 static int
3576 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3577 {
3578 int error;
3579 int result;
3580 struct adapter *adapter;
3581
3582 result = -1;
3583 error = sysctl_handle_int(oidp, &result, 0, req);
3584
3585 if (error || !req->newptr)
3586 return (error);
3587
3588 if (result == 1) {
3589 adapter = (struct adapter *)arg1;
3590 em_print_hw_stats(adapter);
3591 }
3592
3593 return (error);
3594 }
3595
3596 static int
3597 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3598 {
3599 struct em_int_delay_info *info;
3600 struct adapter *adapter;
3601 uint32_t regval;
3602 int error;
3603 int usecs;
3604 int ticks;
3605
3606 info = (struct em_int_delay_info *)arg1;
3607 adapter = info->adapter;
3608 usecs = info->value;
3609 error = sysctl_handle_int(oidp, &usecs, 0, req);
3610 if (error != 0 || req->newptr == NULL)
3611 return (error);
3612 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535))
3613 return (EINVAL);
3614 info->value = usecs;
3615 ticks = E1000_USECS_TO_TICKS(usecs);
3616
3617 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3618 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
3619 regval = (regval & ~0xffff) | (ticks & 0xffff);
3620 /* Handle a few special cases. */
3621 switch (info->offset) {
3622 case E1000_RDTR:
3623 case E1000_82542_RDTR:
3624 regval |= E1000_RDT_FPDB;
3625 break;
3626 case E1000_TIDV:
3627 case E1000_82542_TIDV:
3628 if (ticks == 0) {
3629 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
3630 /* Don't write 0 into the TIDV register. */
3631 regval++;
3632 } else
3633 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3634 break;
3635 }
3636 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
3637 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3638 return (0);
3639 }
3640
3641 static void
3642 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
3643 const char *description, struct em_int_delay_info *info,
3644 int offset, int value)
3645 {
3646 info->adapter = adapter;
3647 info->offset = offset;
3648 info->value = value;
3649 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
3650 SYSCTL_CHILDREN(adapter->sysctl_tree),
3651 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
3652 info, 0, em_sysctl_int_delay, "I", description);
3653 }
3654
3655 static int
3656 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3657 {
3658 struct adapter *adapter = (void *)arg1;
3659 int error;
3660 int throttle;
3661
3662 throttle = em_int_throttle_ceil;
3663 error = sysctl_handle_int(oidp, &throttle, 0, req);
3664 if (error || req->newptr == NULL)
3665 return error;
3666 if (throttle < 0 || throttle > 1000000000 / 256)
3667 return EINVAL;
3668 if (throttle) {
3669 /*
3670 * Set the interrupt throttling rate in 256ns increments,
3671 * recalculate sysctl value assignment to get exact frequency.
3672 */
3673 throttle = 1000000000 / 256 / throttle;
3674 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3675 em_int_throttle_ceil = 1000000000 / 256 / throttle;
3676 E1000_WRITE_REG(&adapter->hw, ITR, throttle);
3677 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3678 } else {
3679 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3680 em_int_throttle_ceil = 0;
3681 E1000_WRITE_REG(&adapter->hw, ITR, 0);
3682 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3683 }
3684 device_printf(adapter->dev, "Interrupt moderation set to %d/sec\n",
3685 em_int_throttle_ceil);
3686 return 0;
3687 }
Port diff from OpenBSD to DragonFly