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added -y/--side-by-side option
[dfdiff.git] / sys / dev / netif / em / if_em.c
blob07a7aa6bf11a146efe3e65798ff3e1ff7d697899
1 /*
2 *
3 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 *
5 * Copyright (c) 2001-2006, Intel Corporation
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright notice,
12 * this list of conditions and the following disclaimer.
13 *
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * 3. Neither the name of the Intel Corporation nor the names of its
19 * contributors may be used to endorse or promote products derived from
20 * this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 *
35 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 *
37 * This code is derived from software contributed to The DragonFly Project
38 * by Matthew Dillon <dillon@backplane.com>
39 *
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
42 * are met:
43 *
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
49 * distribution.
50 * 3. Neither the name of The DragonFly Project nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific, prior written permission.
53 *
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
57 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
58 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
59 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
60 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
61 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
62 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
64 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
65 * SUCH DAMAGE.
66 *
67 * $DragonFly: src/sys/dev/netif/em/if_em.c,v 1.70 2008/05/02 07:40:32 sephe Exp $
68 * $FreeBSD$
69 */
70 /*
71 * SERIALIZATION API RULES:
72 *
73 * - If the driver uses the same serializer for the interrupt as for the
74 * ifnet, most of the serialization will be done automatically for the
75 * driver.
76 *
77 * - ifmedia entry points will be serialized by the ifmedia code using the
78 * ifnet serializer.
79 *
80 * - if_* entry points except for if_input will be serialized by the IF
81 * and protocol layers.
82 *
83 * - The device driver must be sure to serialize access from timeout code
84 * installed by the device driver.
85 *
86 * - The device driver typically holds the serializer at the time it wishes
87 * to call if_input. If so, it should pass the serializer to if_input and
88 * note that the serializer might be dropped temporarily by if_input
89 * (e.g. in case it has to bridge the packet to another interface).
90 *
91 * NOTE! Since callers into the device driver hold the ifnet serializer,
92 * the device driver may be holding a serializer at the time it calls
93 * if_input even if it is not serializer-aware.
94 */
95
96 #include "opt_polling.h"
97 #include "opt_inet.h"
98 #include "opt_serializer.h"
99 #include "opt_ethernet.h"
100
101 #include <sys/param.h>
102 #include <sys/bus.h>
103 #include <sys/endian.h>
104 #include <sys/kernel.h>
105 #include <sys/ktr.h>
106 #include <sys/malloc.h>
107 #include <sys/mbuf.h>
108 #include <sys/module.h>
109 #include <sys/rman.h>
110 #include <sys/serialize.h>
111 #include <sys/socket.h>
112 #include <sys/sockio.h>
113 #include <sys/sysctl.h>
114
115 #include <net/bpf.h>
116 #include <net/ethernet.h>
117 #include <net/if.h>
118 #include <net/if_arp.h>
119 #include <net/if_dl.h>
120 #include <net/if_media.h>
121 #include <net/if_types.h>
122 #include <net/ifq_var.h>
123 #include <net/vlan/if_vlan_var.h>
124 #include <net/vlan/if_vlan_ether.h>
125
126 #ifdef INET
127 #include <netinet/in.h>
128 #include <netinet/in_systm.h>
129 #include <netinet/in_var.h>
130 #include <netinet/ip.h>
131 #include <netinet/tcp.h>
132 #include <netinet/udp.h>
133 #endif
134
135 #include <dev/netif/em/if_em_hw.h>
136 #include <dev/netif/em/if_em.h>
137
138 #define EM_X60_WORKAROUND
139
140 /*********************************************************************
141 * Set this to one to display debug statistics
142 *********************************************************************/
143 int em_display_debug_stats = 0;
144
145 /*********************************************************************
146 * Driver version
147 *********************************************************************/
148
149 char em_driver_version[] = "6.2.9";
150
151
152 /*********************************************************************
153 * PCI Device ID Table
154 *
155 * Used by probe to select devices to load on
156 * Last field stores an index into em_strings
157 * Last entry must be all 0s
158 *
159 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
160 *********************************************************************/
161
162 static em_vendor_info_t em_vendor_info_array[] =
163 {
164 /* Intel(R) PRO/1000 Network Connection */
165 { 0x8086, E1000_DEV_ID_82540EM, PCI_ANY_ID, PCI_ANY_ID, 0},
166 { 0x8086, E1000_DEV_ID_82540EM_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
167 { 0x8086, E1000_DEV_ID_82540EP, PCI_ANY_ID, PCI_ANY_ID, 0},
168 { 0x8086, E1000_DEV_ID_82540EP_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
169 { 0x8086, E1000_DEV_ID_82540EP_LP, PCI_ANY_ID, PCI_ANY_ID, 0},
170
171 { 0x8086, E1000_DEV_ID_82541EI, PCI_ANY_ID, PCI_ANY_ID, 0},
172 { 0x8086, E1000_DEV_ID_82541ER, PCI_ANY_ID, PCI_ANY_ID, 0},
173 { 0x8086, E1000_DEV_ID_82541ER_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
174 { 0x8086, E1000_DEV_ID_82541EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
175 { 0x8086, E1000_DEV_ID_82541GI, PCI_ANY_ID, PCI_ANY_ID, 0},
176 { 0x8086, E1000_DEV_ID_82541GI_LF, PCI_ANY_ID, PCI_ANY_ID, 0},
177 { 0x8086, E1000_DEV_ID_82541GI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
178
179 { 0x8086, E1000_DEV_ID_82542, PCI_ANY_ID, PCI_ANY_ID, 0},
180
181 { 0x8086, E1000_DEV_ID_82543GC_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
182 { 0x8086, E1000_DEV_ID_82543GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
183
184 { 0x8086, E1000_DEV_ID_82544EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
185 { 0x8086, E1000_DEV_ID_82544EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
186 { 0x8086, E1000_DEV_ID_82544GC_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
187 { 0x8086, E1000_DEV_ID_82544GC_LOM, PCI_ANY_ID, PCI_ANY_ID, 0},
188
189 { 0x8086, E1000_DEV_ID_82545EM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
190 { 0x8086, E1000_DEV_ID_82545EM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
191 { 0x8086, E1000_DEV_ID_82545GM_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
192 { 0x8086, E1000_DEV_ID_82545GM_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
193 { 0x8086, E1000_DEV_ID_82545GM_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
194
195 { 0x8086, E1000_DEV_ID_82546EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
196 { 0x8086, E1000_DEV_ID_82546EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
197 { 0x8086, E1000_DEV_ID_82546EB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
198 { 0x8086, E1000_DEV_ID_82546GB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
199 { 0x8086, E1000_DEV_ID_82546GB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
200 { 0x8086, E1000_DEV_ID_82546GB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
201 { 0x8086, E1000_DEV_ID_82546GB_PCIE, PCI_ANY_ID, PCI_ANY_ID, 0},
202 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
203 { 0x8086, E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3,
204 PCI_ANY_ID, PCI_ANY_ID, 0},
205
206 { 0x8086, E1000_DEV_ID_82547EI, PCI_ANY_ID, PCI_ANY_ID, 0},
207 { 0x8086, E1000_DEV_ID_82547EI_MOBILE, PCI_ANY_ID, PCI_ANY_ID, 0},
208 { 0x8086, E1000_DEV_ID_82547GI, PCI_ANY_ID, PCI_ANY_ID, 0},
209
210 { 0x8086, E1000_DEV_ID_82571EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
211 { 0x8086, E1000_DEV_ID_82571EB_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
212 { 0x8086, E1000_DEV_ID_82571EB_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
213 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER,
214 PCI_ANY_ID, PCI_ANY_ID, 0},
215 { 0x8086, E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE,
216 PCI_ANY_ID, PCI_ANY_ID, 0},
217
218 { 0x8086, E1000_DEV_ID_82571EB_QUAD_FIBER,
219 PCI_ANY_ID, PCI_ANY_ID, 0},
220 { 0x8086, E1000_DEV_ID_82571PT_QUAD_COPPER,
221 PCI_ANY_ID, PCI_ANY_ID, 0},
222 { 0x8086, E1000_DEV_ID_82572EI_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
223 { 0x8086, E1000_DEV_ID_82572EI_FIBER, PCI_ANY_ID, PCI_ANY_ID, 0},
224 { 0x8086, E1000_DEV_ID_82572EI_SERDES, PCI_ANY_ID, PCI_ANY_ID, 0},
225 { 0x8086, E1000_DEV_ID_82572EI, PCI_ANY_ID, PCI_ANY_ID, 0},
226
227 { 0x8086, E1000_DEV_ID_82573E, PCI_ANY_ID, PCI_ANY_ID, 0},
228 { 0x8086, E1000_DEV_ID_82573E_IAMT, PCI_ANY_ID, PCI_ANY_ID, 0},
229 { 0x8086, E1000_DEV_ID_82573L, PCI_ANY_ID, PCI_ANY_ID, 0},
230
231 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_SPT,
232 PCI_ANY_ID, PCI_ANY_ID, 0},
233 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_SPT,
234 PCI_ANY_ID, PCI_ANY_ID, 0},
235 { 0x8086, E1000_DEV_ID_80003ES2LAN_COPPER_DPT,
236 PCI_ANY_ID, PCI_ANY_ID, 0},
237 { 0x8086, E1000_DEV_ID_80003ES2LAN_SERDES_DPT,
238 PCI_ANY_ID, PCI_ANY_ID, 0},
239
240 { 0x8086, E1000_DEV_ID_ICH8_IGP_M_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
241 { 0x8086, E1000_DEV_ID_ICH8_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
242 { 0x8086, E1000_DEV_ID_ICH8_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
243 { 0x8086, E1000_DEV_ID_ICH8_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
244 { 0x8086, E1000_DEV_ID_ICH8_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
245 { 0x8086, E1000_DEV_ID_ICH8_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
246 { 0x8086, E1000_DEV_ID_ICH8_IGP_M, PCI_ANY_ID, PCI_ANY_ID, 0},
247
248 { 0x8086, E1000_DEV_ID_ICH9_IGP_AMT, PCI_ANY_ID, PCI_ANY_ID, 0},
249 { 0x8086, E1000_DEV_ID_ICH9_IGP_C, PCI_ANY_ID, PCI_ANY_ID, 0},
250 { 0x8086, E1000_DEV_ID_ICH9_IFE, PCI_ANY_ID, PCI_ANY_ID, 0},
251 { 0x8086, E1000_DEV_ID_ICH9_IFE_GT, PCI_ANY_ID, PCI_ANY_ID, 0},
252 { 0x8086, E1000_DEV_ID_ICH9_IFE_G, PCI_ANY_ID, PCI_ANY_ID, 0},
253
254 { 0x8086, E1000_DEV_ID_82575EB_COPPER, PCI_ANY_ID, PCI_ANY_ID, 0},
255 { 0x8086, E1000_DEV_ID_82575EB_FIBER_SERDES,
256 PCI_ANY_ID, PCI_ANY_ID, 0},
257 { 0x8086, E1000_DEV_ID_82575GB_QUAD_COPPER,
258 PCI_ANY_ID, PCI_ANY_ID, 0},
259 { 0x8086, 0x101A, PCI_ANY_ID, PCI_ANY_ID, 0},
260 { 0x8086, 0x1014, PCI_ANY_ID, PCI_ANY_ID, 0},
261 /* required last entry */
262 { 0, 0, 0, 0, 0}
263 };
264
265 /*********************************************************************
266 * Table of branding strings for all supported NICs.
267 *********************************************************************/
268
269 static const char *em_strings[] = {
270 "Intel(R) PRO/1000 Network Connection"
271 };
272
273 /*********************************************************************
274 * Function prototypes
275 *********************************************************************/
276 static int em_probe(device_t);
277 static int em_attach(device_t);
278 static int em_detach(device_t);
279 static int em_shutdown(device_t);
280 static void em_intr(void *);
281 static int em_suspend(device_t);
282 static int em_resume(device_t);
283 static void em_start(struct ifnet *);
284 static int em_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
285 static void em_watchdog(struct ifnet *);
286 static void em_init(void *);
287 static void em_stop(void *);
288 static void em_media_status(struct ifnet *, struct ifmediareq *);
289 static int em_media_change(struct ifnet *);
290 static void em_identify_hardware(struct adapter *);
291 static int em_allocate_pci_resources(device_t);
292 static void em_free_pci_resources(device_t);
293 static void em_local_timer(void *);
294 static int em_hardware_init(struct adapter *);
295 static void em_setup_interface(device_t, struct adapter *);
296 static int em_setup_transmit_structures(struct adapter *);
297 static void em_initialize_transmit_unit(struct adapter *);
298 static int em_setup_receive_structures(struct adapter *);
299 static void em_initialize_receive_unit(struct adapter *);
300 static void em_enable_intr(struct adapter *);
301 static void em_disable_intr(struct adapter *);
302 static void em_free_transmit_structures(struct adapter *);
303 static void em_free_receive_structures(struct adapter *);
304 static void em_update_stats_counters(struct adapter *);
305 static void em_txeof(struct adapter *);
306 static int em_allocate_receive_structures(struct adapter *);
307 static void em_rxeof(struct adapter *, int);
308 static void em_receive_checksum(struct adapter *, struct em_rx_desc *,
309 struct mbuf *);
310 static void em_transmit_checksum_setup(struct adapter *, struct mbuf *,
311 uint32_t *, uint32_t *);
312 static void em_set_promisc(struct adapter *);
313 static void em_disable_promisc(struct adapter *);
314 static void em_set_multi(struct adapter *);
315 static void em_print_hw_stats(struct adapter *);
316 static void em_update_link_status(struct adapter *);
317 static int em_get_buf(int i, struct adapter *, struct mbuf *, int how);
318 static void em_enable_vlans(struct adapter *);
319 static void em_disable_vlans(struct adapter *);
320 static int em_encap(struct adapter *, struct mbuf *);
321 static void em_smartspeed(struct adapter *);
322 static int em_82547_fifo_workaround(struct adapter *, int);
323 static void em_82547_update_fifo_head(struct adapter *, int);
324 static int em_82547_tx_fifo_reset(struct adapter *);
325 static void em_82547_move_tail(void *);
326 static void em_82547_move_tail_serialized(struct adapter *);
327 static int em_dma_malloc(struct adapter *, bus_size_t,
328 struct em_dma_alloc *);
329 static void em_dma_free(struct adapter *, struct em_dma_alloc *);
330 static void em_print_debug_info(struct adapter *);
331 static int em_is_valid_ether_addr(uint8_t *);
332 static int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
333 static int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
334 static uint32_t em_fill_descriptors(bus_addr_t address, uint32_t length,
335 PDESC_ARRAY desc_array);
336 static int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
337 static int em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
338 static void em_add_int_delay_sysctl(struct adapter *, const char *,
339 const char *,
340 struct em_int_delay_info *, int, int);
341
342 /*********************************************************************
343 * FreeBSD Device Interface Entry Points
344 *********************************************************************/
345
346 static device_method_t em_methods[] = {
347 /* Device interface */
348 DEVMETHOD(device_probe, em_probe),
349 DEVMETHOD(device_attach, em_attach),
350 DEVMETHOD(device_detach, em_detach),
351 DEVMETHOD(device_shutdown, em_shutdown),
352 DEVMETHOD(device_suspend, em_suspend),
353 DEVMETHOD(device_resume, em_resume),
354 {0, 0}
355 };
356
357 static driver_t em_driver = {
358 "em", em_methods, sizeof(struct adapter),
359 };
360
361 static devclass_t em_devclass;
362
363 DECLARE_DUMMY_MODULE(if_em);
364 DRIVER_MODULE(if_em, pci, em_driver, em_devclass, 0, 0);
365
366 /*********************************************************************
367 * Tunable default values.
368 *********************************************************************/
369
370 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
371 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
372
373 static int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV);
374 static int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR);
375 static int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV);
376 static int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV);
377 static int em_int_throttle_ceil = 10000;
378 static int em_rxd = EM_DEFAULT_RXD;
379 static int em_txd = EM_DEFAULT_TXD;
380 static int em_smart_pwr_down = FALSE;
381
382 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt);
383 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt);
384 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt);
385 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt);
386 TUNABLE_INT("hw.em.int_throttle_ceil", &em_int_throttle_ceil);
387 TUNABLE_INT("hw.em.rxd", &em_rxd);
388 TUNABLE_INT("hw.em.txd", &em_txd);
389 TUNABLE_INT("hw.em.smart_pwr_down", &em_smart_pwr_down);
390
391 /*
392 * Kernel trace for characterization of operations
393 */
394 #if !defined(KTR_IF_EM)
395 #define KTR_IF_EM KTR_ALL
396 #endif
397 KTR_INFO_MASTER(if_em);
398 KTR_INFO(KTR_IF_EM, if_em, intr_beg, 0, "intr begin", 0);
399 KTR_INFO(KTR_IF_EM, if_em, intr_end, 1, "intr end", 0);
400 KTR_INFO(KTR_IF_EM, if_em, pkt_receive, 4, "rx packet", 0);
401 KTR_INFO(KTR_IF_EM, if_em, pkt_txqueue, 5, "tx packet", 0);
402 KTR_INFO(KTR_IF_EM, if_em, pkt_txclean, 6, "tx clean", 0);
403 #define logif(name) KTR_LOG(if_em_ ## name)
404
405 /*********************************************************************
406 * Device identification routine
407 *
408 * em_probe determines if the driver should be loaded on
409 * adapter based on PCI vendor/device id of the adapter.
410 *
411 * return 0 on success, positive on failure
412 *********************************************************************/
413
414 static int
415 em_probe(device_t dev)
416 {
417 em_vendor_info_t *ent;
418
419 uint16_t pci_vendor_id = 0;
420 uint16_t pci_device_id = 0;
421 uint16_t pci_subvendor_id = 0;
422 uint16_t pci_subdevice_id = 0;
423 char adapter_name[60];
424
425 INIT_DEBUGOUT("em_probe: begin");
426
427 pci_vendor_id = pci_get_vendor(dev);
428 if (pci_vendor_id != EM_VENDOR_ID)
429 return (ENXIO);
430
431 pci_device_id = pci_get_device(dev);
432 pci_subvendor_id = pci_get_subvendor(dev);
433 pci_subdevice_id = pci_get_subdevice(dev);
434
435 ent = em_vendor_info_array;
436 while (ent->vendor_id != 0) {
437 if ((pci_vendor_id == ent->vendor_id) &&
438 (pci_device_id == ent->device_id) &&
439
440 ((pci_subvendor_id == ent->subvendor_id) ||
441 (ent->subvendor_id == PCI_ANY_ID)) &&
442
443 ((pci_subdevice_id == ent->subdevice_id) ||
444 (ent->subdevice_id == PCI_ANY_ID))) {
445 ksnprintf(adapter_name, sizeof(adapter_name),
446 "%s, Version - %s", em_strings[ent->index],
447 em_driver_version);
448 device_set_desc_copy(dev, adapter_name);
449 device_set_async_attach(dev, TRUE);
450 return (0);
451 }
452 ent++;
453 }
454
455 return (ENXIO);
456 }
457
458 /*********************************************************************
459 * Device initialization routine
460 *
461 * The attach entry point is called when the driver is being loaded.
462 * This routine identifies the type of hardware, allocates all resources
463 * and initializes the hardware.
464 *
465 * return 0 on success, positive on failure
466 *********************************************************************/
467
468 static int
469 em_attach(device_t dev)
470 {
471 struct adapter *adapter;
472 int tsize, rsize;
473 int error = 0;
474
475 INIT_DEBUGOUT("em_attach: begin");
476
477 adapter = device_get_softc(dev);
478
479 callout_init(&adapter->timer);
480 callout_init(&adapter->tx_fifo_timer);
481
482 adapter->dev = dev;
483 adapter->osdep.dev = dev;
484
485 /* SYSCTL stuff */
486 sysctl_ctx_init(&adapter->sysctl_ctx);
487 adapter->sysctl_tree = SYSCTL_ADD_NODE(&adapter->sysctl_ctx,
488 SYSCTL_STATIC_CHILDREN(_hw),
489 OID_AUTO,
490 device_get_nameunit(dev),
491 CTLFLAG_RD,
492 0, "");
493
494 if (adapter->sysctl_tree == NULL) {
495 device_printf(dev, "Unable to create sysctl tree\n");
496 return EIO;
497 }
498
499 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
500 SYSCTL_CHILDREN(adapter->sysctl_tree),
501 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW,
502 (void *)adapter, 0,
503 em_sysctl_debug_info, "I", "Debug Information");
504
505 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
506 SYSCTL_CHILDREN(adapter->sysctl_tree),
507 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW,
508 (void *)adapter, 0,
509 em_sysctl_stats, "I", "Statistics");
510
511 /* Determine hardware revision */
512 em_identify_hardware(adapter);
513
514 /* Set up some sysctls for the tunable interrupt delays */
515 em_add_int_delay_sysctl(adapter, "rx_int_delay",
516 "receive interrupt delay in usecs",
517 &adapter->rx_int_delay,
518 E1000_REG_OFFSET(&adapter->hw, RDTR),
519 em_rx_int_delay_dflt);
520 em_add_int_delay_sysctl(adapter, "tx_int_delay",
521 "transmit interrupt delay in usecs",
522 &adapter->tx_int_delay,
523 E1000_REG_OFFSET(&adapter->hw, TIDV),
524 em_tx_int_delay_dflt);
525 if (adapter->hw.mac_type >= em_82540) {
526 em_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
527 "receive interrupt delay limit in usecs",
528 &adapter->rx_abs_int_delay,
529 E1000_REG_OFFSET(&adapter->hw, RADV),
530 em_rx_abs_int_delay_dflt);
531 em_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
532 "transmit interrupt delay limit in usecs",
533 &adapter->tx_abs_int_delay,
534 E1000_REG_OFFSET(&adapter->hw, TADV),
535 em_tx_abs_int_delay_dflt);
536 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
537 SYSCTL_CHILDREN(adapter->sysctl_tree),
538 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
539 adapter, 0, em_sysctl_int_throttle, "I", NULL);
540 }
541
542 /*
543 * Validate number of transmit and receive descriptors. It
544 * must not exceed hardware maximum, and must be multiple
545 * of EM_DBA_ALIGN.
546 */
547 if (((em_txd * sizeof(struct em_tx_desc)) % EM_DBA_ALIGN) != 0 ||
548 (adapter->hw.mac_type >= em_82544 && em_txd > EM_MAX_TXD) ||
549 (adapter->hw.mac_type < em_82544 && em_txd > EM_MAX_TXD_82543) ||
550 (em_txd < EM_MIN_TXD)) {
551 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
552 EM_DEFAULT_TXD, em_txd);
553 adapter->num_tx_desc = EM_DEFAULT_TXD;
554 } else {
555 adapter->num_tx_desc = em_txd;
556 }
557
558 if (((em_rxd * sizeof(struct em_rx_desc)) % EM_DBA_ALIGN) != 0 ||
559 (adapter->hw.mac_type >= em_82544 && em_rxd > EM_MAX_RXD) ||
560 (adapter->hw.mac_type < em_82544 && em_rxd > EM_MAX_RXD_82543) ||
561 (em_rxd < EM_MIN_RXD)) {
562 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
563 EM_DEFAULT_RXD, em_rxd);
564 adapter->num_rx_desc = EM_DEFAULT_RXD;
565 } else {
566 adapter->num_rx_desc = em_rxd;
567 }
568
569 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
570 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "rxd",
571 CTLFLAG_RD, &adapter->num_rx_desc, 0, NULL);
572 SYSCTL_ADD_INT(&adapter->sysctl_ctx,
573 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO, "txd",
574 CTLFLAG_RD, &adapter->num_tx_desc, 0, NULL);
575
576 adapter->hw.autoneg = DO_AUTO_NEG;
577 adapter->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
578 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
579 adapter->hw.tbi_compatibility_en = TRUE;
580 adapter->rx_buffer_len = EM_RXBUFFER_2048;
581
582 adapter->hw.phy_init_script = 1;
583 adapter->hw.phy_reset_disable = FALSE;
584
585 #ifndef EM_MASTER_SLAVE
586 adapter->hw.master_slave = em_ms_hw_default;
587 #else
588 adapter->hw.master_slave = EM_MASTER_SLAVE;
589 #endif
590
591 /*
592 * Set the max frame size assuming standard ethernet
593 * sized frames.
594 */
595 adapter->hw.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
596
597 adapter->hw.min_frame_size =
598 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
599
600 /*
601 * This controls when hardware reports transmit completion
602 * status.
603 */
604 adapter->hw.report_tx_early = 1;
605
606 error = em_allocate_pci_resources(dev);
607 if (error)
608 goto fail;
609
610 /* Initialize eeprom parameters */
611 em_init_eeprom_params(&adapter->hw);
612
613 tsize = roundup2(adapter->num_tx_desc * sizeof(struct em_tx_desc),
614 EM_DBA_ALIGN);
615
616 /* Allocate Transmit Descriptor ring */
617 error = em_dma_malloc(adapter, tsize, &adapter->txdma);
618 if (error) {
619 device_printf(dev, "Unable to allocate TxDescriptor memory\n");
620 goto fail;
621 }
622 adapter->tx_desc_base = (struct em_tx_desc *)adapter->txdma.dma_vaddr;
623
624 rsize = roundup2(adapter->num_rx_desc * sizeof(struct em_rx_desc),
625 EM_DBA_ALIGN);
626
627 /* Allocate Receive Descriptor ring */
628 error = em_dma_malloc(adapter, rsize, &adapter->rxdma);
629 if (error) {
630 device_printf(dev, "Unable to allocate rx_desc memory\n");
631 goto fail;
632 }
633 adapter->rx_desc_base = (struct em_rx_desc *)adapter->rxdma.dma_vaddr;
634
635 /* Initialize the hardware */
636 if (em_hardware_init(adapter)) {
637 device_printf(dev, "Unable to initialize the hardware\n");
638 error = EIO;
639 goto fail;
640 }
641
642 /* Copy the permanent MAC address out of the EEPROM */
643 if (em_read_mac_addr(&adapter->hw) < 0) {
644 device_printf(dev,
645 "EEPROM read error while reading MAC address\n");
646 error = EIO;
647 goto fail;
648 }
649
650 if (!em_is_valid_ether_addr(adapter->hw.mac_addr)) {
651 device_printf(dev, "Invalid MAC address\n");
652 error = EIO;
653 goto fail;
654 }
655
656 /* Setup OS specific network interface */
657 em_setup_interface(dev, adapter);
658
659 /* Initialize statistics */
660 em_clear_hw_cntrs(&adapter->hw);
661 em_update_stats_counters(adapter);
662 adapter->hw.get_link_status = 1;
663 em_update_link_status(adapter);
664
665 /* Indicate SOL/IDER usage */
666 if (em_check_phy_reset_block(&adapter->hw)) {
667 device_printf(dev, "PHY reset is blocked due to "
668 "SOL/IDER session.\n");
669 }
670
671 /* Identify 82544 on PCIX */
672 em_get_bus_info(&adapter->hw);
673 if (adapter->hw.bus_type == em_bus_type_pcix &&
674 adapter->hw.mac_type == em_82544)
675 adapter->pcix_82544 = TRUE;
676 else
677 adapter->pcix_82544 = FALSE;
678
679 error = bus_setup_intr(dev, adapter->res_interrupt, INTR_NETSAFE,
680 em_intr, adapter,
681 &adapter->int_handler_tag,
682 adapter->interface_data.ac_if.if_serializer);
683 if (error) {
684 device_printf(dev, "Error registering interrupt handler!\n");
685 ether_ifdetach(&adapter->interface_data.ac_if);
686 goto fail;
687 }
688
689 INIT_DEBUGOUT("em_attach: end");
690 return(0);
691
692 fail:
693 em_detach(dev);
694 return(error);
695 }
696
697 /*********************************************************************
698 * Device removal routine
699 *
700 * The detach entry point is called when the driver is being removed.
701 * This routine stops the adapter and deallocates all the resources
702 * that were allocated for driver operation.
703 *
704 * return 0 on success, positive on failure
705 *********************************************************************/
706
707 static int
708 em_detach(device_t dev)
709 {
710 struct adapter *adapter = device_get_softc(dev);
711
712 INIT_DEBUGOUT("em_detach: begin");
713
714 if (device_is_attached(dev)) {
715 struct ifnet *ifp = &adapter->interface_data.ac_if;
716
717 lwkt_serialize_enter(ifp->if_serializer);
718 adapter->in_detach = 1;
719 em_stop(adapter);
720 em_phy_hw_reset(&adapter->hw);
721 bus_teardown_intr(dev, adapter->res_interrupt,
722 adapter->int_handler_tag);
723 lwkt_serialize_exit(ifp->if_serializer);
724
725 ether_ifdetach(ifp);
726 }
727 bus_generic_detach(dev);
728
729 em_free_pci_resources(dev);
730
731 /* Free Transmit Descriptor ring */
732 if (adapter->tx_desc_base != NULL) {
733 em_dma_free(adapter, &adapter->txdma);
734 adapter->tx_desc_base = NULL;
735 }
736
737 /* Free Receive Descriptor ring */
738 if (adapter->rx_desc_base != NULL) {
739 em_dma_free(adapter, &adapter->rxdma);
740 adapter->rx_desc_base = NULL;
741 }
742
743 /* Free sysctl tree */
744 if (adapter->sysctl_tree != NULL) {
745 adapter->sysctl_tree = NULL;
746 sysctl_ctx_free(&adapter->sysctl_ctx);
747 }
748
749 return (0);
750 }
751
752 /*********************************************************************
753 *
754 * Shutdown entry point
755 *
756 **********************************************************************/
757
758 static int
759 em_shutdown(device_t dev)
760 {
761 struct adapter *adapter = device_get_softc(dev);
762 struct ifnet *ifp = &adapter->interface_data.ac_if;
763
764 lwkt_serialize_enter(ifp->if_serializer);
765 em_stop(adapter);
766 lwkt_serialize_exit(ifp->if_serializer);
767
768 return (0);
769 }
770
771 /*
772 * Suspend/resume device methods.
773 */
774 static int
775 em_suspend(device_t dev)
776 {
777 struct adapter *adapter = device_get_softc(dev);
778 struct ifnet *ifp = &adapter->interface_data.ac_if;
779
780 lwkt_serialize_enter(ifp->if_serializer);
781 em_stop(adapter);
782 lwkt_serialize_exit(ifp->if_serializer);
783 return (0);
784 }
785
786 static int
787 em_resume(device_t dev)
788 {
789 struct adapter *adapter = device_get_softc(dev);
790 struct ifnet *ifp = &adapter->interface_data.ac_if;
791
792 lwkt_serialize_enter(ifp->if_serializer);
793 ifp->if_flags &= ~IFF_RUNNING;
794 em_init(adapter);
795 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
796 em_start(ifp);
797 lwkt_serialize_exit(ifp->if_serializer);
798
799 return bus_generic_resume(dev);
800 }
801
802 /*********************************************************************
803 * Transmit entry point
804 *
805 * em_start is called by the stack to initiate a transmit.
806 * The driver will remain in this routine as long as there are
807 * packets to transmit and transmit resources are available.
808 * In case resources are not available stack is notified and
809 * the packet is requeued.
810 **********************************************************************/
811
812 static void
813 em_start(struct ifnet *ifp)
814 {
815 struct mbuf *m_head;
816 struct adapter *adapter = ifp->if_softc;
817
818 ASSERT_SERIALIZED(ifp->if_serializer);
819
820 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
821 return;
822 if (!adapter->link_active)
823 return;
824 while (!ifq_is_empty(&ifp->if_snd)) {
825 m_head = ifq_poll(&ifp->if_snd);
826
827 if (m_head == NULL)
828 break;
829
830 logif(pkt_txqueue);
831 if (em_encap(adapter, m_head)) {
832 ifp->if_flags |= IFF_OACTIVE;
833 break;
834 }
835 ifq_dequeue(&ifp->if_snd, m_head);
836
837 /* Send a copy of the frame to the BPF listener */
838 ETHER_BPF_MTAP(ifp, m_head);
839
840 /* Set timeout in case hardware has problems transmitting. */
841 ifp->if_timer = EM_TX_TIMEOUT;
842 }
843 }
844
845 /*********************************************************************
846 * Ioctl entry point
847 *
848 * em_ioctl is called when the user wants to configure the
849 * interface.
850 *
851 * return 0 on success, positive on failure
852 **********************************************************************/
853
854 static int
855 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
856 {
857 int max_frame_size, mask, error = 0, reinit = 0;
858 struct ifreq *ifr = (struct ifreq *) data;
859 struct adapter *adapter = ifp->if_softc;
860 uint16_t eeprom_data = 0;
861
862 ASSERT_SERIALIZED(ifp->if_serializer);
863
864 if (adapter->in_detach)
865 return 0;
866
867 switch (command) {
868 case SIOCSIFMTU:
869 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
870 switch (adapter->hw.mac_type) {
871 case em_82573:
872 /*
873 * 82573 only supports jumbo frames
874 * if ASPM is disabled.
875 */
876 em_read_eeprom(&adapter->hw, EEPROM_INIT_3GIO_3,
877 1, &eeprom_data);
878 if (eeprom_data & EEPROM_WORD1A_ASPM_MASK) {
879 max_frame_size = ETHER_MAX_LEN;
880 break;
881 }
882 /* Allow Jumbo frames */
883 /* FALLTHROUGH */
884 case em_82571:
885 case em_82572:
886 case em_ich9lan:
887 case em_80003es2lan: /* Limit Jumbo Frame size */
888 max_frame_size = 9234;
889 break;
890 case em_ich8lan:
891 /* ICH8 does not support jumbo frames */
892 max_frame_size = ETHER_MAX_LEN;
893 break;
894 default:
895 max_frame_size = MAX_JUMBO_FRAME_SIZE;
896 break;
897 }
898 if (ifr->ifr_mtu >
899 max_frame_size - ETHER_HDR_LEN - ETHER_CRC_LEN) {
900 error = EINVAL;
901 } else {
902 ifp->if_mtu = ifr->ifr_mtu;
903 adapter->hw.max_frame_size =
904 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
905 ifp->if_flags &= ~IFF_RUNNING;
906 em_init(adapter);
907 }
908 break;
909 case SIOCSIFFLAGS:
910 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS "
911 "(Set Interface Flags)");
912 if (ifp->if_flags & IFF_UP) {
913 if (!(ifp->if_flags & IFF_RUNNING)) {
914 em_init(adapter);
915 } else if ((ifp->if_flags ^ adapter->if_flags) &
916 IFF_PROMISC) {
917 em_disable_promisc(adapter);
918 em_set_promisc(adapter);
919 }
920 } else {
921 if (ifp->if_flags & IFF_RUNNING)
922 em_stop(adapter);
923 }
924 adapter->if_flags = ifp->if_flags;
925 break;
926 case SIOCADDMULTI:
927 case SIOCDELMULTI:
928 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
929 if (ifp->if_flags & IFF_RUNNING) {
930 em_disable_intr(adapter);
931 em_set_multi(adapter);
932 if (adapter->hw.mac_type == em_82542_rev2_0)
933 em_initialize_receive_unit(adapter);
934 #ifdef DEVICE_POLLING
935 /* Do not enable interrupt if polling(4) is enabled */
936 if ((ifp->if_flags & IFF_POLLING) == 0)
937 #endif
938 em_enable_intr(adapter);
939 }
940 break;
941 case SIOCSIFMEDIA:
942 /* Check SOL/IDER usage */
943 if (em_check_phy_reset_block(&adapter->hw)) {
944 if_printf(ifp, "Media change is blocked due to "
945 "SOL/IDER session.\n");
946 break;
947 }
948 /* FALLTHROUGH */
949 case SIOCGIFMEDIA:
950 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA "
951 "(Get/Set Interface Media)");
952 error = ifmedia_ioctl(ifp, ifr, &adapter->media, command);
953 break;
954 case SIOCSIFCAP:
955 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
956 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
957 if (mask & IFCAP_HWCSUM) {
958 ifp->if_capenable ^= IFCAP_HWCSUM;
959 reinit = 1;
960 }
961 if (mask & IFCAP_VLAN_HWTAGGING) {
962 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
963 reinit = 1;
964 }
965 if (reinit && (ifp->if_flags & IFF_RUNNING)) {
966 ifp->if_flags &= ~IFF_RUNNING;
967 em_init(adapter);
968 }
969 break;
970 default:
971 error = ether_ioctl(ifp, command, data);
972 break;
973 }
974
975 return (error);
976 }
977
978 /*********************************************************************
979 * Watchdog entry point
980 *
981 * This routine is called whenever hardware quits transmitting.
982 *
983 **********************************************************************/
984
985 static void
986 em_watchdog(struct ifnet *ifp)
987 {
988 struct adapter *adapter = ifp->if_softc;
989
990 /*
991 * If we are in this routine because of pause frames, then
992 * don't reset the hardware.
993 */
994 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_TXOFF) {
995 ifp->if_timer = EM_TX_TIMEOUT;
996 return;
997 }
998
999 if (em_check_for_link(&adapter->hw) == 0)
1000 if_printf(ifp, "watchdog timeout -- resetting\n");
1001
1002 ifp->if_flags &= ~IFF_RUNNING;
1003 em_init(adapter);
1004
1005 adapter->watchdog_timeouts++;
1006 }
1007
1008 /*********************************************************************
1009 * Init entry point
1010 *
1011 * This routine is used in two ways. It is used by the stack as
1012 * init entry point in network interface structure. It is also used
1013 * by the driver as a hw/sw initialization routine to get to a
1014 * consistent state.
1015 *
1016 * return 0 on success, positive on failure
1017 **********************************************************************/
1018
1019 static void
1020 em_init(void *arg)
1021 {
1022 struct adapter *adapter = arg;
1023 uint32_t pba;
1024 struct ifnet *ifp = &adapter->interface_data.ac_if;
1025
1026 ASSERT_SERIALIZED(ifp->if_serializer);
1027
1028 INIT_DEBUGOUT("em_init: begin");
1029
1030 if (ifp->if_flags & IFF_RUNNING)
1031 return;
1032
1033 em_stop(adapter);
1034
1035 /*
1036 * Packet Buffer Allocation (PBA)
1037 * Writing PBA sets the receive portion of the buffer
1038 * the remainder is used for the transmit buffer.
1039 *
1040 * Devices before the 82547 had a Packet Buffer of 64K.
1041 * Default allocation: PBA=48K for Rx, leaving 16K for Tx.
1042 * After the 82547 the buffer was reduced to 40K.
1043 * Default allocation: PBA=30K for Rx, leaving 10K for Tx.
1044 * Note: default does not leave enough room for Jumbo Frame >10k.
1045 */
1046 switch (adapter->hw.mac_type) {
1047 case em_82547:
1048 case em_82547_rev_2: /* 82547: Total Packet Buffer is 40K */
1049 if (adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1050 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */
1051 else
1052 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */
1053
1054 adapter->tx_fifo_head = 0;
1055 adapter->tx_head_addr = pba << EM_TX_HEAD_ADDR_SHIFT;
1056 adapter->tx_fifo_size =
1057 (E1000_PBA_40K - pba) << EM_PBA_BYTES_SHIFT;
1058 break;
1059 /* Total Packet Buffer on these is 48K */
1060 case em_82571:
1061 case em_82572:
1062 case em_80003es2lan:
1063 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1064 break;
1065 case em_82573: /* 82573: Total Packet Buffer is 32K */
1066 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1067 break;
1068 case em_ich8lan:
1069 pba = E1000_PBA_8K;
1070 break;
1071 case em_ich9lan:
1072 #define E1000_PBA_10K 0x000A
1073 pba = E1000_PBA_10K;
1074 break;
1075 default:
1076 /* Devices before 82547 had a Packet Buffer of 64K. */
1077 if(adapter->hw.max_frame_size > EM_RXBUFFER_8192)
1078 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1079 else
1080 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1081 }
1082
1083 INIT_DEBUGOUT1("em_init: pba=%dK",pba);
1084 E1000_WRITE_REG(&adapter->hw, PBA, pba);
1085
1086 /* Get the latest mac address, User can use a LAA */
1087 bcopy(adapter->interface_data.ac_enaddr, adapter->hw.mac_addr,
1088 ETHER_ADDR_LEN);
1089
1090 /* Initialize the hardware */
1091 if (em_hardware_init(adapter)) {
1092 if_printf(ifp, "Unable to initialize the hardware\n");
1093 return;
1094 }
1095 em_update_link_status(adapter);
1096
1097 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1098 em_enable_vlans(adapter);
1099
1100 /* Set hardware offload abilities */
1101 if (adapter->hw.mac_type >= em_82543) {
1102 if (ifp->if_capenable & IFCAP_TXCSUM)
1103 ifp->if_hwassist = EM_CHECKSUM_FEATURES;
1104 else
1105 ifp->if_hwassist = 0;
1106 }
1107
1108 /* Prepare transmit descriptors and buffers */
1109 if (em_setup_transmit_structures(adapter)) {
1110 if_printf(ifp, "Could not setup transmit structures\n");
1111 em_stop(adapter);
1112 return;
1113 }
1114 em_initialize_transmit_unit(adapter);
1115
1116 /* Setup Multicast table */
1117 em_set_multi(adapter);
1118
1119 /* Prepare receive descriptors and buffers */
1120 if (em_setup_receive_structures(adapter)) {
1121 if_printf(ifp, "Could not setup receive structures\n");
1122 em_stop(adapter);
1123 return;
1124 }
1125 em_initialize_receive_unit(adapter);
1126
1127 /* Don't lose promiscuous settings */
1128 em_set_promisc(adapter);
1129
1130 ifp->if_flags |= IFF_RUNNING;
1131 ifp->if_flags &= ~IFF_OACTIVE;
1132
1133 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1134 em_clear_hw_cntrs(&adapter->hw);
1135
1136 #ifdef DEVICE_POLLING
1137 /* Do not enable interrupt if polling(4) is enabled */
1138 if (ifp->if_flags & IFF_POLLING)
1139 em_disable_intr(adapter);
1140 else
1141 #endif
1142 em_enable_intr(adapter);
1143
1144 /* Don't reset the phy next time init gets called */
1145 adapter->hw.phy_reset_disable = TRUE;
1146 }
1147
1148 #ifdef DEVICE_POLLING
1149
1150 static void
1151 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1152 {
1153 struct adapter *adapter = ifp->if_softc;
1154 uint32_t reg_icr;
1155
1156 ASSERT_SERIALIZED(ifp->if_serializer);
1157
1158 switch(cmd) {
1159 case POLL_REGISTER:
1160 em_disable_intr(adapter);
1161 break;
1162 case POLL_DEREGISTER:
1163 em_enable_intr(adapter);
1164 break;
1165 case POLL_AND_CHECK_STATUS:
1166 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1167 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1168 callout_stop(&adapter->timer);
1169 adapter->hw.get_link_status = 1;
1170 em_check_for_link(&adapter->hw);
1171 em_update_link_status(adapter);
1172 callout_reset(&adapter->timer, hz, em_local_timer,
1173 adapter);
1174 }
1175 /* fall through */
1176 case POLL_ONLY:
1177 if (ifp->if_flags & IFF_RUNNING) {
1178 em_rxeof(adapter, count);
1179 em_txeof(adapter);
1180
1181 if (!ifq_is_empty(&ifp->if_snd))
1182 em_start(ifp);
1183 }
1184 break;
1185 }
1186 }
1187
1188 #endif /* DEVICE_POLLING */
1189
1190 /*********************************************************************
1191 *
1192 * Interrupt Service routine
1193 *
1194 *********************************************************************/
1195 static void
1196 em_intr(void *arg)
1197 {
1198 uint32_t reg_icr;
1199 struct ifnet *ifp;
1200 struct adapter *adapter = arg;
1201
1202 ifp = &adapter->interface_data.ac_if;
1203
1204 logif(intr_beg);
1205 ASSERT_SERIALIZED(ifp->if_serializer);
1206
1207 reg_icr = E1000_READ_REG(&adapter->hw, ICR);
1208 if ((adapter->hw.mac_type >= em_82571 &&
1209 (reg_icr & E1000_ICR_INT_ASSERTED) == 0) ||
1210 reg_icr == 0) {
1211 logif(intr_end);
1212 return;
1213 }
1214
1215 /*
1216 * XXX: some laptops trigger several spurious interrupts on em(4)
1217 * when in the resume cycle. The ICR register reports all-ones
1218 * value in this case. Processing such interrupts would lead to
1219 * a freeze. I don't know why.
1220 */
1221 if (reg_icr == 0xffffffff) {
1222 logif(intr_end);
1223 return;
1224 }
1225
1226 /*
1227 * note: do not attempt to improve efficiency by looping. This
1228 * only results in unnecessary piecemeal collection of received
1229 * packets and unnecessary piecemeal cleanups of the transmit ring.
1230 */
1231 if (ifp->if_flags & IFF_RUNNING) {
1232 em_rxeof(adapter, -1);
1233 em_txeof(adapter);
1234 }
1235
1236 /* Link status change */
1237 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1238 callout_stop(&adapter->timer);
1239 adapter->hw.get_link_status = 1;
1240 em_check_for_link(&adapter->hw);
1241 em_update_link_status(adapter);
1242 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1243 }
1244
1245 if (reg_icr & E1000_ICR_RXO)
1246 adapter->rx_overruns++;
1247
1248 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1249 em_start(ifp);
1250 logif(intr_end);
1251 }
1252
1253 /*********************************************************************
1254 *
1255 * Media Ioctl callback
1256 *
1257 * This routine is called whenever the user queries the status of
1258 * the interface using ifconfig.
1259 *
1260 **********************************************************************/
1261 static void
1262 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1263 {
1264 struct adapter *adapter = ifp->if_softc;
1265 u_char fiber_type = IFM_1000_SX;
1266
1267 INIT_DEBUGOUT("em_media_status: begin");
1268
1269 ASSERT_SERIALIZED(ifp->if_serializer);
1270
1271 em_check_for_link(&adapter->hw);
1272 em_update_link_status(adapter);
1273
1274 ifmr->ifm_status = IFM_AVALID;
1275 ifmr->ifm_active = IFM_ETHER;
1276
1277 if (!adapter->link_active)
1278 return;
1279
1280 ifmr->ifm_status |= IFM_ACTIVE;
1281
1282 if (adapter->hw.media_type == em_media_type_fiber ||
1283 adapter->hw.media_type == em_media_type_internal_serdes) {
1284 if (adapter->hw.mac_type == em_82545)
1285 fiber_type = IFM_1000_LX;
1286 ifmr->ifm_active |= fiber_type | IFM_FDX;
1287 } else {
1288 switch (adapter->link_speed) {
1289 case 10:
1290 ifmr->ifm_active |= IFM_10_T;
1291 break;
1292 case 100:
1293 ifmr->ifm_active |= IFM_100_TX;
1294 break;
1295 case 1000:
1296 ifmr->ifm_active |= IFM_1000_T;
1297 break;
1298 }
1299 if (adapter->link_duplex == FULL_DUPLEX)
1300 ifmr->ifm_active |= IFM_FDX;
1301 else
1302 ifmr->ifm_active |= IFM_HDX;
1303 }
1304 }
1305
1306 /*********************************************************************
1307 *
1308 * Media Ioctl callback
1309 *
1310 * This routine is called when the user changes speed/duplex using
1311 * media/mediopt option with ifconfig.
1312 *
1313 **********************************************************************/
1314 static int
1315 em_media_change(struct ifnet *ifp)
1316 {
1317 struct adapter *adapter = ifp->if_softc;
1318 struct ifmedia *ifm = &adapter->media;
1319
1320 INIT_DEBUGOUT("em_media_change: begin");
1321
1322 ASSERT_SERIALIZED(ifp->if_serializer);
1323
1324 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1325 return (EINVAL);
1326
1327 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1328 case IFM_AUTO:
1329 adapter->hw.autoneg = DO_AUTO_NEG;
1330 adapter->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1331 break;
1332 case IFM_1000_LX:
1333 case IFM_1000_SX:
1334 case IFM_1000_T:
1335 adapter->hw.autoneg = DO_AUTO_NEG;
1336 adapter->hw.autoneg_advertised = ADVERTISE_1000_FULL;
1337 break;
1338 case IFM_100_TX:
1339 adapter->hw.autoneg = FALSE;
1340 adapter->hw.autoneg_advertised = 0;
1341 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1342 adapter->hw.forced_speed_duplex = em_100_full;
1343 else
1344 adapter->hw.forced_speed_duplex = em_100_half;
1345 break;
1346 case IFM_10_T:
1347 adapter->hw.autoneg = FALSE;
1348 adapter->hw.autoneg_advertised = 0;
1349 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1350 adapter->hw.forced_speed_duplex = em_10_full;
1351 else
1352 adapter->hw.forced_speed_duplex = em_10_half;
1353 break;
1354 default:
1355 if_printf(ifp, "Unsupported media type\n");
1356 }
1357 /*
1358 * As the speed/duplex settings may have changed we need to
1359 * reset the PHY.
1360 */
1361 adapter->hw.phy_reset_disable = FALSE;
1362
1363 ifp->if_flags &= ~IFF_RUNNING;
1364 em_init(adapter);
1365
1366 return(0);
1367 }
1368
1369 static void
1370 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize,
1371 int error)
1372 {
1373 struct em_q *q = arg;
1374
1375 if (error)
1376 return;
1377 KASSERT(nsegs <= EM_MAX_SCATTER,
1378 ("Too many DMA segments returned when mapping tx packet"));
1379 q->nsegs = nsegs;
1380 bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
1381 }
1382
1383 /*********************************************************************
1384 *
1385 * This routine maps the mbufs to tx descriptors.
1386 *
1387 * return 0 on success, positive on failure
1388 **********************************************************************/
1389 static int
1390 em_encap(struct adapter *adapter, struct mbuf *m_head)
1391 {
1392 uint32_t txd_upper = 0, txd_lower = 0, txd_used = 0, txd_saved = 0;
1393 int i, j, error, last = 0;
1394
1395 struct em_q q;
1396 struct em_buffer *tx_buffer = NULL, *tx_buffer_first;
1397 bus_dmamap_t map;
1398 struct em_tx_desc *current_tx_desc = NULL;
1399 struct ifnet *ifp = &adapter->interface_data.ac_if;
1400
1401 /*
1402 * Force a cleanup if number of TX descriptors
1403 * available hits the threshold
1404 */
1405 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1406 em_txeof(adapter);
1407 if (adapter->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1408 adapter->no_tx_desc_avail1++;
1409 return (ENOBUFS);
1410 }
1411 }
1412
1413 /*
1414 * Capture the first descriptor index, this descriptor will have
1415 * the index of the EOP which is the only one that now gets a
1416 * DONE bit writeback.
1417 */
1418 tx_buffer_first = &adapter->tx_buffer_area[adapter->next_avail_tx_desc];
1419
1420 /*
1421 * Map the packet for DMA.
1422 */
1423 map = tx_buffer_first->map;
1424 error = bus_dmamap_load_mbuf(adapter->txtag, map, m_head, em_tx_cb,
1425 &q, BUS_DMA_NOWAIT);
1426 if (error != 0) {
1427 adapter->no_tx_dma_setup++;
1428 return (error);
1429 }
1430 KASSERT(q.nsegs != 0, ("em_encap: empty packet"));
1431
1432 if (q.nsegs > (adapter->num_tx_desc_avail - 2)) {
1433 adapter->no_tx_desc_avail2++;
1434 error = ENOBUFS;
1435 goto fail;
1436 }
1437
1438 if (ifp->if_hwassist > 0) {
1439 em_transmit_checksum_setup(adapter, m_head,
1440 &txd_upper, &txd_lower);
1441 }
1442
1443 i = adapter->next_avail_tx_desc;
1444 if (adapter->pcix_82544)
1445 txd_saved = i;
1446
1447 /* Set up our transmit descriptors */
1448 for (j = 0; j < q.nsegs; j++) {
1449 /* If adapter is 82544 and on PCIX bus */
1450 if(adapter->pcix_82544) {
1451 DESC_ARRAY desc_array;
1452 uint32_t array_elements, counter;
1453
1454 /*
1455 * Check the Address and Length combination and
1456 * split the data accordingly
1457 */
1458 array_elements = em_fill_descriptors(q.segs[j].ds_addr,
1459 q.segs[j].ds_len, &desc_array);
1460 for (counter = 0; counter < array_elements; counter++) {
1461 if (txd_used == adapter->num_tx_desc_avail) {
1462 adapter->next_avail_tx_desc = txd_saved;
1463 adapter->no_tx_desc_avail2++;
1464 error = ENOBUFS;
1465 goto fail;
1466 }
1467 tx_buffer = &adapter->tx_buffer_area[i];
1468 current_tx_desc = &adapter->tx_desc_base[i];
1469 current_tx_desc->buffer_addr = htole64(
1470 desc_array.descriptor[counter].address);
1471 current_tx_desc->lower.data = htole32(
1472 adapter->txd_cmd | txd_lower |
1473 (uint16_t)desc_array.descriptor[counter].length);
1474 current_tx_desc->upper.data = htole32(txd_upper);
1475
1476 last = i;
1477 if (++i == adapter->num_tx_desc)
1478 i = 0;
1479
1480 tx_buffer->m_head = NULL;
1481 tx_buffer->next_eop = -1;
1482 txd_used++;
1483 }
1484 } else {
1485 tx_buffer = &adapter->tx_buffer_area[i];
1486 current_tx_desc = &adapter->tx_desc_base[i];
1487
1488 current_tx_desc->buffer_addr = htole64(q.segs[j].ds_addr);
1489 current_tx_desc->lower.data = htole32(
1490 adapter->txd_cmd | txd_lower | q.segs[j].ds_len);
1491 current_tx_desc->upper.data = htole32(txd_upper);
1492
1493 last = i;
1494 if (++i == adapter->num_tx_desc)
1495 i = 0;
1496
1497 tx_buffer->m_head = NULL;
1498 tx_buffer->next_eop = -1;
1499 }
1500 }
1501
1502 adapter->next_avail_tx_desc = i;
1503 if (adapter->pcix_82544)
1504 adapter->num_tx_desc_avail -= txd_used;
1505 else
1506 adapter->num_tx_desc_avail -= q.nsegs;
1507
1508 /* Find out if we are in vlan mode */
1509 if (m_head->m_flags & M_VLANTAG) {
1510 /* Set the vlan id */
1511 current_tx_desc->upper.fields.special =
1512 htole16(m_head->m_pkthdr.ether_vlantag);
1513
1514 /* Tell hardware to add tag */
1515 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);
1516 }
1517
1518 tx_buffer->m_head = m_head;
1519 tx_buffer_first->map = tx_buffer->map;
1520 tx_buffer->map = map;
1521 bus_dmamap_sync(adapter->txtag, map, BUS_DMASYNC_PREWRITE);
1522
1523 /*
1524 * Last Descriptor of Packet needs End Of Packet (EOP)
1525 * and Report Status (RS)
1526 */
1527 current_tx_desc->lower.data |=
1528 htole32(E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS);
1529
1530 /*
1531 * Keep track in the first buffer which descriptor will be
1532 * written back.
1533 */
1534 tx_buffer_first->next_eop = last;
1535
1536 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
1537 BUS_DMASYNC_PREWRITE);
1538
1539 /*
1540 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
1541 * that this frame is available to transmit.
1542 */
1543 if (adapter->hw.mac_type == em_82547 &&
1544 adapter->link_duplex == HALF_DUPLEX) {
1545 em_82547_move_tail_serialized(adapter);
1546 } else {
1547 E1000_WRITE_REG(&adapter->hw, TDT, i);
1548 if (adapter->hw.mac_type == em_82547) {
1549 em_82547_update_fifo_head(adapter,
1550 m_head->m_pkthdr.len);
1551 }
1552 }
1553
1554 return (0);
1555 fail:
1556 bus_dmamap_unload(adapter->txtag, map);
1557 return error;
1558 }
1559
1560 /*********************************************************************
1561 *
1562 * 82547 workaround to avoid controller hang in half-duplex environment.
1563 * The workaround is to avoid queuing a large packet that would span
1564 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1565 * in this case. We do that only when FIFO is quiescent.
1566 *
1567 **********************************************************************/
1568 static void
1569 em_82547_move_tail(void *arg)
1570 {
1571 struct adapter *adapter = arg;
1572 struct ifnet *ifp = &adapter->interface_data.ac_if;
1573
1574 lwkt_serialize_enter(ifp->if_serializer);
1575 em_82547_move_tail_serialized(adapter);
1576 lwkt_serialize_exit(ifp->if_serializer);
1577 }
1578
1579 static void
1580 em_82547_move_tail_serialized(struct adapter *adapter)
1581 {
1582 uint16_t hw_tdt;
1583 uint16_t sw_tdt;
1584 struct em_tx_desc *tx_desc;
1585 uint16_t length = 0;
1586 boolean_t eop = 0;
1587
1588 hw_tdt = E1000_READ_REG(&adapter->hw, TDT);
1589 sw_tdt = adapter->next_avail_tx_desc;
1590
1591 while (hw_tdt != sw_tdt) {
1592 tx_desc = &adapter->tx_desc_base[hw_tdt];
1593 length += tx_desc->lower.flags.length;
1594 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1595 if (++hw_tdt == adapter->num_tx_desc)
1596 hw_tdt = 0;
1597
1598 if (eop) {
1599 if (em_82547_fifo_workaround(adapter, length)) {
1600 adapter->tx_fifo_wrk_cnt++;
1601 callout_reset(&adapter->tx_fifo_timer, 1,
1602 em_82547_move_tail, adapter);
1603 break;
1604 }
1605 E1000_WRITE_REG(&adapter->hw, TDT, hw_tdt);
1606 em_82547_update_fifo_head(adapter, length);
1607 length = 0;
1608 }
1609 }
1610 }
1611
1612 static int
1613 em_82547_fifo_workaround(struct adapter *adapter, int len)
1614 {
1615 int fifo_space, fifo_pkt_len;
1616
1617 fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1618
1619 if (adapter->link_duplex == HALF_DUPLEX) {
1620 fifo_space = adapter->tx_fifo_size - adapter->tx_fifo_head;
1621
1622 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1623 if (em_82547_tx_fifo_reset(adapter))
1624 return (0);
1625 else
1626 return (1);
1627 }
1628 }
1629
1630 return (0);
1631 }
1632
1633 static void
1634 em_82547_update_fifo_head(struct adapter *adapter, int len)
1635 {
1636 int fifo_pkt_len = roundup2(len + EM_FIFO_HDR, EM_FIFO_HDR);
1637
1638 /* tx_fifo_head is always 16 byte aligned */
1639 adapter->tx_fifo_head += fifo_pkt_len;
1640 if (adapter->tx_fifo_head >= adapter->tx_fifo_size)
1641 adapter->tx_fifo_head -= adapter->tx_fifo_size;
1642 }
1643
1644 static int
1645 em_82547_tx_fifo_reset(struct adapter *adapter)
1646 {
1647 uint32_t tctl;
1648
1649 if (E1000_READ_REG(&adapter->hw, TDT) == E1000_READ_REG(&adapter->hw, TDH) &&
1650 E1000_READ_REG(&adapter->hw, TDFT) == E1000_READ_REG(&adapter->hw, TDFH) &&
1651 E1000_READ_REG(&adapter->hw, TDFTS) == E1000_READ_REG(&adapter->hw, TDFHS) &&
1652 E1000_READ_REG(&adapter->hw, TDFPC) == 0) {
1653 /* Disable TX unit */
1654 tctl = E1000_READ_REG(&adapter->hw, TCTL);
1655 E1000_WRITE_REG(&adapter->hw, TCTL, tctl & ~E1000_TCTL_EN);
1656
1657 /* Reset FIFO pointers */
1658 E1000_WRITE_REG(&adapter->hw, TDFT, adapter->tx_head_addr);
1659 E1000_WRITE_REG(&adapter->hw, TDFH, adapter->tx_head_addr);
1660 E1000_WRITE_REG(&adapter->hw, TDFTS, adapter->tx_head_addr);
1661 E1000_WRITE_REG(&adapter->hw, TDFHS, adapter->tx_head_addr);
1662
1663 /* Re-enable TX unit */
1664 E1000_WRITE_REG(&adapter->hw, TCTL, tctl);
1665 E1000_WRITE_FLUSH(&adapter->hw);
1666
1667 adapter->tx_fifo_head = 0;
1668 adapter->tx_fifo_reset_cnt++;
1669
1670 return (TRUE);
1671 } else {
1672 return (FALSE);
1673 }
1674 }
1675
1676 static void
1677 em_set_promisc(struct adapter *adapter)
1678 {
1679 uint32_t reg_rctl;
1680 struct ifnet *ifp = &adapter->interface_data.ac_if;
1681
1682 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1683
1684 adapter->em_insert_vlan_header = 0;
1685 if (ifp->if_flags & IFF_PROMISC) {
1686 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1687 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1688
1689 /*
1690 * Disable VLAN stripping in promiscous mode.
1691 * This enables bridging of vlan tagged frames to occur
1692 * and also allows vlan tags to be seen in tcpdump.
1693 */
1694 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1695 em_disable_vlans(adapter);
1696 adapter->em_insert_vlan_header = 1;
1697 } else if (ifp->if_flags & IFF_ALLMULTI) {
1698 reg_rctl |= E1000_RCTL_MPE;
1699 reg_rctl &= ~E1000_RCTL_UPE;
1700 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1701 }
1702 }
1703
1704 static void
1705 em_disable_promisc(struct adapter *adapter)
1706 {
1707 struct ifnet *ifp = &adapter->interface_data.ac_if;
1708
1709 uint32_t reg_rctl;
1710
1711 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1712
1713 reg_rctl &= (~E1000_RCTL_UPE);
1714 reg_rctl &= (~E1000_RCTL_MPE);
1715 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1716
1717 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
1718 em_enable_vlans(adapter);
1719 adapter->em_insert_vlan_header = 0;
1720 }
1721
1722 /*********************************************************************
1723 * Multicast Update
1724 *
1725 * This routine is called whenever multicast address list is updated.
1726 *
1727 **********************************************************************/
1728
1729 static void
1730 em_set_multi(struct adapter *adapter)
1731 {
1732 uint32_t reg_rctl = 0;
1733 uint8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
1734 struct ifmultiaddr *ifma;
1735 int mcnt = 0;
1736 struct ifnet *ifp = &adapter->interface_data.ac_if;
1737
1738 IOCTL_DEBUGOUT("em_set_multi: begin");
1739
1740 if (adapter->hw.mac_type == em_82542_rev2_0) {
1741 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1742 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1743 em_pci_clear_mwi(&adapter->hw);
1744 reg_rctl |= E1000_RCTL_RST;
1745 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1746 msec_delay(5);
1747 }
1748
1749 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1750 if (ifma->ifma_addr->sa_family != AF_LINK)
1751 continue;
1752
1753 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1754 break;
1755
1756 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1757 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
1758 mcnt++;
1759 }
1760
1761 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1762 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1763 reg_rctl |= E1000_RCTL_MPE;
1764 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1765 } else {
1766 em_mc_addr_list_update(&adapter->hw, mta, mcnt, 0, 1);
1767 }
1768
1769 if (adapter->hw.mac_type == em_82542_rev2_0) {
1770 reg_rctl = E1000_READ_REG(&adapter->hw, RCTL);
1771 reg_rctl &= ~E1000_RCTL_RST;
1772 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
1773 msec_delay(5);
1774 if (adapter->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1775 em_pci_set_mwi(&adapter->hw);
1776 }
1777 }
1778
1779 /*********************************************************************
1780 * Timer routine
1781 *
1782 * This routine checks for link status and updates statistics.
1783 *
1784 **********************************************************************/
1785
1786 static void
1787 em_local_timer(void *arg)
1788 {
1789 struct ifnet *ifp;
1790 struct adapter *adapter = arg;
1791 ifp = &adapter->interface_data.ac_if;
1792
1793 lwkt_serialize_enter(ifp->if_serializer);
1794
1795 em_check_for_link(&adapter->hw);
1796 em_update_link_status(adapter);
1797 em_update_stats_counters(adapter);
1798 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING)
1799 em_print_hw_stats(adapter);
1800 em_smartspeed(adapter);
1801
1802 callout_reset(&adapter->timer, hz, em_local_timer, adapter);
1803
1804 lwkt_serialize_exit(ifp->if_serializer);
1805 }
1806
1807 static void
1808 em_update_link_status(struct adapter *adapter)
1809 {
1810 struct ifnet *ifp;
1811 ifp = &adapter->interface_data.ac_if;
1812
1813 if (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU) {
1814 if (adapter->link_active == 0) {
1815 em_get_speed_and_duplex(&adapter->hw,
1816 &adapter->link_speed,
1817 &adapter->link_duplex);
1818 /* Check if we may set SPEED_MODE bit on PCI-E */
1819 if (adapter->link_speed == SPEED_1000 &&
1820 (adapter->hw.mac_type == em_82571 ||
1821 adapter->hw.mac_type == em_82572)) {
1822 int tarc0;
1823
1824 tarc0 = E1000_READ_REG(&adapter->hw, TARC0);
1825 tarc0 |= SPEED_MODE_BIT;
1826 E1000_WRITE_REG(&adapter->hw, TARC0, tarc0);
1827 }
1828 if (bootverbose) {
1829 if_printf(&adapter->interface_data.ac_if,
1830 "Link is up %d Mbps %s\n",
1831 adapter->link_speed,
1832 adapter->link_duplex == FULL_DUPLEX ?
1833 "Full Duplex" : "Half Duplex");
1834 }
1835 adapter->link_active = 1;
1836 adapter->smartspeed = 0;
1837 ifp->if_baudrate = adapter->link_speed * 1000000;
1838 ifp->if_link_state = LINK_STATE_UP;
1839 if_link_state_change(ifp);
1840 }
1841 } else {
1842 if (adapter->link_active == 1) {
1843 ifp->if_baudrate = 0;
1844 adapter->link_speed = 0;
1845 adapter->link_duplex = 0;
1846 if (bootverbose) {
1847 if_printf(&adapter->interface_data.ac_if,
1848 "Link is Down\n");
1849 }
1850 adapter->link_active = 0;
1851 ifp->if_link_state = LINK_STATE_DOWN;
1852 if_link_state_change(ifp);
1853 }
1854 }
1855 }
1856
1857 /*********************************************************************
1858 *
1859 * This routine disables all traffic on the adapter by issuing a
1860 * global reset on the MAC and deallocates TX/RX buffers.
1861 *
1862 **********************************************************************/
1863
1864 static void
1865 em_stop(void *arg)
1866 {
1867 struct ifnet *ifp;
1868 struct adapter * adapter = arg;
1869 ifp = &adapter->interface_data.ac_if;
1870
1871 ASSERT_SERIALIZED(ifp->if_serializer);
1872
1873 INIT_DEBUGOUT("em_stop: begin");
1874 em_disable_intr(adapter);
1875 em_reset_hw(&adapter->hw);
1876 callout_stop(&adapter->timer);
1877 callout_stop(&adapter->tx_fifo_timer);
1878 em_free_transmit_structures(adapter);
1879 em_free_receive_structures(adapter);
1880
1881 /* Tell the stack that the interface is no longer active */
1882 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1883 ifp->if_timer = 0;
1884 }
1885
1886 /*********************************************************************
1887 *
1888 * Determine hardware revision.
1889 *
1890 **********************************************************************/
1891 static void
1892 em_identify_hardware(struct adapter *adapter)
1893 {
1894 device_t dev = adapter->dev;
1895
1896 /* Make sure our PCI config space has the necessary stuff set */
1897 adapter->hw.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
1898 if (!((adapter->hw.pci_cmd_word & PCIM_CMD_BUSMASTEREN) &&
1899 (adapter->hw.pci_cmd_word & PCIM_CMD_MEMEN))) {
1900 device_printf(dev, "Memory Access and/or Bus Master bits "
1901 "were not set!\n");
1902 adapter->hw.pci_cmd_word |= PCIM_CMD_BUSMASTEREN |
1903 PCIM_CMD_MEMEN;
1904 pci_write_config(dev, PCIR_COMMAND,
1905 adapter->hw.pci_cmd_word, 2);
1906 }
1907
1908 /* Save off the information about this board */
1909 adapter->hw.vendor_id = pci_get_vendor(dev);
1910 adapter->hw.device_id = pci_get_device(dev);
1911 adapter->hw.revision_id = pci_get_revid(dev);
1912 adapter->hw.subsystem_vendor_id = pci_get_subvendor(dev);
1913 adapter->hw.subsystem_id = pci_get_subdevice(dev);
1914
1915 /* Identify the MAC */
1916 if (em_set_mac_type(&adapter->hw))
1917 device_printf(dev, "Unknown MAC Type\n");
1918
1919 if (adapter->hw.mac_type == em_82541 ||
1920 adapter->hw.mac_type == em_82541_rev_2 ||
1921 adapter->hw.mac_type == em_82547 ||
1922 adapter->hw.mac_type == em_82547_rev_2)
1923 adapter->hw.phy_init_script = TRUE;
1924 }
1925
1926 static int
1927 em_allocate_pci_resources(device_t dev)
1928 {
1929 struct adapter *adapter = device_get_softc(dev);
1930 int rid;
1931
1932 rid = PCIR_BAR(0);
1933 adapter->res_memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1934 &rid, RF_ACTIVE);
1935 if (adapter->res_memory == NULL) {
1936 device_printf(dev, "Unable to allocate bus resource: memory\n");
1937 return ENXIO;
1938 }
1939 adapter->osdep.mem_bus_space_tag =
1940 rman_get_bustag(adapter->res_memory);
1941 adapter->osdep.mem_bus_space_handle =
1942 rman_get_bushandle(adapter->res_memory);
1943 adapter->hw.hw_addr = (uint8_t *)&adapter->osdep.mem_bus_space_handle;
1944
1945 if (adapter->hw.mac_type > em_82543) {
1946 /* Figure our where our IO BAR is ? */
1947 for (rid = PCIR_BAR(0); rid < PCIR_CIS;) {
1948 uint32_t val;
1949
1950 val = pci_read_config(dev, rid, 4);
1951 if (EM_BAR_TYPE(val) == EM_BAR_TYPE_IO) {
1952 adapter->io_rid = rid;
1953 break;
1954 }
1955 rid += 4;
1956 /* check for 64bit BAR */
1957 if (EM_BAR_MEM_TYPE(val) == EM_BAR_MEM_TYPE_64BIT)
1958 rid += 4;
1959 }
1960 if (rid >= PCIR_CIS) {
1961 device_printf(dev, "Unable to locate IO BAR\n");
1962 return (ENXIO);
1963 }
1964
1965 adapter->res_ioport = bus_alloc_resource_any(dev,
1966 SYS_RES_IOPORT, &adapter->io_rid, RF_ACTIVE);
1967 if (!(adapter->res_ioport)) {
1968 device_printf(dev, "Unable to allocate bus resource: "
1969 "ioport\n");
1970 return ENXIO;
1971 }
1972 adapter->hw.io_base = 0;
1973 adapter->osdep.io_bus_space_tag =
1974 rman_get_bustag(adapter->res_ioport);
1975 adapter->osdep.io_bus_space_handle =
1976 rman_get_bushandle(adapter->res_ioport);
1977 }
1978
1979 /* For ICH8 we need to find the flash memory. */
1980 if ((adapter->hw.mac_type == em_ich8lan) ||
1981 (adapter->hw.mac_type == em_ich9lan)) {
1982 rid = EM_FLASH;
1983 adapter->flash_mem = bus_alloc_resource_any(dev,
1984 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1985 if (adapter->flash_mem == NULL) {
1986 device_printf(dev, "Unable to allocate bus resource: "
1987 "flash memory\n");
1988 return ENXIO;
1989 }
1990 adapter->osdep.flash_bus_space_tag =
1991 rman_get_bustag(adapter->flash_mem);
1992 adapter->osdep.flash_bus_space_handle =
1993 rman_get_bushandle(adapter->flash_mem);
1994 }
1995
1996 rid = 0x0;
1997 adapter->res_interrupt = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1998 &rid, RF_SHAREABLE | RF_ACTIVE);
1999 if (adapter->res_interrupt == NULL) {
2000 device_printf(dev, "Unable to allocate bus resource: "
2001 "interrupt\n");
2002 return ENXIO;
2003 }
2004
2005 adapter->hw.back = &adapter->osdep;
2006
2007 return 0;
2008 }
2009
2010 static void
2011 em_free_pci_resources(device_t dev)
2012 {
2013 struct adapter *adapter = device_get_softc(dev);
2014
2015 if (adapter->res_interrupt != NULL) {
2016 bus_release_resource(dev, SYS_RES_IRQ, 0,
2017 adapter->res_interrupt);
2018 }
2019 if (adapter->res_memory != NULL) {
2020 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
2021 adapter->res_memory);
2022 }
2023
2024 if (adapter->res_ioport != NULL) {
2025 bus_release_resource(dev, SYS_RES_IOPORT, adapter->io_rid,
2026 adapter->res_ioport);
2027 }
2028
2029 if (adapter->flash_mem != NULL) {
2030 bus_release_resource(dev, SYS_RES_MEMORY, EM_FLASH,
2031 adapter->flash_mem);
2032 }
2033 }
2034
2035 /*********************************************************************
2036 *
2037 * Initialize the hardware to a configuration as specified by the
2038 * adapter structure. The controller is reset, the EEPROM is
2039 * verified, the MAC address is set, then the shared initialization
2040 * routines are called.
2041 *
2042 **********************************************************************/
2043 static int
2044 em_hardware_init(struct adapter *adapter)
2045 {
2046 uint16_t rx_buffer_size;
2047
2048 INIT_DEBUGOUT("em_hardware_init: begin");
2049 /* Issue a global reset */
2050 em_reset_hw(&adapter->hw);
2051
2052 /* When hardware is reset, fifo_head is also reset */
2053 adapter->tx_fifo_head = 0;
2054
2055 /* Make sure we have a good EEPROM before we read from it */
2056 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2057 if (em_validate_eeprom_checksum(&adapter->hw) < 0) {
2058 device_printf(adapter->dev,
2059 "The EEPROM Checksum Is Not Valid\n");
2060 return (EIO);
2061 }
2062 }
2063
2064 if (em_read_part_num(&adapter->hw, &(adapter->part_num)) < 0) {
2065 device_printf(adapter->dev,
2066 "EEPROM read error while reading part number\n");
2067 return (EIO);
2068 }
2069
2070 /* Set up smart power down as default off on newer adapters. */
2071 if (!em_smart_pwr_down &&
2072 (adapter->hw.mac_type == em_82571 ||
2073 adapter->hw.mac_type == em_82572)) {
2074 uint16_t phy_tmp = 0;
2075
2076 /* Speed up time to link by disabling smart power down. */
2077 em_read_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
2078 &phy_tmp);
2079 phy_tmp &= ~IGP02E1000_PM_SPD;
2080 em_write_phy_reg(&adapter->hw, IGP02E1000_PHY_POWER_MGMT,
2081 phy_tmp);
2082 }
2083
2084 /*
2085 * These parameters control the automatic generation (Tx) and
2086 * response (Rx) to Ethernet PAUSE frames.
2087 * - High water mark should allow for at least two frames to be
2088 * received after sending an XOFF.
2089 * - Low water mark works best when it is very near the high water mark.
2090 * This allows the receiver to restart by sending XON when it has
2091 * drained a bit. Here we use an arbitary value of 1500 which will
2092 * restart after one full frame is pulled from the buffer. There
2093 * could be several smaller frames in the buffer and if so they will
2094 * not trigger the XON until their total number reduces the buffer
2095 * by 1500.
2096 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
2097 */
2098 rx_buffer_size = ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff) << 10);
2099
2100 adapter->hw.fc_high_water =
2101 rx_buffer_size - roundup2(adapter->hw.max_frame_size, 1024);
2102 adapter->hw.fc_low_water = adapter->hw.fc_high_water - 1500;
2103 if (adapter->hw.mac_type == em_80003es2lan)
2104 adapter->hw.fc_pause_time = 0xFFFF;
2105 else
2106 adapter->hw.fc_pause_time = 1000;
2107 adapter->hw.fc_send_xon = TRUE;
2108 adapter->hw.fc = E1000_FC_FULL;
2109
2110 if (em_init_hw(&adapter->hw) < 0) {
2111 device_printf(adapter->dev, "Hardware Initialization Failed");
2112 return (EIO);
2113 }
2114
2115 em_check_for_link(&adapter->hw);
2116
2117 return (0);
2118 }
2119
2120 /*********************************************************************
2121 *
2122 * Setup networking device structure and register an interface.
2123 *
2124 **********************************************************************/
2125 static void
2126 em_setup_interface(device_t dev, struct adapter *adapter)
2127 {
2128 struct ifnet *ifp;
2129 u_char fiber_type = IFM_1000_SX; /* default type */
2130 INIT_DEBUGOUT("em_setup_interface: begin");
2131
2132 ifp = &adapter->interface_data.ac_if;
2133 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2134 ifp->if_mtu = ETHERMTU;
2135 ifp->if_baudrate = 1000000000;
2136 ifp->if_init = em_init;
2137 ifp->if_softc = adapter;
2138 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2139 ifp->if_ioctl = em_ioctl;
2140 ifp->if_start = em_start;
2141 #ifdef DEVICE_POLLING
2142 ifp->if_poll = em_poll;
2143 #endif
2144 ifp->if_watchdog = em_watchdog;
2145 ifq_set_maxlen(&ifp->if_snd, adapter->num_tx_desc - 1);
2146 ifq_set_ready(&ifp->if_snd);
2147
2148 if (adapter->hw.mac_type >= em_82543)
2149 ifp->if_capabilities |= IFCAP_HWCSUM;
2150
2151 ifp->if_capenable = ifp->if_capabilities;
2152
2153 ether_ifattach(ifp, adapter->hw.mac_addr, NULL);
2154
2155 #ifdef PROFILE_SERIALIZER
2156 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2157 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2158 "serializer_sleep", CTLFLAG_RW,
2159 &ifp->if_serializer->sleep_cnt, 0, NULL);
2160 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2161 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2162 "serializer_tryfail", CTLFLAG_RW,
2163 &ifp->if_serializer->tryfail_cnt, 0, NULL);
2164 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2165 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2166 "serializer_enter", CTLFLAG_RW,
2167 &ifp->if_serializer->enter_cnt, 0, NULL);
2168 SYSCTL_ADD_UINT(&adapter->sysctl_ctx,
2169 SYSCTL_CHILDREN(adapter->sysctl_tree), OID_AUTO,
2170 "serializer_try", CTLFLAG_RW,
2171 &ifp->if_serializer->try_cnt, 0, NULL);
2172 #endif
2173
2174 /*
2175 * Tell the upper layer(s) we support long frames.
2176 */
2177 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2178 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2179 #if 0
2180 ifp->if_capenable |= IFCAP_VLAN_MTU;
2181 #endif
2182
2183 /*
2184 * Specify the media types supported by this adapter and register
2185 * callbacks to update media and link information
2186 */
2187 ifmedia_init(&adapter->media, IFM_IMASK, em_media_change,
2188 em_media_status);
2189 if (adapter->hw.media_type == em_media_type_fiber ||
2190 adapter->hw.media_type == em_media_type_internal_serdes) {
2191 if (adapter->hw.mac_type == em_82545)
2192 fiber_type = IFM_1000_LX;
2193 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type | IFM_FDX,
2194 0, NULL);
2195 ifmedia_add(&adapter->media, IFM_ETHER | fiber_type, 0, NULL);
2196 } else {
2197 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T, 0, NULL);
2198 ifmedia_add(&adapter->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2199 0, NULL);
2200 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX,
2201 0, NULL);
2202 ifmedia_add(&adapter->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2203 0, NULL);
2204 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
2205 0, NULL);
2206 ifmedia_add(&adapter->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2207 }
2208 ifmedia_add(&adapter->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2209 ifmedia_set(&adapter->media, IFM_ETHER | IFM_AUTO);
2210 }
2211
2212 /*********************************************************************
2213 *
2214 * Workaround for SmartSpeed on 82541 and 82547 controllers
2215 *
2216 **********************************************************************/
2217 static void
2218 em_smartspeed(struct adapter *adapter)
2219 {
2220 uint16_t phy_tmp;
2221
2222 if (adapter->link_active || (adapter->hw.phy_type != em_phy_igp) ||
2223 !adapter->hw.autoneg ||
2224 !(adapter->hw.autoneg_advertised & ADVERTISE_1000_FULL))
2225 return;
2226
2227 if (adapter->smartspeed == 0) {
2228 /*
2229 * If Master/Slave config fault is asserted twice,
2230 * we assume back-to-back.
2231 */
2232 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2233 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2234 return;
2235 em_read_phy_reg(&adapter->hw, PHY_1000T_STATUS, &phy_tmp);
2236 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2237 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2238 if (phy_tmp & CR_1000T_MS_ENABLE) {
2239 phy_tmp &= ~CR_1000T_MS_ENABLE;
2240 em_write_phy_reg(&adapter->hw,
2241 PHY_1000T_CTRL, phy_tmp);
2242 adapter->smartspeed++;
2243 if (adapter->hw.autoneg &&
2244 !em_phy_setup_autoneg(&adapter->hw) &&
2245 !em_read_phy_reg(&adapter->hw, PHY_CTRL,
2246 &phy_tmp)) {
2247 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2248 MII_CR_RESTART_AUTO_NEG);
2249 em_write_phy_reg(&adapter->hw,
2250 PHY_CTRL, phy_tmp);
2251 }
2252 }
2253 }
2254 return;
2255 } else if (adapter->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2256 /* If still no link, perhaps using 2/3 pair cable */
2257 em_read_phy_reg(&adapter->hw, PHY_1000T_CTRL, &phy_tmp);
2258 phy_tmp |= CR_1000T_MS_ENABLE;
2259 em_write_phy_reg(&adapter->hw, PHY_1000T_CTRL, phy_tmp);
2260 if (adapter->hw.autoneg &&
2261 !em_phy_setup_autoneg(&adapter->hw) &&
2262 !em_read_phy_reg(&adapter->hw, PHY_CTRL, &phy_tmp)) {
2263 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2264 MII_CR_RESTART_AUTO_NEG);
2265 em_write_phy_reg(&adapter->hw, PHY_CTRL, phy_tmp);
2266 }
2267 }
2268 /* Restart process after EM_SMARTSPEED_MAX iterations */
2269 if (adapter->smartspeed++ == EM_SMARTSPEED_MAX)
2270 adapter->smartspeed = 0;
2271 }
2272
2273 /*
2274 * Manage DMA'able memory.
2275 */
2276 static void
2277 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2278 {
2279 if (error)
2280 return;
2281 *(bus_addr_t *)arg = segs->ds_addr;
2282 }
2283
2284 static int
2285 em_dma_malloc(struct adapter *adapter, bus_size_t size,
2286 struct em_dma_alloc *dma)
2287 {
2288 device_t dev = adapter->dev;
2289 int error;
2290
2291 error = bus_dma_tag_create(NULL, /* parent */
2292 EM_DBA_ALIGN, 0, /* alignment, bounds */
2293 BUS_SPACE_MAXADDR, /* lowaddr */
2294 BUS_SPACE_MAXADDR, /* highaddr */
2295 NULL, NULL, /* filter, filterarg */
2296 size, /* maxsize */
2297 1, /* nsegments */
2298 size, /* maxsegsize */
2299 0, /* flags */
2300 &dma->dma_tag);
2301 if (error) {
2302 device_printf(dev, "%s: bus_dma_tag_create failed; error %d\n",
2303 __func__, error);
2304 return error;
2305 }
2306
2307 error = bus_dmamem_alloc(dma->dma_tag, (void**)&dma->dma_vaddr,
2308 BUS_DMA_WAITOK, &dma->dma_map);
2309 if (error) {
2310 device_printf(dev, "%s: bus_dmammem_alloc failed; "
2311 "size %llu, error %d\n",
2312 __func__, (uintmax_t)size, error);
2313 goto fail;
2314 }
2315
2316 error = bus_dmamap_load(dma->dma_tag, dma->dma_map,
2317 dma->dma_vaddr, size,
2318 em_dmamap_cb, &dma->dma_paddr,
2319 BUS_DMA_WAITOK);
2320 if (error) {
2321 device_printf(dev, "%s: bus_dmamap_load failed; error %u\n",
2322 __func__, error);
2323 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2324 goto fail;
2325 }
2326
2327 return 0;
2328 fail:
2329 bus_dma_tag_destroy(dma->dma_tag);
2330 dma->dma_tag = NULL;
2331 return error;
2332 }
2333
2334 static void
2335 em_dma_free(struct adapter *adapter, struct em_dma_alloc *dma)
2336 {
2337 if (dma->dma_tag != NULL) {
2338 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2339 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
2340 bus_dma_tag_destroy(dma->dma_tag);
2341 dma->dma_tag = NULL;
2342 }
2343 }
2344
2345 /*********************************************************************
2346 *
2347 * Allocate and initialize transmit structures.
2348 *
2349 **********************************************************************/
2350 static int
2351 em_setup_transmit_structures(struct adapter *adapter)
2352 {
2353 struct em_buffer *tx_buffer;
2354 bus_size_t size;
2355 int error, i;
2356
2357 /*
2358 * Setup DMA descriptor areas.
2359 */
2360 size = roundup2(adapter->hw.max_frame_size, MCLBYTES);
2361 if (bus_dma_tag_create(NULL, /* parent */
2362 1, 0, /* alignment, bounds */
2363 BUS_SPACE_MAXADDR, /* lowaddr */
2364 BUS_SPACE_MAXADDR, /* highaddr */
2365 NULL, NULL, /* filter, filterarg */
2366 size, /* maxsize */
2367 EM_MAX_SCATTER, /* nsegments */
2368 size, /* maxsegsize */
2369 0, /* flags */
2370 &adapter->txtag)) {
2371 device_printf(adapter->dev, "Unable to allocate TX DMA tag\n");
2372 return(ENOMEM);
2373 }
2374
2375 adapter->tx_buffer_area =
2376 kmalloc(sizeof(struct em_buffer) * adapter->num_tx_desc,
2377 M_DEVBUF, M_WAITOK | M_ZERO);
2378
2379 bzero(adapter->tx_desc_base,
2380 sizeof(struct em_tx_desc) * adapter->num_tx_desc);
2381 tx_buffer = adapter->tx_buffer_area;
2382 for (i = 0; i < adapter->num_tx_desc; i++) {
2383 error = bus_dmamap_create(adapter->txtag, 0, &tx_buffer->map);
2384 if (error) {
2385 device_printf(adapter->dev,
2386 "Unable to create TX DMA map\n");
2387 goto fail;
2388 }
2389 tx_buffer++;
2390 }
2391
2392 adapter->next_avail_tx_desc = 0;
2393 adapter->next_tx_to_clean = 0;
2394
2395 /* Set number of descriptors available */
2396 adapter->num_tx_desc_avail = adapter->num_tx_desc;
2397
2398 /* Set checksum context */
2399 adapter->active_checksum_context = OFFLOAD_NONE;
2400
2401 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2402 BUS_DMASYNC_PREWRITE);
2403
2404 return (0);
2405 fail:
2406 em_free_transmit_structures(adapter);
2407 return (error);
2408 }
2409
2410 /*********************************************************************
2411 *
2412 * Enable transmit unit.
2413 *
2414 **********************************************************************/
2415 static void
2416 em_initialize_transmit_unit(struct adapter *adapter)
2417 {
2418 uint32_t reg_tctl;
2419 uint32_t reg_tipg = 0;
2420 uint64_t bus_addr;
2421
2422 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2423
2424 /* Setup the Base and Length of the Tx Descriptor Ring */
2425 bus_addr = adapter->txdma.dma_paddr;
2426 E1000_WRITE_REG(&adapter->hw, TDLEN,
2427 adapter->num_tx_desc * sizeof(struct em_tx_desc));
2428 E1000_WRITE_REG(&adapter->hw, TDBAH, (uint32_t)(bus_addr >> 32));
2429 E1000_WRITE_REG(&adapter->hw, TDBAL, (uint32_t)bus_addr);
2430
2431 /* Setup the HW Tx Head and Tail descriptor pointers */
2432 E1000_WRITE_REG(&adapter->hw, TDT, 0);
2433 E1000_WRITE_REG(&adapter->hw, TDH, 0);
2434
2435 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2436 E1000_READ_REG(&adapter->hw, TDBAL),
2437 E1000_READ_REG(&adapter->hw, TDLEN));
2438
2439 /* Set the default values for the Tx Inter Packet Gap timer */
2440 switch (adapter->hw.mac_type) {
2441 case em_82542_rev2_0:
2442 case em_82542_rev2_1:
2443 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2444 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2445 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2446 break;
2447 case em_80003es2lan:
2448 reg_tipg = DEFAULT_82543_TIPG_IPGR1;
2449 reg_tipg |=
2450 DEFAULT_80003ES2LAN_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2451 break;
2452 default:
2453 if (adapter->hw.media_type == em_media_type_fiber ||
2454 adapter->hw.media_type == em_media_type_internal_serdes)
2455 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2456 else
2457 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2458 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2459 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2460 }
2461
2462 E1000_WRITE_REG(&adapter->hw, TIPG, reg_tipg);
2463 E1000_WRITE_REG(&adapter->hw, TIDV, adapter->tx_int_delay.value);
2464 if (adapter->hw.mac_type >= em_82540) {
2465 E1000_WRITE_REG(&adapter->hw, TADV,
2466 adapter->tx_abs_int_delay.value);
2467 }
2468
2469 /* Program the Transmit Control Register */
2470 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
2471 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2472 if (adapter->hw.mac_type >= em_82571)
2473 reg_tctl |= E1000_TCTL_MULR;
2474 if (adapter->link_duplex == 1)
2475 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2476 else
2477 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2478
2479 /* This write will effectively turn on the transmit unit. */
2480 E1000_WRITE_REG(&adapter->hw, TCTL, reg_tctl);
2481
2482 /* Setup Transmit Descriptor Base Settings */
2483 adapter->txd_cmd = E1000_TXD_CMD_IFCS;
2484
2485 if (adapter->tx_int_delay.value > 0)
2486 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2487 }
2488
2489 /*********************************************************************
2490 *
2491 * Free all transmit related data structures.
2492 *
2493 **********************************************************************/
2494 static void
2495 em_free_transmit_structures(struct adapter *adapter)
2496 {
2497 struct em_buffer *tx_buffer;
2498 int i;
2499
2500 INIT_DEBUGOUT("free_transmit_structures: begin");
2501
2502 if (adapter->tx_buffer_area != NULL) {
2503 tx_buffer = adapter->tx_buffer_area;
2504 for (i = 0; i < adapter->num_tx_desc; i++, tx_buffer++) {
2505 if (tx_buffer->m_head != NULL) {
2506 bus_dmamap_unload(adapter->txtag,
2507 tx_buffer->map);
2508 m_freem(tx_buffer->m_head);
2509 }
2510
2511 if (tx_buffer->map != NULL) {
2512 bus_dmamap_destroy(adapter->txtag, tx_buffer->map);
2513 tx_buffer->map = NULL;
2514 }
2515 tx_buffer->m_head = NULL;
2516 }
2517 }
2518 if (adapter->tx_buffer_area != NULL) {
2519 kfree(adapter->tx_buffer_area, M_DEVBUF);
2520 adapter->tx_buffer_area = NULL;
2521 }
2522 if (adapter->txtag != NULL) {
2523 bus_dma_tag_destroy(adapter->txtag);
2524 adapter->txtag = NULL;
2525 }
2526 }
2527
2528 /*********************************************************************
2529 *
2530 * The offload context needs to be set when we transfer the first
2531 * packet of a particular protocol (TCP/UDP). We change the
2532 * context only if the protocol type changes.
2533 *
2534 **********************************************************************/
2535 static void
2536 em_transmit_checksum_setup(struct adapter *adapter,
2537 struct mbuf *mp,
2538 uint32_t *txd_upper,
2539 uint32_t *txd_lower)
2540 {
2541 struct em_context_desc *TXD;
2542 struct em_buffer *tx_buffer;
2543 int curr_txd;
2544
2545 if (mp->m_pkthdr.csum_flags) {
2546 if (mp->m_pkthdr.csum_flags & CSUM_TCP) {
2547 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2548 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2549 if (adapter->active_checksum_context == OFFLOAD_TCP_IP)
2550 return;
2551 else
2552 adapter->active_checksum_context = OFFLOAD_TCP_IP;
2553 } else if (mp->m_pkthdr.csum_flags & CSUM_UDP) {
2554 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2555 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2556 if (adapter->active_checksum_context == OFFLOAD_UDP_IP)
2557 return;
2558 else
2559 adapter->active_checksum_context = OFFLOAD_UDP_IP;
2560 } else {
2561 *txd_upper = 0;
2562 *txd_lower = 0;
2563 return;
2564 }
2565 } else {
2566 *txd_upper = 0;
2567 *txd_lower = 0;
2568 return;
2569 }
2570
2571 /*
2572 * If we reach this point, the checksum offload context
2573 * needs to be reset.
2574 */
2575 curr_txd = adapter->next_avail_tx_desc;
2576 tx_buffer = &adapter->tx_buffer_area[curr_txd];
2577 TXD = (struct em_context_desc *) &adapter->tx_desc_base[curr_txd];
2578
2579 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
2580 TXD->lower_setup.ip_fields.ipcso =
2581 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
2582 TXD->lower_setup.ip_fields.ipcse =
2583 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1);
2584
2585 TXD->upper_setup.tcp_fields.tucss =
2586 ETHER_HDR_LEN + sizeof(struct ip);
2587 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2588
2589 if (adapter->active_checksum_context == OFFLOAD_TCP_IP) {
2590 TXD->upper_setup.tcp_fields.tucso =
2591 ETHER_HDR_LEN + sizeof(struct ip) +
2592 offsetof(struct tcphdr, th_sum);
2593 } else if (adapter->active_checksum_context == OFFLOAD_UDP_IP) {
2594 TXD->upper_setup.tcp_fields.tucso =
2595 ETHER_HDR_LEN + sizeof(struct ip) +
2596 offsetof(struct udphdr, uh_sum);
2597 }
2598
2599 TXD->tcp_seg_setup.data = htole32(0);
2600 TXD->cmd_and_length = htole32(adapter->txd_cmd | E1000_TXD_CMD_DEXT);
2601
2602 tx_buffer->m_head = NULL;
2603 tx_buffer->next_eop = -1;
2604
2605 if (++curr_txd == adapter->num_tx_desc)
2606 curr_txd = 0;
2607
2608 adapter->num_tx_desc_avail--;
2609 adapter->next_avail_tx_desc = curr_txd;
2610 }
2611
2612 /**********************************************************************
2613 *
2614 * Examine each tx_buffer in the used queue. If the hardware is done
2615 * processing the packet then free associated resources. The
2616 * tx_buffer is put back on the free queue.
2617 *
2618 **********************************************************************/
2619
2620 static void
2621 em_txeof(struct adapter *adapter)
2622 {
2623 int first, last, done, num_avail;
2624 struct em_buffer *tx_buffer;
2625 struct em_tx_desc *tx_desc, *eop_desc;
2626 struct ifnet *ifp = &adapter->interface_data.ac_if;
2627
2628 if (adapter->num_tx_desc_avail == adapter->num_tx_desc)
2629 return;
2630
2631 num_avail = adapter->num_tx_desc_avail;
2632 first = adapter->next_tx_to_clean;
2633 tx_desc = &adapter->tx_desc_base[first];
2634 tx_buffer = &adapter->tx_buffer_area[first];
2635 last = tx_buffer->next_eop;
2636 KKASSERT(last >= 0 && last < adapter->num_tx_desc);
2637 eop_desc = &adapter->tx_desc_base[last];
2638
2639 /*
2640 * Now caculate the terminating index for the cleanup loop below
2641 */
2642 if (++last == adapter->num_tx_desc)
2643 last = 0;
2644 done = last;
2645
2646 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2647 BUS_DMASYNC_POSTREAD);
2648
2649 while (eop_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2650 while (first != done) {
2651 tx_desc->upper.data = 0;
2652 tx_desc->lower.data = 0;
2653 num_avail++;
2654
2655 logif(pkt_txclean);
2656
2657 if (tx_buffer->m_head) {
2658 ifp->if_opackets++;
2659 bus_dmamap_sync(adapter->txtag, tx_buffer->map,
2660 BUS_DMASYNC_POSTWRITE);
2661 bus_dmamap_unload(adapter->txtag,
2662 tx_buffer->map);
2663
2664 m_freem(tx_buffer->m_head);
2665 tx_buffer->m_head = NULL;
2666 }
2667 tx_buffer->next_eop = -1;
2668
2669 if (++first == adapter->num_tx_desc)
2670 first = 0;
2671
2672 tx_buffer = &adapter->tx_buffer_area[first];
2673 tx_desc = &adapter->tx_desc_base[first];
2674 }
2675 /* See if we can continue to the next packet */
2676 last = tx_buffer->next_eop;
2677 if (last != -1) {
2678 KKASSERT(last >= 0 && last < adapter->num_tx_desc);
2679 eop_desc = &adapter->tx_desc_base[last];
2680 if (++last == adapter->num_tx_desc)
2681 last = 0;
2682 done = last;
2683 } else {
2684 break;
2685 }
2686 }
2687
2688 bus_dmamap_sync(adapter->txdma.dma_tag, adapter->txdma.dma_map,
2689 BUS_DMASYNC_PREWRITE);
2690
2691 adapter->next_tx_to_clean = first;
2692
2693 /*
2694 * If we have enough room, clear IFF_OACTIVE to tell the stack
2695 * that it is OK to send packets.
2696 * If there are no pending descriptors, clear the timeout. Otherwise,
2697 * if some descriptors have been freed, restart the timeout.
2698 */
2699 if (num_avail > EM_TX_CLEANUP_THRESHOLD) {
2700 ifp->if_flags &= ~IFF_OACTIVE;
2701 if (num_avail == adapter->num_tx_desc)
2702 ifp->if_timer = 0;
2703 else if (num_avail == adapter->num_tx_desc_avail)
2704 ifp->if_timer = EM_TX_TIMEOUT;
2705 }
2706 adapter->num_tx_desc_avail = num_avail;
2707 }
2708
2709 /*********************************************************************
2710 *
2711 * Get a buffer from system mbuf buffer pool.
2712 *
2713 **********************************************************************/
2714 static int
2715 em_get_buf(int i, struct adapter *adapter, struct mbuf *nmp, int how)
2716 {
2717 struct mbuf *mp = nmp;
2718 struct em_buffer *rx_buffer;
2719 struct ifnet *ifp;
2720 bus_addr_t paddr;
2721 int error;
2722
2723 ifp = &adapter->interface_data.ac_if;
2724
2725 if (mp == NULL) {
2726 mp = m_getcl(how, MT_DATA, M_PKTHDR);
2727 if (mp == NULL) {
2728 adapter->mbuf_cluster_failed++;
2729 return (ENOBUFS);
2730 }
2731 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2732 } else {
2733 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2734 mp->m_data = mp->m_ext.ext_buf;
2735 mp->m_next = NULL;
2736 }
2737
2738 if (ifp->if_mtu <= ETHERMTU)
2739 m_adj(mp, ETHER_ALIGN);
2740
2741 rx_buffer = &adapter->rx_buffer_area[i];
2742
2743 /*
2744 * Using memory from the mbuf cluster pool, invoke the
2745 * bus_dma machinery to arrange the memory mapping.
2746 */
2747 error = bus_dmamap_load(adapter->rxtag, rx_buffer->map,
2748 mtod(mp, void *), mp->m_len,
2749 em_dmamap_cb, &paddr, 0);
2750 if (error) {
2751 m_freem(mp);
2752 return (error);
2753 }
2754 rx_buffer->m_head = mp;
2755 adapter->rx_desc_base[i].buffer_addr = htole64(paddr);
2756 bus_dmamap_sync(adapter->rxtag, rx_buffer->map, BUS_DMASYNC_PREREAD);
2757
2758 return (0);
2759 }
2760
2761 /*********************************************************************
2762 *
2763 * Allocate memory for rx_buffer structures. Since we use one
2764 * rx_buffer per received packet, the maximum number of rx_buffer's
2765 * that we'll need is equal to the number of receive descriptors
2766 * that we've allocated.
2767 *
2768 **********************************************************************/
2769 static int
2770 em_allocate_receive_structures(struct adapter *adapter)
2771 {
2772 int i, error, size;
2773 struct em_buffer *rx_buffer;
2774
2775 size = adapter->num_rx_desc * sizeof(struct em_buffer);
2776 adapter->rx_buffer_area = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
2777
2778 error = bus_dma_tag_create(NULL, /* parent */
2779 1, 0, /* alignment, bounds */
2780 BUS_SPACE_MAXADDR, /* lowaddr */
2781 BUS_SPACE_MAXADDR, /* highaddr */
2782 NULL, NULL, /* filter, filterarg */
2783 MCLBYTES, /* maxsize */
2784 1, /* nsegments */
2785 MCLBYTES, /* maxsegsize */
2786 0, /* flags */
2787 &adapter->rxtag);
2788 if (error) {
2789 device_printf(adapter->dev, "%s: bus_dma_tag_create failed; "
2790 "error %u\n", __func__, error);
2791 goto fail;
2792 }
2793
2794 rx_buffer = adapter->rx_buffer_area;
2795 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2796 error = bus_dmamap_create(adapter->rxtag, BUS_DMA_NOWAIT,
2797 &rx_buffer->map);
2798 if (error) {
2799 device_printf(adapter->dev,
2800 "%s: bus_dmamap_create failed; "
2801 "error %u\n", __func__, error);
2802 goto fail;
2803 }
2804 }
2805
2806 for (i = 0; i < adapter->num_rx_desc; i++) {
2807 error = em_get_buf(i, adapter, NULL, MB_DONTWAIT);
2808 if (error)
2809 goto fail;
2810 }
2811
2812 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
2813 BUS_DMASYNC_PREWRITE);
2814
2815 return (0);
2816 fail:
2817 em_free_receive_structures(adapter);
2818 return (error);
2819 }
2820
2821 /*********************************************************************
2822 *
2823 * Allocate and initialize receive structures.
2824 *
2825 **********************************************************************/
2826 static int
2827 em_setup_receive_structures(struct adapter *adapter)
2828 {
2829 int error;
2830
2831 bzero(adapter->rx_desc_base,
2832 sizeof(struct em_rx_desc) * adapter->num_rx_desc);
2833
2834 error = em_allocate_receive_structures(adapter);
2835 if (error)
2836 return (error);
2837
2838 /* Setup our descriptor pointers */
2839 adapter->next_rx_desc_to_check = 0;
2840
2841 return (0);
2842 }
2843
2844 /*********************************************************************
2845 *
2846 * Enable receive unit.
2847 *
2848 **********************************************************************/
2849 static void
2850 em_initialize_receive_unit(struct adapter *adapter)
2851 {
2852 uint32_t reg_rctl;
2853 uint32_t reg_rxcsum;
2854 struct ifnet *ifp;
2855 uint64_t bus_addr;
2856
2857 INIT_DEBUGOUT("em_initialize_receive_unit: begin");
2858
2859 ifp = &adapter->interface_data.ac_if;
2860
2861 /*
2862 * Make sure receives are disabled while setting
2863 * up the descriptor ring
2864 */
2865 E1000_WRITE_REG(&adapter->hw, RCTL, 0);
2866
2867 /* Set the Receive Delay Timer Register */
2868 E1000_WRITE_REG(&adapter->hw, RDTR,
2869 adapter->rx_int_delay.value | E1000_RDT_FPDB);
2870
2871 if(adapter->hw.mac_type >= em_82540) {
2872 E1000_WRITE_REG(&adapter->hw, RADV,
2873 adapter->rx_abs_int_delay.value);
2874
2875 /* Set the interrupt throttling rate in 256ns increments */
2876 if (em_int_throttle_ceil) {
2877 E1000_WRITE_REG(&adapter->hw, ITR,
2878 1000000000 / 256 / em_int_throttle_ceil);
2879 } else {
2880 E1000_WRITE_REG(&adapter->hw, ITR, 0);
2881 }
2882 }
2883
2884 /* Setup the Base and Length of the Rx Descriptor Ring */
2885 bus_addr = adapter->rxdma.dma_paddr;
2886 E1000_WRITE_REG(&adapter->hw, RDLEN, adapter->num_rx_desc *
2887 sizeof(struct em_rx_desc));
2888 E1000_WRITE_REG(&adapter->hw, RDBAH, (uint32_t)(bus_addr >> 32));
2889 E1000_WRITE_REG(&adapter->hw, RDBAL, (uint32_t)bus_addr);
2890
2891 /* Setup the Receive Control Register */
2892 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2893 E1000_RCTL_RDMTS_HALF |
2894 (adapter->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
2895
2896 if (adapter->hw.tbi_compatibility_on == TRUE)
2897 reg_rctl |= E1000_RCTL_SBP;
2898
2899 switch (adapter->rx_buffer_len) {
2900 default:
2901 case EM_RXBUFFER_2048:
2902 reg_rctl |= E1000_RCTL_SZ_2048;
2903 break;
2904 case EM_RXBUFFER_4096:
2905 reg_rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX |
2906 E1000_RCTL_LPE;
2907 break;
2908 case EM_RXBUFFER_8192:
2909 reg_rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX |
2910 E1000_RCTL_LPE;
2911 break;
2912 case EM_RXBUFFER_16384:
2913 reg_rctl |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX |
2914 E1000_RCTL_LPE;
2915 break;
2916 }
2917
2918 if (ifp->if_mtu > ETHERMTU)
2919 reg_rctl |= E1000_RCTL_LPE;
2920
2921 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
2922 if ((adapter->hw.mac_type >= em_82543) &&
2923 (ifp->if_capenable & IFCAP_RXCSUM)) {
2924 reg_rxcsum = E1000_READ_REG(&adapter->hw, RXCSUM);
2925 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
2926 E1000_WRITE_REG(&adapter->hw, RXCSUM, reg_rxcsum);
2927 }
2928
2929 #ifdef EM_X60_WORKAROUND
2930 if (adapter->hw.mac_type == em_82573)
2931 E1000_WRITE_REG(&adapter->hw, RDTR, 32);
2932 #endif
2933
2934 /* Enable Receives */
2935 E1000_WRITE_REG(&adapter->hw, RCTL, reg_rctl);
2936
2937 /* Setup the HW Rx Head and Tail Descriptor Pointers */
2938 E1000_WRITE_REG(&adapter->hw, RDH, 0);
2939 E1000_WRITE_REG(&adapter->hw, RDT, adapter->num_rx_desc - 1);
2940 }
2941
2942 /*********************************************************************
2943 *
2944 * Free receive related data structures.
2945 *
2946 **********************************************************************/
2947 static void
2948 em_free_receive_structures(struct adapter *adapter)
2949 {
2950 struct em_buffer *rx_buffer;
2951 int i;
2952
2953 INIT_DEBUGOUT("free_receive_structures: begin");
2954
2955 if (adapter->rx_buffer_area != NULL) {
2956 rx_buffer = adapter->rx_buffer_area;
2957 for (i = 0; i < adapter->num_rx_desc; i++, rx_buffer++) {
2958 if (rx_buffer->m_head != NULL) {
2959 bus_dmamap_unload(adapter->rxtag,
2960 rx_buffer->map);
2961 m_freem(rx_buffer->m_head);
2962 rx_buffer->m_head = NULL;
2963 }
2964 if (rx_buffer->map != NULL) {
2965 bus_dmamap_destroy(adapter->rxtag,
2966 rx_buffer->map);
2967 rx_buffer->map = NULL;
2968 }
2969 }
2970 }
2971 if (adapter->rx_buffer_area != NULL) {
2972 kfree(adapter->rx_buffer_area, M_DEVBUF);
2973 adapter->rx_buffer_area = NULL;
2974 }
2975 if (adapter->rxtag != NULL) {
2976 bus_dma_tag_destroy(adapter->rxtag);
2977 adapter->rxtag = NULL;
2978 }
2979 }
2980
2981 /*********************************************************************
2982 *
2983 * This routine executes in interrupt context. It replenishes
2984 * the mbufs in the descriptor and sends data which has been
2985 * dma'ed into host memory to upper layer.
2986 *
2987 * We loop at most count times if count is > 0, or until done if
2988 * count < 0.
2989 *
2990 *********************************************************************/
2991 static void
2992 em_rxeof(struct adapter *adapter, int count)
2993 {
2994 struct ifnet *ifp;
2995 struct mbuf *mp;
2996 uint8_t accept_frame = 0;
2997 uint8_t eop = 0;
2998 uint16_t len, desc_len, prev_len_adj;
2999 int i;
3000 #ifdef ETHER_INPUT_CHAIN
3001 struct mbuf_chain chain[MAXCPU];
3002 int j;
3003 #endif
3004
3005 /* Pointer to the receive descriptor being examined. */
3006 struct em_rx_desc *current_desc;
3007
3008 ifp = &adapter->interface_data.ac_if;
3009 i = adapter->next_rx_desc_to_check;
3010 current_desc = &adapter->rx_desc_base[i];
3011
3012 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3013 BUS_DMASYNC_POSTREAD);
3014
3015 if (!(current_desc->status & E1000_RXD_STAT_DD))
3016 return;
3017
3018 #ifdef ETHER_INPUT_CHAIN
3019 for (j = 0; j < ncpus; ++j)
3020 chain[j].mc_head = chain[j].mc_tail = NULL;
3021 #endif
3022
3023 while ((current_desc->status & E1000_RXD_STAT_DD) && count != 0) {
3024 logif(pkt_receive);
3025 mp = adapter->rx_buffer_area[i].m_head;
3026 bus_dmamap_sync(adapter->rxtag, adapter->rx_buffer_area[i].map,
3027 BUS_DMASYNC_POSTREAD);
3028 bus_dmamap_unload(adapter->rxtag,
3029 adapter->rx_buffer_area[i].map);
3030
3031 accept_frame = 1;
3032 prev_len_adj = 0;
3033 desc_len = le16toh(current_desc->length);
3034 if (current_desc->status & E1000_RXD_STAT_EOP) {
3035 count--;
3036 eop = 1;
3037 if (desc_len < ETHER_CRC_LEN) {
3038 len = 0;
3039 prev_len_adj = ETHER_CRC_LEN - desc_len;
3040 } else {
3041 len = desc_len - ETHER_CRC_LEN;
3042 }
3043 } else {
3044 eop = 0;
3045 len = desc_len;
3046 }
3047
3048 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3049 uint8_t last_byte;
3050 uint32_t pkt_len = desc_len;
3051
3052 if (adapter->fmp != NULL)
3053 pkt_len += adapter->fmp->m_pkthdr.len;
3054
3055 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3056
3057 if (TBI_ACCEPT(&adapter->hw, current_desc->status,
3058 current_desc->errors,
3059 pkt_len, last_byte)) {
3060 em_tbi_adjust_stats(&adapter->hw,
3061 &adapter->stats,
3062 pkt_len,
3063 adapter->hw.mac_addr);
3064 if (len > 0)
3065 len--;
3066 } else {
3067 accept_frame = 0;
3068 }
3069 }
3070
3071 if (accept_frame) {
3072 if (em_get_buf(i, adapter, NULL, MB_DONTWAIT) == ENOBUFS) {
3073 adapter->dropped_pkts++;
3074 em_get_buf(i, adapter, mp, MB_DONTWAIT);
3075 if (adapter->fmp != NULL)
3076 m_freem(adapter->fmp);
3077 adapter->fmp = NULL;
3078 adapter->lmp = NULL;
3079 goto skip;
3080 }
3081
3082 /* Assign correct length to the current fragment */
3083 mp->m_len = len;
3084
3085 if (adapter->fmp == NULL) {
3086 mp->m_pkthdr.len = len;
3087 adapter->fmp = mp; /* Store the first mbuf */
3088 adapter->lmp = mp;
3089 } else {
3090 /* Chain mbuf's together */
3091 /*
3092 * Adjust length of previous mbuf in chain if
3093 * we received less than 4 bytes in the last
3094 * descriptor.
3095 */
3096 if (prev_len_adj > 0) {
3097 adapter->lmp->m_len -= prev_len_adj;
3098 adapter->fmp->m_pkthdr.len -= prev_len_adj;
3099 }
3100 adapter->lmp->m_next = mp;
3101 adapter->lmp = adapter->lmp->m_next;
3102 adapter->fmp->m_pkthdr.len += len;
3103 }
3104
3105 if (eop) {
3106 adapter->fmp->m_pkthdr.rcvif = ifp;
3107 ifp->if_ipackets++;
3108
3109 em_receive_checksum(adapter, current_desc,
3110 adapter->fmp);
3111 if (current_desc->status & E1000_RXD_STAT_VP) {
3112 VLAN_INPUT_TAG(adapter->fmp,
3113 (current_desc->special &
3114 E1000_RXD_SPC_VLAN_MASK));
3115 } else {
3116 #ifdef ETHER_INPUT_CHAIN
3117 ether_input_chain(ifp, adapter->fmp,
3118 chain);
3119 #else
3120 ifp->if_input(ifp, adapter->fmp);
3121 #endif
3122 }
3123 adapter->fmp = NULL;
3124 adapter->lmp = NULL;
3125 }
3126 } else {
3127 adapter->dropped_pkts++;
3128 em_get_buf(i, adapter, mp, MB_DONTWAIT);
3129 if (adapter->fmp != NULL)
3130 m_freem(adapter->fmp);
3131 adapter->fmp = NULL;
3132 adapter->lmp = NULL;
3133 }
3134
3135 skip:
3136 /* Zero out the receive descriptors status. */
3137 current_desc->status = 0;
3138
3139 /* Advance our pointers to the next descriptor. */
3140 if (++i == adapter->num_rx_desc) {
3141 i = 0;
3142 current_desc = adapter->rx_desc_base;
3143 } else {
3144 current_desc++;
3145 }
3146 }
3147
3148 #ifdef ETHER_INPUT_CHAIN
3149 ether_input_dispatch(chain);
3150 #endif
3151
3152 bus_dmamap_sync(adapter->rxdma.dma_tag, adapter->rxdma.dma_map,
3153 BUS_DMASYNC_PREWRITE);
3154
3155 adapter->next_rx_desc_to_check = i;
3156
3157 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3158 if (--i < 0)
3159 i = adapter->num_rx_desc - 1;
3160
3161 E1000_WRITE_REG(&adapter->hw, RDT, i);
3162 }
3163
3164 /*********************************************************************
3165 *
3166 * Verify that the hardware indicated that the checksum is valid.
3167 * Inform the stack about the status of checksum so that stack
3168 * doesn't spend time verifying the checksum.
3169 *
3170 *********************************************************************/
3171 static void
3172 em_receive_checksum(struct adapter *adapter,
3173 struct em_rx_desc *rx_desc,
3174 struct mbuf *mp)
3175 {
3176 /* 82543 or newer only */
3177 if ((adapter->hw.mac_type < em_82543) ||
3178 /* Ignore Checksum bit is set */
3179 (rx_desc->status & E1000_RXD_STAT_IXSM)) {
3180 mp->m_pkthdr.csum_flags = 0;
3181 return;
3182 }
3183
3184 if (rx_desc->status & E1000_RXD_STAT_IPCS) {
3185 /* Did it pass? */
3186 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3187 /* IP Checksum Good */
3188 mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
3189 mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3190 } else {
3191 mp->m_pkthdr.csum_flags = 0;
3192 }
3193 }
3194
3195 if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
3196 /* Did it pass? */
3197 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3198 mp->m_pkthdr.csum_flags |=
3199 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR |
3200 CSUM_FRAG_NOT_CHECKED);
3201 mp->m_pkthdr.csum_data = htons(0xffff);
3202 }
3203 }
3204 }
3205
3206
3207 static void
3208 em_enable_vlans(struct adapter *adapter)
3209 {
3210 uint32_t ctrl;
3211
3212 E1000_WRITE_REG(&adapter->hw, VET, ETHERTYPE_VLAN);
3213
3214 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3215 ctrl |= E1000_CTRL_VME;
3216 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3217 }
3218
3219 static void
3220 em_disable_vlans(struct adapter *adapter)
3221 {
3222 uint32_t ctrl;
3223
3224 ctrl = E1000_READ_REG(&adapter->hw, CTRL);
3225 ctrl &= ~E1000_CTRL_VME;
3226 E1000_WRITE_REG(&adapter->hw, CTRL, ctrl);
3227 }
3228
3229 /*
3230 * note: we must call bus_enable_intr() prior to enabling the hardware
3231 * interrupt and bus_disable_intr() after disabling the hardware interrupt
3232 * in order to avoid handler execution races from scheduled interrupt
3233 * threads.
3234 */
3235 static void
3236 em_enable_intr(struct adapter *adapter)
3237 {
3238 struct ifnet *ifp = &adapter->interface_data.ac_if;
3239
3240 if ((ifp->if_flags & IFF_POLLING) == 0) {
3241 lwkt_serialize_handler_enable(ifp->if_serializer);
3242 E1000_WRITE_REG(&adapter->hw, IMS, (IMS_ENABLE_MASK));
3243 }
3244 }
3245
3246 static void
3247 em_disable_intr(struct adapter *adapter)
3248 {
3249 /*
3250 * The first version of 82542 had an errata where when link was forced
3251 * it would stay up even up even if the cable was disconnected.
3252 * Sequence errors were used to detect the disconnect and then the
3253 * driver would unforce the link. This code in the in the ISR. For
3254 * this to work correctly the Sequence error interrupt had to be
3255 * enabled all the time.
3256 */
3257 if (adapter->hw.mac_type == em_82542_rev2_0) {
3258 E1000_WRITE_REG(&adapter->hw, IMC,
3259 (0xffffffff & ~E1000_IMC_RXSEQ));
3260 } else {
3261 E1000_WRITE_REG(&adapter->hw, IMC, 0xffffffff);
3262 }
3263
3264 lwkt_serialize_handler_disable(adapter->interface_data.ac_if.if_serializer);
3265 }
3266
3267 static int
3268 em_is_valid_ether_addr(uint8_t *addr)
3269 {
3270 static const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3271
3272 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3273 return (FALSE);
3274 else
3275 return (TRUE);
3276 }
3277
3278 void
3279 em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3280 {
3281 pci_write_config(((struct em_osdep *)hw->back)->dev, reg, *value, 2);
3282 }
3283
3284 void
3285 em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3286 {
3287 *value = pci_read_config(((struct em_osdep *)hw->back)->dev, reg, 2);
3288 }
3289
3290 void
3291 em_pci_set_mwi(struct em_hw *hw)
3292 {
3293 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3294 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE), 2);
3295 }
3296
3297 void
3298 em_pci_clear_mwi(struct em_hw *hw)
3299 {
3300 pci_write_config(((struct em_osdep *)hw->back)->dev, PCIR_COMMAND,
3301 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE), 2);
3302 }
3303
3304 uint32_t
3305 em_io_read(struct em_hw *hw, unsigned long port)
3306 {
3307 struct em_osdep *io = hw->back;
3308
3309 return bus_space_read_4(io->io_bus_space_tag,
3310 io->io_bus_space_handle, port);
3311 }
3312
3313 void
3314 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value)
3315 {
3316 struct em_osdep *io = hw->back;
3317
3318 bus_space_write_4(io->io_bus_space_tag,
3319 io->io_bus_space_handle, port, value);
3320 }
3321
3322 /*
3323 * We may eventually really do this, but its unnecessary
3324 * for now so we just return unsupported.
3325 */
3326 int32_t
3327 em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value)
3328 {
3329 return (0);
3330 }
3331
3332
3333 /*********************************************************************
3334 * 82544 Coexistence issue workaround.
3335 * There are 2 issues.
3336 * 1. Transmit Hang issue.
3337 * To detect this issue, following equation can be used...
3338 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3339 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3340 *
3341 * 2. DAC issue.
3342 * To detect this issue, following equation can be used...
3343 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3344 * If SUM[3:0] is in between 9 to c, we will have this issue.
3345 *
3346 *
3347 * WORKAROUND:
3348 * Make sure we do not have ending address as 1,2,3,4(Hang) or
3349 * 9,a,b,c (DAC)
3350 *
3351 *************************************************************************/
3352 static uint32_t
3353 em_fill_descriptors(bus_addr_t address, uint32_t length, PDESC_ARRAY desc_array)
3354 {
3355 /* Since issue is sensitive to length and address.*/
3356 /* Let us first check the address...*/
3357 uint32_t safe_terminator;
3358 if (length <= 4) {
3359 desc_array->descriptor[0].address = address;
3360 desc_array->descriptor[0].length = length;
3361 desc_array->elements = 1;
3362 return (desc_array->elements);
3363 }
3364 safe_terminator = (uint32_t)((((uint32_t)address & 0x7) + (length & 0xF)) & 0xF);
3365 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3366 if (safe_terminator == 0 ||
3367 (safe_terminator > 4 && safe_terminator < 9) ||
3368 (safe_terminator > 0xC && safe_terminator <= 0xF)) {
3369 desc_array->descriptor[0].address = address;
3370 desc_array->descriptor[0].length = length;
3371 desc_array->elements = 1;
3372 return (desc_array->elements);
3373 }
3374
3375 desc_array->descriptor[0].address = address;
3376 desc_array->descriptor[0].length = length - 4;
3377 desc_array->descriptor[1].address = address + (length - 4);
3378 desc_array->descriptor[1].length = 4;
3379 desc_array->elements = 2;
3380 return (desc_array->elements);
3381 }
3382
3383 /**********************************************************************
3384 *
3385 * Update the board statistics counters.
3386 *
3387 **********************************************************************/
3388 static void
3389 em_update_stats_counters(struct adapter *adapter)
3390 {
3391 struct ifnet *ifp;
3392
3393 if (adapter->hw.media_type == em_media_type_copper ||
3394 (E1000_READ_REG(&adapter->hw, STATUS) & E1000_STATUS_LU)) {
3395 adapter->stats.symerrs += E1000_READ_REG(&adapter->hw, SYMERRS);
3396 adapter->stats.sec += E1000_READ_REG(&adapter->hw, SEC);
3397 }
3398 adapter->stats.crcerrs += E1000_READ_REG(&adapter->hw, CRCERRS);
3399 adapter->stats.mpc += E1000_READ_REG(&adapter->hw, MPC);
3400 adapter->stats.scc += E1000_READ_REG(&adapter->hw, SCC);
3401 adapter->stats.ecol += E1000_READ_REG(&adapter->hw, ECOL);
3402
3403 adapter->stats.mcc += E1000_READ_REG(&adapter->hw, MCC);
3404 adapter->stats.latecol += E1000_READ_REG(&adapter->hw, LATECOL);
3405 adapter->stats.colc += E1000_READ_REG(&adapter->hw, COLC);
3406 adapter->stats.dc += E1000_READ_REG(&adapter->hw, DC);
3407 adapter->stats.rlec += E1000_READ_REG(&adapter->hw, RLEC);
3408 adapter->stats.xonrxc += E1000_READ_REG(&adapter->hw, XONRXC);
3409 adapter->stats.xontxc += E1000_READ_REG(&adapter->hw, XONTXC);
3410 adapter->stats.xoffrxc += E1000_READ_REG(&adapter->hw, XOFFRXC);
3411 adapter->stats.xofftxc += E1000_READ_REG(&adapter->hw, XOFFTXC);
3412 adapter->stats.fcruc += E1000_READ_REG(&adapter->hw, FCRUC);
3413 adapter->stats.prc64 += E1000_READ_REG(&adapter->hw, PRC64);
3414 adapter->stats.prc127 += E1000_READ_REG(&adapter->hw, PRC127);
3415 adapter->stats.prc255 += E1000_READ_REG(&adapter->hw, PRC255);
3416 adapter->stats.prc511 += E1000_READ_REG(&adapter->hw, PRC511);
3417 adapter->stats.prc1023 += E1000_READ_REG(&adapter->hw, PRC1023);
3418 adapter->stats.prc1522 += E1000_READ_REG(&adapter->hw, PRC1522);
3419 adapter->stats.gprc += E1000_READ_REG(&adapter->hw, GPRC);
3420 adapter->stats.bprc += E1000_READ_REG(&adapter->hw, BPRC);
3421 adapter->stats.mprc += E1000_READ_REG(&adapter->hw, MPRC);
3422 adapter->stats.gptc += E1000_READ_REG(&adapter->hw, GPTC);
3423
3424 /* For the 64-bit byte counters the low dword must be read first. */
3425 /* Both registers clear on the read of the high dword */
3426
3427 adapter->stats.gorcl += E1000_READ_REG(&adapter->hw, GORCL);
3428 adapter->stats.gorch += E1000_READ_REG(&adapter->hw, GORCH);
3429 adapter->stats.gotcl += E1000_READ_REG(&adapter->hw, GOTCL);
3430 adapter->stats.gotch += E1000_READ_REG(&adapter->hw, GOTCH);
3431
3432 adapter->stats.rnbc += E1000_READ_REG(&adapter->hw, RNBC);
3433 adapter->stats.ruc += E1000_READ_REG(&adapter->hw, RUC);
3434 adapter->stats.rfc += E1000_READ_REG(&adapter->hw, RFC);
3435 adapter->stats.roc += E1000_READ_REG(&adapter->hw, ROC);
3436 adapter->stats.rjc += E1000_READ_REG(&adapter->hw, RJC);
3437
3438 adapter->stats.torl += E1000_READ_REG(&adapter->hw, TORL);
3439 adapter->stats.torh += E1000_READ_REG(&adapter->hw, TORH);
3440 adapter->stats.totl += E1000_READ_REG(&adapter->hw, TOTL);
3441 adapter->stats.toth += E1000_READ_REG(&adapter->hw, TOTH);
3442
3443 adapter->stats.tpr += E1000_READ_REG(&adapter->hw, TPR);
3444 adapter->stats.tpt += E1000_READ_REG(&adapter->hw, TPT);
3445 adapter->stats.ptc64 += E1000_READ_REG(&adapter->hw, PTC64);
3446 adapter->stats.ptc127 += E1000_READ_REG(&adapter->hw, PTC127);
3447 adapter->stats.ptc255 += E1000_READ_REG(&adapter->hw, PTC255);
3448 adapter->stats.ptc511 += E1000_READ_REG(&adapter->hw, PTC511);
3449 adapter->stats.ptc1023 += E1000_READ_REG(&adapter->hw, PTC1023);
3450 adapter->stats.ptc1522 += E1000_READ_REG(&adapter->hw, PTC1522);
3451 adapter->stats.mptc += E1000_READ_REG(&adapter->hw, MPTC);
3452 adapter->stats.bptc += E1000_READ_REG(&adapter->hw, BPTC);
3453
3454 if (adapter->hw.mac_type >= em_82543) {
3455 adapter->stats.algnerrc +=
3456 E1000_READ_REG(&adapter->hw, ALGNERRC);
3457 adapter->stats.rxerrc +=
3458 E1000_READ_REG(&adapter->hw, RXERRC);
3459 adapter->stats.tncrs +=
3460 E1000_READ_REG(&adapter->hw, TNCRS);
3461 adapter->stats.cexterr +=
3462 E1000_READ_REG(&adapter->hw, CEXTERR);
3463 adapter->stats.tsctc +=
3464 E1000_READ_REG(&adapter->hw, TSCTC);
3465 adapter->stats.tsctfc +=
3466 E1000_READ_REG(&adapter->hw, TSCTFC);
3467 }
3468 ifp = &adapter->interface_data.ac_if;
3469
3470 /* Fill out the OS statistics structure */
3471 ifp->if_collisions = adapter->stats.colc;
3472
3473 /* Rx Errors */
3474 ifp->if_ierrors =
3475 adapter->dropped_pkts +
3476 adapter->stats.rxerrc +
3477 adapter->stats.crcerrs +
3478 adapter->stats.algnerrc +
3479 adapter->stats.ruc + adapter->stats.roc +
3480 adapter->stats.mpc + adapter->stats.cexterr +
3481 adapter->rx_overruns;
3482
3483 /* Tx Errors */
3484 ifp->if_oerrors = adapter->stats.ecol + adapter->stats.latecol +
3485 adapter->watchdog_timeouts;
3486 }
3487
3488
3489 /**********************************************************************
3490 *
3491 * This routine is called only when em_display_debug_stats is enabled.
3492 * This routine provides a way to take a look at important statistics
3493 * maintained by the driver and hardware.
3494 *
3495 **********************************************************************/
3496 static void
3497 em_print_debug_info(struct adapter *adapter)
3498 {
3499 device_t dev= adapter->dev;
3500 uint8_t *hw_addr = adapter->hw.hw_addr;
3501
3502 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3503 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x\n",
3504 E1000_READ_REG(&adapter->hw, CTRL),
3505 E1000_READ_REG(&adapter->hw, RCTL));
3506 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk\n",
3507 ((E1000_READ_REG(&adapter->hw, PBA) & 0xffff0000) >> 16),
3508 (E1000_READ_REG(&adapter->hw, PBA) & 0xffff));
3509 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3510 adapter->hw.fc_high_water, adapter->hw.fc_low_water);
3511 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3512 E1000_READ_REG(&adapter->hw, TIDV),
3513 E1000_READ_REG(&adapter->hw, TADV));
3514 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3515 E1000_READ_REG(&adapter->hw, RDTR),
3516 E1000_READ_REG(&adapter->hw, RADV));
3517 device_printf(dev, "fifo workaround = %lld, fifo_reset_count = %lld\n",
3518 (long long)adapter->tx_fifo_wrk_cnt,
3519 (long long)adapter->tx_fifo_reset_cnt);
3520 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3521 E1000_READ_REG(&adapter->hw, TDH),
3522 E1000_READ_REG(&adapter->hw, TDT));
3523 device_printf(dev, "Num Tx descriptors avail = %d\n",
3524 adapter->num_tx_desc_avail);
3525 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3526 adapter->no_tx_desc_avail1);
3527 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3528 adapter->no_tx_desc_avail2);
3529 device_printf(dev, "Std mbuf failed = %ld\n",
3530 adapter->mbuf_alloc_failed);
3531 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3532 adapter->mbuf_cluster_failed);
3533 device_printf(dev, "Driver dropped packets = %ld\n",
3534 adapter->dropped_pkts);
3535 }
3536
3537 static void
3538 em_print_hw_stats(struct adapter *adapter)
3539 {
3540 device_t dev= adapter->dev;
3541
3542 device_printf(dev, "Excessive collisions = %lld\n",
3543 (long long)adapter->stats.ecol);
3544 device_printf(dev, "Symbol errors = %lld\n",
3545 (long long)adapter->stats.symerrs);
3546 device_printf(dev, "Sequence errors = %lld\n",
3547 (long long)adapter->stats.sec);
3548 device_printf(dev, "Defer count = %lld\n",
3549 (long long)adapter->stats.dc);
3550
3551 device_printf(dev, "Missed Packets = %lld\n",
3552 (long long)adapter->stats.mpc);
3553 device_printf(dev, "Receive No Buffers = %lld\n",
3554 (long long)adapter->stats.rnbc);
3555 /* RLEC is inaccurate on some hardware, calculate our own. */
3556 device_printf(dev, "Receive Length errors = %lld\n",
3557 (long long)adapter->stats.roc +
3558 (long long)adapter->stats.ruc);
3559 device_printf(dev, "Receive errors = %lld\n",
3560 (long long)adapter->stats.rxerrc);
3561 device_printf(dev, "Crc errors = %lld\n",
3562 (long long)adapter->stats.crcerrs);
3563 device_printf(dev, "Alignment errors = %lld\n",
3564 (long long)adapter->stats.algnerrc);
3565 device_printf(dev, "Carrier extension errors = %lld\n",
3566 (long long)adapter->stats.cexterr);
3567 device_printf(dev, "RX overruns = %lu\n", adapter->rx_overruns);
3568 device_printf(dev, "Watchdog timeouts = %lu\n",
3569 adapter->watchdog_timeouts);
3570
3571 device_printf(dev, "XON Rcvd = %lld\n",
3572 (long long)adapter->stats.xonrxc);
3573 device_printf(dev, "XON Xmtd = %lld\n",
3574 (long long)adapter->stats.xontxc);
3575 device_printf(dev, "XOFF Rcvd = %lld\n",
3576 (long long)adapter->stats.xoffrxc);
3577 device_printf(dev, "XOFF Xmtd = %lld\n",
3578 (long long)adapter->stats.xofftxc);
3579
3580 device_printf(dev, "Good Packets Rcvd = %lld\n",
3581 (long long)adapter->stats.gprc);
3582 device_printf(dev, "Good Packets Xmtd = %lld\n",
3583 (long long)adapter->stats.gptc);
3584 }
3585
3586 static int
3587 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3588 {
3589 int error;
3590 int result;
3591 struct adapter *adapter;
3592
3593 result = -1;
3594 error = sysctl_handle_int(oidp, &result, 0, req);
3595
3596 if (error || !req->newptr)
3597 return (error);
3598
3599 if (result == 1) {
3600 adapter = (struct adapter *)arg1;
3601 em_print_debug_info(adapter);
3602 }
3603
3604 return (error);
3605 }
3606
3607 static int
3608 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3609 {
3610 int error;
3611 int result;
3612 struct adapter *adapter;
3613
3614 result = -1;
3615 error = sysctl_handle_int(oidp, &result, 0, req);
3616
3617 if (error || !req->newptr)
3618 return (error);
3619
3620 if (result == 1) {
3621 adapter = (struct adapter *)arg1;
3622 em_print_hw_stats(adapter);
3623 }
3624
3625 return (error);
3626 }
3627
3628 static int
3629 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3630 {
3631 struct em_int_delay_info *info;
3632 struct adapter *adapter;
3633 uint32_t regval;
3634 int error;
3635 int usecs;
3636 int ticks;
3637
3638 info = (struct em_int_delay_info *)arg1;
3639 adapter = info->adapter;
3640 usecs = info->value;
3641 error = sysctl_handle_int(oidp, &usecs, 0, req);
3642 if (error != 0 || req->newptr == NULL)
3643 return (error);
3644 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535))
3645 return (EINVAL);
3646 info->value = usecs;
3647 ticks = E1000_USECS_TO_TICKS(usecs);
3648
3649 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3650 regval = E1000_READ_OFFSET(&adapter->hw, info->offset);
3651 regval = (regval & ~0xffff) | (ticks & 0xffff);
3652 /* Handle a few special cases. */
3653 switch (info->offset) {
3654 case E1000_RDTR:
3655 case E1000_82542_RDTR:
3656 regval |= E1000_RDT_FPDB;
3657 break;
3658 case E1000_TIDV:
3659 case E1000_82542_TIDV:
3660 if (ticks == 0) {
3661 adapter->txd_cmd &= ~E1000_TXD_CMD_IDE;
3662 /* Don't write 0 into the TIDV register. */
3663 regval++;
3664 } else
3665 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3666 break;
3667 }
3668 E1000_WRITE_OFFSET(&adapter->hw, info->offset, regval);
3669 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3670 return (0);
3671 }
3672
3673 static void
3674 em_add_int_delay_sysctl(struct adapter *adapter, const char *name,
3675 const char *description, struct em_int_delay_info *info,
3676 int offset, int value)
3677 {
3678 info->adapter = adapter;
3679 info->offset = offset;
3680 info->value = value;
3681 SYSCTL_ADD_PROC(&adapter->sysctl_ctx,
3682 SYSCTL_CHILDREN(adapter->sysctl_tree),
3683 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
3684 info, 0, em_sysctl_int_delay, "I", description);
3685 }
3686
3687 static int
3688 em_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3689 {
3690 struct adapter *adapter = (void *)arg1;
3691 int error;
3692 int throttle;
3693
3694 throttle = em_int_throttle_ceil;
3695 error = sysctl_handle_int(oidp, &throttle, 0, req);
3696 if (error || req->newptr == NULL)
3697 return error;
3698 if (throttle < 0 || throttle > 1000000000 / 256)
3699 return EINVAL;
3700 if (throttle) {
3701 /*
3702 * Set the interrupt throttling rate in 256ns increments,
3703 * recalculate sysctl value assignment to get exact frequency.
3704 */
3705 throttle = 1000000000 / 256 / throttle;
3706 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3707 em_int_throttle_ceil = 1000000000 / 256 / throttle;
3708 E1000_WRITE_REG(&adapter->hw, ITR, throttle);
3709 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3710 } else {
3711 lwkt_serialize_enter(adapter->interface_data.ac_if.if_serializer);
3712 em_int_throttle_ceil = 0;
3713 E1000_WRITE_REG(&adapter->hw, ITR, 0);
3714 lwkt_serialize_exit(adapter->interface_data.ac_if.if_serializer);
3715 }
3716 device_printf(adapter->dev, "Interrupt moderation set to %d/sec\n",
3717 em_int_throttle_ceil);
3718 return 0;
3719 }
Port diff from OpenBSD to DragonFly