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Import 2.3.10pre5
[davej-history.git] / drivers / net / de4x5.c
blobccd35038e020ada057dab6dbee42731c437170e7
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from
383 <Geert.Uytterhoeven@cs.kuleuven.ac.be>
384 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
385 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
386 **Incompatible with 2.0.x from here.**
387 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
388 from <lma@varesearch.com>
389 Add TP, AUI and BNC cases to 21140m_autoconf() for
390 case where a 21140 under SROM control uses, e.g. AUI
391 from problem report by <delchini@lpnp09.in2p3.fr>
392 Add MII parallel detection to 2114x_autoconf() for
393 case where no autonegotiation partner exists from
394 problem report by <mlapsley@ndirect.co.uk>.
395 Add ability to force connection type directly even
396 when using SROM control from problem report by
397 <earl@exis.net>.
398 Updated the PCI interface to conform with the latest
399 version. I hope nothing is broken...
400 Add TX done interrupt modification from suggestion
401 by <Austin.Donnelly@cl.cam.ac.uk>.
402 Fix is_anc_capable() bug reported by
403 <Austin.Donnelly@cl.cam.ac.uk>.
404 Fix type[13]_infoblock() bug: during MII search, PHY
405 lp->rst not run because lp->ibn not initialised -
406 from report & fix by <paubert@iram.es>.
407 Fix probe bug with EISA & PCI cards present from
408 report by <eirik@netcom.com>.
409 0.541 24-Aug-98 Fix compiler problems associated with i386-string
410 ops from multiple bug reports and temporary fix
411 from <paubert@iram.es>.
412 Fix pci_probe() to correctly emulate the old
413 pcibios_find_class() function.
414 Add an_exception() for old ZYNX346 and fix compile
415 warning on PPC & SPARC, from <ecd@skynet.be>.
416 Fix lastPCI to correctly work with compiled in
417 kernels and modules from bug report by
418 <Zlatko.Calusic@CARNet.hr> et al.
419 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
420 when media is unconnected.
421 Change dev->interrupt to lp->interrupt to ensure
422 alignment for Alpha's and avoid their unaligned
423 access traps. This flag is merely for log messages:
424 should do something more definitive though...
425 0.543 30-Dec-98 Add SMP spin locking.
426 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
427 a 21143 by <mmporter@home.com>.
428 Change PCI/EISA bus probing order.
429
430 =========================================================================
431 */
432
433 static const char *version = "de4x5.c:V0.544 1999/5/8 davies@maniac.ultranet.com\n";
434
435 #include <linux/config.h>
436 #include <linux/module.h>
437
438 #include <linux/kernel.h>
439 #include <linux/sched.h>
440 #include <linux/string.h>
441 #include <linux/interrupt.h>
442 #include <linux/ptrace.h>
443 #include <linux/errno.h>
444 #include <linux/ioport.h>
445 #include <linux/malloc.h>
446 #include <linux/pci.h>
447 #include <linux/delay.h>
448 #include <linux/init.h>
449 #include <linux/version.h>
450
451 #include <asm/bitops.h>
452 #include <asm/io.h>
453 #include <asm/dma.h>
454 #include <asm/byteorder.h>
455 #include <asm/unaligned.h>
456 #include <asm/uaccess.h>
457 #include <asm/spinlock.h>
458
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462
463 #include <linux/time.h>
464 #include <linux/types.h>
465 #include <linux/unistd.h>
466 #include <linux/ctype.h>
467
468 #include "de4x5.h"
469
470 #define c_char const char
471 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
472
473 /*
474 ** MII Information
475 */
476 struct phy_table {
477 int reset; /* Hard reset required? */
478 int id; /* IEEE OUI */
479 int ta; /* One cycle TA time - 802.3u is confusing here */
480 struct { /* Non autonegotiation (parallel) speed det. */
481 int reg;
482 int mask;
483 int value;
484 } spd;
485 };
486
487 struct mii_phy {
488 int reset; /* Hard reset required? */
489 int id; /* IEEE OUI */
490 int ta; /* One cycle TA time */
491 struct { /* Non autonegotiation (parallel) speed det. */
492 int reg;
493 int mask;
494 int value;
495 } spd;
496 int addr; /* MII address for the PHY */
497 u_char *gep; /* Start of GEP sequence block in SROM */
498 u_char *rst; /* Start of reset sequence in SROM */
499 u_int mc; /* Media Capabilities */
500 u_int ana; /* NWay Advertisement */
501 u_int fdx; /* Full DupleX capabilites for each media */
502 u_int ttm; /* Transmit Threshold Mode for each media */
503 u_int mci; /* 21142 MII Connector Interrupt info */
504 };
505
506 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
507
508 struct sia_phy {
509 u_char mc; /* Media Code */
510 u_char ext; /* csr13-15 valid when set */
511 int csr13; /* SIA Connectivity Register */
512 int csr14; /* SIA TX/RX Register */
513 int csr15; /* SIA General Register */
514 int gepc; /* SIA GEP Control Information */
515 int gep; /* SIA GEP Data */
516 };
517
518 /*
519 ** Define the know universe of PHY devices that can be
520 ** recognised by this driver.
521 */
522 static struct phy_table phy_info[] = {
523 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
524 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
525 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
526 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
527 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
528 };
529
530 /*
531 ** These GENERIC values assumes that the PHY devices follow 802.3u and
532 ** allow parallel detection to set the link partner ability register.
533 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
534 */
535 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
536 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
537 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
538
539 /*
540 ** Define special SROM detection cases
541 */
542 static c_char enet_det[][ETH_ALEN] = {
543 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
544 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
545 };
546
547 #define SMC 1
548 #define ACCTON 2
549
550 /*
551 ** SROM Repair definitions. If a broken SROM is detected a card may
552 ** use this information to help figure out what to do. This is a
553 ** "stab in the dark" and so far for SMC9332's only.
554 */
555 static c_char srom_repair_info[][100] = {
556 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
557 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
558 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
559 0x00,0x18,}
560 };
561
562
563 #ifdef DE4X5_DEBUG
564 static int de4x5_debug = DE4X5_DEBUG;
565 #else
566 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
567 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
568 #endif
569
570 /*
571 ** Allow per adapter set up. For modules this is simply a command line
572 ** parameter, e.g.:
573 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
574 **
575 ** For a compiled in driver, place e.g.
576 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
577 ** here
578 */
579 #ifdef DE4X5_PARM
580 static char *args = DE4X5_PARM;
581 #else
582 static char *args = NULL;
583 #endif
584
585 struct parameters {
586 int fdx;
587 int autosense;
588 };
589
590 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
591
592 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
593
594 /*
595 ** Ethernet PROM defines
596 */
597 #define PROBE_LENGTH 32
598 #define ETH_PROM_SIG 0xAA5500FFUL
599
600 /*
601 ** Ethernet Info
602 */
603 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
604 #define IEEE802_3_SZ 1518 /* Packet + CRC */
605 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
606 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
607 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
608 #define PKT_HDR_LEN 14 /* Addresses and data length info */
609 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
610 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
611
612
613 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
614 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
615
616 /*
617 ** EISA bus defines
618 */
619 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
620 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
621
622 #define MAX_EISA_SLOTS 16
623 #define EISA_SLOT_INC 0x1000
624 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
625
626 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
627 #define DE4X5_NAME_LENGTH 8
628
629 /*
630 ** Ethernet PROM defines for DC21040
631 */
632 #define PROBE_LENGTH 32
633 #define ETH_PROM_SIG 0xAA5500FFUL
634
635 /*
636 ** PCI Bus defines
637 */
638 #define PCI_MAX_BUS_NUM 8
639 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
640 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
641 #define NO_MORE_PCI -2 /* PCI bus search all done */
642
643 /*
644 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
645 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
646 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
647 ** and hence the RX descriptor ring's first entry.
648 */
649 #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
650 #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
651 #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
652 #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
653 #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
654 #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
655
656 #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
657 #define CACHE_ALIGN CAL_16LONG
658 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
659 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
660 #define DESC_ALIGN
661
662 #ifndef DEC_ONLY /* See README.de4x5 for using this */
663 static int dec_only = 0;
664 #else
665 static int dec_only = 1;
666 #endif
667
668 /*
669 ** DE4X5 IRQ ENABLE/DISABLE
670 */
671 #define ENABLE_IRQs { \
672 imr |= lp->irq_en;\
673 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
674 }
675
676 #define DISABLE_IRQs {\
677 imr = inl(DE4X5_IMR);\
678 imr &= ~lp->irq_en;\
679 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
680 }
681
682 #define UNMASK_IRQs {\
683 imr |= lp->irq_mask;\
684 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
685 }
686
687 #define MASK_IRQs {\
688 imr = inl(DE4X5_IMR);\
689 imr &= ~lp->irq_mask;\
690 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
691 }
692
693 /*
694 ** DE4X5 START/STOP
695 */
696 #define START_DE4X5 {\
697 omr = inl(DE4X5_OMR);\
698 omr |= OMR_ST | OMR_SR;\
699 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
700 }
701
702 #define STOP_DE4X5 {\
703 omr = inl(DE4X5_OMR);\
704 omr &= ~(OMR_ST|OMR_SR);\
705 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
706 }
707
708 /*
709 ** DE4X5 SIA RESET
710 */
711 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
712
713 /*
714 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
715 */
716 #define DE4X5_AUTOSENSE_MS 250
717
718 /*
719 ** SROM Structure
720 */
721 struct de4x5_srom {
722 char sub_vendor_id[2];
723 char sub_system_id[2];
724 char reserved[12];
725 char id_block_crc;
726 char reserved2;
727 char version;
728 char num_controllers;
729 char ieee_addr[6];
730 char info[100];
731 short chksum;
732 };
733 #define SUB_VENDOR_ID 0x500a
734
735 /*
736 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
737 ** and have sizes of both a power of 2 and a multiple of 4.
738 ** A size of 256 bytes for each buffer could be chosen because over 90% of
739 ** all packets in our network are <256 bytes long and 64 longword alignment
740 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
741 ** descriptors are needed for machines with an ALPHA CPU.
742 */
743 #define NUM_RX_DESC 8 /* Number of RX descriptors */
744 #define NUM_TX_DESC 32 /* Number of TX descriptors */
745 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
746 /* Multiple of 4 for DC21040 */
747 /* Allows 512 byte alignment */
748 struct de4x5_desc {
749 volatile s32 status;
750 u32 des1;
751 u32 buf;
752 u32 next;
753 DESC_ALIGN
754 };
755
756 /*
757 ** The DE4X5 private structure
758 */
759 #define DE4X5_PKT_STAT_SZ 16
760 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
761 increase DE4X5_PKT_STAT_SZ */
762
763 struct de4x5_private {
764 char adapter_name[80]; /* Adapter name */
765 u_long interrupt; /* Aligned ISR flag */
766 struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
767 struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
768 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
769 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
770 int rx_new, rx_old; /* RX descriptor ring pointers */
771 int tx_new, tx_old; /* TX descriptor ring pointers */
772 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
773 char frame[64]; /* Min sized packet for loopback*/
774 spinlock_t lock; /* Adapter specific spinlock */
775 struct net_device_stats stats; /* Public stats */
776 struct {
777 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
778 u_int unicast;
779 u_int multicast;
780 u_int broadcast;
781 u_int excessive_collisions;
782 u_int tx_underruns;
783 u_int excessive_underruns;
784 u_int rx_runt_frames;
785 u_int rx_collision;
786 u_int rx_dribble;
787 u_int rx_overflow;
788 } pktStats;
789 char rxRingSize;
790 char txRingSize;
791 int bus; /* EISA or PCI */
792 int bus_num; /* PCI Bus number */
793 int device; /* Device number on PCI bus */
794 int state; /* Adapter OPENED or CLOSED */
795 int chipset; /* DC21040, DC21041 or DC21140 */
796 s32 irq_mask; /* Interrupt Mask (Enable) bits */
797 s32 irq_en; /* Summary interrupt bits */
798 int media; /* Media (eg TP), mode (eg 100B)*/
799 int c_media; /* Remember the last media conn */
800 int fdx; /* media full duplex flag */
801 int linkOK; /* Link is OK */
802 int autosense; /* Allow/disallow autosensing */
803 int tx_enable; /* Enable descriptor polling */
804 int setup_f; /* Setup frame filtering type */
805 int local_state; /* State within a 'media' state */
806 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
807 struct sia_phy sia; /* SIA PHY Information */
808 int active; /* Index to active PHY device */
809 int mii_cnt; /* Number of attached PHY's */
810 int timeout; /* Scheduling counter */
811 struct timer_list timer; /* Timer info for kernel */
812 int tmp; /* Temporary global per card */
813 struct {
814 void *priv; /* Original kmalloc'd mem addr */
815 void *buf; /* Original kmalloc'd mem addr */
816 u_long lock; /* Lock the cache accesses */
817 s32 csr0; /* Saved Bus Mode Register */
818 s32 csr6; /* Saved Operating Mode Reg. */
819 s32 csr7; /* Saved IRQ Mask Register */
820 s32 gep; /* Saved General Purpose Reg. */
821 s32 gepc; /* Control info for GEP */
822 s32 csr13; /* Saved SIA Connectivity Reg. */
823 s32 csr14; /* Saved SIA TX/RX Register */
824 s32 csr15; /* Saved SIA General Register */
825 int save_cnt; /* Flag if state already saved */
826 struct sk_buff *skb; /* Save the (re-ordered) skb's */
827 } cache;
828 struct de4x5_srom srom; /* A copy of the SROM */
829 struct device *next_module; /* Link to the next module */
830 int rx_ovf; /* Check for 'RX overflow' tag */
831 int useSROM; /* For non-DEC card use SROM */
832 int useMII; /* Infoblock using the MII */
833 int asBitValid; /* Autosense bits in GEP? */
834 int asPolarity; /* 0 => asserted high */
835 int asBit; /* Autosense bit number in GEP */
836 int defMedium; /* SROM default medium */
837 int tcount; /* Last infoblock number */
838 int infoblock_init; /* Initialised this infoblock? */
839 int infoleaf_offset; /* SROM infoleaf for controller */
840 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
841 int infoblock_media; /* infoblock media */
842 int (*infoleaf_fn)(struct device *); /* Pointer to infoleaf function */
843 u_char *rst; /* Pointer to Type 5 reset info */
844 u_char ibn; /* Infoblock number */
845 struct parameters params; /* Command line/ #defined params */
846 };
847
848 /*
849 ** Kludge to get around the fact that the CSR addresses have different
850 ** offsets in the PCI and EISA boards. Also note that the ethernet address
851 ** PROM is accessed differently.
852 */
853 static struct bus_type {
854 int bus;
855 int bus_num;
856 int device;
857 int chipset;
858 struct de4x5_srom srom;
859 int autosense;
860 int useSROM;
861 } bus;
862
863 /*
864 ** To get around certain poxy cards that don't provide an SROM
865 ** for the second and more DECchip, I have to key off the first
866 ** chip's address. I'll assume there's not a bad SROM iff:
867 **
868 ** o the chipset is the same
869 ** o the bus number is the same and > 0
870 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
871 **
872 ** Also have to save the irq for those cards whose hardware designers
873 ** can't follow the PCI to PCI Bridge Architecture spec.
874 */
875 static struct {
876 int chipset;
877 int bus;
878 int irq;
879 u_char addr[ETH_ALEN];
880 } last = {0,};
881
882 /*
883 ** The transmit ring full condition is described by the tx_old and tx_new
884 ** pointers by:
885 ** tx_old = tx_new Empty ring
886 ** tx_old = tx_new+1 Full ring
887 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
888 */
889 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
890 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
891 lp->tx_old -lp->tx_new-1)
892
893 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
894
895 /*
896 ** Public Functions
897 */
898 static int de4x5_open(struct device *dev);
899 static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
900 static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
901 static int de4x5_close(struct device *dev);
902 static struct net_device_stats *de4x5_get_stats(struct device *dev);
903 static void de4x5_local_stats(struct device *dev, char *buf, int pkt_len);
904 static void set_multicast_list(struct device *dev);
905 static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
906
907 /*
908 ** Private functions
909 */
910 static int de4x5_hw_init(struct device *dev, u_long iobase);
911 static int de4x5_init(struct device *dev);
912 static int de4x5_sw_reset(struct device *dev);
913 static int de4x5_rx(struct device *dev);
914 static int de4x5_tx(struct device *dev);
915 static int de4x5_ast(struct device *dev);
916 static int de4x5_txur(struct device *dev);
917 static int de4x5_rx_ovfc(struct device *dev);
918
919 static int autoconf_media(struct device *dev);
920 static void create_packet(struct device *dev, char *frame, int len);
921 static void de4x5_us_delay(u32 usec);
922 static void de4x5_ms_delay(u32 msec);
923 static void load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb);
924 static int dc21040_autoconf(struct device *dev);
925 static int dc21041_autoconf(struct device *dev);
926 static int dc21140m_autoconf(struct device *dev);
927 static int dc2114x_autoconf(struct device *dev);
928 static int srom_autoconf(struct device *dev);
929 static int de4x5_suspect_state(struct device *dev, int timeout, int prev_state, int (*fn)(struct device *, int), int (*asfn)(struct device *));
930 static int dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct device *, int));
931 static int test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
932 static int test_for_100Mb(struct device *dev, int msec);
933 static int wait_for_link(struct device *dev);
934 static int test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec);
935 static int is_spd_100(struct device *dev);
936 static int is_100_up(struct device *dev);
937 static int is_10_up(struct device *dev);
938 static int is_anc_capable(struct device *dev);
939 static int ping_media(struct device *dev, int msec);
940 static struct sk_buff *de4x5_alloc_rx_buff(struct device *dev, int index, int len);
941 static void de4x5_free_rx_buffs(struct device *dev);
942 static void de4x5_free_tx_buffs(struct device *dev);
943 static void de4x5_save_skbs(struct device *dev);
944 static void de4x5_rst_desc_ring(struct device *dev);
945 static void de4x5_cache_state(struct device *dev, int flag);
946 static void de4x5_put_cache(struct device *dev, struct sk_buff *skb);
947 static void de4x5_putb_cache(struct device *dev, struct sk_buff *skb);
948 static struct sk_buff *de4x5_get_cache(struct device *dev);
949 static void de4x5_setup_intr(struct device *dev);
950 static void de4x5_init_connection(struct device *dev);
951 static int de4x5_reset_phy(struct device *dev);
952 static void reset_init_sia(struct device *dev, s32 sicr, s32 strr, s32 sigr);
953 static int test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec);
954 static int test_tp(struct device *dev, s32 msec);
955 static int EISA_signature(char *name, s32 eisa_id);
956 static int PCI_signature(char *name, struct bus_type *lp);
957 static void DevicePresent(u_long iobase);
958 static void enet_addr_rst(u_long aprom_addr);
959 static int de4x5_bad_srom(struct bus_type *lp);
960 static short srom_rd(u_long address, u_char offset);
961 static void srom_latch(u_int command, u_long address);
962 static void srom_command(u_int command, u_long address);
963 static void srom_address(u_int command, u_long address, u_char offset);
964 static short srom_data(u_int command, u_long address);
965 /*static void srom_busy(u_int command, u_long address);*/
966 static void sendto_srom(u_int command, u_long addr);
967 static int getfrom_srom(u_long addr);
968 static int srom_map_media(struct device *dev);
969 static int srom_infoleaf_info(struct device *dev);
970 static void srom_init(struct device *dev);
971 static void srom_exec(struct device *dev, u_char *p);
972 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
973 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
974 static int mii_rdata(u_long ioaddr);
975 static void mii_wdata(int data, int len, u_long ioaddr);
976 static void mii_ta(u_long rw, u_long ioaddr);
977 static int mii_swap(int data, int len);
978 static void mii_address(u_char addr, u_long ioaddr);
979 static void sendto_mii(u32 command, int data, u_long ioaddr);
980 static int getfrom_mii(u32 command, u_long ioaddr);
981 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
982 static int mii_get_phy(struct device *dev);
983 static void SetMulticastFilter(struct device *dev);
984 static int get_hw_addr(struct device *dev);
985 static void srom_repair(struct device *dev, int card);
986 static int test_bad_enet(struct device *dev, int status);
987 static int an_exception(struct bus_type *lp);
988 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
989 static void eisa_probe(struct device *dev, u_long iobase);
990 #endif
991 static void pci_probe(struct device *dev, u_long iobase);
992 static void srom_search(struct pci_dev *pdev);
993 static char *build_setup_frame(struct device *dev, int mode);
994 static void disable_ast(struct device *dev);
995 static void enable_ast(struct device *dev, u32 time_out);
996 static long de4x5_switch_mac_port(struct device *dev);
997 static int gep_rd(struct device *dev);
998 static void gep_wr(s32 data, struct device *dev);
999 static void timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec);
1000 static void yawn(struct device *dev, int state);
1001 static void link_modules(struct device *dev, struct device *tmp);
1002 static void de4x5_parse_params(struct device *dev);
1003 static void de4x5_dbg_open(struct device *dev);
1004 static void de4x5_dbg_mii(struct device *dev, int k);
1005 static void de4x5_dbg_media(struct device *dev);
1006 static void de4x5_dbg_srom(struct de4x5_srom *p);
1007 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1008 static int de4x5_strncmp(char *a, char *b, int n);
1009 static int dc21041_infoleaf(struct device *dev);
1010 static int dc21140_infoleaf(struct device *dev);
1011 static int dc21142_infoleaf(struct device *dev);
1012 static int dc21143_infoleaf(struct device *dev);
1013 static int type0_infoblock(struct device *dev, u_char count, u_char *p);
1014 static int type1_infoblock(struct device *dev, u_char count, u_char *p);
1015 static int type2_infoblock(struct device *dev, u_char count, u_char *p);
1016 static int type3_infoblock(struct device *dev, u_char count, u_char *p);
1017 static int type4_infoblock(struct device *dev, u_char count, u_char *p);
1018 static int type5_infoblock(struct device *dev, u_char count, u_char *p);
1019 static int compact_infoblock(struct device *dev, u_char count, u_char *p);
1020
1021 #ifdef MODULE
1022 int init_module(void);
1023 void cleanup_module(void);
1024 static struct device *unlink_modules(struct device *p);
1025 static struct device *insert_device(struct device *dev, u_long iobase,
1026 int (*init)(struct device *));
1027 static int count_adapters(void);
1028 static int loading_module = 1;
1029 MODULE_PARM(de4x5_debug, "i");
1030 MODULE_PARM(dec_only, "i");
1031 MODULE_PARM(args, "s");
1032 # else
1033 static int loading_module = 0;
1034 #endif /* MODULE */
1035
1036 static char name[DE4X5_NAME_LENGTH + 1];
1037 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1038 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1039 static int lastEISA = 0;
1040 # ifdef DE4X5_FORCE_EISA /* Force an EISA bus probe or not */
1041 static int forceEISA = 1;
1042 # else
1043 static int forceEISA = 0;
1044 # endif
1045 #endif
1046 static int num_de4x5s = 0;
1047 static int cfrv = 0, useSROM = 0;
1048 static int lastPCI = -1;
1049 static struct device *lastModule = NULL;
1050 static struct pci_dev *pdev = NULL;
1051
1052 /*
1053 ** List the SROM infoleaf functions and chipsets
1054 */
1055 struct InfoLeaf {
1056 int chipset;
1057 int (*fn)(struct device *);
1058 };
1059 static struct InfoLeaf infoleaf_array[] = {
1060 {DC21041, dc21041_infoleaf},
1061 {DC21140, dc21140_infoleaf},
1062 {DC21142, dc21142_infoleaf},
1063 {DC21143, dc21143_infoleaf}
1064 };
1065 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1066
1067 /*
1068 ** List the SROM info block functions
1069 */
1070 static int (*dc_infoblock[])(struct device *dev, u_char, u_char *) = {
1071 type0_infoblock,
1072 type1_infoblock,
1073 type2_infoblock,
1074 type3_infoblock,
1075 type4_infoblock,
1076 type5_infoblock,
1077 compact_infoblock
1078 };
1079
1080 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1081
1082 /*
1083 ** Miscellaneous defines...
1084 */
1085 #define RESET_DE4X5 {\
1086 int i;\
1087 i=inl(DE4X5_BMR);\
1088 de4x5_ms_delay(1);\
1089 outl(i | BMR_SWR, DE4X5_BMR);\
1090 de4x5_ms_delay(1);\
1091 outl(i, DE4X5_BMR);\
1092 de4x5_ms_delay(1);\
1093 for (i=0;i<5;i++) {inl(DE4X5_BMR); de4x5_ms_delay(1);}\
1094 de4x5_ms_delay(1);\
1095 }
1096
1097 #define PHY_HARD_RESET {\
1098 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1099 mdelay(1); /* Assert for 1ms */\
1100 outl(0x00, DE4X5_GEP);\
1101 mdelay(2); /* Wait for 2ms */\
1102 }
1103
1104 \f
1105 /*
1106 ** Autoprobing in modules is allowed here. See the top of the file for
1107 ** more info.
1108 */
1109 int __init
1110 de4x5_probe(struct device *dev)
1111 {
1112 u_long iobase = dev->base_addr;
1113
1114 pci_probe(dev, iobase);
1115 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1116 if ((lastPCI == NO_MORE_PCI) && ((num_de4x5s == 0) || forceEISA)) {
1117 eisa_probe(dev, iobase);
1118 }
1119 #endif
1120
1121 return (dev->priv ? 0 : -ENODEV);
1122 }
1123
1124 static int __init
1125 de4x5_hw_init(struct device *dev, u_long iobase)
1126 {
1127 struct bus_type *lp = &bus;
1128 int i, status=0;
1129 char *tmp;
1130
1131 /* Ensure we're not sleeping */
1132 if (lp->bus == EISA) {
1133 outb(WAKEUP, PCI_CFPM);
1134 } else {
1135 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1136 PCI_CFDA_PSM, WAKEUP);
1137 }
1138 de4x5_ms_delay(10);
1139
1140 RESET_DE4X5;
1141
1142 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1143 return -ENXIO; /* Hardware could not reset */
1144 }
1145
1146 /*
1147 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1148 */
1149 useSROM = FALSE;
1150 if (lp->bus == PCI) {
1151 PCI_signature(name, lp);
1152 } else {
1153 EISA_signature(name, EISA_ID0);
1154 }
1155
1156 if (*name == '\0') { /* Not found a board signature */
1157 return -ENXIO;
1158 }
1159
1160 dev->base_addr = iobase;
1161 if (lp->bus == EISA) {
1162 printk("%s: %s at 0x%04lx (EISA slot %ld)",
1163 dev->name, name, iobase, ((iobase>>12)&0x0f));
1164 } else { /* PCI port address */
1165 printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1166 iobase, lp->bus_num, lp->device);
1167 }
1168
1169 printk(", h/w address ");
1170 status = get_hw_addr(dev);
1171 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1172 printk("%2.2x:", dev->dev_addr[i]);
1173 }
1174 printk("%2.2x,\n", dev->dev_addr[i]);
1175
1176 if (status != 0) {
1177 printk(" which has an Ethernet PROM CRC error.\n");
1178 return -ENXIO;
1179 } else {
1180 struct de4x5_private *lp;
1181
1182 /*
1183 ** Reserve a section of kernel memory for the adapter
1184 ** private area and the TX/RX descriptor rings.
1185 */
1186 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1187 GFP_KERNEL);
1188 if (dev->priv == NULL) {
1189 return -ENOMEM;
1190 }
1191
1192 /*
1193 ** Align to a longword boundary
1194 */
1195 tmp = dev->priv;
1196 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1197 lp = (struct de4x5_private *)dev->priv;
1198 memset(dev->priv, 0, sizeof(struct de4x5_private));
1199 lp->bus = bus.bus;
1200 lp->bus_num = bus.bus_num;
1201 lp->device = bus.device;
1202 lp->chipset = bus.chipset;
1203 lp->cache.priv = tmp;
1204 lp->cache.gepc = GEP_INIT;
1205 lp->asBit = GEP_SLNK;
1206 lp->asPolarity = GEP_SLNK;
1207 lp->asBitValid = TRUE;
1208 lp->timeout = -1;
1209 lp->useSROM = useSROM;
1210 memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1211 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1212 de4x5_parse_params(dev);
1213
1214 /*
1215 ** Choose correct autosensing in case someone messed up
1216 */
1217 lp->autosense = lp->params.autosense;
1218 if (lp->chipset != DC21140) {
1219 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1220 lp->params.autosense = TP;
1221 }
1222 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1223 lp->params.autosense = BNC;
1224 }
1225 }
1226 lp->fdx = lp->params.fdx;
1227 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1228
1229 /*
1230 ** Set up the RX descriptor ring (Intels)
1231 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1232 */
1233 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1234 for (i=0; i<NUM_RX_DESC; i++) {
1235 lp->rx_ring[i].status = 0;
1236 lp->rx_ring[i].des1 = RX_BUFF_SZ;
1237 lp->rx_ring[i].buf = 0;
1238 lp->rx_ring[i].next = 0;
1239 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1240 }
1241
1242 #else
1243 if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
1244 GFP_KERNEL)) == NULL) {
1245 kfree(lp->cache.priv);
1246 lp->cache.priv = NULL;
1247 return -ENOMEM;
1248 }
1249
1250 lp->cache.buf = tmp;
1251 tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
1252 for (i=0; i<NUM_RX_DESC; i++) {
1253 lp->rx_ring[i].status = 0;
1254 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1255 lp->rx_ring[i].buf = cpu_to_le32(virt_to_bus(tmp+i*RX_BUFF_SZ));
1256 lp->rx_ring[i].next = 0;
1257 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1258 }
1259 #endif
1260
1261 barrier();
1262
1263 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1264 DE4X5_EISA_TOTAL_SIZE),
1265 lp->adapter_name);
1266
1267 lp->rxRingSize = NUM_RX_DESC;
1268 lp->txRingSize = NUM_TX_DESC;
1269
1270 /* Write the end of list marker to the descriptor lists */
1271 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1272 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1273
1274 /* Tell the adapter where the TX/RX rings are located. */
1275 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1276 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1277
1278 /* Initialise the IRQ mask and Enable/Disable */
1279 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1280 lp->irq_en = IMR_NIM | IMR_AIM;
1281
1282 /* Create a loopback packet frame for later media probing */
1283 create_packet(dev, lp->frame, sizeof(lp->frame));
1284
1285 /* Check if the RX overflow bug needs testing for */
1286 i = cfrv & 0x000000fe;
1287 if ((lp->chipset == DC21140) && (i == 0x20)) {
1288 lp->rx_ovf = 1;
1289 }
1290
1291 /* Initialise the SROM pointers if possible */
1292 if (lp->useSROM) {
1293 lp->state = INITIALISED;
1294 if (srom_infoleaf_info(dev)) {
1295 return -ENXIO;
1296 }
1297 srom_init(dev);
1298 }
1299
1300 lp->state = CLOSED;
1301
1302 /*
1303 ** Check for an MII interface
1304 */
1305 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1306 mii_get_phy(dev);
1307 }
1308
1309 #ifndef __sparc_v9__
1310 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1311 #else
1312 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1313 #endif
1314 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1315 }
1316
1317 if (de4x5_debug & DEBUG_VERSION) {
1318 printk(version);
1319 }
1320
1321 /* The DE4X5-specific entries in the device structure. */
1322 dev->open = &de4x5_open;
1323 dev->hard_start_xmit = &de4x5_queue_pkt;
1324 dev->stop = &de4x5_close;
1325 dev->get_stats = &de4x5_get_stats;
1326 dev->set_multicast_list = &set_multicast_list;
1327 dev->do_ioctl = &de4x5_ioctl;
1328
1329 dev->mem_start = 0;
1330
1331 /* Fill in the generic fields of the device structure. */
1332 ether_setup(dev);
1333
1334 /* Let the adapter sleep to save power */
1335 yawn(dev, SLEEP);
1336
1337 return status;
1338 }
1339
1340 \f
1341 static int
1342 de4x5_open(struct device *dev)
1343 {
1344 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1345 u_long iobase = dev->base_addr;
1346 int i, status = 0;
1347 s32 omr;
1348
1349 /* Allocate the RX buffers */
1350 for (i=0; i<lp->rxRingSize; i++) {
1351 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1352 de4x5_free_rx_buffs(dev);
1353 return -EAGAIN;
1354 }
1355 }
1356
1357 /*
1358 ** Wake up the adapter
1359 */
1360 yawn(dev, WAKEUP);
1361
1362 /*
1363 ** Re-initialize the DE4X5...
1364 */
1365 status = de4x5_init(dev);
1366 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1367 lp->state = OPEN;
1368 de4x5_dbg_open(dev);
1369
1370 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1371 lp->adapter_name, dev)) {
1372 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1373 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1374 lp->adapter_name, dev)) {
1375 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1376 disable_ast(dev);
1377 de4x5_free_rx_buffs(dev);
1378 de4x5_free_tx_buffs(dev);
1379 yawn(dev, SLEEP);
1380 lp->state = CLOSED;
1381 return -EAGAIN;
1382 } else {
1383 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1384 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1385 }
1386 }
1387
1388 dev->tbusy = 0;
1389 dev->start = 1;
1390 lp->interrupt = UNMASK_INTERRUPTS;
1391 dev->trans_start = jiffies;
1392
1393 START_DE4X5;
1394
1395 de4x5_setup_intr(dev);
1396
1397 if (de4x5_debug & DEBUG_OPEN) {
1398 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1399 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1400 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1401 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1402 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1403 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1404 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1405 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1406 }
1407
1408 MOD_INC_USE_COUNT;
1409
1410 return status;
1411 }
1412
1413 /*
1414 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1415 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1416 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1417 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1418 ** to be data corruption problems if it is larger (UDP errors seen from a
1419 ** ttcp source).
1420 */
1421 static int
1422 de4x5_init(struct device *dev)
1423 {
1424 /* Lock out other processes whilst setting up the hardware */
1425 test_and_set_bit(0, (void *)&dev->tbusy);
1426
1427 de4x5_sw_reset(dev);
1428
1429 /* Autoconfigure the connected port */
1430 autoconf_media(dev);
1431
1432 return 0;
1433 }
1434
1435 static int
1436 de4x5_sw_reset(struct device *dev)
1437 {
1438 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1439 u_long iobase = dev->base_addr;
1440 int i, j, status = 0;
1441 s32 bmr, omr;
1442
1443 /* Select the MII or SRL port now and RESET the MAC */
1444 if (!lp->useSROM) {
1445 if (lp->phy[lp->active].id != 0) {
1446 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1447 } else {
1448 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1449 }
1450 de4x5_switch_mac_port(dev);
1451 }
1452
1453 /*
1454 ** Set the programmable burst length to 8 longwords for all the DC21140
1455 ** Fasternet chips and 4 longwords for all others: DMA errors result
1456 ** without these values. Cache align 16 long.
1457 */
1458 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1459 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1460 outl(bmr, DE4X5_BMR);
1461
1462 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1463 if (lp->chipset == DC21140) {
1464 omr |= (OMR_SDP | OMR_SB);
1465 }
1466 lp->setup_f = PERFECT;
1467 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1468 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1469
1470 lp->rx_new = lp->rx_old = 0;
1471 lp->tx_new = lp->tx_old = 0;
1472
1473 for (i = 0; i < lp->rxRingSize; i++) {
1474 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1475 }
1476
1477 for (i = 0; i < lp->txRingSize; i++) {
1478 lp->tx_ring[i].status = cpu_to_le32(0);
1479 }
1480
1481 barrier();
1482
1483 /* Build the setup frame depending on filtering mode */
1484 SetMulticastFilter(dev);
1485
1486 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
1487 outl(omr|OMR_ST, DE4X5_OMR);
1488
1489 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1490 sti(); /* Ensure timer interrupts */
1491 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1492 mdelay(1);
1493 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1494 }
1495 outl(omr, DE4X5_OMR); /* Stop everything! */
1496
1497 if (j == 0) {
1498 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1499 inl(DE4X5_STS));
1500 status = -EIO;
1501 }
1502
1503 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1504 lp->tx_old = lp->tx_new;
1505
1506 return status;
1507 }
1508
1509 /*
1510 ** Writes a socket buffer address to the next available transmit descriptor.
1511 */
1512 static int
1513 de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
1514 {
1515 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1516 u_long iobase = dev->base_addr;
1517 int status = 0;
1518 u_long flags = 0;
1519
1520 test_and_set_bit(0, (void*)&dev->tbusy); /* Stop send re-tries */
1521 if (lp->tx_enable == NO) { /* Cannot send for now */
1522 return -1;
1523 }
1524
1525 /*
1526 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1527 ** interrupts are lost by delayed descriptor status updates relative to
1528 ** the irq assertion, especially with a busy PCI bus.
1529 */
1530 spin_lock_irqsave(&lp->lock, flags);
1531 de4x5_tx(dev);
1532 spin_unlock_irqrestore(&lp->lock, flags);
1533
1534 /* Test if cache is already locked - requeue skb if so */
1535 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1536 return -1;
1537
1538 /* Transmit descriptor ring full or stale skb */
1539 if (dev->tbusy || lp->tx_skb[lp->tx_new]) {
1540 if (lp->interrupt) {
1541 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1542 } else {
1543 de4x5_put_cache(dev, skb);
1544 }
1545 if (de4x5_debug & DEBUG_TX) {
1546 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%ld\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
1547 }
1548 } else if (skb->len > 0) {
1549 /* If we already have stuff queued locally, use that first */
1550 if (lp->cache.skb && !lp->interrupt) {
1551 de4x5_put_cache(dev, skb);
1552 skb = de4x5_get_cache(dev);
1553 }
1554
1555 while (skb && !dev->tbusy && !lp->tx_skb[lp->tx_new]) {
1556 spin_lock_irqsave(&lp->lock, flags);
1557 test_and_set_bit(0, (void*)&dev->tbusy);
1558 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1559 lp->stats.tx_bytes += skb->len;
1560 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1561
1562 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1563 dev->trans_start = jiffies;
1564
1565 if (TX_BUFFS_AVAIL) {
1566 dev->tbusy = 0; /* Another pkt may be queued */
1567 }
1568 skb = de4x5_get_cache(dev);
1569 spin_unlock_irqrestore(&lp->lock, flags);
1570 }
1571 if (skb) de4x5_putb_cache(dev, skb);
1572 }
1573
1574 lp->cache.lock = 0;
1575
1576 return status;
1577 }
1578
1579 /*
1580 ** The DE4X5 interrupt handler.
1581 **
1582 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1583 ** so that the asserted interrupt always has some real data to work with -
1584 ** if these I/O accesses are ever changed to memory accesses, ensure the
1585 ** STS write is read immediately to complete the transaction if the adapter
1586 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1587 ** is high and descriptor status bits cannot be set before the associated
1588 ** interrupt is asserted and this routine entered.
1589 */
1590 static void
1591 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1592 {
1593 struct device *dev = (struct device *)dev_id;
1594 struct de4x5_private *lp;
1595 s32 imr, omr, sts, limit;
1596 u_long iobase;
1597
1598 if (dev == NULL) {
1599 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1600 return;
1601 }
1602 lp = (struct de4x5_private *)dev->priv;
1603 spin_lock(&lp->lock);
1604 iobase = dev->base_addr;
1605
1606 DISABLE_IRQs; /* Ensure non re-entrancy */
1607
1608 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1609 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1610
1611 synchronize_irq();
1612
1613 for (limit=0; limit<8; limit++) {
1614 sts = inl(DE4X5_STS); /* Read IRQ status */
1615 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1616
1617 if (!(sts & lp->irq_mask)) break;/* All done */
1618
1619 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1620 de4x5_rx(dev);
1621
1622 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1623 de4x5_tx(dev);
1624
1625 if (sts & STS_LNF) { /* TP Link has failed */
1626 lp->irq_mask &= ~IMR_LFM;
1627 }
1628
1629 if (sts & STS_UNF) { /* Transmit underrun */
1630 de4x5_txur(dev);
1631 }
1632
1633 if (sts & STS_SE) { /* Bus Error */
1634 STOP_DE4X5;
1635 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1636 dev->name, sts);
1637 return;
1638 }
1639 }
1640
1641 /* Load the TX ring with any locally stored packets */
1642 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1643 while (lp->cache.skb && !dev->tbusy && lp->tx_enable) {
1644 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1645 }
1646 lp->cache.lock = 0;
1647 }
1648
1649 lp->interrupt = UNMASK_INTERRUPTS;
1650 ENABLE_IRQs;
1651 spin_unlock(&lp->lock);
1652
1653 return;
1654 }
1655
1656 static int
1657 de4x5_rx(struct device *dev)
1658 {
1659 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1660 u_long iobase = dev->base_addr;
1661 int entry;
1662 s32 status;
1663
1664 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1665 entry=lp->rx_new) {
1666 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1667
1668 if (lp->rx_ovf) {
1669 if (inl(DE4X5_MFC) & MFC_FOCM) {
1670 de4x5_rx_ovfc(dev);
1671 break;
1672 }
1673 }
1674
1675 if (status & RD_FS) { /* Remember the start of frame */
1676 lp->rx_old = entry;
1677 }
1678
1679 if (status & RD_LS) { /* Valid frame status */
1680 if (lp->tx_enable) lp->linkOK++;
1681 if (status & RD_ES) { /* There was an error. */
1682 lp->stats.rx_errors++; /* Update the error stats. */
1683 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1684 if (status & RD_CE) lp->stats.rx_crc_errors++;
1685 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1686 if (status & RD_TL) lp->stats.rx_length_errors++;
1687 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1688 if (status & RD_CS) lp->pktStats.rx_collision++;
1689 if (status & RD_DB) lp->pktStats.rx_dribble++;
1690 if (status & RD_OF) lp->pktStats.rx_overflow++;
1691 } else { /* A valid frame received */
1692 struct sk_buff *skb;
1693 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1694 >> 16) - 4;
1695
1696 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1697 printk("%s: Insufficient memory; nuking packet.\n",
1698 dev->name);
1699 lp->stats.rx_dropped++;
1700 } else {
1701 de4x5_dbg_rx(skb, pkt_len);
1702
1703 /* Push up the protocol stack */
1704 skb->protocol=eth_type_trans(skb,dev);
1705 netif_rx(skb);
1706
1707 /* Update stats */
1708 lp->stats.rx_packets++;
1709 lp->stats.rx_bytes += pkt_len;
1710 de4x5_local_stats(dev, skb->data, pkt_len);
1711 }
1712 }
1713
1714 /* Change buffer ownership for this frame, back to the adapter */
1715 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1716 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1717 barrier();
1718 }
1719 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1720 barrier();
1721 }
1722
1723 /*
1724 ** Update entry information
1725 */
1726 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1727 }
1728
1729 return 0;
1730 }
1731
1732 /*
1733 ** Buffer sent - check for TX buffer errors.
1734 */
1735 static int
1736 de4x5_tx(struct device *dev)
1737 {
1738 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1739 u_long iobase = dev->base_addr;
1740 int entry;
1741 s32 status;
1742
1743 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1744 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1745 if (status < 0) { /* Buffer not sent yet */
1746 break;
1747 } else if (status != 0x7fffffff) { /* Not setup frame */
1748 if (status & TD_ES) { /* An error happened */
1749 lp->stats.tx_errors++;
1750 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1751 if (status & TD_LC) lp->stats.tx_window_errors++;
1752 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1753 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1754 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1755
1756 if (TX_PKT_PENDING) {
1757 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1758 }
1759 } else { /* Packet sent */
1760 lp->stats.tx_packets++;
1761 if (lp->tx_enable) lp->linkOK++;
1762 }
1763 /* Update the collision counter */
1764 lp->stats.collisions += ((status & TD_EC) ? 16 :
1765 ((status & TD_CC) >> 3));
1766
1767 /* Free the buffer. */
1768 if (lp->tx_skb[entry] != NULL) {
1769 dev_kfree_skb(lp->tx_skb[entry]);
1770 lp->tx_skb[entry] = NULL;
1771 }
1772 }
1773
1774 /* Update all the pointers */
1775 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1776 }
1777
1778 if (TX_BUFFS_AVAIL && dev->tbusy) { /* Any resources available? */
1779 dev->tbusy = 0; /* Clear TX busy flag */
1780 if (lp->interrupt) mark_bh(NET_BH);
1781 }
1782
1783 return 0;
1784 }
1785
1786 static int
1787 de4x5_ast(struct device *dev)
1788 {
1789 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1790 int next_tick = DE4X5_AUTOSENSE_MS;
1791
1792 disable_ast(dev);
1793
1794 if (lp->useSROM) {
1795 next_tick = srom_autoconf(dev);
1796 } else if (lp->chipset == DC21140) {
1797 next_tick = dc21140m_autoconf(dev);
1798 } else if (lp->chipset == DC21041) {
1799 next_tick = dc21041_autoconf(dev);
1800 } else if (lp->chipset == DC21040) {
1801 next_tick = dc21040_autoconf(dev);
1802 }
1803 lp->linkOK = 0;
1804 enable_ast(dev, next_tick);
1805
1806 return 0;
1807 }
1808
1809 static int
1810 de4x5_txur(struct device *dev)
1811 {
1812 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1813 u_long iobase = dev->base_addr;
1814 int omr;
1815
1816 omr = inl(DE4X5_OMR);
1817 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1818 omr &= ~(OMR_ST|OMR_SR);
1819 outl(omr, DE4X5_OMR);
1820 while (inl(DE4X5_STS) & STS_TS);
1821 if ((omr & OMR_TR) < OMR_TR) {
1822 omr += 0x4000;
1823 } else {
1824 omr |= OMR_SF;
1825 }
1826 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1827 }
1828
1829 return 0;
1830 }
1831
1832 static int
1833 de4x5_rx_ovfc(struct device *dev)
1834 {
1835 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1836 u_long iobase = dev->base_addr;
1837 int omr;
1838
1839 omr = inl(DE4X5_OMR);
1840 outl(omr & ~OMR_SR, DE4X5_OMR);
1841 while (inl(DE4X5_STS) & STS_RS);
1842
1843 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1844 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1845 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1846 }
1847
1848 outl(omr, DE4X5_OMR);
1849
1850 return 0;
1851 }
1852
1853 static int
1854 de4x5_close(struct device *dev)
1855 {
1856 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1857 u_long iobase = dev->base_addr;
1858 s32 imr, omr;
1859
1860 disable_ast(dev);
1861 dev->start = 0;
1862 dev->tbusy = 1;
1863
1864 if (de4x5_debug & DEBUG_CLOSE) {
1865 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1866 dev->name, inl(DE4X5_STS));
1867 }
1868
1869 /*
1870 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1871 */
1872 DISABLE_IRQs;
1873 STOP_DE4X5;
1874
1875 /* Free the associated irq */
1876 free_irq(dev->irq, dev);
1877 lp->state = CLOSED;
1878
1879 /* Free any socket buffers */
1880 de4x5_free_rx_buffs(dev);
1881 de4x5_free_tx_buffs(dev);
1882
1883 MOD_DEC_USE_COUNT;
1884
1885 /* Put the adapter to sleep to save power */
1886 yawn(dev, SLEEP);
1887
1888 return 0;
1889 }
1890
1891 static struct net_device_stats *
1892 de4x5_get_stats(struct device *dev)
1893 {
1894 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1895 u_long iobase = dev->base_addr;
1896
1897 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1898
1899 return &lp->stats;
1900 }
1901
1902 static void
1903 de4x5_local_stats(struct device *dev, char *buf, int pkt_len)
1904 {
1905 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1906 int i;
1907
1908 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1909 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1910 lp->pktStats.bins[i]++;
1911 i = DE4X5_PKT_STAT_SZ;
1912 }
1913 }
1914 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1915 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1916 lp->pktStats.broadcast++;
1917 } else {
1918 lp->pktStats.multicast++;
1919 }
1920 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1921 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1922 lp->pktStats.unicast++;
1923 }
1924
1925 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1926 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1927 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1928 }
1929
1930 return;
1931 }
1932
1933 /*
1934 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1935 ** If the flag is changed on a descriptor that is being read by the hardware,
1936 ** I assume PCI transaction ordering will mean you are either successful or
1937 ** just miss asserting the change to the hardware. Anyway you're messing with
1938 ** a descriptor you don't own, but this shouldn't kill the chip provided
1939 ** the descriptor register is read only to the hardware.
1940 */
1941 static void
1942 load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb)
1943 {
1944 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1945 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1946
1947 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(virt_to_bus(buf));
1948 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1949 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1950 lp->tx_skb[lp->tx_new] = skb;
1951 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1952 barrier();
1953
1954 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1955 barrier();
1956
1957 return;
1958 }
1959
1960 /*
1961 ** Set or clear the multicast filter for this adaptor.
1962 */
1963 static void
1964 set_multicast_list(struct device *dev)
1965 {
1966 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1967 u_long iobase = dev->base_addr;
1968
1969 /* First, double check that the adapter is open */
1970 if (lp->state == OPEN) {
1971 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1972 u32 omr;
1973 omr = inl(DE4X5_OMR);
1974 omr |= OMR_PR;
1975 outl(omr, DE4X5_OMR);
1976 } else {
1977 SetMulticastFilter(dev);
1978 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1979 SETUP_FRAME_LEN, NULL);
1980
1981 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1982 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1983 dev->trans_start = jiffies;
1984 }
1985 }
1986
1987 return;
1988 }
1989
1990 /*
1991 ** Calculate the hash code and update the logical address filter
1992 ** from a list of ethernet multicast addresses.
1993 ** Little endian crc one liner from Matt Thomas, DEC.
1994 */
1995 static void
1996 SetMulticastFilter(struct device *dev)
1997 {
1998 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1999 struct dev_mc_list *dmi=dev->mc_list;
2000 u_long iobase = dev->base_addr;
2001 int i, j, bit, byte;
2002 u16 hashcode;
2003 u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
2004 char *pa;
2005 unsigned char *addrs;
2006
2007 omr = inl(DE4X5_OMR);
2008 omr &= ~(OMR_PR | OMR_PM);
2009 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
2010
2011 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
2012 omr |= OMR_PM; /* Pass all multicasts */
2013 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
2014 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
2015 addrs=dmi->dmi_addr;
2016 dmi=dmi->next;
2017 if ((*addrs & 0x01) == 1) { /* multicast address? */
2018 crc = 0xffffffff; /* init CRC for each address */
2019 for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
2020 /* process each address bit */
2021 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
2022 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
2023 }
2024 }
2025 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
2026
2027 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
2028 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2029
2030 byte <<= 1; /* calc offset into setup frame */
2031 if (byte & 0x02) {
2032 byte -= 1;
2033 }
2034 lp->setup_frame[byte] |= bit;
2035 }
2036 }
2037 } else { /* Perfect filtering */
2038 for (j=0; j<dev->mc_count; j++) {
2039 addrs=dmi->dmi_addr;
2040 dmi=dmi->next;
2041 for (i=0; i<ETH_ALEN; i++) {
2042 *(pa + (i&1)) = *addrs++;
2043 if (i & 0x01) pa += 4;
2044 }
2045 }
2046 }
2047 outl(omr, DE4X5_OMR);
2048
2049 return;
2050 }
2051
2052 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
2053 /*
2054 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2055 ** the motherboard. Upto 15 EISA devices are supported.
2056 */
2057 static void __init
2058 eisa_probe(struct device *dev, u_long ioaddr)
2059 {
2060 int i, maxSlots, status, device;
2061 u_char irq;
2062 u_short vendor;
2063 u32 cfid;
2064 u_long iobase;
2065 struct bus_type *lp = &bus;
2066 char name[DE4X5_STRLEN];
2067
2068 if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2069
2070 lp->bus = EISA;
2071
2072 if (ioaddr == 0) { /* Autoprobing */
2073 iobase = EISA_SLOT_INC; /* Get the first slot address */
2074 i = 1;
2075 maxSlots = MAX_EISA_SLOTS;
2076 } else { /* Probe a specific location */
2077 iobase = ioaddr;
2078 i = (ioaddr >> 12);
2079 maxSlots = i + 1;
2080 }
2081
2082 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2083 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE)) continue;
2084 if (!EISA_signature(name, EISA_ID)) continue;
2085
2086 cfid = (u32) inl(PCI_CFID);
2087 cfrv = (u_short) inl(PCI_CFRV);
2088 device = (cfid >> 8) & 0x00ffff00;
2089 vendor = (u_short) cfid;
2090
2091 /* Read the EISA Configuration Registers */
2092 irq = inb(EISA_REG0);
2093 irq = de4x5_irq[(irq >> 1) & 0x03];
2094
2095 if (is_DC2114x) {
2096 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2097 }
2098 lp->chipset = device;
2099
2100 /* Write the PCI Configuration Registers */
2101 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2102 outl(0x00006000, PCI_CFLT);
2103 outl(iobase, PCI_CBIO);
2104
2105 DevicePresent(EISA_APROM);
2106
2107 dev->irq = irq;
2108 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2109 num_de4x5s++;
2110 if (loading_module) link_modules(lastModule, dev);
2111 lastEISA = i;
2112 return;
2113 }
2114 }
2115
2116 if (ioaddr == 0) lastEISA = i;
2117
2118 return;
2119 }
2120 #endif /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__) */
2121
2122 /*
2123 ** PCI bus I/O device probe
2124 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2125 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2126 ** enabled by the user first in the set up utility. Hence we just check for
2127 ** enabled features and silently ignore the card if they're not.
2128 **
2129 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2130 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2131 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2132 ** PC doesn't conform to the PCI standard)!
2133 **
2134 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2135 ** kernels use the V0.535[n] drivers.
2136 */
2137 #define PCI_LAST_DEV 32
2138
2139 static void __init
2140 pci_probe(struct device *dev, u_long ioaddr)
2141 {
2142 u_char pb, pbus, dev_num, dnum, timer;
2143 u_short vendor, index, status;
2144 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2145 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2146 struct bus_type *lp = &bus;
2147
2148 if (lastPCI == NO_MORE_PCI) return;
2149
2150 if (!pcibios_present()) {
2151 lastPCI = NO_MORE_PCI;
2152 return; /* No PCI bus in this machine! */
2153 }
2154
2155 lp->bus = PCI;
2156 lp->bus_num = 0;
2157
2158 if ((ioaddr < 0x1000) && loading_module) {
2159 pbus = (u_short)(ioaddr >> 8);
2160 dnum = (u_short)(ioaddr & 0xff);
2161 } else {
2162 pbus = 0;
2163 dnum = 0;
2164 }
2165
2166 for (index=lastPCI+1;(pdev = pci_find_class(class, pdev))!=NULL;index++) {
2167 dev_num = PCI_SLOT(pdev->devfn);
2168 pb = pdev->bus->number;
2169 if ((pbus || dnum) && ((pbus != pb) || (dnum != dev_num))) continue;
2170
2171 vendor = pdev->vendor;
2172 device = pdev->device << 8;
2173 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2174
2175 /* Search for an SROM on this bus */
2176 if (lp->bus_num != pb) {
2177 lp->bus_num = pb;
2178 srom_search(pdev);
2179 }
2180
2181 /* Get the chip configuration revision register */
2182 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2183
2184 /* Set the device number information */
2185 lp->device = dev_num;
2186 lp->bus_num = pb;
2187
2188 /* Set the chipset information */
2189 if (is_DC2114x) {
2190 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2191 }
2192 lp->chipset = device;
2193
2194 /* Get the board I/O address (64 bits on sparc64) */
2195 iobase = pdev->base_address[0] & CBIO_MASK;
2196
2197 /* Fetch the IRQ to be used */
2198 irq = pdev->irq;
2199 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2200
2201 /* Check if I/O accesses and Bus Mastering are enabled */
2202 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2203 #ifdef __powerpc__
2204 if (!(status & PCI_COMMAND_IO)) {
2205 status |= PCI_COMMAND_IO;
2206 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2207 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2208 }
2209 #endif /* __powerpc__ */
2210 if (!(status & PCI_COMMAND_IO)) continue;
2211
2212 if (!(status & PCI_COMMAND_MASTER)) {
2213 status |= PCI_COMMAND_MASTER;
2214 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2215 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2216 }
2217 if (!(status & PCI_COMMAND_MASTER)) continue;
2218
2219 /* Check the latency timer for values >= 0x60 */
2220 pcibios_read_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, &timer);
2221 if (timer < 0x60) {
2222 pcibios_write_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, 0x60);
2223 }
2224
2225 DevicePresent(DE4X5_APROM);
2226 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2227 dev->irq = irq;
2228 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2229 num_de4x5s++;
2230 lastPCI = index;
2231 if (loading_module) link_modules(lastModule, dev);
2232 return;
2233 }
2234 } else if (ioaddr != 0) {
2235 printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2236 iobase);
2237 }
2238 }
2239
2240 lastPCI = NO_MORE_PCI;
2241
2242 return;
2243 }
2244
2245 /*
2246 ** This function searches the current bus (which is >0) for a DECchip with an
2247 ** SROM, so that in multiport cards that have one SROM shared between multiple
2248 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2249 ** For single port cards this is a time waster...
2250 */
2251 static void __init
2252 srom_search(struct pci_dev *dev)
2253 {
2254 u_char pb;
2255 u_short vendor, status;
2256 u_int irq = 0, device;
2257 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2258 int i, j;
2259 struct bus_type *lp = &bus;
2260
2261 for (; (dev=dev->sibling)!= NULL;) {
2262 pb = dev->bus->number;
2263 vendor = dev->vendor;
2264 device = dev->device << 8;
2265 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2266
2267 /* Get the chip configuration revision register */
2268 pcibios_read_config_dword(pb, dev->devfn, PCI_REVISION_ID, &cfrv);
2269
2270 /* Set the device number information */
2271 lp->device = PCI_SLOT(dev->devfn);
2272 lp->bus_num = pb;
2273
2274 /* Set the chipset information */
2275 if (is_DC2114x) {
2276 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2277 }
2278 lp->chipset = device;
2279
2280 /* Get the board I/O address (64 bits on sparc64) */
2281 iobase = dev->base_address[0] & CBIO_MASK;
2282
2283 /* Fetch the IRQ to be used */
2284 irq = dev->irq;
2285 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2286
2287 /* Check if I/O accesses are enabled */
2288 pcibios_read_config_word(pb, dev->devfn, PCI_COMMAND, &status);
2289 if (!(status & PCI_COMMAND_IO)) continue;
2290
2291 /* Search for a valid SROM attached to this DECchip */
2292 DevicePresent(DE4X5_APROM);
2293 for (j=0, i=0; i<ETH_ALEN; i++) {
2294 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2295 }
2296 if ((j != 0) && (j != 0x5fa)) {
2297 last.chipset = device;
2298 last.bus = pb;
2299 last.irq = irq;
2300 for (i=0; i<ETH_ALEN; i++) {
2301 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2302 }
2303 return;
2304 }
2305 }
2306
2307 return;
2308 }
2309
2310 static void __init
2311 link_modules(struct device *dev, struct device *tmp)
2312 {
2313 struct device *p=dev;
2314
2315 if (p) {
2316 while (((struct de4x5_private *)(p->priv))->next_module) {
2317 p = ((struct de4x5_private *)(p->priv))->next_module;
2318 }
2319
2320 if (dev != tmp) {
2321 ((struct de4x5_private *)(p->priv))->next_module = tmp;
2322 } else {
2323 ((struct de4x5_private *)(p->priv))->next_module = NULL;
2324 }
2325 }
2326
2327 return;
2328 }
2329
2330 /*
2331 ** Auto configure the media here rather than setting the port at compile
2332 ** time. This routine is called by de4x5_init() and when a loss of media is
2333 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2334 ** [TP] or no recent receive activity) to check whether the user has been
2335 ** sneaky and changed the port on us.
2336 */
2337 static int
2338 autoconf_media(struct device *dev)
2339 {
2340 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2341 u_long iobase = dev->base_addr;
2342 int next_tick = DE4X5_AUTOSENSE_MS;
2343
2344 lp->linkOK = 0;
2345 lp->c_media = AUTO; /* Bogus last media */
2346 disable_ast(dev);
2347 inl(DE4X5_MFC); /* Zero the lost frames counter */
2348 lp->media = INIT;
2349 lp->tcount = 0;
2350
2351 if (lp->useSROM) {
2352 next_tick = srom_autoconf(dev);
2353 } else if (lp->chipset == DC21040) {
2354 next_tick = dc21040_autoconf(dev);
2355 } else if (lp->chipset == DC21041) {
2356 next_tick = dc21041_autoconf(dev);
2357 } else if (lp->chipset == DC21140) {
2358 next_tick = dc21140m_autoconf(dev);
2359 }
2360
2361 enable_ast(dev, next_tick);
2362
2363 return (lp->media);
2364 }
2365
2366 /*
2367 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2368 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2369 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2370 ** The only way to test for that is to place a loopback packet onto the
2371 ** network and watch for errors. Since we're messing with the interrupt mask
2372 ** register, disable the board interrupts and do not allow any more packets to
2373 ** be queued to the hardware. Re-enable everything only when the media is
2374 ** found.
2375 ** I may have to "age out" locally queued packets so that the higher layer
2376 ** timeouts don't effectively duplicate packets on the network.
2377 */
2378 static int
2379 dc21040_autoconf(struct device *dev)
2380 {
2381 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2382 u_long iobase = dev->base_addr;
2383 int next_tick = DE4X5_AUTOSENSE_MS;
2384 s32 imr;
2385
2386 switch (lp->media) {
2387 case INIT:
2388 DISABLE_IRQs;
2389 lp->tx_enable = NO;
2390 lp->timeout = -1;
2391 de4x5_save_skbs(dev);
2392 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2393 lp->media = TP;
2394 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2395 lp->media = BNC_AUI;
2396 } else if (lp->autosense == EXT_SIA) {
2397 lp->media = EXT_SIA;
2398 } else {
2399 lp->media = NC;
2400 }
2401 lp->local_state = 0;
2402 next_tick = dc21040_autoconf(dev);
2403 break;
2404
2405 case TP:
2406 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2407 TP_SUSPECT, test_tp);
2408 break;
2409
2410 case TP_SUSPECT:
2411 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2412 break;
2413
2414 case BNC:
2415 case AUI:
2416 case BNC_AUI:
2417 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2418 BNC_AUI_SUSPECT, ping_media);
2419 break;
2420
2421 case BNC_AUI_SUSPECT:
2422 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2423 break;
2424
2425 case EXT_SIA:
2426 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2427 NC, EXT_SIA_SUSPECT, ping_media);
2428 break;
2429
2430 case EXT_SIA_SUSPECT:
2431 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2432 break;
2433
2434 case NC:
2435 /* default to TP for all */
2436 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2437 if (lp->media != lp->c_media) {
2438 de4x5_dbg_media(dev);
2439 lp->c_media = lp->media;
2440 }
2441 lp->media = INIT;
2442 lp->tx_enable = NO;
2443 break;
2444 }
2445
2446 return next_tick;
2447 }
2448
2449 static int
2450 dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout,
2451 int next_state, int suspect_state,
2452 int (*fn)(struct device *, int))
2453 {
2454 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2455 int next_tick = DE4X5_AUTOSENSE_MS;
2456 int linkBad;
2457
2458 switch (lp->local_state) {
2459 case 0:
2460 reset_init_sia(dev, csr13, csr14, csr15);
2461 lp->local_state++;
2462 next_tick = 500;
2463 break;
2464
2465 case 1:
2466 if (!lp->tx_enable) {
2467 linkBad = fn(dev, timeout);
2468 if (linkBad < 0) {
2469 next_tick = linkBad & ~TIMER_CB;
2470 } else {
2471 if (linkBad && (lp->autosense == AUTO)) {
2472 lp->local_state = 0;
2473 lp->media = next_state;
2474 } else {
2475 de4x5_init_connection(dev);
2476 }
2477 }
2478 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2479 lp->media = suspect_state;
2480 next_tick = 3000;
2481 }
2482 break;
2483 }
2484
2485 return next_tick;
2486 }
2487
2488 static int
2489 de4x5_suspect_state(struct device *dev, int timeout, int prev_state,
2490 int (*fn)(struct device *, int),
2491 int (*asfn)(struct device *))
2492 {
2493 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2494 int next_tick = DE4X5_AUTOSENSE_MS;
2495 int linkBad;
2496
2497 switch (lp->local_state) {
2498 case 1:
2499 if (lp->linkOK) {
2500 lp->media = prev_state;
2501 } else {
2502 lp->local_state++;
2503 next_tick = asfn(dev);
2504 }
2505 break;
2506
2507 case 2:
2508 linkBad = fn(dev, timeout);
2509 if (linkBad < 0) {
2510 next_tick = linkBad & ~TIMER_CB;
2511 } else if (!linkBad) {
2512 lp->local_state--;
2513 lp->media = prev_state;
2514 } else {
2515 lp->media = INIT;
2516 lp->tcount++;
2517 }
2518 }
2519
2520 return next_tick;
2521 }
2522
2523 /*
2524 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2525 ** before BNC, because the BNC port will indicate activity if it's not
2526 ** terminated correctly. The only way to test for that is to place a loopback
2527 ** packet onto the network and watch for errors. Since we're messing with
2528 ** the interrupt mask register, disable the board interrupts and do not allow
2529 ** any more packets to be queued to the hardware. Re-enable everything only
2530 ** when the media is found.
2531 */
2532 static int
2533 dc21041_autoconf(struct device *dev)
2534 {
2535 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2536 u_long iobase = dev->base_addr;
2537 s32 sts, irqs, irq_mask, imr, omr;
2538 int next_tick = DE4X5_AUTOSENSE_MS;
2539
2540 switch (lp->media) {
2541 case INIT:
2542 DISABLE_IRQs;
2543 lp->tx_enable = NO;
2544 lp->timeout = -1;
2545 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2546 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2547 lp->media = TP; /* On chip auto negotiation is broken */
2548 } else if (lp->autosense == TP) {
2549 lp->media = TP;
2550 } else if (lp->autosense == BNC) {
2551 lp->media = BNC;
2552 } else if (lp->autosense == AUI) {
2553 lp->media = AUI;
2554 } else {
2555 lp->media = NC;
2556 }
2557 lp->local_state = 0;
2558 next_tick = dc21041_autoconf(dev);
2559 break;
2560
2561 case TP_NW:
2562 if (lp->timeout < 0) {
2563 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2564 outl(omr | OMR_FDX, DE4X5_OMR);
2565 }
2566 irqs = STS_LNF | STS_LNP;
2567 irq_mask = IMR_LFM | IMR_LPM;
2568 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2569 if (sts < 0) {
2570 next_tick = sts & ~TIMER_CB;
2571 } else {
2572 if (sts & STS_LNP) {
2573 lp->media = ANS;
2574 } else {
2575 lp->media = AUI;
2576 }
2577 next_tick = dc21041_autoconf(dev);
2578 }
2579 break;
2580
2581 case ANS:
2582 if (!lp->tx_enable) {
2583 irqs = STS_LNP;
2584 irq_mask = IMR_LPM;
2585 sts = test_ans(dev, irqs, irq_mask, 3000);
2586 if (sts < 0) {
2587 next_tick = sts & ~TIMER_CB;
2588 } else {
2589 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2590 lp->media = TP;
2591 next_tick = dc21041_autoconf(dev);
2592 } else {
2593 lp->local_state = 1;
2594 de4x5_init_connection(dev);
2595 }
2596 }
2597 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2598 lp->media = ANS_SUSPECT;
2599 next_tick = 3000;
2600 }
2601 break;
2602
2603 case ANS_SUSPECT:
2604 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2605 break;
2606
2607 case TP:
2608 if (!lp->tx_enable) {
2609 if (lp->timeout < 0) {
2610 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2611 outl(omr & ~OMR_FDX, DE4X5_OMR);
2612 }
2613 irqs = STS_LNF | STS_LNP;
2614 irq_mask = IMR_LFM | IMR_LPM;
2615 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2616 if (sts < 0) {
2617 next_tick = sts & ~TIMER_CB;
2618 } else {
2619 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2620 if (inl(DE4X5_SISR) & SISR_NRA) {
2621 lp->media = AUI; /* Non selected port activity */
2622 } else {
2623 lp->media = BNC;
2624 }
2625 next_tick = dc21041_autoconf(dev);
2626 } else {
2627 lp->local_state = 1;
2628 de4x5_init_connection(dev);
2629 }
2630 }
2631 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2632 lp->media = TP_SUSPECT;
2633 next_tick = 3000;
2634 }
2635 break;
2636
2637 case TP_SUSPECT:
2638 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2639 break;
2640
2641 case AUI:
2642 if (!lp->tx_enable) {
2643 if (lp->timeout < 0) {
2644 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2645 outl(omr & ~OMR_FDX, DE4X5_OMR);
2646 }
2647 irqs = 0;
2648 irq_mask = 0;
2649 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2650 if (sts < 0) {
2651 next_tick = sts & ~TIMER_CB;
2652 } else {
2653 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2654 lp->media = BNC;
2655 next_tick = dc21041_autoconf(dev);
2656 } else {
2657 lp->local_state = 1;
2658 de4x5_init_connection(dev);
2659 }
2660 }
2661 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2662 lp->media = AUI_SUSPECT;
2663 next_tick = 3000;
2664 }
2665 break;
2666
2667 case AUI_SUSPECT:
2668 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2669 break;
2670
2671 case BNC:
2672 switch (lp->local_state) {
2673 case 0:
2674 if (lp->timeout < 0) {
2675 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2676 outl(omr & ~OMR_FDX, DE4X5_OMR);
2677 }
2678 irqs = 0;
2679 irq_mask = 0;
2680 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2681 if (sts < 0) {
2682 next_tick = sts & ~TIMER_CB;
2683 } else {
2684 lp->local_state++; /* Ensure media connected */
2685 next_tick = dc21041_autoconf(dev);
2686 }
2687 break;
2688
2689 case 1:
2690 if (!lp->tx_enable) {
2691 if ((sts = ping_media(dev, 3000)) < 0) {
2692 next_tick = sts & ~TIMER_CB;
2693 } else {
2694 if (sts) {
2695 lp->local_state = 0;
2696 lp->media = NC;
2697 } else {
2698 de4x5_init_connection(dev);
2699 }
2700 }
2701 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2702 lp->media = BNC_SUSPECT;
2703 next_tick = 3000;
2704 }
2705 break;
2706 }
2707 break;
2708
2709 case BNC_SUSPECT:
2710 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2711 break;
2712
2713 case NC:
2714 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2715 outl(omr | OMR_FDX, DE4X5_OMR);
2716 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2717 if (lp->media != lp->c_media) {
2718 de4x5_dbg_media(dev);
2719 lp->c_media = lp->media;
2720 }
2721 lp->media = INIT;
2722 lp->tx_enable = NO;
2723 break;
2724 }
2725
2726 return next_tick;
2727 }
2728
2729 /*
2730 ** Some autonegotiation chips are broken in that they do not return the
2731 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2732 ** register, except at the first power up negotiation.
2733 */
2734 static int
2735 dc21140m_autoconf(struct device *dev)
2736 {
2737 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2738 int ana, anlpa, cap, cr, slnk, sr;
2739 int next_tick = DE4X5_AUTOSENSE_MS;
2740 u_long imr, omr, iobase = dev->base_addr;
2741
2742 switch(lp->media) {
2743 case INIT:
2744 if (lp->timeout < 0) {
2745 DISABLE_IRQs;
2746 lp->tx_enable = FALSE;
2747 lp->linkOK = 0;
2748 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2749 }
2750 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2751 next_tick &= ~TIMER_CB;
2752 } else {
2753 if (lp->useSROM) {
2754 if (srom_map_media(dev) < 0) {
2755 lp->tcount++;
2756 return next_tick;
2757 }
2758 srom_exec(dev, lp->phy[lp->active].gep);
2759 if (lp->infoblock_media == ANS) {
2760 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2761 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2762 }
2763 } else {
2764 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2765 SET_10Mb;
2766 if (lp->autosense == _100Mb) {
2767 lp->media = _100Mb;
2768 } else if (lp->autosense == _10Mb) {
2769 lp->media = _10Mb;
2770 } else if ((lp->autosense == AUTO) &&
2771 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2772 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2773 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2774 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2775 lp->media = ANS;
2776 } else if (lp->autosense == AUTO) {
2777 lp->media = SPD_DET;
2778 } else if (is_spd_100(dev) && is_100_up(dev)) {
2779 lp->media = _100Mb;
2780 } else {
2781 lp->media = NC;
2782 }
2783 }
2784 lp->local_state = 0;
2785 next_tick = dc21140m_autoconf(dev);
2786 }
2787 break;
2788
2789 case ANS:
2790 switch (lp->local_state) {
2791 case 0:
2792 if (lp->timeout < 0) {
2793 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2794 }
2795 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2796 if (cr < 0) {
2797 next_tick = cr & ~TIMER_CB;
2798 } else {
2799 if (cr) {
2800 lp->local_state = 0;
2801 lp->media = SPD_DET;
2802 } else {
2803 lp->local_state++;
2804 }
2805 next_tick = dc21140m_autoconf(dev);
2806 }
2807 break;
2808
2809 case 1:
2810 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2811 next_tick = sr & ~TIMER_CB;
2812 } else {
2813 lp->media = SPD_DET;
2814 lp->local_state = 0;
2815 if (sr) { /* Success! */
2816 lp->tmp = MII_SR_ASSC;
2817 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2818 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2819 if (!(anlpa & MII_ANLPA_RF) &&
2820 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2821 if (cap & MII_ANA_100M) {
2822 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2823 lp->media = _100Mb;
2824 } else if (cap & MII_ANA_10M) {
2825 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2826
2827 lp->media = _10Mb;
2828 }
2829 }
2830 } /* Auto Negotiation failed to finish */
2831 next_tick = dc21140m_autoconf(dev);
2832 } /* Auto Negotiation failed to start */
2833 break;
2834 }
2835 break;
2836
2837 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2838 if (lp->timeout < 0) {
2839 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2840 (~gep_rd(dev) & GEP_LNP));
2841 SET_100Mb_PDET;
2842 }
2843 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2844 next_tick = slnk & ~TIMER_CB;
2845 } else {
2846 if (is_spd_100(dev) && is_100_up(dev)) {
2847 lp->media = _100Mb;
2848 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2849 lp->media = _10Mb;
2850 } else {
2851 lp->media = NC;
2852 }
2853 next_tick = dc21140m_autoconf(dev);
2854 }
2855 break;
2856
2857 case _100Mb: /* Set 100Mb/s */
2858 next_tick = 3000;
2859 if (!lp->tx_enable) {
2860 SET_100Mb;
2861 de4x5_init_connection(dev);
2862 } else {
2863 if (!lp->linkOK && (lp->autosense == AUTO)) {
2864 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2865 lp->media = INIT;
2866 lp->tcount++;
2867 next_tick = DE4X5_AUTOSENSE_MS;
2868 }
2869 }
2870 }
2871 break;
2872
2873 case BNC:
2874 case AUI:
2875 case _10Mb: /* Set 10Mb/s */
2876 next_tick = 3000;
2877 if (!lp->tx_enable) {
2878 SET_10Mb;
2879 de4x5_init_connection(dev);
2880 } else {
2881 if (!lp->linkOK && (lp->autosense == AUTO)) {
2882 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2883 lp->media = INIT;
2884 lp->tcount++;
2885 next_tick = DE4X5_AUTOSENSE_MS;
2886 }
2887 }
2888 }
2889 break;
2890
2891 case NC:
2892 if (lp->media != lp->c_media) {
2893 de4x5_dbg_media(dev);
2894 lp->c_media = lp->media;
2895 }
2896 lp->media = INIT;
2897 lp->tx_enable = FALSE;
2898 break;
2899 }
2900
2901 return next_tick;
2902 }
2903
2904 /*
2905 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2906 ** changing how I figure out the media - but trying to keep it backwards
2907 ** compatible with the de500-xa and de500-aa.
2908 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2909 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2910 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2911 ** active.
2912 ** When autonegotiation is working, the ANS part searches the SROM for
2913 ** the highest common speed (TP) link that both can run and if that can
2914 ** be full duplex. That infoblock is executed and then the link speed set.
2915 **
2916 ** Only _10Mb and _100Mb are tested here.
2917 */
2918 static int
2919 dc2114x_autoconf(struct device *dev)
2920 {
2921 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2922 u_long iobase = dev->base_addr;
2923 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2924 int next_tick = DE4X5_AUTOSENSE_MS;
2925
2926 switch (lp->media) {
2927 case INIT:
2928 if (lp->timeout < 0) {
2929 DISABLE_IRQs;
2930 lp->tx_enable = FALSE;
2931 lp->linkOK = 0;
2932 lp->timeout = -1;
2933 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2934 if (lp->params.autosense & ~AUTO) {
2935 srom_map_media(dev); /* Fixed media requested */
2936 if (lp->media != lp->params.autosense) {
2937 lp->tcount++;
2938 lp->media = INIT;
2939 return next_tick;
2940 }
2941 lp->media = INIT;
2942 }
2943 }
2944 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2945 next_tick &= ~TIMER_CB;
2946 } else {
2947 if (lp->autosense == _100Mb) {
2948 lp->media = _100Mb;
2949 } else if (lp->autosense == _10Mb) {
2950 lp->media = _10Mb;
2951 } else if (lp->autosense == TP) {
2952 lp->media = TP;
2953 } else if (lp->autosense == BNC) {
2954 lp->media = BNC;
2955 } else if (lp->autosense == AUI) {
2956 lp->media = AUI;
2957 } else {
2958 lp->media = SPD_DET;
2959 if ((lp->infoblock_media == ANS) &&
2960 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2961 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2962 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2963 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2964 lp->media = ANS;
2965 }
2966 }
2967 lp->local_state = 0;
2968 next_tick = dc2114x_autoconf(dev);
2969 }
2970 break;
2971
2972 case ANS:
2973 switch (lp->local_state) {
2974 case 0:
2975 if (lp->timeout < 0) {
2976 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2977 }
2978 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2979 if (cr < 0) {
2980 next_tick = cr & ~TIMER_CB;
2981 } else {
2982 if (cr) {
2983 lp->local_state = 0;
2984 lp->media = SPD_DET;
2985 } else {
2986 lp->local_state++;
2987 }
2988 next_tick = dc2114x_autoconf(dev);
2989 }
2990 break;
2991
2992 case 1:
2993 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2994 next_tick = sr & ~TIMER_CB;
2995 } else {
2996 lp->media = SPD_DET;
2997 lp->local_state = 0;
2998 if (sr) { /* Success! */
2999 lp->tmp = MII_SR_ASSC;
3000 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3001 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3002 if (!(anlpa & MII_ANLPA_RF) &&
3003 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3004 if (cap & MII_ANA_100M) {
3005 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3006 lp->media = _100Mb;
3007 } else if (cap & MII_ANA_10M) {
3008 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3009 lp->media = _10Mb;
3010 }
3011 }
3012 } /* Auto Negotiation failed to finish */
3013 next_tick = dc2114x_autoconf(dev);
3014 } /* Auto Negotiation failed to start */
3015 break;
3016 }
3017 break;
3018
3019 case AUI:
3020 if (!lp->tx_enable) {
3021 if (lp->timeout < 0) {
3022 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3023 outl(omr & ~OMR_FDX, DE4X5_OMR);
3024 }
3025 irqs = 0;
3026 irq_mask = 0;
3027 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3028 if (sts < 0) {
3029 next_tick = sts & ~TIMER_CB;
3030 } else {
3031 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3032 lp->media = BNC;
3033 next_tick = dc2114x_autoconf(dev);
3034 } else {
3035 lp->local_state = 1;
3036 de4x5_init_connection(dev);
3037 }
3038 }
3039 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3040 lp->media = AUI_SUSPECT;
3041 next_tick = 3000;
3042 }
3043 break;
3044
3045 case AUI_SUSPECT:
3046 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3047 break;
3048
3049 case BNC:
3050 switch (lp->local_state) {
3051 case 0:
3052 if (lp->timeout < 0) {
3053 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3054 outl(omr & ~OMR_FDX, DE4X5_OMR);
3055 }
3056 irqs = 0;
3057 irq_mask = 0;
3058 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3059 if (sts < 0) {
3060 next_tick = sts & ~TIMER_CB;
3061 } else {
3062 lp->local_state++; /* Ensure media connected */
3063 next_tick = dc2114x_autoconf(dev);
3064 }
3065 break;
3066
3067 case 1:
3068 if (!lp->tx_enable) {
3069 if ((sts = ping_media(dev, 3000)) < 0) {
3070 next_tick = sts & ~TIMER_CB;
3071 } else {
3072 if (sts) {
3073 lp->local_state = 0;
3074 lp->tcount++;
3075 lp->media = INIT;
3076 } else {
3077 de4x5_init_connection(dev);
3078 }
3079 }
3080 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3081 lp->media = BNC_SUSPECT;
3082 next_tick = 3000;
3083 }
3084 break;
3085 }
3086 break;
3087
3088 case BNC_SUSPECT:
3089 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3090 break;
3091
3092 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3093 if (srom_map_media(dev) < 0) {
3094 lp->tcount++;
3095 lp->media = INIT;
3096 return next_tick;
3097 }
3098 if (lp->media == _100Mb) {
3099 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3100 lp->media = SPD_DET;
3101 return (slnk & ~TIMER_CB);
3102 }
3103 } else {
3104 if (wait_for_link(dev) < 0) {
3105 lp->media = SPD_DET;
3106 return PDET_LINK_WAIT;
3107 }
3108 }
3109 if (lp->media == ANS) { /* Do MII parallel detection */
3110 if (is_spd_100(dev)) {
3111 lp->media = _100Mb;
3112 } else {
3113 lp->media = _10Mb;
3114 }
3115 next_tick = dc2114x_autoconf(dev);
3116 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3117 (((lp->media == _10Mb) || (lp->media == TP) ||
3118 (lp->media == BNC) || (lp->media == AUI)) &&
3119 is_10_up(dev))) {
3120 next_tick = dc2114x_autoconf(dev);
3121 } else {
3122 lp->tcount++;
3123 lp->media = INIT;
3124 }
3125 break;
3126
3127 case _10Mb:
3128 next_tick = 3000;
3129 if (!lp->tx_enable) {
3130 SET_10Mb;
3131 de4x5_init_connection(dev);
3132 } else {
3133 if (!lp->linkOK && (lp->autosense == AUTO)) {
3134 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3135 lp->media = INIT;
3136 lp->tcount++;
3137 next_tick = DE4X5_AUTOSENSE_MS;
3138 }
3139 }
3140 }
3141 break;
3142
3143 case _100Mb:
3144 next_tick = 3000;
3145 if (!lp->tx_enable) {
3146 SET_100Mb;
3147 de4x5_init_connection(dev);
3148 } else {
3149 if (!lp->linkOK && (lp->autosense == AUTO)) {
3150 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3151 lp->media = INIT;
3152 lp->tcount++;
3153 next_tick = DE4X5_AUTOSENSE_MS;
3154 }
3155 }
3156 }
3157 break;
3158
3159 default:
3160 lp->tcount++;
3161 printk("Huh?: media:%02x\n", lp->media);
3162 lp->media = INIT;
3163 break;
3164 }
3165
3166 return next_tick;
3167 }
3168
3169 static int
3170 srom_autoconf(struct device *dev)
3171 {
3172 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3173
3174 return lp->infoleaf_fn(dev);
3175 }
3176
3177 /*
3178 ** This mapping keeps the original media codes and FDX flag unchanged.
3179 ** While it isn't strictly necessary, it helps me for the moment...
3180 ** The early return avoids a media state / SROM media space clash.
3181 */
3182 static int
3183 srom_map_media(struct device *dev)
3184 {
3185 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3186
3187 lp->fdx = 0;
3188 if (lp->infoblock_media == lp->media)
3189 return 0;
3190
3191 switch(lp->infoblock_media) {
3192 case SROM_10BASETF:
3193 if (!lp->params.fdx) return -1;
3194 lp->fdx = TRUE;
3195 case SROM_10BASET:
3196 if (lp->params.fdx && !lp->fdx) return -1;
3197 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3198 lp->media = _10Mb;
3199 } else {
3200 lp->media = TP;
3201 }
3202 break;
3203
3204 case SROM_10BASE2:
3205 lp->media = BNC;
3206 break;
3207
3208 case SROM_10BASE5:
3209 lp->media = AUI;
3210 break;
3211
3212 case SROM_100BASETF:
3213 if (!lp->params.fdx) return -1;
3214 lp->fdx = TRUE;
3215 case SROM_100BASET:
3216 if (lp->params.fdx && !lp->fdx) return -1;
3217 lp->media = _100Mb;
3218 break;
3219
3220 case SROM_100BASET4:
3221 lp->media = _100Mb;
3222 break;
3223
3224 case SROM_100BASEFF:
3225 if (!lp->params.fdx) return -1;
3226 lp->fdx = TRUE;
3227 case SROM_100BASEF:
3228 if (lp->params.fdx && !lp->fdx) return -1;
3229 lp->media = _100Mb;
3230 break;
3231
3232 case ANS:
3233 lp->media = ANS;
3234 break;
3235
3236 default:
3237 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3238 lp->infoblock_media);
3239 return -1;
3240 break;
3241 }
3242
3243 return 0;
3244 }
3245
3246 static void
3247 de4x5_init_connection(struct device *dev)
3248 {
3249 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3250 u_long iobase = dev->base_addr;
3251 u_long flags = 0;
3252
3253 if (lp->media != lp->c_media) {
3254 de4x5_dbg_media(dev);
3255 lp->c_media = lp->media; /* Stop scrolling media messages */
3256 }
3257
3258 spin_lock_irqsave(&lp->lock, flags);
3259 de4x5_rst_desc_ring(dev);
3260 de4x5_setup_intr(dev);
3261 lp->tx_enable = YES;
3262 dev->tbusy = 0;
3263 spin_unlock_irqrestore(&lp->lock, flags);
3264 outl(POLL_DEMAND, DE4X5_TPD);
3265 mark_bh(NET_BH);
3266
3267 return;
3268 }
3269
3270 /*
3271 ** General PHY reset function. Some MII devices don't reset correctly
3272 ** since their MII address pins can float at voltages that are dependent
3273 ** on the signal pin use. Do a double reset to ensure a reset.
3274 */
3275 static int
3276 de4x5_reset_phy(struct device *dev)
3277 {
3278 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3279 u_long iobase = dev->base_addr;
3280 int next_tick = 0;
3281
3282 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3283 if (lp->timeout < 0) {
3284 if (lp->useSROM) {
3285 if (lp->phy[lp->active].rst) {
3286 srom_exec(dev, lp->phy[lp->active].rst);
3287 srom_exec(dev, lp->phy[lp->active].rst);
3288 } else if (lp->rst) { /* Type 5 infoblock reset */
3289 srom_exec(dev, lp->rst);
3290 srom_exec(dev, lp->rst);
3291 }
3292 } else {
3293 PHY_HARD_RESET;
3294 }
3295 if (lp->useMII) {
3296 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3297 }
3298 }
3299 if (lp->useMII) {
3300 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3301 }
3302 } else if (lp->chipset == DC21140) {
3303 PHY_HARD_RESET;
3304 }
3305
3306 return next_tick;
3307 }
3308
3309 static int
3310 test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3311 {
3312 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3313 u_long iobase = dev->base_addr;
3314 s32 sts, csr12;
3315
3316 if (lp->timeout < 0) {
3317 lp->timeout = msec/100;
3318 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3319 reset_init_sia(dev, csr13, csr14, csr15);
3320 }
3321
3322 /* set up the interrupt mask */
3323 outl(irq_mask, DE4X5_IMR);
3324
3325 /* clear all pending interrupts */
3326 sts = inl(DE4X5_STS);
3327 outl(sts, DE4X5_STS);
3328
3329 /* clear csr12 NRA and SRA bits */
3330 if ((lp->chipset == DC21041) || lp->useSROM) {
3331 csr12 = inl(DE4X5_SISR);
3332 outl(csr12, DE4X5_SISR);
3333 }
3334 }
3335
3336 sts = inl(DE4X5_STS) & ~TIMER_CB;
3337
3338 if (!(sts & irqs) && --lp->timeout) {
3339 sts = 100 | TIMER_CB;
3340 } else {
3341 lp->timeout = -1;
3342 }
3343
3344 return sts;
3345 }
3346
3347 static int
3348 test_tp(struct device *dev, s32 msec)
3349 {
3350 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3351 u_long iobase = dev->base_addr;
3352 int sisr;
3353
3354 if (lp->timeout < 0) {
3355 lp->timeout = msec/100;
3356 }
3357
3358 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3359
3360 if (sisr && --lp->timeout) {
3361 sisr = 100 | TIMER_CB;
3362 } else {
3363 lp->timeout = -1;
3364 }
3365
3366 return sisr;
3367 }
3368
3369 /*
3370 ** Samples the 100Mb Link State Signal. The sample interval is important
3371 ** because too fast a rate can give erroneous results and confuse the
3372 ** speed sense algorithm.
3373 */
3374 #define SAMPLE_INTERVAL 500 /* ms */
3375 #define SAMPLE_DELAY 2000 /* ms */
3376 static int
3377 test_for_100Mb(struct device *dev, int msec)
3378 {
3379 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3380 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3381
3382 if (lp->timeout < 0) {
3383 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3384 if (msec > SAMPLE_DELAY) {
3385 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3386 gep = SAMPLE_DELAY | TIMER_CB;
3387 return gep;
3388 } else {
3389 lp->timeout = msec/SAMPLE_INTERVAL;
3390 }
3391 }
3392
3393 if (lp->phy[lp->active].id || lp->useSROM) {
3394 gep = is_100_up(dev) | is_spd_100(dev);
3395 } else {
3396 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3397 }
3398 if (!(gep & ret) && --lp->timeout) {
3399 gep = SAMPLE_INTERVAL | TIMER_CB;
3400 } else {
3401 lp->timeout = -1;
3402 }
3403
3404 return gep;
3405 }
3406
3407 static int
3408 wait_for_link(struct device *dev)
3409 {
3410 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3411
3412 if (lp->timeout < 0) {
3413 lp->timeout = 1;
3414 }
3415
3416 if (lp->timeout--) {
3417 return TIMER_CB;
3418 } else {
3419 lp->timeout = -1;
3420 }
3421
3422 return 0;
3423 }
3424
3425 /*
3426 **
3427 **
3428 */
3429 static int
3430 test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec)
3431 {
3432 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3433 int test;
3434 u_long iobase = dev->base_addr;
3435
3436 if (lp->timeout < 0) {
3437 lp->timeout = msec/100;
3438 }
3439
3440 if (pol) pol = ~0;
3441 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3442 test = (reg ^ pol) & mask;
3443
3444 if (test && --lp->timeout) {
3445 reg = 100 | TIMER_CB;
3446 } else {
3447 lp->timeout = -1;
3448 }
3449
3450 return reg;
3451 }
3452
3453 static int
3454 is_spd_100(struct device *dev)
3455 {
3456 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3457 u_long iobase = dev->base_addr;
3458 int spd;
3459
3460 if (lp->useMII) {
3461 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3462 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3463 spd &= lp->phy[lp->active].spd.mask;
3464 } else if (!lp->useSROM) { /* de500-xa */
3465 spd = ((~gep_rd(dev)) & GEP_SLNK);
3466 } else {
3467 if ((lp->ibn == 2) || !lp->asBitValid)
3468 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3469
3470 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3471 (lp->linkOK & ~lp->asBitValid);
3472 }
3473
3474 return spd;
3475 }
3476
3477 static int
3478 is_100_up(struct device *dev)
3479 {
3480 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3481 u_long iobase = dev->base_addr;
3482
3483 if (lp->useMII) {
3484 /* Double read for sticky bits & temporary drops */
3485 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3486 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3487 } else if (!lp->useSROM) { /* de500-xa */
3488 return ((~gep_rd(dev)) & GEP_SLNK);
3489 } else {
3490 if ((lp->ibn == 2) || !lp->asBitValid)
3491 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3492
3493 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3494 (lp->linkOK & ~lp->asBitValid));
3495 }
3496 }
3497
3498 static int
3499 is_10_up(struct device *dev)
3500 {
3501 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3502 u_long iobase = dev->base_addr;
3503
3504 if (lp->useMII) {
3505 /* Double read for sticky bits & temporary drops */
3506 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3507 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3508 } else if (!lp->useSROM) { /* de500-xa */
3509 return ((~gep_rd(dev)) & GEP_LNP);
3510 } else {
3511 if ((lp->ibn == 2) || !lp->asBitValid)
3512 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3513 (~inl(DE4X5_SISR)&SISR_LS10):
3514 0);
3515
3516 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3517 (lp->linkOK & ~lp->asBitValid));
3518 }
3519 }
3520
3521 static int
3522 is_anc_capable(struct device *dev)
3523 {
3524 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3525 u_long iobase = dev->base_addr;
3526
3527 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3528 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3529 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3530 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3531 } else {
3532 return 0;
3533 }
3534 }
3535
3536 /*
3537 ** Send a packet onto the media and watch for send errors that indicate the
3538 ** media is bad or unconnected.
3539 */
3540 static int
3541 ping_media(struct device *dev, int msec)
3542 {
3543 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3544 u_long iobase = dev->base_addr;
3545 int sisr;
3546
3547 if (lp->timeout < 0) {
3548 lp->timeout = msec/100;
3549
3550 lp->tmp = lp->tx_new; /* Remember the ring position */
3551 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), NULL);
3552 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3553 outl(POLL_DEMAND, DE4X5_TPD);
3554 }
3555
3556 sisr = inl(DE4X5_SISR);
3557
3558 if ((!(sisr & SISR_NCR)) &&
3559 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3560 (--lp->timeout)) {
3561 sisr = 100 | TIMER_CB;
3562 } else {
3563 if ((!(sisr & SISR_NCR)) &&
3564 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3565 lp->timeout) {
3566 sisr = 0;
3567 } else {
3568 sisr = 1;
3569 }
3570 lp->timeout = -1;
3571 }
3572
3573 return sisr;
3574 }
3575
3576 /*
3577 ** This function does 2 things: on Intels it kmalloc's another buffer to
3578 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3579 ** into which the packet is copied.
3580 */
3581 static struct sk_buff *
3582 de4x5_alloc_rx_buff(struct device *dev, int index, int len)
3583 {
3584 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3585 struct sk_buff *p;
3586
3587 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3588 struct sk_buff *ret;
3589 u_long i=0, tmp;
3590
3591 p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3592 if (!p) return NULL;
3593
3594 p->dev = dev;
3595 tmp = virt_to_bus(p->data);
3596 i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3597 skb_reserve(p, i);
3598 lp->rx_ring[index].buf = tmp + i;
3599
3600 ret = lp->rx_skb[index];
3601 lp->rx_skb[index] = p;
3602
3603 if ((u_long) ret > 1) {
3604 skb_put(ret, len);
3605 }
3606
3607 return ret;
3608
3609 #else
3610 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3611
3612 p = dev_alloc_skb(len + 2);
3613 if (!p) return NULL;
3614
3615 p->dev = dev;
3616 skb_reserve(p, 2); /* Align */
3617 if (index < lp->rx_old) { /* Wrapped buffer */
3618 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3619 memcpy(skb_put(p,tlen),
3620 bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),tlen);
3621 memcpy(skb_put(p,len-tlen),
3622 bus_to_virt(le32_to_cpu(lp->rx_ring[0].buf)), len-tlen);
3623 } else { /* Linear buffer */
3624 memcpy(skb_put(p,len),
3625 bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),len);
3626 }
3627
3628 return p;
3629 #endif
3630 }
3631
3632 static void
3633 de4x5_free_rx_buffs(struct device *dev)
3634 {
3635 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3636 int i;
3637
3638 for (i=0; i<lp->rxRingSize; i++) {
3639 if ((u_long) lp->rx_skb[i] > 1) {
3640 dev_kfree_skb(lp->rx_skb[i]);
3641 }
3642 lp->rx_ring[i].status = 0;
3643 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3644 }
3645
3646 return;
3647 }
3648
3649 static void
3650 de4x5_free_tx_buffs(struct device *dev)
3651 {
3652 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3653 int i;
3654
3655 for (i=0; i<lp->txRingSize; i++) {
3656 if (lp->tx_skb[i]) {
3657 dev_kfree_skb(lp->tx_skb[i]);
3658 lp->tx_skb[i] = NULL;
3659 }
3660 lp->tx_ring[i].status = 0;
3661 }
3662
3663 /* Unload the locally queued packets */
3664 while (lp->cache.skb) {
3665 dev_kfree_skb(de4x5_get_cache(dev));
3666 }
3667
3668 return;
3669 }
3670
3671 /*
3672 ** When a user pulls a connection, the DECchip can end up in a
3673 ** 'running - waiting for end of transmission' state. This means that we
3674 ** have to perform a chip soft reset to ensure that we can synchronize
3675 ** the hardware and software and make any media probes using a loopback
3676 ** packet meaningful.
3677 */
3678 static void
3679 de4x5_save_skbs(struct device *dev)
3680 {
3681 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3682 u_long iobase = dev->base_addr;
3683 s32 omr;
3684
3685 if (!lp->cache.save_cnt) {
3686 STOP_DE4X5;
3687 de4x5_tx(dev); /* Flush any sent skb's */
3688 de4x5_free_tx_buffs(dev);
3689 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3690 de4x5_sw_reset(dev);
3691 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3692 lp->cache.save_cnt++;
3693 START_DE4X5;
3694 }
3695
3696 return;
3697 }
3698
3699 static void
3700 de4x5_rst_desc_ring(struct device *dev)
3701 {
3702 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3703 u_long iobase = dev->base_addr;
3704 int i;
3705 s32 omr;
3706
3707 if (lp->cache.save_cnt) {
3708 STOP_DE4X5;
3709 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
3710 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
3711
3712 lp->rx_new = lp->rx_old = 0;
3713 lp->tx_new = lp->tx_old = 0;
3714
3715 for (i = 0; i < lp->rxRingSize; i++) {
3716 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3717 }
3718
3719 for (i = 0; i < lp->txRingSize; i++) {
3720 lp->tx_ring[i].status = cpu_to_le32(0);
3721 }
3722
3723 barrier();
3724 lp->cache.save_cnt--;
3725 START_DE4X5;
3726 }
3727
3728 return;
3729 }
3730
3731 static void
3732 de4x5_cache_state(struct device *dev, int flag)
3733 {
3734 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3735 u_long iobase = dev->base_addr;
3736
3737 switch(flag) {
3738 case DE4X5_SAVE_STATE:
3739 lp->cache.csr0 = inl(DE4X5_BMR);
3740 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3741 lp->cache.csr7 = inl(DE4X5_IMR);
3742 break;
3743
3744 case DE4X5_RESTORE_STATE:
3745 outl(lp->cache.csr0, DE4X5_BMR);
3746 outl(lp->cache.csr6, DE4X5_OMR);
3747 outl(lp->cache.csr7, DE4X5_IMR);
3748 if (lp->chipset == DC21140) {
3749 gep_wr(lp->cache.gepc, dev);
3750 gep_wr(lp->cache.gep, dev);
3751 } else {
3752 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3753 lp->cache.csr15);
3754 }
3755 break;
3756 }
3757
3758 return;
3759 }
3760
3761 static void
3762 de4x5_put_cache(struct device *dev, struct sk_buff *skb)
3763 {
3764 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3765 struct sk_buff *p;
3766
3767 if (lp->cache.skb) {
3768 for (p=lp->cache.skb; p->next; p=p->next);
3769 p->next = skb;
3770 } else {
3771 lp->cache.skb = skb;
3772 }
3773 skb->next = NULL;
3774
3775 return;
3776 }
3777
3778 static void
3779 de4x5_putb_cache(struct device *dev, struct sk_buff *skb)
3780 {
3781 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3782 struct sk_buff *p = lp->cache.skb;
3783
3784 lp->cache.skb = skb;
3785 skb->next = p;
3786
3787 return;
3788 }
3789
3790 static struct sk_buff *
3791 de4x5_get_cache(struct device *dev)
3792 {
3793 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3794 struct sk_buff *p = lp->cache.skb;
3795
3796 if (p) {
3797 lp->cache.skb = p->next;
3798 p->next = NULL;
3799 }
3800
3801 return p;
3802 }
3803
3804 /*
3805 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3806 ** is received and the auto-negotiation status is NWAY OK.
3807 */
3808 static int
3809 test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec)
3810 {
3811 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3812 u_long iobase = dev->base_addr;
3813 s32 sts, ans;
3814
3815 if (lp->timeout < 0) {
3816 lp->timeout = msec/100;
3817 outl(irq_mask, DE4X5_IMR);
3818
3819 /* clear all pending interrupts */
3820 sts = inl(DE4X5_STS);
3821 outl(sts, DE4X5_STS);
3822 }
3823
3824 ans = inl(DE4X5_SISR) & SISR_ANS;
3825 sts = inl(DE4X5_STS) & ~TIMER_CB;
3826
3827 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3828 sts = 100 | TIMER_CB;
3829 } else {
3830 lp->timeout = -1;
3831 }
3832
3833 return sts;
3834 }
3835
3836 static void
3837 de4x5_setup_intr(struct device *dev)
3838 {
3839 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3840 u_long iobase = dev->base_addr;
3841 s32 imr, sts;
3842
3843 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3844 imr = 0;
3845 UNMASK_IRQs;
3846 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3847 outl(sts, DE4X5_STS);
3848 ENABLE_IRQs;
3849 }
3850
3851 return;
3852 }
3853
3854 /*
3855 **
3856 */
3857 static void
3858 reset_init_sia(struct device *dev, s32 csr13, s32 csr14, s32 csr15)
3859 {
3860 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3861 u_long iobase = dev->base_addr;
3862
3863 RESET_SIA;
3864 if (lp->useSROM) {
3865 if (lp->ibn == 3) {
3866 srom_exec(dev, lp->phy[lp->active].rst);
3867 srom_exec(dev, lp->phy[lp->active].gep);
3868 outl(1, DE4X5_SICR);
3869 return;
3870 } else {
3871 csr15 = lp->cache.csr15;
3872 csr14 = lp->cache.csr14;
3873 csr13 = lp->cache.csr13;
3874 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3875 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3876 }
3877 } else {
3878 outl(csr15, DE4X5_SIGR);
3879 }
3880 outl(csr14, DE4X5_STRR);
3881 outl(csr13, DE4X5_SICR);
3882
3883 de4x5_ms_delay(10);
3884
3885 return;
3886 }
3887
3888 /*
3889 ** Create a loopback ethernet packet
3890 */
3891 static void
3892 create_packet(struct device *dev, char *frame, int len)
3893 {
3894 int i;
3895 char *buf = frame;
3896
3897 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3898 *buf++ = dev->dev_addr[i];
3899 }
3900 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3901 *buf++ = dev->dev_addr[i];
3902 }
3903
3904 *buf++ = 0; /* Packet length (2 bytes) */
3905 *buf++ = 1;
3906
3907 return;
3908 }
3909
3910 /*
3911 ** Known delay in microseconds
3912 */
3913 static void
3914 de4x5_us_delay(u32 usec)
3915 {
3916 udelay(usec);
3917
3918 return;
3919 }
3920
3921 /*
3922 ** Known delay in milliseconds, in millisecond steps.
3923 */
3924 static void
3925 de4x5_ms_delay(u32 msec)
3926 {
3927 u_int i;
3928
3929 for (i=0; i<msec; i++) {
3930 de4x5_us_delay(1000);
3931 }
3932
3933 return;
3934 }
3935
3936
3937 /*
3938 ** Look for a particular board name in the EISA configuration space
3939 */
3940 static int
3941 EISA_signature(char *name, s32 eisa_id)
3942 {
3943 static c_char *signatures[] = DE4X5_SIGNATURE;
3944 char ManCode[DE4X5_STRLEN];
3945 union {
3946 s32 ID;
3947 char Id[4];
3948 } Eisa;
3949 int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3950
3951 *name = '\0';
3952 Eisa.ID = inl(eisa_id);
3953
3954 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3955 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3956 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3957 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3958 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3959 ManCode[5]='\0';
3960
3961 for (i=0;i<siglen;i++) {
3962 if (strstr(ManCode, signatures[i]) != NULL) {
3963 strcpy(name,ManCode);
3964 status = 1;
3965 break;
3966 }
3967 }
3968
3969 return status; /* return the device name string */
3970 }
3971
3972 /*
3973 ** Look for a particular board name in the PCI configuration space
3974 */
3975 static int
3976 PCI_signature(char *name, struct bus_type *lp)
3977 {
3978 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
3979 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3980
3981 if (lp->chipset == DC21040) {
3982 strcpy(name, "DE434/5");
3983 return status;
3984 } else { /* Search for a DEC name in the SROM */
3985 int i = *((char *)&lp->srom + 19) * 3;
3986 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3987 }
3988 name[8] = '\0';
3989 for (i=0; i<siglen; i++) {
3990 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3991 }
3992 if (i == siglen) {
3993 if (dec_only) {
3994 *name = '\0';
3995 } else { /* Use chip name to avoid confusion */
3996 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3997 ((lp->chipset == DC21041) ? "DC21041" :
3998 ((lp->chipset == DC21140) ? "DC21140" :
3999 ((lp->chipset == DC21142) ? "DC21142" :
4000 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4001 )))))));
4002 }
4003 if (lp->chipset != DC21041) {
4004 useSROM = TRUE; /* card is not recognisably DEC */
4005 }
4006 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4007 useSROM = TRUE;
4008 }
4009
4010 return status;
4011 }
4012
4013 /*
4014 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4015 ** the DC21040, else read the SROM for the other chips.
4016 ** The SROM may not be present in a multi-MAC card, so first read the
4017 ** MAC address and check for a bad address. If there is a bad one then exit
4018 ** immediately with the prior srom contents intact (the h/w address will
4019 ** be fixed up later).
4020 */
4021 static void
4022 DevicePresent(u_long aprom_addr)
4023 {
4024 int i, j=0;
4025 struct bus_type *lp = &bus;
4026
4027 if (lp->chipset == DC21040) {
4028 if (lp->bus == EISA) {
4029 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4030 } else {
4031 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4032 }
4033 } else { /* Read new srom */
4034 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4035 for (i=0; i<(ETH_ALEN>>1); i++) {
4036 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4037 *p = le16_to_cpu(tmp);
4038 j += *p++;
4039 }
4040 if ((j == 0) || (j == 0x2fffd)) {
4041 return;
4042 }
4043
4044 p=(short *)&lp->srom;
4045 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4046 tmp = srom_rd(aprom_addr, i);
4047 *p++ = le16_to_cpu(tmp);
4048 }
4049 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4050 }
4051
4052 return;
4053 }
4054
4055 /*
4056 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4057 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4058 ** it...from depca.c.
4059 */
4060 static void
4061 enet_addr_rst(u_long aprom_addr)
4062 {
4063 union {
4064 struct {
4065 u32 a;
4066 u32 b;
4067 } llsig;
4068 char Sig[sizeof(u32) << 1];
4069 } dev;
4070 short sigLength=0;
4071 s8 data;
4072 int i, j;
4073
4074 dev.llsig.a = ETH_PROM_SIG;
4075 dev.llsig.b = ETH_PROM_SIG;
4076 sigLength = sizeof(u32) << 1;
4077
4078 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4079 data = inb(aprom_addr);
4080 if (dev.Sig[j] == data) { /* track signature */
4081 j++;
4082 } else { /* lost signature; begin search again */
4083 if (data == dev.Sig[0]) { /* rare case.... */
4084 j=1;
4085 } else {
4086 j=0;
4087 }
4088 }
4089 }
4090
4091 return;
4092 }
4093
4094 /*
4095 ** For the bad status case and no SROM, then add one to the previous
4096 ** address. However, need to add one backwards in case we have 0xff
4097 ** as one or more of the bytes. Only the last 3 bytes should be checked
4098 ** as the first three are invariant - assigned to an organisation.
4099 */
4100 static int
4101 get_hw_addr(struct device *dev)
4102 {
4103 u_long iobase = dev->base_addr;
4104 int broken, i, k, tmp, status = 0;
4105 u_short j,chksum;
4106 struct bus_type *lp = &bus;
4107
4108 broken = de4x5_bad_srom(lp);
4109
4110 for (i=0,k=0,j=0;j<3;j++) {
4111 k <<= 1;
4112 if (k > 0xffff) k-=0xffff;
4113
4114 if (lp->bus == PCI) {
4115 if (lp->chipset == DC21040) {
4116 while ((tmp = inl(DE4X5_APROM)) < 0);
4117 k += (u_char) tmp;
4118 dev->dev_addr[i++] = (u_char) tmp;
4119 while ((tmp = inl(DE4X5_APROM)) < 0);
4120 k += (u_short) (tmp << 8);
4121 dev->dev_addr[i++] = (u_char) tmp;
4122 } else if (!broken) {
4123 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4124 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4125 } else if ((broken == SMC) || (broken == ACCTON)) {
4126 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4127 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4128 }
4129 } else {
4130 k += (u_char) (tmp = inb(EISA_APROM));
4131 dev->dev_addr[i++] = (u_char) tmp;
4132 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4133 dev->dev_addr[i++] = (u_char) tmp;
4134 }
4135
4136 if (k > 0xffff) k-=0xffff;
4137 }
4138 if (k == 0xffff) k=0;
4139
4140 if (lp->bus == PCI) {
4141 if (lp->chipset == DC21040) {
4142 while ((tmp = inl(DE4X5_APROM)) < 0);
4143 chksum = (u_char) tmp;
4144 while ((tmp = inl(DE4X5_APROM)) < 0);
4145 chksum |= (u_short) (tmp << 8);
4146 if ((k != chksum) && (dec_only)) status = -1;
4147 }
4148 } else {
4149 chksum = (u_char) inb(EISA_APROM);
4150 chksum |= (u_short) (inb(EISA_APROM) << 8);
4151 if ((k != chksum) && (dec_only)) status = -1;
4152 }
4153
4154 /* If possible, try to fix a broken card - SMC only so far */
4155 srom_repair(dev, broken);
4156
4157 #ifdef CONFIG_PMAC
4158 /*
4159 ** If the address starts with 00 a0, we have to bit-reverse
4160 ** each byte of the address.
4161 */
4162 if (dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0xa0) {
4163 for (i = 0; i < ETH_ALEN; ++i) {
4164 int x = dev->dev_addr[i];
4165 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4166 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4167 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4168 }
4169 }
4170 #endif /* CONFIG_PMAC */
4171
4172 /* Test for a bad enet address */
4173 status = test_bad_enet(dev, status);
4174
4175 return status;
4176 }
4177
4178 /*
4179 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4180 ** didn't seem to work here...?
4181 */
4182 static int
4183 de4x5_bad_srom(struct bus_type *lp)
4184 {
4185 int i, status = 0;
4186
4187 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4188 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4189 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4190 if (i == 0) {
4191 status = SMC;
4192 } else if (i == 1) {
4193 status = ACCTON;
4194 }
4195 break;
4196 }
4197 }
4198
4199 return status;
4200 }
4201
4202 static int
4203 de4x5_strncmp(char *a, char *b, int n)
4204 {
4205 int ret=0;
4206
4207 for (;n && !ret;n--) {
4208 ret = *a++ - *b++;
4209 }
4210
4211 return ret;
4212 }
4213
4214 static void
4215 srom_repair(struct device *dev, int card)
4216 {
4217 struct bus_type *lp = &bus;
4218
4219 switch(card) {
4220 case SMC:
4221 memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4222 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4223 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4224 useSROM = TRUE;
4225 break;
4226 }
4227
4228 return;
4229 }
4230
4231 /*
4232 ** Assume that the irq's do not follow the PCI spec - this is seems
4233 ** to be true so far (2 for 2).
4234 */
4235 static int
4236 test_bad_enet(struct device *dev, int status)
4237 {
4238 struct bus_type *lp = &bus;
4239 int i, tmp;
4240
4241 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4242 if ((tmp == 0) || (tmp == 0x5fa)) {
4243 if ((lp->chipset == last.chipset) &&
4244 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4245 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4246 for (i=ETH_ALEN-1; i>2; --i) {
4247 dev->dev_addr[i] += 1;
4248 if (dev->dev_addr[i] != 0) break;
4249 }
4250 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4251 if (!an_exception(lp)) {
4252 dev->irq = last.irq;
4253 }
4254
4255 status = 0;
4256 }
4257 } else if (!status) {
4258 last.chipset = lp->chipset;
4259 last.bus = lp->bus_num;
4260 last.irq = dev->irq;
4261 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4262 }
4263
4264 return status;
4265 }
4266
4267 /*
4268 ** List of board exceptions with correctly wired IRQs
4269 */
4270 static int
4271 an_exception(struct bus_type *lp)
4272 {
4273 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4274 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4275 return -1;
4276 }
4277
4278 return 0;
4279 }
4280
4281 /*
4282 ** SROM Read
4283 */
4284 static short
4285 srom_rd(u_long addr, u_char offset)
4286 {
4287 sendto_srom(SROM_RD | SROM_SR, addr);
4288
4289 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4290 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4291 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4292
4293 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4294 }
4295
4296 static void
4297 srom_latch(u_int command, u_long addr)
4298 {
4299 sendto_srom(command, addr);
4300 sendto_srom(command | DT_CLK, addr);
4301 sendto_srom(command, addr);
4302
4303 return;
4304 }
4305
4306 static void
4307 srom_command(u_int command, u_long addr)
4308 {
4309 srom_latch(command, addr);
4310 srom_latch(command, addr);
4311 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4312
4313 return;
4314 }
4315
4316 static void
4317 srom_address(u_int command, u_long addr, u_char offset)
4318 {
4319 int i;
4320 char a;
4321
4322 a = (char)(offset << 2);
4323 for (i=0; i<6; i++, a <<= 1) {
4324 srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
4325 }
4326 de4x5_us_delay(1);
4327
4328 i = (getfrom_srom(addr) >> 3) & 0x01;
4329
4330 return;
4331 }
4332
4333 static short
4334 srom_data(u_int command, u_long addr)
4335 {
4336 int i;
4337 short word = 0;
4338 s32 tmp;
4339
4340 for (i=0; i<16; i++) {
4341 sendto_srom(command | DT_CLK, addr);
4342 tmp = getfrom_srom(addr);
4343 sendto_srom(command, addr);
4344
4345 word = (word << 1) | ((tmp >> 3) & 0x01);
4346 }
4347
4348 sendto_srom(command & 0x0000ff00, addr);
4349
4350 return word;
4351 }
4352
4353 /*
4354 static void
4355 srom_busy(u_int command, u_long addr)
4356 {
4357 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4358
4359 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4360 de4x5_ms_delay(1);
4361 }
4362
4363 sendto_srom(command & 0x0000ff00, addr);
4364
4365 return;
4366 }
4367 */
4368
4369 static void
4370 sendto_srom(u_int command, u_long addr)
4371 {
4372 outl(command, addr);
4373 udelay(1);
4374
4375 return;
4376 }
4377
4378 static int
4379 getfrom_srom(u_long addr)
4380 {
4381 s32 tmp;
4382
4383 tmp = inl(addr);
4384 udelay(1);
4385
4386 return tmp;
4387 }
4388
4389 static int
4390 srom_infoleaf_info(struct device *dev)
4391 {
4392 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4393 int i, count;
4394 u_char *p;
4395
4396 /* Find the infoleaf decoder function that matches this chipset */
4397 for (i=0; i<INFOLEAF_SIZE; i++) {
4398 if (lp->chipset == infoleaf_array[i].chipset) break;
4399 }
4400 if (i == INFOLEAF_SIZE) {
4401 lp->useSROM = FALSE;
4402 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4403 dev->name);
4404 return -ENXIO;
4405 }
4406
4407 lp->infoleaf_fn = infoleaf_array[i].fn;
4408
4409 /* Find the information offset that this function should use */
4410 count = *((u_char *)&lp->srom + 19);
4411 p = (u_char *)&lp->srom + 26;
4412
4413 if (count > 1) {
4414 for (i=count; i; --i, p+=3) {
4415 if (lp->device == *p) break;
4416 }
4417 if (i == 0) {
4418 lp->useSROM = FALSE;
4419 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4420 dev->name, lp->device);
4421 return -ENXIO;
4422 }
4423 }
4424
4425 lp->infoleaf_offset = TWIDDLE(p+1);
4426
4427 return 0;
4428 }
4429
4430 /*
4431 ** This routine loads any type 1 or 3 MII info into the mii device
4432 ** struct and executes any type 5 code to reset PHY devices for this
4433 ** controller.
4434 ** The info for the MII devices will be valid since the index used
4435 ** will follow the discovery process from MII address 1-31 then 0.
4436 */
4437 static void
4438 srom_init(struct device *dev)
4439 {
4440 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4441 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4442 u_char count;
4443
4444 p+=2;
4445 if (lp->chipset == DC21140) {
4446 lp->cache.gepc = (*p++ | GEP_CTRL);
4447 gep_wr(lp->cache.gepc, dev);
4448 }
4449
4450 /* Block count */
4451 count = *p++;
4452
4453 /* Jump the infoblocks to find types */
4454 for (;count; --count) {
4455 if (*p < 128) {
4456 p += COMPACT_LEN;
4457 } else if (*(p+1) == 5) {
4458 type5_infoblock(dev, 1, p);
4459 p += ((*p & BLOCK_LEN) + 1);
4460 } else if (*(p+1) == 4) {
4461 p += ((*p & BLOCK_LEN) + 1);
4462 } else if (*(p+1) == 3) {
4463 type3_infoblock(dev, 1, p);
4464 p += ((*p & BLOCK_LEN) + 1);
4465 } else if (*(p+1) == 2) {
4466 p += ((*p & BLOCK_LEN) + 1);
4467 } else if (*(p+1) == 1) {
4468 type1_infoblock(dev, 1, p);
4469 p += ((*p & BLOCK_LEN) + 1);
4470 } else {
4471 p += ((*p & BLOCK_LEN) + 1);
4472 }
4473 }
4474
4475 return;
4476 }
4477
4478 /*
4479 ** A generic routine that writes GEP control, data and reset information
4480 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4481 */
4482 static void
4483 srom_exec(struct device *dev, u_char *p)
4484 {
4485 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4486 u_long iobase = dev->base_addr;
4487 u_char count = (p ? *p++ : 0);
4488 u_short *w = (u_short *)p;
4489
4490 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4491
4492 if (lp->chipset != DC21140) RESET_SIA;
4493
4494 while (count--) {
4495 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4496 *p++ : TWIDDLE(w++)), dev);
4497 mdelay(2); /* 2ms per action */
4498 }
4499
4500 if (lp->chipset != DC21140) {
4501 outl(lp->cache.csr14, DE4X5_STRR);
4502 outl(lp->cache.csr13, DE4X5_SICR);
4503 }
4504
4505 return;
4506 }
4507
4508 /*
4509 ** Basically this function is a NOP since it will never be called,
4510 ** unless I implement the DC21041 SROM functions. There's no need
4511 ** since the existing code will be satisfactory for all boards.
4512 */
4513 static int
4514 dc21041_infoleaf(struct device *dev)
4515 {
4516 return DE4X5_AUTOSENSE_MS;
4517 }
4518
4519 static int
4520 dc21140_infoleaf(struct device *dev)
4521 {
4522 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4523 u_char count = 0;
4524 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4525 int next_tick = DE4X5_AUTOSENSE_MS;
4526
4527 /* Read the connection type */
4528 p+=2;
4529
4530 /* GEP control */
4531 lp->cache.gepc = (*p++ | GEP_CTRL);
4532
4533 /* Block count */
4534 count = *p++;
4535
4536 /* Recursively figure out the info blocks */
4537 if (*p < 128) {
4538 next_tick = dc_infoblock[COMPACT](dev, count, p);
4539 } else {
4540 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4541 }
4542
4543 if (lp->tcount == count) {
4544 lp->media = NC;
4545 if (lp->media != lp->c_media) {
4546 de4x5_dbg_media(dev);
4547 lp->c_media = lp->media;
4548 }
4549 lp->media = INIT;
4550 lp->tcount = 0;
4551 lp->tx_enable = FALSE;
4552 }
4553
4554 return next_tick & ~TIMER_CB;
4555 }
4556
4557 static int
4558 dc21142_infoleaf(struct device *dev)
4559 {
4560 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4561 u_char count = 0;
4562 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4563 int next_tick = DE4X5_AUTOSENSE_MS;
4564
4565 /* Read the connection type */
4566 p+=2;
4567
4568 /* Block count */
4569 count = *p++;
4570
4571 /* Recursively figure out the info blocks */
4572 if (*p < 128) {
4573 next_tick = dc_infoblock[COMPACT](dev, count, p);
4574 } else {
4575 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4576 }
4577
4578 if (lp->tcount == count) {
4579 lp->media = NC;
4580 if (lp->media != lp->c_media) {
4581 de4x5_dbg_media(dev);
4582 lp->c_media = lp->media;
4583 }
4584 lp->media = INIT;
4585 lp->tcount = 0;
4586 lp->tx_enable = FALSE;
4587 }
4588
4589 return next_tick & ~TIMER_CB;
4590 }
4591
4592 static int
4593 dc21143_infoleaf(struct device *dev)
4594 {
4595 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4596 u_char count = 0;
4597 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4598 int next_tick = DE4X5_AUTOSENSE_MS;
4599
4600 /* Read the connection type */
4601 p+=2;
4602
4603 /* Block count */
4604 count = *p++;
4605
4606 /* Recursively figure out the info blocks */
4607 if (*p < 128) {
4608 next_tick = dc_infoblock[COMPACT](dev, count, p);
4609 } else {
4610 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4611 }
4612 if (lp->tcount == count) {
4613 lp->media = NC;
4614 if (lp->media != lp->c_media) {
4615 de4x5_dbg_media(dev);
4616 lp->c_media = lp->media;
4617 }
4618 lp->media = INIT;
4619 lp->tcount = 0;
4620 lp->tx_enable = FALSE;
4621 }
4622
4623 return next_tick & ~TIMER_CB;
4624 }
4625
4626 /*
4627 ** The compact infoblock is only designed for DC21140[A] chips, so
4628 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4629 */
4630 static int
4631 compact_infoblock(struct device *dev, u_char count, u_char *p)
4632 {
4633 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4634 u_char flags, csr6;
4635
4636 /* Recursively figure out the info blocks */
4637 if (--count > lp->tcount) {
4638 if (*(p+COMPACT_LEN) < 128) {
4639 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4640 } else {
4641 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4642 }
4643 }
4644
4645 if ((lp->media == INIT) && (lp->timeout < 0)) {
4646 lp->ibn = COMPACT;
4647 lp->active = 0;
4648 gep_wr(lp->cache.gepc, dev);
4649 lp->infoblock_media = (*p++) & COMPACT_MC;
4650 lp->cache.gep = *p++;
4651 csr6 = *p++;
4652 flags = *p++;
4653
4654 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4655 lp->defMedium = (flags & 0x40) ? -1 : 0;
4656 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4657 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4658 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4659 lp->useMII = FALSE;
4660
4661 de4x5_switch_mac_port(dev);
4662 }
4663
4664 return dc21140m_autoconf(dev);
4665 }
4666
4667 /*
4668 ** This block describes non MII media for the DC21140[A] only.
4669 */
4670 static int
4671 type0_infoblock(struct device *dev, u_char count, u_char *p)
4672 {
4673 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4674 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4675
4676 /* Recursively figure out the info blocks */
4677 if (--count > lp->tcount) {
4678 if (*(p+len) < 128) {
4679 return dc_infoblock[COMPACT](dev, count, p+len);
4680 } else {
4681 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4682 }
4683 }
4684
4685 if ((lp->media == INIT) && (lp->timeout < 0)) {
4686 lp->ibn = 0;
4687 lp->active = 0;
4688 gep_wr(lp->cache.gepc, dev);
4689 p+=2;
4690 lp->infoblock_media = (*p++) & BLOCK0_MC;
4691 lp->cache.gep = *p++;
4692 csr6 = *p++;
4693 flags = *p++;
4694
4695 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4696 lp->defMedium = (flags & 0x40) ? -1 : 0;
4697 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4698 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4699 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4700 lp->useMII = FALSE;
4701
4702 de4x5_switch_mac_port(dev);
4703 }
4704
4705 return dc21140m_autoconf(dev);
4706 }
4707
4708 /* These functions are under construction! */
4709
4710 static int
4711 type1_infoblock(struct device *dev, u_char count, u_char *p)
4712 {
4713 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4714 u_char len = (*p & BLOCK_LEN)+1;
4715
4716 /* Recursively figure out the info blocks */
4717 if (--count > lp->tcount) {
4718 if (*(p+len) < 128) {
4719 return dc_infoblock[COMPACT](dev, count, p+len);
4720 } else {
4721 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4722 }
4723 }
4724
4725 p += 2;
4726 if (lp->state == INITIALISED) {
4727 lp->ibn = 1;
4728 lp->active = *p++;
4729 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4730 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4731 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4732 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4733 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4734 lp->phy[lp->active].ttm = TWIDDLE(p);
4735 return 0;
4736 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4737 lp->ibn = 1;
4738 lp->active = *p;
4739 lp->infoblock_csr6 = OMR_MII_100;
4740 lp->useMII = TRUE;
4741 lp->infoblock_media = ANS;
4742
4743 de4x5_switch_mac_port(dev);
4744 }
4745
4746 return dc21140m_autoconf(dev);
4747 }
4748
4749 static int
4750 type2_infoblock(struct device *dev, u_char count, u_char *p)
4751 {
4752 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4753 u_char len = (*p & BLOCK_LEN)+1;
4754
4755 /* Recursively figure out the info blocks */
4756 if (--count > lp->tcount) {
4757 if (*(p+len) < 128) {
4758 return dc_infoblock[COMPACT](dev, count, p+len);
4759 } else {
4760 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4761 }
4762 }
4763
4764 if ((lp->media == INIT) && (lp->timeout < 0)) {
4765 lp->ibn = 2;
4766 lp->active = 0;
4767 p += 2;
4768 lp->infoblock_media = (*p) & MEDIA_CODE;
4769
4770 if ((*p++) & EXT_FIELD) {
4771 lp->cache.csr13 = TWIDDLE(p); p += 2;
4772 lp->cache.csr14 = TWIDDLE(p); p += 2;
4773 lp->cache.csr15 = TWIDDLE(p); p += 2;
4774 } else {
4775 lp->cache.csr13 = CSR13;
4776 lp->cache.csr14 = CSR14;
4777 lp->cache.csr15 = CSR15;
4778 }
4779 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4780 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4781 lp->infoblock_csr6 = OMR_SIA;
4782 lp->useMII = FALSE;
4783
4784 de4x5_switch_mac_port(dev);
4785 }
4786
4787 return dc2114x_autoconf(dev);
4788 }
4789
4790 static int
4791 type3_infoblock(struct device *dev, u_char count, u_char *p)
4792 {
4793 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4794 u_char len = (*p & BLOCK_LEN)+1;
4795
4796 /* Recursively figure out the info blocks */
4797 if (--count > lp->tcount) {
4798 if (*(p+len) < 128) {
4799 return dc_infoblock[COMPACT](dev, count, p+len);
4800 } else {
4801 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4802 }
4803 }
4804
4805 p += 2;
4806 if (lp->state == INITIALISED) {
4807 lp->ibn = 3;
4808 lp->active = *p++;
4809 if (MOTO_SROM_BUG) lp->active = 0;
4810 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4811 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4812 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4813 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4814 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4815 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4816 lp->phy[lp->active].mci = *p;
4817 return 0;
4818 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4819 lp->ibn = 3;
4820 lp->active = *p;
4821 lp->infoblock_csr6 = OMR_MII_100;
4822 lp->useMII = TRUE;
4823 lp->infoblock_media = ANS;
4824
4825 de4x5_switch_mac_port(dev);
4826 }
4827
4828 return dc2114x_autoconf(dev);
4829 }
4830
4831 static int
4832 type4_infoblock(struct device *dev, u_char count, u_char *p)
4833 {
4834 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4835 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4836
4837 /* Recursively figure out the info blocks */
4838 if (--count > lp->tcount) {
4839 if (*(p+len) < 128) {
4840 return dc_infoblock[COMPACT](dev, count, p+len);
4841 } else {
4842 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4843 }
4844 }
4845
4846 if ((lp->media == INIT) && (lp->timeout < 0)) {
4847 lp->ibn = 4;
4848 lp->active = 0;
4849 p+=2;
4850 lp->infoblock_media = (*p++) & MEDIA_CODE;
4851 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4852 lp->cache.csr14 = CSR14;
4853 lp->cache.csr15 = CSR15;
4854 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4855 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4856 csr6 = *p++;
4857 flags = *p++;
4858
4859 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4860 lp->defMedium = (flags & 0x40) ? -1 : 0;
4861 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4862 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4863 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4864 lp->useMII = FALSE;
4865
4866 de4x5_switch_mac_port(dev);
4867 }
4868
4869 return dc2114x_autoconf(dev);
4870 }
4871
4872 /*
4873 ** This block type provides information for resetting external devices
4874 ** (chips) through the General Purpose Register.
4875 */
4876 static int
4877 type5_infoblock(struct device *dev, u_char count, u_char *p)
4878 {
4879 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4880 u_char len = (*p & BLOCK_LEN)+1;
4881
4882 /* Recursively figure out the info blocks */
4883 if (--count > lp->tcount) {
4884 if (*(p+len) < 128) {
4885 return dc_infoblock[COMPACT](dev, count, p+len);
4886 } else {
4887 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4888 }
4889 }
4890
4891 /* Must be initializing to run this code */
4892 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4893 p+=2;
4894 lp->rst = p;
4895 srom_exec(dev, lp->rst);
4896 }
4897
4898 return DE4X5_AUTOSENSE_MS;
4899 }
4900
4901 /*
4902 ** MII Read/Write
4903 */
4904
4905 static int
4906 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4907 {
4908 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4909 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4910 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4911 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4912 mii_address(phyreg, ioaddr); /* PHY Register to read */
4913 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4914
4915 return mii_rdata(ioaddr); /* Read data */
4916 }
4917
4918 static void
4919 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4920 {
4921 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4922 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4923 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4924 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4925 mii_address(phyreg, ioaddr); /* PHY Register to write */
4926 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4927 data = mii_swap(data, 16); /* Swap data bit ordering */
4928 mii_wdata(data, 16, ioaddr); /* Write data */
4929
4930 return;
4931 }
4932
4933 static int
4934 mii_rdata(u_long ioaddr)
4935 {
4936 int i;
4937 s32 tmp = 0;
4938
4939 for (i=0; i<16; i++) {
4940 tmp <<= 1;
4941 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4942 }
4943
4944 return tmp;
4945 }
4946
4947 static void
4948 mii_wdata(int data, int len, u_long ioaddr)
4949 {
4950 int i;
4951
4952 for (i=0; i<len; i++) {
4953 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4954 data >>= 1;
4955 }
4956
4957 return;
4958 }
4959
4960 static void
4961 mii_address(u_char addr, u_long ioaddr)
4962 {
4963 int i;
4964
4965 addr = mii_swap(addr, 5);
4966 for (i=0; i<5; i++) {
4967 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4968 addr >>= 1;
4969 }
4970
4971 return;
4972 }
4973
4974 static void
4975 mii_ta(u_long rw, u_long ioaddr)
4976 {
4977 if (rw == MII_STWR) {
4978 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4979 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4980 } else {
4981 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4982 }
4983
4984 return;
4985 }
4986
4987 static int
4988 mii_swap(int data, int len)
4989 {
4990 int i, tmp = 0;
4991
4992 for (i=0; i<len; i++) {
4993 tmp <<= 1;
4994 tmp |= (data & 1);
4995 data >>= 1;
4996 }
4997
4998 return tmp;
4999 }
5000
5001 static void
5002 sendto_mii(u32 command, int data, u_long ioaddr)
5003 {
5004 u32 j;
5005
5006 j = (data & 1) << 17;
5007 outl(command | j, ioaddr);
5008 udelay(1);
5009 outl(command | MII_MDC | j, ioaddr);
5010 udelay(1);
5011
5012 return;
5013 }
5014
5015 static int
5016 getfrom_mii(u32 command, u_long ioaddr)
5017 {
5018 outl(command, ioaddr);
5019 udelay(1);
5020 outl(command | MII_MDC, ioaddr);
5021 udelay(1);
5022
5023 return ((inl(ioaddr) >> 19) & 1);
5024 }
5025
5026 /*
5027 ** Here's 3 ways to calculate the OUI from the ID registers.
5028 */
5029 static int
5030 mii_get_oui(u_char phyaddr, u_long ioaddr)
5031 {
5032 /*
5033 union {
5034 u_short reg;
5035 u_char breg[2];
5036 } a;
5037 int i, r2, r3, ret=0;*/
5038 int r2, r3;
5039
5040 /* Read r2 and r3 */
5041 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5042 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5043 /* SEEQ and Cypress way * /
5044 / * Shuffle r2 and r3 * /
5045 a.reg=0;
5046 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5047 r2 = ((r2>>2)&0x3fff);
5048
5049 / * Bit reverse r3 * /
5050 for (i=0;i<8;i++) {
5051 ret<<=1;
5052 ret |= (r3&1);
5053 r3>>=1;
5054 }
5055
5056 / * Bit reverse r2 * /
5057 for (i=0;i<16;i++) {
5058 a.reg<<=1;
5059 a.reg |= (r2&1);
5060 r2>>=1;
5061 }
5062
5063 / * Swap r2 bytes * /
5064 i=a.breg[0];
5065 a.breg[0]=a.breg[1];
5066 a.breg[1]=i;
5067
5068 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5069 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5070 return r2; /* (I did it) My way */
5071 }
5072
5073 /*
5074 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5075 */
5076 static int
5077 mii_get_phy(struct device *dev)
5078 {
5079 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5080 u_long iobase = dev->base_addr;
5081 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5082 int id;
5083
5084 lp->active = 0;
5085 lp->useMII = TRUE;
5086
5087 /* Search the MII address space for possible PHY devices */
5088 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5089 lp->phy[lp->active].addr = i;
5090 if (i==0) n++; /* Count cycles */
5091 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5092 id = mii_get_oui(i, DE4X5_MII);
5093 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5094 for (j=0; j<limit; j++) { /* Search PHY table */
5095 if (id != phy_info[j].id) continue; /* ID match? */
5096 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5097 if (k < DE4X5_MAX_PHY) {
5098 memcpy((char *)&lp->phy[k],
5099 (char *)&phy_info[j], sizeof(struct phy_table));
5100 lp->phy[k].addr = i;
5101 lp->mii_cnt++;
5102 lp->active++;
5103 } else {
5104 goto purgatory; /* Stop the search */
5105 }
5106 break;
5107 }
5108 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5109 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5110 lp->phy[k].addr = i;
5111 lp->phy[k].id = id;
5112 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5113 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5114 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5115 lp->mii_cnt++;
5116 lp->active++;
5117 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5118 j = de4x5_debug;
5119 de4x5_debug |= DEBUG_MII;
5120 de4x5_dbg_mii(dev, k);
5121 de4x5_debug = j;
5122 printk("\n");
5123 }
5124 }
5125 purgatory:
5126 lp->active = 0;
5127 if (lp->phy[0].id) { /* Reset the PHY devices */
5128 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5129 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5130 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5131
5132 de4x5_dbg_mii(dev, k);
5133 }
5134 }
5135 if (!lp->mii_cnt) lp->useMII = FALSE;
5136
5137 return lp->mii_cnt;
5138 }
5139
5140 static char *
5141 build_setup_frame(struct device *dev, int mode)
5142 {
5143 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5144 int i;
5145 char *pa = lp->setup_frame;
5146
5147 /* Initialise the setup frame */
5148 if (mode == ALL) {
5149 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5150 }
5151
5152 if (lp->setup_f == HASH_PERF) {
5153 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5154 *(pa + i) = dev->dev_addr[i]; /* Host address */
5155 if (i & 0x01) pa += 2;
5156 }
5157 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5158 } else {
5159 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5160 *(pa + (i&1)) = dev->dev_addr[i];
5161 if (i & 0x01) pa += 4;
5162 }
5163 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5164 *(pa + (i&1)) = (char) 0xff;
5165 if (i & 0x01) pa += 4;
5166 }
5167 }
5168
5169 return pa; /* Points to the next entry */
5170 }
5171
5172 static void
5173 enable_ast(struct device *dev, u32 time_out)
5174 {
5175 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5176
5177 return;
5178 }
5179
5180 static void
5181 disable_ast(struct device *dev)
5182 {
5183 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5184
5185 del_timer(&lp->timer);
5186
5187 return;
5188 }
5189
5190 static long
5191 de4x5_switch_mac_port(struct device *dev)
5192 {
5193 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5194 u_long iobase = dev->base_addr;
5195 s32 omr;
5196
5197 STOP_DE4X5;
5198
5199 /* Assert the OMR_PS bit in CSR6 */
5200 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5201 OMR_FDX));
5202 omr |= lp->infoblock_csr6;
5203 if (omr & OMR_PS) omr |= OMR_HBD;
5204 outl(omr, DE4X5_OMR);
5205
5206 /* Soft Reset */
5207 RESET_DE4X5;
5208
5209 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5210 if (lp->chipset == DC21140) {
5211 gep_wr(lp->cache.gepc, dev);
5212 gep_wr(lp->cache.gep, dev);
5213 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5214 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5215 }
5216
5217 /* Restore CSR6 */
5218 outl(omr, DE4X5_OMR);
5219
5220 /* Reset CSR8 */
5221 inl(DE4X5_MFC);
5222
5223 return omr;
5224 }
5225
5226 static void
5227 gep_wr(s32 data, struct device *dev)
5228 {
5229 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5230 u_long iobase = dev->base_addr;
5231
5232 if (lp->chipset == DC21140) {
5233 outl(data, DE4X5_GEP);
5234 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5235 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5236 }
5237
5238 return;
5239 }
5240
5241 static int
5242 gep_rd(struct device *dev)
5243 {
5244 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5245 u_long iobase = dev->base_addr;
5246
5247 if (lp->chipset == DC21140) {
5248 return inl(DE4X5_GEP);
5249 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5250 return (inl(DE4X5_SIGR) & 0x000fffff);
5251 }
5252
5253 return 0;
5254 }
5255
5256 static void
5257 timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5258 {
5259 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5260 int dt;
5261
5262 /* First, cancel any pending timer events */
5263 del_timer(&lp->timer);
5264
5265 /* Convert msec to ticks */
5266 dt = (msec * HZ) / 1000;
5267 if (dt==0) dt=1;
5268
5269 /* Set up timer */
5270 lp->timer.expires = jiffies + dt;
5271 lp->timer.function = fn;
5272 lp->timer.data = data;
5273 add_timer(&lp->timer);
5274
5275 return;
5276 }
5277
5278 static void
5279 yawn(struct device *dev, int state)
5280 {
5281 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5282 u_long iobase = dev->base_addr;
5283
5284 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5285
5286 if(lp->bus == EISA) {
5287 switch(state) {
5288 case WAKEUP:
5289 outb(WAKEUP, PCI_CFPM);
5290 de4x5_ms_delay(10);
5291 break;
5292
5293 case SNOOZE:
5294 outb(SNOOZE, PCI_CFPM);
5295 break;
5296
5297 case SLEEP:
5298 outl(0, DE4X5_SICR);
5299 outb(SLEEP, PCI_CFPM);
5300 break;
5301 }
5302 } else {
5303 switch(state) {
5304 case WAKEUP:
5305 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5306 PCI_CFDA_PSM, WAKEUP);
5307 de4x5_ms_delay(10);
5308 break;
5309
5310 case SNOOZE:
5311 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5312 PCI_CFDA_PSM, SNOOZE);
5313 break;
5314
5315 case SLEEP:
5316 outl(0, DE4X5_SICR);
5317 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5318 PCI_CFDA_PSM, SLEEP);
5319 break;
5320 }
5321 }
5322
5323 return;
5324 }
5325
5326 static void
5327 de4x5_parse_params(struct device *dev)
5328 {
5329 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5330 char *p, *q, t;
5331
5332 lp->params.fdx = 0;
5333 lp->params.autosense = AUTO;
5334
5335 if (args == NULL) return;
5336
5337 if ((p = strstr(args, dev->name))) {
5338 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5339 t = *q;
5340 *q = '\0';
5341
5342 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5343 if (strstr(p, "force_eisa") || strstr(p, "FORCE_EISA")) forceEISA = 1;
5344 #endif
5345 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5346
5347 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5348 if (strstr(p, "TP")) {
5349 lp->params.autosense = TP;
5350 } else if (strstr(p, "TP_NW")) {
5351 lp->params.autosense = TP_NW;
5352 } else if (strstr(p, "BNC")) {
5353 lp->params.autosense = BNC;
5354 } else if (strstr(p, "AUI")) {
5355 lp->params.autosense = AUI;
5356 } else if (strstr(p, "BNC_AUI")) {
5357 lp->params.autosense = BNC;
5358 } else if (strstr(p, "10Mb")) {
5359 lp->params.autosense = _10Mb;
5360 } else if (strstr(p, "100Mb")) {
5361 lp->params.autosense = _100Mb;
5362 } else if (strstr(p, "AUTO")) {
5363 lp->params.autosense = AUTO;
5364 }
5365 }
5366 *q = t;
5367 }
5368
5369 return;
5370 }
5371
5372 static void
5373 de4x5_dbg_open(struct device *dev)
5374 {
5375 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5376 int i;
5377
5378 if (de4x5_debug & DEBUG_OPEN) {
5379 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5380 printk("\tphysical address: ");
5381 for (i=0;i<6;i++) {
5382 printk("%2.2x:",(short)dev->dev_addr[i]);
5383 }
5384 printk("\n");
5385 printk("Descriptor head addresses:\n");
5386 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5387 printk("Descriptor addresses:\nRX: ");
5388 for (i=0;i<lp->rxRingSize-1;i++){
5389 if (i < 3) {
5390 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5391 }
5392 }
5393 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5394 printk("TX: ");
5395 for (i=0;i<lp->txRingSize-1;i++){
5396 if (i < 3) {
5397 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5398 }
5399 }
5400 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5401 printk("Descriptor buffers:\nRX: ");
5402 for (i=0;i<lp->rxRingSize-1;i++){
5403 if (i < 3) {
5404 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5405 }
5406 }
5407 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5408 printk("TX: ");
5409 for (i=0;i<lp->txRingSize-1;i++){
5410 if (i < 3) {
5411 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5412 }
5413 }
5414 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5415 printk("Ring size: \nRX: %d\nTX: %d\n",
5416 (short)lp->rxRingSize,
5417 (short)lp->txRingSize);
5418 }
5419
5420 return;
5421 }
5422
5423 static void
5424 de4x5_dbg_mii(struct device *dev, int k)
5425 {
5426 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5427 u_long iobase = dev->base_addr;
5428
5429 if (de4x5_debug & DEBUG_MII) {
5430 printk("\nMII device address: %d\n", lp->phy[k].addr);
5431 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5432 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5433 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5435 if (lp->phy[k].id != BROADCOM_T4) {
5436 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5437 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5438 }
5439 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5440 if (lp->phy[k].id != BROADCOM_T4) {
5441 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5442 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5443 } else {
5444 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5445 }
5446 }
5447
5448 return;
5449 }
5450
5451 static void
5452 de4x5_dbg_media(struct device *dev)
5453 {
5454 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5455
5456 if (lp->media != lp->c_media) {
5457 if (de4x5_debug & DEBUG_MEDIA) {
5458 printk("%s: media is %s%s\n", dev->name,
5459 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5460 (lp->media == TP ? "TP" :
5461 (lp->media == ANS ? "TP/Nway" :
5462 (lp->media == BNC ? "BNC" :
5463 (lp->media == AUI ? "AUI" :
5464 (lp->media == BNC_AUI ? "BNC/AUI" :
5465 (lp->media == EXT_SIA ? "EXT SIA" :
5466 (lp->media == _100Mb ? "100Mb/s" :
5467 (lp->media == _10Mb ? "10Mb/s" :
5468 "???"
5469 ))))))))), (lp->fdx?" full duplex.":"."));
5470 }
5471 lp->c_media = lp->media;
5472 }
5473
5474 return;
5475 }
5476
5477 static void
5478 de4x5_dbg_srom(struct de4x5_srom *p)
5479 {
5480 int i;
5481
5482 if (de4x5_debug & DEBUG_SROM) {
5483 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5484 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5485 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5486 printk("SROM version: %02x\n", (u_char)(p->version));
5487 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5488
5489 printk("Hardware Address: ");
5490 for (i=0;i<ETH_ALEN-1;i++) {
5491 printk("%02x:", (u_char)*(p->ieee_addr+i));
5492 }
5493 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5494 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5495 for (i=0; i<64; i++) {
5496 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5497 }
5498 }
5499
5500 return;
5501 }
5502
5503 static void
5504 de4x5_dbg_rx(struct sk_buff *skb, int len)
5505 {
5506 int i, j;
5507
5508 if (de4x5_debug & DEBUG_RX) {
5509 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5510 (u_char)skb->data[0],
5511 (u_char)skb->data[1],
5512 (u_char)skb->data[2],
5513 (u_char)skb->data[3],
5514 (u_char)skb->data[4],
5515 (u_char)skb->data[5],
5516 (u_char)skb->data[6],
5517 (u_char)skb->data[7],
5518 (u_char)skb->data[8],
5519 (u_char)skb->data[9],
5520 (u_char)skb->data[10],
5521 (u_char)skb->data[11],
5522 (u_char)skb->data[12],
5523 (u_char)skb->data[13],
5524 len);
5525 if (de4x5_debug & DEBUG_RX) {
5526 for (j=0; len>0;j+=16, len-=16) {
5527 printk(" %03x: ",j);
5528 for (i=0; i<16 && i<len; i++) {
5529 printk("%02x ",(u_char)skb->data[i+j]);
5530 }
5531 printk("\n");
5532 }
5533 }
5534 }
5535
5536 return;
5537 }
5538
5539 /*
5540 ** Perform IOCTL call functions here. Some are privileged operations and the
5541 ** effective uid is checked in those cases. In the normal course of events
5542 ** this function is only used for my testing.
5543 */
5544 static int
5545 de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
5546 {
5547 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5548 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5549 u_long iobase = dev->base_addr;
5550 int i, j, status = 0;
5551 s32 omr;
5552 union {
5553 u8 addr[144];
5554 u16 sval[72];
5555 u32 lval[36];
5556 } tmp;
5557 u_long flags = 0;
5558
5559 switch(ioc->cmd) {
5560 case DE4X5_GET_HWADDR: /* Get the hardware address */
5561 ioc->len = ETH_ALEN;
5562 for (i=0; i<ETH_ALEN; i++) {
5563 tmp.addr[i] = dev->dev_addr[i];
5564 }
5565 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5566 break;
5567
5568 case DE4X5_SET_HWADDR: /* Set the hardware address */
5569 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5570 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5571 for (i=0; i<ETH_ALEN; i++) {
5572 dev->dev_addr[i] = tmp.addr[i];
5573 }
5574 build_setup_frame(dev, PHYS_ADDR_ONLY);
5575 /* Set up the descriptor and give ownership to the card */
5576 while (test_and_set_bit(0, (void *)&dev->tbusy) != 0) barrier();
5577 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5578 SETUP_FRAME_LEN, NULL);
5579 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5580 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5581 dev->tbusy = 0; /* Unlock the TX ring */
5582 break;
5583
5584 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5585 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5586 omr = inl(DE4X5_OMR);
5587 omr |= OMR_PR;
5588 outl(omr, DE4X5_OMR);
5589 dev->flags |= IFF_PROMISC;
5590 break;
5591
5592 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5593 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5594 omr = inl(DE4X5_OMR);
5595 omr &= ~OMR_PR;
5596 outb(omr, DE4X5_OMR);
5597 dev->flags &= ~IFF_PROMISC;
5598 break;
5599
5600 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5601 printk("%s: Boo!\n", dev->name);
5602 break;
5603
5604 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5605 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5606 omr = inl(DE4X5_OMR);
5607 omr |= OMR_PM;
5608 outl(omr, DE4X5_OMR);
5609 break;
5610
5611 case DE4X5_GET_STATS: /* Get the driver statistics */
5612 ioc->len = sizeof(lp->pktStats);
5613 spin_lock_irqsave(&lp->lock, flags);
5614 if (copy_to_user(ioc->data, &lp->pktStats, ioc->len)) return -EFAULT;
5615 spin_unlock_irqrestore(&lp->lock, flags);
5616 break;
5617
5618 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5619 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5620 spin_lock_irqsave(&lp->lock, flags);
5621 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5622 spin_unlock_irqrestore(&lp->lock, flags);
5623 break;
5624
5625 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5626 tmp.addr[0] = inl(DE4X5_OMR);
5627 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5628 break;
5629
5630 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5631 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5632 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5633 outl(tmp.addr[0], DE4X5_OMR);
5634 break;
5635
5636 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5637 j = 0;
5638 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5639 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5640 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5641 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5642 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5643 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5644 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5645 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5646 ioc->len = j;
5647 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5648 break;
5649
5650 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5651 /*
5652 case DE4X5_DUMP:
5653 j = 0;
5654 tmp.addr[j++] = dev->irq;
5655 for (i=0; i<ETH_ALEN; i++) {
5656 tmp.addr[j++] = dev->dev_addr[i];
5657 }
5658 tmp.addr[j++] = lp->rxRingSize;
5659 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5660 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5661
5662 for (i=0;i<lp->rxRingSize-1;i++){
5663 if (i < 3) {
5664 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5665 }
5666 }
5667 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5668 for (i=0;i<lp->txRingSize-1;i++){
5669 if (i < 3) {
5670 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5671 }
5672 }
5673 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5674
5675 for (i=0;i<lp->rxRingSize-1;i++){
5676 if (i < 3) {
5677 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5678 }
5679 }
5680 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5681 for (i=0;i<lp->txRingSize-1;i++){
5682 if (i < 3) {
5683 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5684 }
5685 }
5686 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5687
5688 for (i=0;i<lp->rxRingSize;i++){
5689 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5690 }
5691 for (i=0;i<lp->txRingSize;i++){
5692 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5693 }
5694
5695 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5696 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5697 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5698 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5699 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5700 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5701 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5702 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5703 tmp.lval[j>>2] = lp->chipset; j+=4;
5704 if (lp->chipset == DC21140) {
5705 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5706 } else {
5707 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5708 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5709 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5710 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5711 }
5712 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5713 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5714 tmp.lval[j>>2] = lp->active; j+=4;
5715 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5716 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5717 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5718 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5719 if (lp->phy[lp->active].id != BROADCOM_T4) {
5720 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5721 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5722 }
5723 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5724 if (lp->phy[lp->active].id != BROADCOM_T4) {
5725 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5726 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5727 } else {
5728 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5729 }
5730 }
5731
5732 tmp.addr[j++] = lp->txRingSize;
5733 tmp.addr[j++] = dev->tbusy;
5734
5735 ioc->len = j;
5736 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5737 break;
5738
5739 */
5740 default:
5741 return -EOPNOTSUPP;
5742 }
5743
5744 return status;
5745 }
5746
5747 #ifdef MODULE
5748 /*
5749 ** Note now that module autoprobing is allowed under EISA and PCI. The
5750 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5751 ** to "do the right thing".
5752 */
5753 #define LP(a) ((struct de4x5_private *)(a))
5754 static struct device *mdev = NULL;
5755 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5756 MODULE_PARM(io, "i");
5757
5758 int
5759 init_module(void)
5760 {
5761 int i, num, status = -EIO;
5762 struct device *p;
5763
5764 num = count_adapters();
5765
5766 for (i=0; i<num; i++) {
5767 if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5768 return -ENOMEM;
5769
5770 if (!mdev) mdev = p;
5771
5772 if (register_netdev(p) != 0) {
5773 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5774 if (lp) {
5775 release_region(p->base_addr, (lp->bus == PCI ?
5776 DE4X5_PCI_TOTAL_SIZE :
5777 DE4X5_EISA_TOTAL_SIZE));
5778 if (lp->cache.buf) { /* MAC buffers allocated? */
5779 kfree(lp->cache.buf); /* Free the MAC buffers */
5780 }
5781 if (lp->cache.priv) { /* Private area allocated? */
5782 kfree(lp->cache.priv); /* Free the private area */
5783 }
5784 }
5785 kfree(p);
5786 } else {
5787 status = 0; /* At least one adapter will work */
5788 lastModule = p;
5789 }
5790 }
5791
5792 return status;
5793 }
5794
5795 void
5796 cleanup_module(void)
5797 {
5798 while (mdev != NULL) {
5799 mdev = unlink_modules(mdev);
5800 }
5801
5802 return;
5803 }
5804
5805 static struct device *
5806 unlink_modules(struct device *p)
5807 {
5808 struct device *next = NULL;
5809
5810 if (p->priv) { /* Private areas allocated? */
5811 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5812
5813 next = lp->next_module;
5814 if (lp->cache.buf) { /* MAC buffers allocated? */
5815 kfree(lp->cache.buf); /* Free the MAC buffers */
5816 }
5817 release_region(p->base_addr, (lp->bus == PCI ?
5818 DE4X5_PCI_TOTAL_SIZE :
5819 DE4X5_EISA_TOTAL_SIZE));
5820 kfree(lp->cache.priv); /* Free the private area */
5821 }
5822 unregister_netdev(p);
5823 kfree(p); /* Free the device structure */
5824
5825 return next;
5826 }
5827
5828 static int
5829 count_adapters(void)
5830 {
5831 int i, j=0;
5832 u_short vendor;
5833 u_int class = DE4X5_CLASS_CODE;
5834 u_int device;
5835
5836 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5837 char name[DE4X5_STRLEN];
5838 u_long iobase = 0x1000;
5839
5840 for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5841 if (EISA_signature(name, EISA_ID)) j++;
5842 }
5843 #endif
5844 if (!pcibios_present()) return j;
5845
5846 for (i=0; (pdev=pci_find_class(class, pdev))!= NULL; i++) {
5847 vendor = pdev->vendor;
5848 device = pdev->device << 8;
5849 if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5850 }
5851
5852 return j;
5853 }
5854
5855 /*
5856 ** If at end of eth device list and can't use current entry, malloc
5857 ** one up. If memory could not be allocated, print an error message.
5858 */
5859 static struct device * __init
5860 insert_device(struct device *dev, u_long iobase, int (*init)(struct device *))
5861 {
5862 struct device *new;
5863
5864 new = (struct device *)kmalloc(sizeof(struct device)+8, GFP_KERNEL);
5865 if (new == NULL) {
5866 printk("de4x5.c: Device not initialised, insufficient memory\n");
5867 return NULL;
5868 } else {
5869 memset((char *)new, 0, sizeof(struct device)+8);
5870 new->name = (char *)(new + 1);
5871 new->base_addr = iobase; /* assign the io address */
5872 new->init = init; /* initialisation routine */
5873 }
5874
5875 return new;
5876 }
5877
5878 #endif /* MODULE */
5879
5880 \f
5881 /*
5882 * Local variables:
5883 * compile-command: "gcc -D__KERNEL__ -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5884 *
5885 * Delete -D__SMP__ below if you didn't define this in your kernel
5886 * Delete -DMODVERSIONS below if you didn't define this in your kernel
5887 *
5888 * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -DMODVERSIONS -include /linux/include/linux/modversions.h -c de4x5.c"
5889 * End:
5890 */
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