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Ok. I didn't make 2.4.0 in 2000. Tough. I tried, but we had some
[davej-history.git] / drivers / net / de4x5.c
blobb8e1e297d5626603b11e1f62eaf8e704847dcd13
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
238 TO DO:
239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
245
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the SA_SHIRQ flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added SA_INTERRUPT temporary fix from
357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
369 problem reports by
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432
433 =========================================================================
434 */
435
436 static const char *version = "de4x5.c:V0.545 1999/11/28 davies@maniac.ultranet.com\n";
437
438 #include <linux/config.h>
439 #include <linux/module.h>
440
441 #include <linux/kernel.h>
442 #include <linux/sched.h>
443 #include <linux/string.h>
444 #include <linux/interrupt.h>
445 #include <linux/ptrace.h>
446 #include <linux/errno.h>
447 #include <linux/ioport.h>
448 #include <linux/malloc.h>
449 #include <linux/pci.h>
450 #include <linux/delay.h>
451 #include <linux/init.h>
452 #include <linux/version.h>
453 #include <linux/spinlock.h>
454
455 #include <asm/bitops.h>
456 #include <asm/io.h>
457 #include <asm/dma.h>
458 #include <asm/byteorder.h>
459 #include <asm/unaligned.h>
460 #include <asm/uaccess.h>
461 #ifdef CONFIG_PPC
462 #include <asm/machdep.h>
463 #endif /* CONFIG_PPC */
464
465 #include <linux/netdevice.h>
466 #include <linux/etherdevice.h>
467 #include <linux/skbuff.h>
468
469 #include <linux/time.h>
470 #include <linux/types.h>
471 #include <linux/unistd.h>
472 #include <linux/ctype.h>
473
474 #include "de4x5.h"
475
476 #define c_char const char
477 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
478
479 /*
480 ** MII Information
481 */
482 struct phy_table {
483 int reset; /* Hard reset required? */
484 int id; /* IEEE OUI */
485 int ta; /* One cycle TA time - 802.3u is confusing here */
486 struct { /* Non autonegotiation (parallel) speed det. */
487 int reg;
488 int mask;
489 int value;
490 } spd;
491 };
492
493 struct mii_phy {
494 int reset; /* Hard reset required? */
495 int id; /* IEEE OUI */
496 int ta; /* One cycle TA time */
497 struct { /* Non autonegotiation (parallel) speed det. */
498 int reg;
499 int mask;
500 int value;
501 } spd;
502 int addr; /* MII address for the PHY */
503 u_char *gep; /* Start of GEP sequence block in SROM */
504 u_char *rst; /* Start of reset sequence in SROM */
505 u_int mc; /* Media Capabilities */
506 u_int ana; /* NWay Advertisement */
507 u_int fdx; /* Full DupleX capabilites for each media */
508 u_int ttm; /* Transmit Threshold Mode for each media */
509 u_int mci; /* 21142 MII Connector Interrupt info */
510 };
511
512 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
513
514 struct sia_phy {
515 u_char mc; /* Media Code */
516 u_char ext; /* csr13-15 valid when set */
517 int csr13; /* SIA Connectivity Register */
518 int csr14; /* SIA TX/RX Register */
519 int csr15; /* SIA General Register */
520 int gepc; /* SIA GEP Control Information */
521 int gep; /* SIA GEP Data */
522 };
523
524 /*
525 ** Define the know universe of PHY devices that can be
526 ** recognised by this driver.
527 */
528 static struct phy_table phy_info[] = {
529 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
530 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
531 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
532 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
533 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
534 };
535
536 /*
537 ** These GENERIC values assumes that the PHY devices follow 802.3u and
538 ** allow parallel detection to set the link partner ability register.
539 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
540 */
541 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
542 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
543 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
544
545 /*
546 ** Define special SROM detection cases
547 */
548 static c_char enet_det[][ETH_ALEN] = {
549 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
550 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
551 };
552
553 #define SMC 1
554 #define ACCTON 2
555
556 /*
557 ** SROM Repair definitions. If a broken SROM is detected a card may
558 ** use this information to help figure out what to do. This is a
559 ** "stab in the dark" and so far for SMC9332's only.
560 */
561 static c_char srom_repair_info[][100] = {
562 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
563 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
564 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
565 0x00,0x18,}
566 };
567
568
569 #ifdef DE4X5_DEBUG
570 static int de4x5_debug = DE4X5_DEBUG;
571 #else
572 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
573 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
574 #endif
575
576 /*
577 ** Allow per adapter set up. For modules this is simply a command line
578 ** parameter, e.g.:
579 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
580 **
581 ** For a compiled in driver, place e.g.
582 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
583 ** here
584 */
585 #ifdef DE4X5_PARM
586 static char *args = DE4X5_PARM;
587 #else
588 static char *args = NULL;
589 #endif
590
591 struct parameters {
592 int fdx;
593 int autosense;
594 };
595
596 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
597
598 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
599
600 /*
601 ** Ethernet PROM defines
602 */
603 #define PROBE_LENGTH 32
604 #define ETH_PROM_SIG 0xAA5500FFUL
605
606 /*
607 ** Ethernet Info
608 */
609 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
610 #define IEEE802_3_SZ 1518 /* Packet + CRC */
611 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
612 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
613 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
614 #define PKT_HDR_LEN 14 /* Addresses and data length info */
615 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
616 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
617
618
619 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
620 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
621
622 /*
623 ** EISA bus defines
624 */
625 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
626 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
627
628 #define MAX_EISA_SLOTS 16
629 #define EISA_SLOT_INC 0x1000
630 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
631
632 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
633 #define DE4X5_NAME_LENGTH 8
634
635 /*
636 ** Ethernet PROM defines for DC21040
637 */
638 #define PROBE_LENGTH 32
639 #define ETH_PROM_SIG 0xAA5500FFUL
640
641 /*
642 ** PCI Bus defines
643 */
644 #define PCI_MAX_BUS_NUM 8
645 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
646 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
647 #define NO_MORE_PCI -2 /* PCI bus search all done */
648
649 /*
650 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
651 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
652 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
653 ** and hence the RX descriptor ring's first entry.
654 */
655 #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
656 #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
657 #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
658 #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
659 #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
660 #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
661
662 #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
663 #define CACHE_ALIGN CAL_16LONG
664 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
665 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
666 #define DESC_ALIGN
667
668 #ifndef DEC_ONLY /* See README.de4x5 for using this */
669 static int dec_only = 0;
670 #else
671 static int dec_only = 1;
672 #endif
673
674 /*
675 ** DE4X5 IRQ ENABLE/DISABLE
676 */
677 #define ENABLE_IRQs { \
678 imr |= lp->irq_en;\
679 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
680 }
681
682 #define DISABLE_IRQs {\
683 imr = inl(DE4X5_IMR);\
684 imr &= ~lp->irq_en;\
685 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
686 }
687
688 #define UNMASK_IRQs {\
689 imr |= lp->irq_mask;\
690 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
691 }
692
693 #define MASK_IRQs {\
694 imr = inl(DE4X5_IMR);\
695 imr &= ~lp->irq_mask;\
696 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
697 }
698
699 /*
700 ** DE4X5 START/STOP
701 */
702 #define START_DE4X5 {\
703 omr = inl(DE4X5_OMR);\
704 omr |= OMR_ST | OMR_SR;\
705 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
706 }
707
708 #define STOP_DE4X5 {\
709 omr = inl(DE4X5_OMR);\
710 omr &= ~(OMR_ST|OMR_SR);\
711 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
712 }
713
714 /*
715 ** DE4X5 SIA RESET
716 */
717 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
718
719 /*
720 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
721 */
722 #define DE4X5_AUTOSENSE_MS 250
723
724 /*
725 ** SROM Structure
726 */
727 struct de4x5_srom {
728 char sub_vendor_id[2];
729 char sub_system_id[2];
730 char reserved[12];
731 char id_block_crc;
732 char reserved2;
733 char version;
734 char num_controllers;
735 char ieee_addr[6];
736 char info[100];
737 short chksum;
738 };
739 #define SUB_VENDOR_ID 0x500a
740
741 /*
742 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
743 ** and have sizes of both a power of 2 and a multiple of 4.
744 ** A size of 256 bytes for each buffer could be chosen because over 90% of
745 ** all packets in our network are <256 bytes long and 64 longword alignment
746 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
747 ** descriptors are needed for machines with an ALPHA CPU.
748 */
749 #define NUM_RX_DESC 8 /* Number of RX descriptors */
750 #define NUM_TX_DESC 32 /* Number of TX descriptors */
751 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
752 /* Multiple of 4 for DC21040 */
753 /* Allows 512 byte alignment */
754 struct de4x5_desc {
755 volatile s32 status;
756 u32 des1;
757 u32 buf;
758 u32 next;
759 DESC_ALIGN
760 };
761
762 /*
763 ** The DE4X5 private structure
764 */
765 #define DE4X5_PKT_STAT_SZ 16
766 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
767 increase DE4X5_PKT_STAT_SZ */
768
769 struct pkt_stats {
770 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
771 u_int unicast;
772 u_int multicast;
773 u_int broadcast;
774 u_int excessive_collisions;
775 u_int tx_underruns;
776 u_int excessive_underruns;
777 u_int rx_runt_frames;
778 u_int rx_collision;
779 u_int rx_dribble;
780 u_int rx_overflow;
781 };
782
783 struct de4x5_private {
784 char adapter_name[80]; /* Adapter name */
785 u_long interrupt; /* Aligned ISR flag */
786 struct de4x5_desc *rx_ring; /* RX descriptor ring */
787 struct de4x5_desc *tx_ring; /* TX descriptor ring */
788 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
789 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
790 int rx_new, rx_old; /* RX descriptor ring pointers */
791 int tx_new, tx_old; /* TX descriptor ring pointers */
792 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
793 char frame[64]; /* Min sized packet for loopback*/
794 spinlock_t lock; /* Adapter specific spinlock */
795 struct net_device_stats stats; /* Public stats */
796 struct pkt_stats pktStats; /* Private stats counters */
797 char rxRingSize;
798 char txRingSize;
799 int bus; /* EISA or PCI */
800 int bus_num; /* PCI Bus number */
801 int device; /* Device number on PCI bus */
802 int state; /* Adapter OPENED or CLOSED */
803 int chipset; /* DC21040, DC21041 or DC21140 */
804 s32 irq_mask; /* Interrupt Mask (Enable) bits */
805 s32 irq_en; /* Summary interrupt bits */
806 int media; /* Media (eg TP), mode (eg 100B)*/
807 int c_media; /* Remember the last media conn */
808 int fdx; /* media full duplex flag */
809 int linkOK; /* Link is OK */
810 int autosense; /* Allow/disallow autosensing */
811 int tx_enable; /* Enable descriptor polling */
812 int setup_f; /* Setup frame filtering type */
813 int local_state; /* State within a 'media' state */
814 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
815 struct sia_phy sia; /* SIA PHY Information */
816 int active; /* Index to active PHY device */
817 int mii_cnt; /* Number of attached PHY's */
818 int timeout; /* Scheduling counter */
819 struct timer_list timer; /* Timer info for kernel */
820 int tmp; /* Temporary global per card */
821 struct {
822 void *priv; /* Original kmalloc'd mem addr */
823 u_long lock; /* Lock the cache accesses */
824 s32 csr0; /* Saved Bus Mode Register */
825 s32 csr6; /* Saved Operating Mode Reg. */
826 s32 csr7; /* Saved IRQ Mask Register */
827 s32 gep; /* Saved General Purpose Reg. */
828 s32 gepc; /* Control info for GEP */
829 s32 csr13; /* Saved SIA Connectivity Reg. */
830 s32 csr14; /* Saved SIA TX/RX Register */
831 s32 csr15; /* Saved SIA General Register */
832 int save_cnt; /* Flag if state already saved */
833 struct sk_buff *skb; /* Save the (re-ordered) skb's */
834 } cache;
835 struct de4x5_srom srom; /* A copy of the SROM */
836 struct net_device *next_module; /* Link to the next module */
837 int rx_ovf; /* Check for 'RX overflow' tag */
838 int useSROM; /* For non-DEC card use SROM */
839 int useMII; /* Infoblock using the MII */
840 int asBitValid; /* Autosense bits in GEP? */
841 int asPolarity; /* 0 => asserted high */
842 int asBit; /* Autosense bit number in GEP */
843 int defMedium; /* SROM default medium */
844 int tcount; /* Last infoblock number */
845 int infoblock_init; /* Initialised this infoblock? */
846 int infoleaf_offset; /* SROM infoleaf for controller */
847 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
848 int infoblock_media; /* infoblock media */
849 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
850 u_char *rst; /* Pointer to Type 5 reset info */
851 u_char ibn; /* Infoblock number */
852 struct parameters params; /* Command line/ #defined params */
853 struct pci_dev *pdev; /* Device cookie for DMA alloc */
854 dma_addr_t dma_rings; /* DMA handle for rings */
855 int dma_size; /* Size of the DMA area */
856 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
857 };
858
859 /*
860 ** Kludge to get around the fact that the CSR addresses have different
861 ** offsets in the PCI and EISA boards. Also note that the ethernet address
862 ** PROM is accessed differently.
863 */
864 static struct bus_type {
865 int bus;
866 int bus_num;
867 int device;
868 int chipset;
869 struct de4x5_srom srom;
870 int autosense;
871 int useSROM;
872 } bus;
873
874 /*
875 ** To get around certain poxy cards that don't provide an SROM
876 ** for the second and more DECchip, I have to key off the first
877 ** chip's address. I'll assume there's not a bad SROM iff:
878 **
879 ** o the chipset is the same
880 ** o the bus number is the same and > 0
881 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
882 **
883 ** Also have to save the irq for those cards whose hardware designers
884 ** can't follow the PCI to PCI Bridge Architecture spec.
885 */
886 static struct {
887 int chipset;
888 int bus;
889 int irq;
890 u_char addr[ETH_ALEN];
891 } last = {0,};
892
893 /*
894 ** The transmit ring full condition is described by the tx_old and tx_new
895 ** pointers by:
896 ** tx_old = tx_new Empty ring
897 ** tx_old = tx_new+1 Full ring
898 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
899 */
900 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
901 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
902 lp->tx_old -lp->tx_new-1)
903
904 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
905
906 /*
907 ** Public Functions
908 */
909 static int de4x5_open(struct net_device *dev);
910 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
911 static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
912 static int de4x5_close(struct net_device *dev);
913 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
914 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
915 static void set_multicast_list(struct net_device *dev);
916 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
917
918 /*
919 ** Private functions
920 */
921 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct pci_dev *pdev);
922 static int de4x5_init(struct net_device *dev);
923 static int de4x5_sw_reset(struct net_device *dev);
924 static int de4x5_rx(struct net_device *dev);
925 static int de4x5_tx(struct net_device *dev);
926 static int de4x5_ast(struct net_device *dev);
927 static int de4x5_txur(struct net_device *dev);
928 static int de4x5_rx_ovfc(struct net_device *dev);
929
930 static int autoconf_media(struct net_device *dev);
931 static void create_packet(struct net_device *dev, char *frame, int len);
932 static void de4x5_us_delay(u32 usec);
933 static void de4x5_ms_delay(u32 msec);
934 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
935 static int dc21040_autoconf(struct net_device *dev);
936 static int dc21041_autoconf(struct net_device *dev);
937 static int dc21140m_autoconf(struct net_device *dev);
938 static int dc2114x_autoconf(struct net_device *dev);
939 static int srom_autoconf(struct net_device *dev);
940 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
941 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
942 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
943 static int test_for_100Mb(struct net_device *dev, int msec);
944 static int wait_for_link(struct net_device *dev);
945 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
946 static int is_spd_100(struct net_device *dev);
947 static int is_100_up(struct net_device *dev);
948 static int is_10_up(struct net_device *dev);
949 static int is_anc_capable(struct net_device *dev);
950 static int ping_media(struct net_device *dev, int msec);
951 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
952 static void de4x5_free_rx_buffs(struct net_device *dev);
953 static void de4x5_free_tx_buffs(struct net_device *dev);
954 static void de4x5_save_skbs(struct net_device *dev);
955 static void de4x5_rst_desc_ring(struct net_device *dev);
956 static void de4x5_cache_state(struct net_device *dev, int flag);
957 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
958 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
959 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
960 static void de4x5_setup_intr(struct net_device *dev);
961 static void de4x5_init_connection(struct net_device *dev);
962 static int de4x5_reset_phy(struct net_device *dev);
963 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
964 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
965 static int test_tp(struct net_device *dev, s32 msec);
966 static int EISA_signature(char *name, s32 eisa_id);
967 static int PCI_signature(char *name, struct bus_type *lp);
968 static void DevicePresent(u_long iobase);
969 static void enet_addr_rst(u_long aprom_addr);
970 static int de4x5_bad_srom(struct bus_type *lp);
971 static short srom_rd(u_long address, u_char offset);
972 static void srom_latch(u_int command, u_long address);
973 static void srom_command(u_int command, u_long address);
974 static void srom_address(u_int command, u_long address, u_char offset);
975 static short srom_data(u_int command, u_long address);
976 /*static void srom_busy(u_int command, u_long address);*/
977 static void sendto_srom(u_int command, u_long addr);
978 static int getfrom_srom(u_long addr);
979 static int srom_map_media(struct net_device *dev);
980 static int srom_infoleaf_info(struct net_device *dev);
981 static void srom_init(struct net_device *dev);
982 static void srom_exec(struct net_device *dev, u_char *p);
983 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
984 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
985 static int mii_rdata(u_long ioaddr);
986 static void mii_wdata(int data, int len, u_long ioaddr);
987 static void mii_ta(u_long rw, u_long ioaddr);
988 static int mii_swap(int data, int len);
989 static void mii_address(u_char addr, u_long ioaddr);
990 static void sendto_mii(u32 command, int data, u_long ioaddr);
991 static int getfrom_mii(u32 command, u_long ioaddr);
992 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
993 static int mii_get_phy(struct net_device *dev);
994 static void SetMulticastFilter(struct net_device *dev);
995 static int get_hw_addr(struct net_device *dev);
996 static void srom_repair(struct net_device *dev, int card);
997 static int test_bad_enet(struct net_device *dev, int status);
998 static int an_exception(struct bus_type *lp);
999 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1000 static void eisa_probe(struct net_device *dev, u_long iobase);
1001 #endif
1002 static void pci_probe(struct net_device *dev, u_long iobase);
1003 static void srom_search(struct pci_dev *pdev);
1004 static char *build_setup_frame(struct net_device *dev, int mode);
1005 static void disable_ast(struct net_device *dev);
1006 static void enable_ast(struct net_device *dev, u32 time_out);
1007 static long de4x5_switch_mac_port(struct net_device *dev);
1008 static int gep_rd(struct net_device *dev);
1009 static void gep_wr(s32 data, struct net_device *dev);
1010 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
1011 static void yawn(struct net_device *dev, int state);
1012 static void link_modules(struct net_device *dev, struct net_device *tmp);
1013 static void de4x5_parse_params(struct net_device *dev);
1014 static void de4x5_dbg_open(struct net_device *dev);
1015 static void de4x5_dbg_mii(struct net_device *dev, int k);
1016 static void de4x5_dbg_media(struct net_device *dev);
1017 static void de4x5_dbg_srom(struct de4x5_srom *p);
1018 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
1019 static int de4x5_strncmp(char *a, char *b, int n);
1020 static int dc21041_infoleaf(struct net_device *dev);
1021 static int dc21140_infoleaf(struct net_device *dev);
1022 static int dc21142_infoleaf(struct net_device *dev);
1023 static int dc21143_infoleaf(struct net_device *dev);
1024 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1025 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1026 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1027 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1028 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1029 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1030 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1031
1032 #ifdef MODULE
1033 int init_module(void);
1034 void cleanup_module(void);
1035 static struct net_device *unlink_modules(struct net_device *p);
1036 static struct net_device *insert_device(struct net_device *dev, u_long iobase,
1037 int (*init)(struct net_device *));
1038 static int count_adapters(void);
1039 static int loading_module = 1;
1040 MODULE_PARM(de4x5_debug, "i");
1041 MODULE_PARM(dec_only, "i");
1042 MODULE_PARM(args, "s");
1043 # else
1044 static int loading_module = 0;
1045 #endif /* MODULE */
1046
1047 static char name[DE4X5_NAME_LENGTH + 1];
1048 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1049 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1050 static int lastEISA = 0;
1051 # ifdef DE4X5_FORCE_EISA /* Force an EISA bus probe or not */
1052 static int forceEISA = 1;
1053 # else
1054 static int forceEISA = 0;
1055 # endif
1056 #endif
1057 static int num_de4x5s = 0;
1058 static int cfrv = 0, useSROM = 0;
1059 static int lastPCI = -1;
1060 static struct net_device *lastModule = NULL;
1061 static struct pci_dev *pdev = NULL;
1062
1063 /*
1064 ** List the SROM infoleaf functions and chipsets
1065 */
1066 struct InfoLeaf {
1067 int chipset;
1068 int (*fn)(struct net_device *);
1069 };
1070 static struct InfoLeaf infoleaf_array[] = {
1071 {DC21041, dc21041_infoleaf},
1072 {DC21140, dc21140_infoleaf},
1073 {DC21142, dc21142_infoleaf},
1074 {DC21143, dc21143_infoleaf}
1075 };
1076 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1077
1078 /*
1079 ** List the SROM info block functions
1080 */
1081 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1082 type0_infoblock,
1083 type1_infoblock,
1084 type2_infoblock,
1085 type3_infoblock,
1086 type4_infoblock,
1087 type5_infoblock,
1088 compact_infoblock
1089 };
1090
1091 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1092
1093 /*
1094 ** Miscellaneous defines...
1095 */
1096 #define RESET_DE4X5 {\
1097 int i;\
1098 i=inl(DE4X5_BMR);\
1099 de4x5_ms_delay(1);\
1100 outl(i | BMR_SWR, DE4X5_BMR);\
1101 de4x5_ms_delay(1);\
1102 outl(i, DE4X5_BMR);\
1103 de4x5_ms_delay(1);\
1104 for (i=0;i<5;i++) {inl(DE4X5_BMR); de4x5_ms_delay(1);}\
1105 de4x5_ms_delay(1);\
1106 }
1107
1108 #define PHY_HARD_RESET {\
1109 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1110 mdelay(1); /* Assert for 1ms */\
1111 outl(0x00, DE4X5_GEP);\
1112 mdelay(2); /* Wait for 2ms */\
1113 }
1114
1115 \f
1116 /*
1117 ** Autoprobing in modules is allowed here. See the top of the file for
1118 ** more info.
1119 */
1120 int __init
1121 de4x5_probe(struct net_device *dev)
1122 {
1123 u_long iobase = dev->base_addr;
1124
1125 pci_probe(dev, iobase);
1126 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
1127 if ((lastPCI == NO_MORE_PCI) && ((num_de4x5s == 0) || forceEISA)) {
1128 eisa_probe(dev, iobase);
1129 }
1130 #endif
1131
1132 return (dev->priv ? 0 : -ENODEV);
1133 }
1134
1135 static int __init
1136 de4x5_hw_init(struct net_device *dev, u_long iobase, struct pci_dev *pdev)
1137 {
1138 struct bus_type *lp = &bus;
1139 int i, status=0;
1140 char *tmp;
1141
1142 /* Ensure we're not sleeping */
1143 if (lp->bus == EISA) {
1144 outb(WAKEUP, PCI_CFPM);
1145 } else {
1146 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1147 PCI_CFDA_PSM, WAKEUP);
1148 }
1149 de4x5_ms_delay(10);
1150
1151 RESET_DE4X5;
1152
1153 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1154 return -ENXIO; /* Hardware could not reset */
1155 }
1156
1157 /*
1158 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1159 */
1160 useSROM = FALSE;
1161 if (lp->bus == PCI) {
1162 PCI_signature(name, lp);
1163 } else {
1164 EISA_signature(name, EISA_ID0);
1165 }
1166
1167 if (*name == '\0') { /* Not found a board signature */
1168 return -ENXIO;
1169 }
1170
1171 dev->base_addr = iobase;
1172 if (lp->bus == EISA) {
1173 printk("%s: %s at 0x%04lx (EISA slot %ld)",
1174 dev->name, name, iobase, ((iobase>>12)&0x0f));
1175 } else { /* PCI port address */
1176 printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1177 iobase, lp->bus_num, lp->device);
1178 }
1179
1180 printk(", h/w address ");
1181 status = get_hw_addr(dev);
1182 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1183 printk("%2.2x:", dev->dev_addr[i]);
1184 }
1185 printk("%2.2x,\n", dev->dev_addr[i]);
1186
1187 if (status != 0) {
1188 printk(" which has an Ethernet PROM CRC error.\n");
1189 return -ENXIO;
1190 } else {
1191 struct de4x5_private *lp;
1192
1193 /*
1194 ** Reserve a section of kernel memory for the adapter
1195 ** private area and the TX/RX descriptor rings.
1196 */
1197 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1198 GFP_KERNEL);
1199 if (dev->priv == NULL) {
1200 return -ENOMEM;
1201 }
1202
1203 /*
1204 ** Align to a longword boundary
1205 */
1206 tmp = dev->priv;
1207 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1208 lp = (struct de4x5_private *)dev->priv;
1209 memset(dev->priv, 0, sizeof(struct de4x5_private));
1210 lp->bus = bus.bus;
1211 lp->bus_num = bus.bus_num;
1212 lp->device = bus.device;
1213 lp->chipset = bus.chipset;
1214 lp->cache.priv = tmp;
1215 lp->cache.gepc = GEP_INIT;
1216 lp->asBit = GEP_SLNK;
1217 lp->asPolarity = GEP_SLNK;
1218 lp->asBitValid = TRUE;
1219 lp->timeout = -1;
1220 lp->useSROM = useSROM;
1221 lp->pdev = pdev;
1222 memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1223 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1224 de4x5_parse_params(dev);
1225
1226 /*
1227 ** Choose correct autosensing in case someone messed up
1228 */
1229 lp->autosense = lp->params.autosense;
1230 if (lp->chipset != DC21140) {
1231 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1232 lp->params.autosense = TP;
1233 }
1234 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1235 lp->params.autosense = BNC;
1236 }
1237 }
1238 lp->fdx = lp->params.fdx;
1239 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1240
1241 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1242 #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1243 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + ALIGN;
1244 #endif
1245 lp->rx_ring = pci_alloc_consistent(pdev, lp->dma_size, &lp->dma_rings);
1246 if (lp->rx_ring == NULL) {
1247 kfree(lp->cache.priv);
1248 lp->cache.priv = NULL;
1249 return -ENOMEM;
1250 }
1251
1252 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1253
1254 /*
1255 ** Set up the RX descriptor ring (Intels)
1256 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1257 */
1258 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1259 for (i=0; i<NUM_RX_DESC; i++) {
1260 lp->rx_ring[i].status = 0;
1261 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1262 lp->rx_ring[i].buf = 0;
1263 lp->rx_ring[i].next = 0;
1264 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1265 }
1266
1267 #else
1268 {
1269 dma_addr_t dma_rx_bufs;
1270
1271 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1272 * sizeof(struct de4x5_desc);
1273 dma_rx_bufs = (dma_rx_bufs + ALIGN) & ~ALIGN;
1274 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1275 + NUM_TX_DESC) + ALIGN) & ~ALIGN);
1276 for (i=0; i<NUM_RX_DESC; i++) {
1277 lp->rx_ring[i].status = 0;
1278 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1279 lp->rx_ring[i].buf =
1280 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1281 lp->rx_ring[i].next = 0;
1282 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1283 }
1284
1285 }
1286 #endif
1287
1288 barrier();
1289
1290 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1291 DE4X5_EISA_TOTAL_SIZE),
1292 lp->adapter_name);
1293
1294 lp->rxRingSize = NUM_RX_DESC;
1295 lp->txRingSize = NUM_TX_DESC;
1296
1297 /* Write the end of list marker to the descriptor lists */
1298 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1299 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1300
1301 /* Tell the adapter where the TX/RX rings are located. */
1302 outl(lp->dma_rings, DE4X5_RRBA);
1303 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1304 DE4X5_TRBA);
1305
1306 /* Initialise the IRQ mask and Enable/Disable */
1307 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1308 lp->irq_en = IMR_NIM | IMR_AIM;
1309
1310 /* Create a loopback packet frame for later media probing */
1311 create_packet(dev, lp->frame, sizeof(lp->frame));
1312
1313 /* Check if the RX overflow bug needs testing for */
1314 i = cfrv & 0x000000fe;
1315 if ((lp->chipset == DC21140) && (i == 0x20)) {
1316 lp->rx_ovf = 1;
1317 }
1318
1319 /* Initialise the SROM pointers if possible */
1320 if (lp->useSROM) {
1321 lp->state = INITIALISED;
1322 if (srom_infoleaf_info(dev)) {
1323 return -ENXIO;
1324 }
1325 srom_init(dev);
1326 }
1327
1328 lp->state = CLOSED;
1329
1330 /*
1331 ** Check for an MII interface
1332 */
1333 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1334 mii_get_phy(dev);
1335 }
1336
1337 #ifndef __sparc_v9__
1338 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1339 #else
1340 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1341 #endif
1342 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1343 }
1344
1345 if (de4x5_debug & DEBUG_VERSION) {
1346 printk(version);
1347 }
1348
1349 /* The DE4X5-specific entries in the device structure. */
1350 dev->open = &de4x5_open;
1351 dev->hard_start_xmit = &de4x5_queue_pkt;
1352 dev->stop = &de4x5_close;
1353 dev->get_stats = &de4x5_get_stats;
1354 dev->set_multicast_list = &set_multicast_list;
1355 dev->do_ioctl = &de4x5_ioctl;
1356
1357 dev->mem_start = 0;
1358
1359 /* Fill in the generic fields of the device structure. */
1360 ether_setup(dev);
1361
1362 /* Let the adapter sleep to save power */
1363 yawn(dev, SLEEP);
1364
1365 return status;
1366 }
1367
1368 \f
1369 static int
1370 de4x5_open(struct net_device *dev)
1371 {
1372 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1373 u_long iobase = dev->base_addr;
1374 int i, status = 0;
1375 s32 omr;
1376
1377 /* Allocate the RX buffers */
1378 for (i=0; i<lp->rxRingSize; i++) {
1379 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1380 de4x5_free_rx_buffs(dev);
1381 return -EAGAIN;
1382 }
1383 }
1384
1385 /*
1386 ** Wake up the adapter
1387 */
1388 yawn(dev, WAKEUP);
1389
1390 /*
1391 ** Re-initialize the DE4X5...
1392 */
1393 status = de4x5_init(dev);
1394 lp->lock = (spinlock_t) SPIN_LOCK_UNLOCKED;
1395 lp->state = OPEN;
1396 de4x5_dbg_open(dev);
1397
1398 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1399 lp->adapter_name, dev)) {
1400 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1401 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1402 lp->adapter_name, dev)) {
1403 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1404 disable_ast(dev);
1405 de4x5_free_rx_buffs(dev);
1406 de4x5_free_tx_buffs(dev);
1407 yawn(dev, SLEEP);
1408 lp->state = CLOSED;
1409 return -EAGAIN;
1410 } else {
1411 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1412 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1413 }
1414 }
1415
1416 lp->interrupt = UNMASK_INTERRUPTS;
1417 dev->trans_start = jiffies;
1418
1419 START_DE4X5;
1420
1421 de4x5_setup_intr(dev);
1422
1423 if (de4x5_debug & DEBUG_OPEN) {
1424 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1425 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1426 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1427 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1428 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1429 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1430 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1431 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1432 }
1433
1434 MOD_INC_USE_COUNT;
1435
1436 return status;
1437 }
1438
1439 /*
1440 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1441 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1442 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1443 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1444 ** to be data corruption problems if it is larger (UDP errors seen from a
1445 ** ttcp source).
1446 */
1447 static int
1448 de4x5_init(struct net_device *dev)
1449 {
1450 /* Lock out other processes whilst setting up the hardware */
1451 netif_stop_queue(dev);
1452
1453 de4x5_sw_reset(dev);
1454
1455 /* Autoconfigure the connected port */
1456 autoconf_media(dev);
1457
1458 return 0;
1459 }
1460
1461 static int
1462 de4x5_sw_reset(struct net_device *dev)
1463 {
1464 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1465 u_long iobase = dev->base_addr;
1466 int i, j, status = 0;
1467 s32 bmr, omr;
1468
1469 /* Select the MII or SRL port now and RESET the MAC */
1470 if (!lp->useSROM) {
1471 if (lp->phy[lp->active].id != 0) {
1472 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1473 } else {
1474 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1475 }
1476 de4x5_switch_mac_port(dev);
1477 }
1478
1479 /*
1480 ** Set the programmable burst length to 8 longwords for all the DC21140
1481 ** Fasternet chips and 4 longwords for all others: DMA errors result
1482 ** without these values. Cache align 16 long.
1483 */
1484 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1485 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1486 outl(bmr, DE4X5_BMR);
1487
1488 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1489 if (lp->chipset == DC21140) {
1490 omr |= (OMR_SDP | OMR_SB);
1491 }
1492 lp->setup_f = PERFECT;
1493 outl(lp->dma_rings, DE4X5_RRBA);
1494 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1495 DE4X5_TRBA);
1496
1497 lp->rx_new = lp->rx_old = 0;
1498 lp->tx_new = lp->tx_old = 0;
1499
1500 for (i = 0; i < lp->rxRingSize; i++) {
1501 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1502 }
1503
1504 for (i = 0; i < lp->txRingSize; i++) {
1505 lp->tx_ring[i].status = cpu_to_le32(0);
1506 }
1507
1508 barrier();
1509
1510 /* Build the setup frame depending on filtering mode */
1511 SetMulticastFilter(dev);
1512
1513 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1514 outl(omr|OMR_ST, DE4X5_OMR);
1515
1516 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1517 sti(); /* Ensure timer interrupts */
1518 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1519 mdelay(1);
1520 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1521 }
1522 outl(omr, DE4X5_OMR); /* Stop everything! */
1523
1524 if (j == 0) {
1525 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1526 inl(DE4X5_STS));
1527 status = -EIO;
1528 }
1529
1530 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1531 lp->tx_old = lp->tx_new;
1532
1533 return status;
1534 }
1535
1536 /*
1537 ** Writes a socket buffer address to the next available transmit descriptor.
1538 */
1539 static int
1540 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1541 {
1542 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1543 u_long iobase = dev->base_addr;
1544 int status = 0;
1545 u_long flags = 0;
1546
1547 netif_stop_queue(dev);
1548 if (lp->tx_enable == NO) { /* Cannot send for now */
1549 return -1;
1550 }
1551
1552 /*
1553 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1554 ** interrupts are lost by delayed descriptor status updates relative to
1555 ** the irq assertion, especially with a busy PCI bus.
1556 */
1557 spin_lock_irqsave(&lp->lock, flags);
1558 de4x5_tx(dev);
1559 spin_unlock_irqrestore(&lp->lock, flags);
1560
1561 /* Test if cache is already locked - requeue skb if so */
1562 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1563 return -1;
1564
1565 /* Transmit descriptor ring full or stale skb */
1566 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1567 if (lp->interrupt) {
1568 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1569 } else {
1570 de4x5_put_cache(dev, skb);
1571 }
1572 if (de4x5_debug & DEBUG_TX) {
1573 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1574 }
1575 } else if (skb->len > 0) {
1576 /* If we already have stuff queued locally, use that first */
1577 if (lp->cache.skb && !lp->interrupt) {
1578 de4x5_put_cache(dev, skb);
1579 skb = de4x5_get_cache(dev);
1580 }
1581
1582 while (skb && !netif_queue_stopped(dev) &&
1583 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1584 spin_lock_irqsave(&lp->lock, flags);
1585 netif_stop_queue(dev);
1586 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1587 lp->stats.tx_bytes += skb->len;
1588 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1589
1590 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1591 dev->trans_start = jiffies;
1592
1593 if (TX_BUFFS_AVAIL) {
1594 netif_start_queue(dev); /* Another pkt may be queued */
1595 }
1596 skb = de4x5_get_cache(dev);
1597 spin_unlock_irqrestore(&lp->lock, flags);
1598 }
1599 if (skb) de4x5_putb_cache(dev, skb);
1600 }
1601
1602 lp->cache.lock = 0;
1603
1604 return status;
1605 }
1606
1607 /*
1608 ** The DE4X5 interrupt handler.
1609 **
1610 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1611 ** so that the asserted interrupt always has some real data to work with -
1612 ** if these I/O accesses are ever changed to memory accesses, ensure the
1613 ** STS write is read immediately to complete the transaction if the adapter
1614 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1615 ** is high and descriptor status bits cannot be set before the associated
1616 ** interrupt is asserted and this routine entered.
1617 */
1618 static void
1619 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1620 {
1621 struct net_device *dev = (struct net_device *)dev_id;
1622 struct de4x5_private *lp;
1623 s32 imr, omr, sts, limit;
1624 u_long iobase;
1625
1626 if (dev == NULL) {
1627 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1628 return;
1629 }
1630 lp = (struct de4x5_private *)dev->priv;
1631 spin_lock(&lp->lock);
1632 iobase = dev->base_addr;
1633
1634 DISABLE_IRQs; /* Ensure non re-entrancy */
1635
1636 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1637 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1638
1639 synchronize_irq();
1640
1641 for (limit=0; limit<8; limit++) {
1642 sts = inl(DE4X5_STS); /* Read IRQ status */
1643 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1644
1645 if (!(sts & lp->irq_mask)) break;/* All done */
1646
1647 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1648 de4x5_rx(dev);
1649
1650 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1651 de4x5_tx(dev);
1652
1653 if (sts & STS_LNF) { /* TP Link has failed */
1654 lp->irq_mask &= ~IMR_LFM;
1655 }
1656
1657 if (sts & STS_UNF) { /* Transmit underrun */
1658 de4x5_txur(dev);
1659 }
1660
1661 if (sts & STS_SE) { /* Bus Error */
1662 STOP_DE4X5;
1663 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1664 dev->name, sts);
1665 return;
1666 }
1667 }
1668
1669 /* Load the TX ring with any locally stored packets */
1670 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1671 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1672 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1673 }
1674 lp->cache.lock = 0;
1675 }
1676
1677 lp->interrupt = UNMASK_INTERRUPTS;
1678 ENABLE_IRQs;
1679 spin_unlock(&lp->lock);
1680
1681 return;
1682 }
1683
1684 static int
1685 de4x5_rx(struct net_device *dev)
1686 {
1687 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1688 u_long iobase = dev->base_addr;
1689 int entry;
1690 s32 status;
1691
1692 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1693 entry=lp->rx_new) {
1694 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1695
1696 if (lp->rx_ovf) {
1697 if (inl(DE4X5_MFC) & MFC_FOCM) {
1698 de4x5_rx_ovfc(dev);
1699 break;
1700 }
1701 }
1702
1703 if (status & RD_FS) { /* Remember the start of frame */
1704 lp->rx_old = entry;
1705 }
1706
1707 if (status & RD_LS) { /* Valid frame status */
1708 if (lp->tx_enable) lp->linkOK++;
1709 if (status & RD_ES) { /* There was an error. */
1710 lp->stats.rx_errors++; /* Update the error stats. */
1711 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1712 if (status & RD_CE) lp->stats.rx_crc_errors++;
1713 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1714 if (status & RD_TL) lp->stats.rx_length_errors++;
1715 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1716 if (status & RD_CS) lp->pktStats.rx_collision++;
1717 if (status & RD_DB) lp->pktStats.rx_dribble++;
1718 if (status & RD_OF) lp->pktStats.rx_overflow++;
1719 } else { /* A valid frame received */
1720 struct sk_buff *skb;
1721 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1722 >> 16) - 4;
1723
1724 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1725 printk("%s: Insufficient memory; nuking packet.\n",
1726 dev->name);
1727 lp->stats.rx_dropped++;
1728 } else {
1729 de4x5_dbg_rx(skb, pkt_len);
1730
1731 /* Push up the protocol stack */
1732 skb->protocol=eth_type_trans(skb,dev);
1733 netif_rx(skb);
1734
1735 /* Update stats */
1736 lp->stats.rx_packets++;
1737 lp->stats.rx_bytes += pkt_len;
1738 de4x5_local_stats(dev, skb->data, pkt_len);
1739 }
1740 }
1741
1742 /* Change buffer ownership for this frame, back to the adapter */
1743 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1744 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1745 barrier();
1746 }
1747 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1748 barrier();
1749 }
1750
1751 /*
1752 ** Update entry information
1753 */
1754 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1755 }
1756
1757 return 0;
1758 }
1759
1760 static inline void
1761 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1762 {
1763 pci_unmap_single(lp->pdev, le32_to_cpu(lp->tx_ring[entry].buf),
1764 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1765 PCI_DMA_TODEVICE);
1766 if ((u_long) lp->tx_skb[entry] > 1)
1767 dev_kfree_skb_irq(lp->tx_skb[entry]);
1768 lp->tx_skb[entry] = NULL;
1769 }
1770
1771 /*
1772 ** Buffer sent - check for TX buffer errors.
1773 */
1774 static int
1775 de4x5_tx(struct net_device *dev)
1776 {
1777 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1778 u_long iobase = dev->base_addr;
1779 int entry;
1780 s32 status;
1781
1782 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1783 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1784 if (status < 0) { /* Buffer not sent yet */
1785 break;
1786 } else if (status != 0x7fffffff) { /* Not setup frame */
1787 if (status & TD_ES) { /* An error happened */
1788 lp->stats.tx_errors++;
1789 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1790 if (status & TD_LC) lp->stats.tx_window_errors++;
1791 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1792 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1793 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1794
1795 if (TX_PKT_PENDING) {
1796 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1797 }
1798 } else { /* Packet sent */
1799 lp->stats.tx_packets++;
1800 if (lp->tx_enable) lp->linkOK++;
1801 }
1802 /* Update the collision counter */
1803 lp->stats.collisions += ((status & TD_EC) ? 16 :
1804 ((status & TD_CC) >> 3));
1805
1806 /* Free the buffer. */
1807 if (lp->tx_skb[entry] != NULL)
1808 de4x5_free_tx_buff(lp, entry);
1809 }
1810
1811 /* Update all the pointers */
1812 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1813 }
1814
1815 /* Any resources available? */
1816 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1817 if (lp->interrupt)
1818 netif_wake_queue(dev);
1819 else
1820 netif_start_queue(dev);
1821 }
1822
1823 return 0;
1824 }
1825
1826 static int
1827 de4x5_ast(struct net_device *dev)
1828 {
1829 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1830 int next_tick = DE4X5_AUTOSENSE_MS;
1831
1832 disable_ast(dev);
1833
1834 if (lp->useSROM) {
1835 next_tick = srom_autoconf(dev);
1836 } else if (lp->chipset == DC21140) {
1837 next_tick = dc21140m_autoconf(dev);
1838 } else if (lp->chipset == DC21041) {
1839 next_tick = dc21041_autoconf(dev);
1840 } else if (lp->chipset == DC21040) {
1841 next_tick = dc21040_autoconf(dev);
1842 }
1843 lp->linkOK = 0;
1844 enable_ast(dev, next_tick);
1845
1846 return 0;
1847 }
1848
1849 static int
1850 de4x5_txur(struct net_device *dev)
1851 {
1852 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1853 u_long iobase = dev->base_addr;
1854 int omr;
1855
1856 omr = inl(DE4X5_OMR);
1857 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1858 omr &= ~(OMR_ST|OMR_SR);
1859 outl(omr, DE4X5_OMR);
1860 while (inl(DE4X5_STS) & STS_TS);
1861 if ((omr & OMR_TR) < OMR_TR) {
1862 omr += 0x4000;
1863 } else {
1864 omr |= OMR_SF;
1865 }
1866 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1867 }
1868
1869 return 0;
1870 }
1871
1872 static int
1873 de4x5_rx_ovfc(struct net_device *dev)
1874 {
1875 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1876 u_long iobase = dev->base_addr;
1877 int omr;
1878
1879 omr = inl(DE4X5_OMR);
1880 outl(omr & ~OMR_SR, DE4X5_OMR);
1881 while (inl(DE4X5_STS) & STS_RS);
1882
1883 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1884 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1885 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1886 }
1887
1888 outl(omr, DE4X5_OMR);
1889
1890 return 0;
1891 }
1892
1893 static int
1894 de4x5_close(struct net_device *dev)
1895 {
1896 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1897 u_long iobase = dev->base_addr;
1898 s32 imr, omr;
1899
1900 disable_ast(dev);
1901
1902 netif_stop_queue(dev);
1903
1904 if (de4x5_debug & DEBUG_CLOSE) {
1905 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1906 dev->name, inl(DE4X5_STS));
1907 }
1908
1909 /*
1910 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1911 */
1912 DISABLE_IRQs;
1913 STOP_DE4X5;
1914
1915 /* Free the associated irq */
1916 free_irq(dev->irq, dev);
1917 lp->state = CLOSED;
1918
1919 /* Free any socket buffers */
1920 de4x5_free_rx_buffs(dev);
1921 de4x5_free_tx_buffs(dev);
1922
1923 MOD_DEC_USE_COUNT;
1924
1925 /* Put the adapter to sleep to save power */
1926 yawn(dev, SLEEP);
1927
1928 return 0;
1929 }
1930
1931 static struct net_device_stats *
1932 de4x5_get_stats(struct net_device *dev)
1933 {
1934 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1935 u_long iobase = dev->base_addr;
1936
1937 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1938
1939 return &lp->stats;
1940 }
1941
1942 static void
1943 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1944 {
1945 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1946 int i;
1947
1948 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1949 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1950 lp->pktStats.bins[i]++;
1951 i = DE4X5_PKT_STAT_SZ;
1952 }
1953 }
1954 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1955 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1956 lp->pktStats.broadcast++;
1957 } else {
1958 lp->pktStats.multicast++;
1959 }
1960 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1961 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1962 lp->pktStats.unicast++;
1963 }
1964
1965 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1966 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1967 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1968 }
1969
1970 return;
1971 }
1972
1973 /*
1974 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1975 ** If the flag is changed on a descriptor that is being read by the hardware,
1976 ** I assume PCI transaction ordering will mean you are either successful or
1977 ** just miss asserting the change to the hardware. Anyway you're messing with
1978 ** a descriptor you don't own, but this shouldn't kill the chip provided
1979 ** the descriptor register is read only to the hardware.
1980 */
1981 static void
1982 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1983 {
1984 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1985 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1986 dma_addr_t buf_dma = pci_map_single(lp->pdev, buf, flags & TD_TBS1, PCI_DMA_TODEVICE);
1987
1988 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1989 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1990 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1991 lp->tx_skb[lp->tx_new] = skb;
1992 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1993 barrier();
1994
1995 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1996 barrier();
1997 }
1998
1999 /*
2000 ** Set or clear the multicast filter for this adaptor.
2001 */
2002 static void
2003 set_multicast_list(struct net_device *dev)
2004 {
2005 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2006 u_long iobase = dev->base_addr;
2007
2008 /* First, double check that the adapter is open */
2009 if (lp->state == OPEN) {
2010 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
2011 u32 omr;
2012 omr = inl(DE4X5_OMR);
2013 omr |= OMR_PR;
2014 outl(omr, DE4X5_OMR);
2015 } else {
2016 SetMulticastFilter(dev);
2017 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
2018 SETUP_FRAME_LEN, (struct sk_buff *)1);
2019
2020 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2021 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
2022 dev->trans_start = jiffies;
2023 }
2024 }
2025
2026 return;
2027 }
2028
2029 /*
2030 ** Calculate the hash code and update the logical address filter
2031 ** from a list of ethernet multicast addresses.
2032 ** Little endian crc one liner from Matt Thomas, DEC.
2033 */
2034 static void
2035 SetMulticastFilter(struct net_device *dev)
2036 {
2037 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2038 struct dev_mc_list *dmi=dev->mc_list;
2039 u_long iobase = dev->base_addr;
2040 int i, j, bit, byte;
2041 u16 hashcode;
2042 u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
2043 char *pa;
2044 unsigned char *addrs;
2045
2046 omr = inl(DE4X5_OMR);
2047 omr &= ~(OMR_PR | OMR_PM);
2048 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
2049
2050 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
2051 omr |= OMR_PM; /* Pass all multicasts */
2052 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
2053 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
2054 addrs=dmi->dmi_addr;
2055 dmi=dmi->next;
2056 if ((*addrs & 0x01) == 1) { /* multicast address? */
2057 crc = 0xffffffff; /* init CRC for each address */
2058 for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
2059 /* process each address bit */
2060 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
2061 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
2062 }
2063 }
2064 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
2065
2066 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
2067 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
2068
2069 byte <<= 1; /* calc offset into setup frame */
2070 if (byte & 0x02) {
2071 byte -= 1;
2072 }
2073 lp->setup_frame[byte] |= bit;
2074 }
2075 }
2076 } else { /* Perfect filtering */
2077 for (j=0; j<dev->mc_count; j++) {
2078 addrs=dmi->dmi_addr;
2079 dmi=dmi->next;
2080 for (i=0; i<ETH_ALEN; i++) {
2081 *(pa + (i&1)) = *addrs++;
2082 if (i & 0x01) pa += 4;
2083 }
2084 }
2085 }
2086 outl(omr, DE4X5_OMR);
2087
2088 return;
2089 }
2090
2091 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
2092 /*
2093 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2094 ** the motherboard. Upto 15 EISA devices are supported.
2095 */
2096 static void __init
2097 eisa_probe(struct net_device *dev, u_long ioaddr)
2098 {
2099 int i, maxSlots, status, device;
2100 u_char irq;
2101 u_short vendor;
2102 u32 cfid;
2103 u_long iobase;
2104 struct bus_type *lp = &bus;
2105 char name[DE4X5_STRLEN];
2106
2107 if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2108
2109 lp->bus = EISA;
2110
2111 if (ioaddr == 0) { /* Autoprobing */
2112 iobase = EISA_SLOT_INC; /* Get the first slot address */
2113 i = 1;
2114 maxSlots = MAX_EISA_SLOTS;
2115 } else { /* Probe a specific location */
2116 iobase = ioaddr;
2117 i = (ioaddr >> 12);
2118 maxSlots = i + 1;
2119 }
2120
2121 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2122 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE)) continue;
2123 if (!EISA_signature(name, EISA_ID)) continue;
2124
2125 cfid = (u32) inl(PCI_CFID);
2126 cfrv = (u_short) inl(PCI_CFRV);
2127 device = (cfid >> 8) & 0x00ffff00;
2128 vendor = (u_short) cfid;
2129
2130 /* Read the EISA Configuration Registers */
2131 irq = inb(EISA_REG0);
2132 irq = de4x5_irq[(irq >> 1) & 0x03];
2133
2134 if (is_DC2114x) {
2135 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2136 }
2137 lp->chipset = device;
2138
2139 /* Write the PCI Configuration Registers */
2140 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2141 outl(0x00006000, PCI_CFLT);
2142 outl(iobase, PCI_CBIO);
2143
2144 DevicePresent(EISA_APROM);
2145
2146 dev->irq = irq;
2147 if ((status = de4x5_hw_init(dev, iobase, NULL)) == 0) {
2148 num_de4x5s++;
2149 if (loading_module) link_modules(lastModule, dev);
2150 lastEISA = i;
2151 return;
2152 }
2153 }
2154
2155 if (ioaddr == 0) lastEISA = i;
2156
2157 return;
2158 }
2159 #endif /* !(__sparc_v9__) && !(__powerpc__) && !defined(__alpha__) */
2160
2161 /*
2162 ** PCI bus I/O device probe
2163 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2164 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2165 ** enabled by the user first in the set up utility. Hence we just check for
2166 ** enabled features and silently ignore the card if they're not.
2167 **
2168 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2169 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2170 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2171 ** PC doesn't conform to the PCI standard)!
2172 **
2173 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2174 ** kernels use the V0.535[n] drivers.
2175 */
2176 #define PCI_LAST_DEV 32
2177
2178 static void __init
2179 pci_probe(struct net_device *dev, u_long ioaddr)
2180 {
2181 u_char pb, pbus, dev_num, dnum, timer;
2182 u_short vendor, index, status;
2183 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2184 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2185 struct bus_type *lp = &bus;
2186
2187 if (lastPCI == NO_MORE_PCI) return;
2188
2189 if (!pcibios_present()) {
2190 lastPCI = NO_MORE_PCI;
2191 return; /* No PCI bus in this machine! */
2192 }
2193
2194 lp->bus = PCI;
2195 lp->bus_num = 0;
2196
2197 if ((ioaddr < 0x1000) && loading_module) {
2198 pbus = (u_short)(ioaddr >> 8);
2199 dnum = (u_short)(ioaddr & 0xff);
2200 } else {
2201 pbus = 0;
2202 dnum = 0;
2203 }
2204
2205 for (index=lastPCI+1;(pdev = pci_find_class(class, pdev))!=NULL;index++) {
2206 dev_num = PCI_SLOT(pdev->devfn);
2207 pb = pdev->bus->number;
2208 if ((pbus || dnum) && ((pbus != pb) || (dnum != dev_num))) continue;
2209
2210 vendor = pdev->vendor;
2211 device = pdev->device << 8;
2212 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2213
2214 /* Search for an SROM on this bus */
2215 if (lp->bus_num != pb) {
2216 lp->bus_num = pb;
2217 srom_search(pdev);
2218 }
2219
2220 /* Get the chip configuration revision register */
2221 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2222
2223 /* Set the device number information */
2224 lp->device = dev_num;
2225 lp->bus_num = pb;
2226
2227 /* Set the chipset information */
2228 if (is_DC2114x) {
2229 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2230 }
2231 lp->chipset = device;
2232
2233 /* Get the board I/O address (64 bits on sparc64) */
2234 iobase = pci_resource_start(pdev, 0);
2235
2236 /* Fetch the IRQ to be used */
2237 irq = pdev->irq;
2238 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2239
2240 /* Check if I/O accesses and Bus Mastering are enabled */
2241 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2242 #ifdef __powerpc__
2243 if (!(status & PCI_COMMAND_IO)) {
2244 status |= PCI_COMMAND_IO;
2245 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2246 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2247 }
2248 #endif /* __powerpc__ */
2249 if (!(status & PCI_COMMAND_IO)) continue;
2250
2251 if (!(status & PCI_COMMAND_MASTER)) {
2252 status |= PCI_COMMAND_MASTER;
2253 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2254 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2255 }
2256 if (!(status & PCI_COMMAND_MASTER)) continue;
2257
2258 /* Check the latency timer for values >= 0x60 */
2259 pcibios_read_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, &timer);
2260 if (timer < 0x60) {
2261 pcibios_write_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, 0x60);
2262 }
2263
2264 DevicePresent(DE4X5_APROM);
2265 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2266 dev->irq = irq;
2267 if ((status = de4x5_hw_init(dev, iobase, pdev)) == 0) {
2268 num_de4x5s++;
2269 lastPCI = index;
2270 if (loading_module) link_modules(lastModule, dev);
2271 return;
2272 }
2273 } else if (ioaddr != 0) {
2274 printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2275 iobase);
2276 }
2277 }
2278
2279 lastPCI = NO_MORE_PCI;
2280
2281 return;
2282 }
2283
2284 /*
2285 ** This function searches the current bus (which is >0) for a DECchip with an
2286 ** SROM, so that in multiport cards that have one SROM shared between multiple
2287 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2288 ** For single port cards this is a time waster...
2289 */
2290 static void __init
2291 srom_search(struct pci_dev *dev)
2292 {
2293 u_char pb;
2294 u_short vendor, status;
2295 u_int irq = 0, device;
2296 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2297 int i, j;
2298 struct bus_type *lp = &bus;
2299 struct list_head *walk = &dev->bus_list;
2300
2301 for (walk = walk->next; walk != &dev->bus_list; walk = walk->next) {
2302 struct pci_dev *this_dev = pci_dev_b(walk);
2303
2304 pb = this_dev->bus->number;
2305 vendor = this_dev->vendor;
2306 device = this_dev->device << 8;
2307 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2308
2309 /* Get the chip configuration revision register */
2310 pcibios_read_config_dword(pb, this_dev->devfn, PCI_REVISION_ID, &cfrv);
2311
2312 /* Set the device number information */
2313 lp->device = PCI_SLOT(this_dev->devfn);
2314 lp->bus_num = pb;
2315
2316 /* Set the chipset information */
2317 if (is_DC2114x) {
2318 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2319 }
2320 lp->chipset = device;
2321
2322 /* Get the board I/O address (64 bits on sparc64) */
2323 iobase = pci_resource_start(this_dev, 0);
2324
2325 /* Fetch the IRQ to be used */
2326 irq = this_dev->irq;
2327 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2328
2329 /* Check if I/O accesses are enabled */
2330 pcibios_read_config_word(pb, this_dev->devfn, PCI_COMMAND, &status);
2331 if (!(status & PCI_COMMAND_IO)) continue;
2332
2333 /* Search for a valid SROM attached to this DECchip */
2334 DevicePresent(DE4X5_APROM);
2335 for (j=0, i=0; i<ETH_ALEN; i++) {
2336 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2337 }
2338 if ((j != 0) && (j != 0x5fa)) {
2339 last.chipset = device;
2340 last.bus = pb;
2341 last.irq = irq;
2342 for (i=0; i<ETH_ALEN; i++) {
2343 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2344 }
2345 return;
2346 }
2347 }
2348
2349 return;
2350 }
2351
2352 static void __init
2353 link_modules(struct net_device *dev, struct net_device *tmp)
2354 {
2355 struct net_device *p=dev;
2356
2357 if (p) {
2358 while (((struct de4x5_private *)(p->priv))->next_module) {
2359 p = ((struct de4x5_private *)(p->priv))->next_module;
2360 }
2361
2362 if (dev != tmp) {
2363 ((struct de4x5_private *)(p->priv))->next_module = tmp;
2364 } else {
2365 ((struct de4x5_private *)(p->priv))->next_module = NULL;
2366 }
2367 }
2368
2369 return;
2370 }
2371
2372 /*
2373 ** Auto configure the media here rather than setting the port at compile
2374 ** time. This routine is called by de4x5_init() and when a loss of media is
2375 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2376 ** [TP] or no recent receive activity) to check whether the user has been
2377 ** sneaky and changed the port on us.
2378 */
2379 static int
2380 autoconf_media(struct net_device *dev)
2381 {
2382 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2383 u_long iobase = dev->base_addr;
2384 int next_tick = DE4X5_AUTOSENSE_MS;
2385
2386 lp->linkOK = 0;
2387 lp->c_media = AUTO; /* Bogus last media */
2388 disable_ast(dev);
2389 inl(DE4X5_MFC); /* Zero the lost frames counter */
2390 lp->media = INIT;
2391 lp->tcount = 0;
2392
2393 if (lp->useSROM) {
2394 next_tick = srom_autoconf(dev);
2395 } else if (lp->chipset == DC21040) {
2396 next_tick = dc21040_autoconf(dev);
2397 } else if (lp->chipset == DC21041) {
2398 next_tick = dc21041_autoconf(dev);
2399 } else if (lp->chipset == DC21140) {
2400 next_tick = dc21140m_autoconf(dev);
2401 }
2402
2403 enable_ast(dev, next_tick);
2404
2405 return (lp->media);
2406 }
2407
2408 /*
2409 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2410 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2411 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2412 ** The only way to test for that is to place a loopback packet onto the
2413 ** network and watch for errors. Since we're messing with the interrupt mask
2414 ** register, disable the board interrupts and do not allow any more packets to
2415 ** be queued to the hardware. Re-enable everything only when the media is
2416 ** found.
2417 ** I may have to "age out" locally queued packets so that the higher layer
2418 ** timeouts don't effectively duplicate packets on the network.
2419 */
2420 static int
2421 dc21040_autoconf(struct net_device *dev)
2422 {
2423 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2424 u_long iobase = dev->base_addr;
2425 int next_tick = DE4X5_AUTOSENSE_MS;
2426 s32 imr;
2427
2428 switch (lp->media) {
2429 case INIT:
2430 DISABLE_IRQs;
2431 lp->tx_enable = NO;
2432 lp->timeout = -1;
2433 de4x5_save_skbs(dev);
2434 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2435 lp->media = TP;
2436 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2437 lp->media = BNC_AUI;
2438 } else if (lp->autosense == EXT_SIA) {
2439 lp->media = EXT_SIA;
2440 } else {
2441 lp->media = NC;
2442 }
2443 lp->local_state = 0;
2444 next_tick = dc21040_autoconf(dev);
2445 break;
2446
2447 case TP:
2448 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2449 TP_SUSPECT, test_tp);
2450 break;
2451
2452 case TP_SUSPECT:
2453 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2454 break;
2455
2456 case BNC:
2457 case AUI:
2458 case BNC_AUI:
2459 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2460 BNC_AUI_SUSPECT, ping_media);
2461 break;
2462
2463 case BNC_AUI_SUSPECT:
2464 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2465 break;
2466
2467 case EXT_SIA:
2468 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2469 NC, EXT_SIA_SUSPECT, ping_media);
2470 break;
2471
2472 case EXT_SIA_SUSPECT:
2473 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2474 break;
2475
2476 case NC:
2477 /* default to TP for all */
2478 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2479 if (lp->media != lp->c_media) {
2480 de4x5_dbg_media(dev);
2481 lp->c_media = lp->media;
2482 }
2483 lp->media = INIT;
2484 lp->tx_enable = NO;
2485 break;
2486 }
2487
2488 return next_tick;
2489 }
2490
2491 static int
2492 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2493 int next_state, int suspect_state,
2494 int (*fn)(struct net_device *, int))
2495 {
2496 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2497 int next_tick = DE4X5_AUTOSENSE_MS;
2498 int linkBad;
2499
2500 switch (lp->local_state) {
2501 case 0:
2502 reset_init_sia(dev, csr13, csr14, csr15);
2503 lp->local_state++;
2504 next_tick = 500;
2505 break;
2506
2507 case 1:
2508 if (!lp->tx_enable) {
2509 linkBad = fn(dev, timeout);
2510 if (linkBad < 0) {
2511 next_tick = linkBad & ~TIMER_CB;
2512 } else {
2513 if (linkBad && (lp->autosense == AUTO)) {
2514 lp->local_state = 0;
2515 lp->media = next_state;
2516 } else {
2517 de4x5_init_connection(dev);
2518 }
2519 }
2520 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2521 lp->media = suspect_state;
2522 next_tick = 3000;
2523 }
2524 break;
2525 }
2526
2527 return next_tick;
2528 }
2529
2530 static int
2531 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2532 int (*fn)(struct net_device *, int),
2533 int (*asfn)(struct net_device *))
2534 {
2535 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2536 int next_tick = DE4X5_AUTOSENSE_MS;
2537 int linkBad;
2538
2539 switch (lp->local_state) {
2540 case 1:
2541 if (lp->linkOK) {
2542 lp->media = prev_state;
2543 } else {
2544 lp->local_state++;
2545 next_tick = asfn(dev);
2546 }
2547 break;
2548
2549 case 2:
2550 linkBad = fn(dev, timeout);
2551 if (linkBad < 0) {
2552 next_tick = linkBad & ~TIMER_CB;
2553 } else if (!linkBad) {
2554 lp->local_state--;
2555 lp->media = prev_state;
2556 } else {
2557 lp->media = INIT;
2558 lp->tcount++;
2559 }
2560 }
2561
2562 return next_tick;
2563 }
2564
2565 /*
2566 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2567 ** before BNC, because the BNC port will indicate activity if it's not
2568 ** terminated correctly. The only way to test for that is to place a loopback
2569 ** packet onto the network and watch for errors. Since we're messing with
2570 ** the interrupt mask register, disable the board interrupts and do not allow
2571 ** any more packets to be queued to the hardware. Re-enable everything only
2572 ** when the media is found.
2573 */
2574 static int
2575 dc21041_autoconf(struct net_device *dev)
2576 {
2577 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2578 u_long iobase = dev->base_addr;
2579 s32 sts, irqs, irq_mask, imr, omr;
2580 int next_tick = DE4X5_AUTOSENSE_MS;
2581
2582 switch (lp->media) {
2583 case INIT:
2584 DISABLE_IRQs;
2585 lp->tx_enable = NO;
2586 lp->timeout = -1;
2587 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2588 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2589 lp->media = TP; /* On chip auto negotiation is broken */
2590 } else if (lp->autosense == TP) {
2591 lp->media = TP;
2592 } else if (lp->autosense == BNC) {
2593 lp->media = BNC;
2594 } else if (lp->autosense == AUI) {
2595 lp->media = AUI;
2596 } else {
2597 lp->media = NC;
2598 }
2599 lp->local_state = 0;
2600 next_tick = dc21041_autoconf(dev);
2601 break;
2602
2603 case TP_NW:
2604 if (lp->timeout < 0) {
2605 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2606 outl(omr | OMR_FDX, DE4X5_OMR);
2607 }
2608 irqs = STS_LNF | STS_LNP;
2609 irq_mask = IMR_LFM | IMR_LPM;
2610 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2611 if (sts < 0) {
2612 next_tick = sts & ~TIMER_CB;
2613 } else {
2614 if (sts & STS_LNP) {
2615 lp->media = ANS;
2616 } else {
2617 lp->media = AUI;
2618 }
2619 next_tick = dc21041_autoconf(dev);
2620 }
2621 break;
2622
2623 case ANS:
2624 if (!lp->tx_enable) {
2625 irqs = STS_LNP;
2626 irq_mask = IMR_LPM;
2627 sts = test_ans(dev, irqs, irq_mask, 3000);
2628 if (sts < 0) {
2629 next_tick = sts & ~TIMER_CB;
2630 } else {
2631 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2632 lp->media = TP;
2633 next_tick = dc21041_autoconf(dev);
2634 } else {
2635 lp->local_state = 1;
2636 de4x5_init_connection(dev);
2637 }
2638 }
2639 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2640 lp->media = ANS_SUSPECT;
2641 next_tick = 3000;
2642 }
2643 break;
2644
2645 case ANS_SUSPECT:
2646 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2647 break;
2648
2649 case TP:
2650 if (!lp->tx_enable) {
2651 if (lp->timeout < 0) {
2652 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2653 outl(omr & ~OMR_FDX, DE4X5_OMR);
2654 }
2655 irqs = STS_LNF | STS_LNP;
2656 irq_mask = IMR_LFM | IMR_LPM;
2657 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2658 if (sts < 0) {
2659 next_tick = sts & ~TIMER_CB;
2660 } else {
2661 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2662 if (inl(DE4X5_SISR) & SISR_NRA) {
2663 lp->media = AUI; /* Non selected port activity */
2664 } else {
2665 lp->media = BNC;
2666 }
2667 next_tick = dc21041_autoconf(dev);
2668 } else {
2669 lp->local_state = 1;
2670 de4x5_init_connection(dev);
2671 }
2672 }
2673 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2674 lp->media = TP_SUSPECT;
2675 next_tick = 3000;
2676 }
2677 break;
2678
2679 case TP_SUSPECT:
2680 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2681 break;
2682
2683 case AUI:
2684 if (!lp->tx_enable) {
2685 if (lp->timeout < 0) {
2686 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2687 outl(omr & ~OMR_FDX, DE4X5_OMR);
2688 }
2689 irqs = 0;
2690 irq_mask = 0;
2691 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2692 if (sts < 0) {
2693 next_tick = sts & ~TIMER_CB;
2694 } else {
2695 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2696 lp->media = BNC;
2697 next_tick = dc21041_autoconf(dev);
2698 } else {
2699 lp->local_state = 1;
2700 de4x5_init_connection(dev);
2701 }
2702 }
2703 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2704 lp->media = AUI_SUSPECT;
2705 next_tick = 3000;
2706 }
2707 break;
2708
2709 case AUI_SUSPECT:
2710 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2711 break;
2712
2713 case BNC:
2714 switch (lp->local_state) {
2715 case 0:
2716 if (lp->timeout < 0) {
2717 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2718 outl(omr & ~OMR_FDX, DE4X5_OMR);
2719 }
2720 irqs = 0;
2721 irq_mask = 0;
2722 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2723 if (sts < 0) {
2724 next_tick = sts & ~TIMER_CB;
2725 } else {
2726 lp->local_state++; /* Ensure media connected */
2727 next_tick = dc21041_autoconf(dev);
2728 }
2729 break;
2730
2731 case 1:
2732 if (!lp->tx_enable) {
2733 if ((sts = ping_media(dev, 3000)) < 0) {
2734 next_tick = sts & ~TIMER_CB;
2735 } else {
2736 if (sts) {
2737 lp->local_state = 0;
2738 lp->media = NC;
2739 } else {
2740 de4x5_init_connection(dev);
2741 }
2742 }
2743 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2744 lp->media = BNC_SUSPECT;
2745 next_tick = 3000;
2746 }
2747 break;
2748 }
2749 break;
2750
2751 case BNC_SUSPECT:
2752 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2753 break;
2754
2755 case NC:
2756 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2757 outl(omr | OMR_FDX, DE4X5_OMR);
2758 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2759 if (lp->media != lp->c_media) {
2760 de4x5_dbg_media(dev);
2761 lp->c_media = lp->media;
2762 }
2763 lp->media = INIT;
2764 lp->tx_enable = NO;
2765 break;
2766 }
2767
2768 return next_tick;
2769 }
2770
2771 /*
2772 ** Some autonegotiation chips are broken in that they do not return the
2773 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2774 ** register, except at the first power up negotiation.
2775 */
2776 static int
2777 dc21140m_autoconf(struct net_device *dev)
2778 {
2779 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2780 int ana, anlpa, cap, cr, slnk, sr;
2781 int next_tick = DE4X5_AUTOSENSE_MS;
2782 u_long imr, omr, iobase = dev->base_addr;
2783
2784 switch(lp->media) {
2785 case INIT:
2786 if (lp->timeout < 0) {
2787 DISABLE_IRQs;
2788 lp->tx_enable = FALSE;
2789 lp->linkOK = 0;
2790 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2791 }
2792 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2793 next_tick &= ~TIMER_CB;
2794 } else {
2795 if (lp->useSROM) {
2796 if (srom_map_media(dev) < 0) {
2797 lp->tcount++;
2798 return next_tick;
2799 }
2800 srom_exec(dev, lp->phy[lp->active].gep);
2801 if (lp->infoblock_media == ANS) {
2802 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2803 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2804 }
2805 } else {
2806 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2807 SET_10Mb;
2808 if (lp->autosense == _100Mb) {
2809 lp->media = _100Mb;
2810 } else if (lp->autosense == _10Mb) {
2811 lp->media = _10Mb;
2812 } else if ((lp->autosense == AUTO) &&
2813 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2814 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2815 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2816 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2817 lp->media = ANS;
2818 } else if (lp->autosense == AUTO) {
2819 lp->media = SPD_DET;
2820 } else if (is_spd_100(dev) && is_100_up(dev)) {
2821 lp->media = _100Mb;
2822 } else {
2823 lp->media = NC;
2824 }
2825 }
2826 lp->local_state = 0;
2827 next_tick = dc21140m_autoconf(dev);
2828 }
2829 break;
2830
2831 case ANS:
2832 switch (lp->local_state) {
2833 case 0:
2834 if (lp->timeout < 0) {
2835 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2836 }
2837 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2838 if (cr < 0) {
2839 next_tick = cr & ~TIMER_CB;
2840 } else {
2841 if (cr) {
2842 lp->local_state = 0;
2843 lp->media = SPD_DET;
2844 } else {
2845 lp->local_state++;
2846 }
2847 next_tick = dc21140m_autoconf(dev);
2848 }
2849 break;
2850
2851 case 1:
2852 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2853 next_tick = sr & ~TIMER_CB;
2854 } else {
2855 lp->media = SPD_DET;
2856 lp->local_state = 0;
2857 if (sr) { /* Success! */
2858 lp->tmp = MII_SR_ASSC;
2859 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2860 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2861 if (!(anlpa & MII_ANLPA_RF) &&
2862 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2863 if (cap & MII_ANA_100M) {
2864 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2865 lp->media = _100Mb;
2866 } else if (cap & MII_ANA_10M) {
2867 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2868
2869 lp->media = _10Mb;
2870 }
2871 }
2872 } /* Auto Negotiation failed to finish */
2873 next_tick = dc21140m_autoconf(dev);
2874 } /* Auto Negotiation failed to start */
2875 break;
2876 }
2877 break;
2878
2879 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2880 if (lp->timeout < 0) {
2881 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2882 (~gep_rd(dev) & GEP_LNP));
2883 SET_100Mb_PDET;
2884 }
2885 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2886 next_tick = slnk & ~TIMER_CB;
2887 } else {
2888 if (is_spd_100(dev) && is_100_up(dev)) {
2889 lp->media = _100Mb;
2890 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2891 lp->media = _10Mb;
2892 } else {
2893 lp->media = NC;
2894 }
2895 next_tick = dc21140m_autoconf(dev);
2896 }
2897 break;
2898
2899 case _100Mb: /* Set 100Mb/s */
2900 next_tick = 3000;
2901 if (!lp->tx_enable) {
2902 SET_100Mb;
2903 de4x5_init_connection(dev);
2904 } else {
2905 if (!lp->linkOK && (lp->autosense == AUTO)) {
2906 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2907 lp->media = INIT;
2908 lp->tcount++;
2909 next_tick = DE4X5_AUTOSENSE_MS;
2910 }
2911 }
2912 }
2913 break;
2914
2915 case BNC:
2916 case AUI:
2917 case _10Mb: /* Set 10Mb/s */
2918 next_tick = 3000;
2919 if (!lp->tx_enable) {
2920 SET_10Mb;
2921 de4x5_init_connection(dev);
2922 } else {
2923 if (!lp->linkOK && (lp->autosense == AUTO)) {
2924 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2925 lp->media = INIT;
2926 lp->tcount++;
2927 next_tick = DE4X5_AUTOSENSE_MS;
2928 }
2929 }
2930 }
2931 break;
2932
2933 case NC:
2934 if (lp->media != lp->c_media) {
2935 de4x5_dbg_media(dev);
2936 lp->c_media = lp->media;
2937 }
2938 lp->media = INIT;
2939 lp->tx_enable = FALSE;
2940 break;
2941 }
2942
2943 return next_tick;
2944 }
2945
2946 /*
2947 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2948 ** changing how I figure out the media - but trying to keep it backwards
2949 ** compatible with the de500-xa and de500-aa.
2950 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2951 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2952 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2953 ** active.
2954 ** When autonegotiation is working, the ANS part searches the SROM for
2955 ** the highest common speed (TP) link that both can run and if that can
2956 ** be full duplex. That infoblock is executed and then the link speed set.
2957 **
2958 ** Only _10Mb and _100Mb are tested here.
2959 */
2960 static int
2961 dc2114x_autoconf(struct net_device *dev)
2962 {
2963 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2964 u_long iobase = dev->base_addr;
2965 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2966 int next_tick = DE4X5_AUTOSENSE_MS;
2967
2968 switch (lp->media) {
2969 case INIT:
2970 if (lp->timeout < 0) {
2971 DISABLE_IRQs;
2972 lp->tx_enable = FALSE;
2973 lp->linkOK = 0;
2974 lp->timeout = -1;
2975 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2976 if (lp->params.autosense & ~AUTO) {
2977 srom_map_media(dev); /* Fixed media requested */
2978 if (lp->media != lp->params.autosense) {
2979 lp->tcount++;
2980 lp->media = INIT;
2981 return next_tick;
2982 }
2983 lp->media = INIT;
2984 }
2985 }
2986 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2987 next_tick &= ~TIMER_CB;
2988 } else {
2989 if (lp->autosense == _100Mb) {
2990 lp->media = _100Mb;
2991 } else if (lp->autosense == _10Mb) {
2992 lp->media = _10Mb;
2993 } else if (lp->autosense == TP) {
2994 lp->media = TP;
2995 } else if (lp->autosense == BNC) {
2996 lp->media = BNC;
2997 } else if (lp->autosense == AUI) {
2998 lp->media = AUI;
2999 } else {
3000 lp->media = SPD_DET;
3001 if ((lp->infoblock_media == ANS) &&
3002 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3003 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3004 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3005 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3006 lp->media = ANS;
3007 }
3008 }
3009 lp->local_state = 0;
3010 next_tick = dc2114x_autoconf(dev);
3011 }
3012 break;
3013
3014 case ANS:
3015 switch (lp->local_state) {
3016 case 0:
3017 if (lp->timeout < 0) {
3018 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3019 }
3020 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3021 if (cr < 0) {
3022 next_tick = cr & ~TIMER_CB;
3023 } else {
3024 if (cr) {
3025 lp->local_state = 0;
3026 lp->media = SPD_DET;
3027 } else {
3028 lp->local_state++;
3029 }
3030 next_tick = dc2114x_autoconf(dev);
3031 }
3032 break;
3033
3034 case 1:
3035 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3036 next_tick = sr & ~TIMER_CB;
3037 } else {
3038 lp->media = SPD_DET;
3039 lp->local_state = 0;
3040 if (sr) { /* Success! */
3041 lp->tmp = MII_SR_ASSC;
3042 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3043 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3044 if (!(anlpa & MII_ANLPA_RF) &&
3045 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3046 if (cap & MII_ANA_100M) {
3047 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3048 lp->media = _100Mb;
3049 } else if (cap & MII_ANA_10M) {
3050 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3051 lp->media = _10Mb;
3052 }
3053 }
3054 } /* Auto Negotiation failed to finish */
3055 next_tick = dc2114x_autoconf(dev);
3056 } /* Auto Negotiation failed to start */
3057 break;
3058 }
3059 break;
3060
3061 case AUI:
3062 if (!lp->tx_enable) {
3063 if (lp->timeout < 0) {
3064 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3065 outl(omr & ~OMR_FDX, DE4X5_OMR);
3066 }
3067 irqs = 0;
3068 irq_mask = 0;
3069 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3070 if (sts < 0) {
3071 next_tick = sts & ~TIMER_CB;
3072 } else {
3073 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3074 lp->media = BNC;
3075 next_tick = dc2114x_autoconf(dev);
3076 } else {
3077 lp->local_state = 1;
3078 de4x5_init_connection(dev);
3079 }
3080 }
3081 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3082 lp->media = AUI_SUSPECT;
3083 next_tick = 3000;
3084 }
3085 break;
3086
3087 case AUI_SUSPECT:
3088 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3089 break;
3090
3091 case BNC:
3092 switch (lp->local_state) {
3093 case 0:
3094 if (lp->timeout < 0) {
3095 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3096 outl(omr & ~OMR_FDX, DE4X5_OMR);
3097 }
3098 irqs = 0;
3099 irq_mask = 0;
3100 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3101 if (sts < 0) {
3102 next_tick = sts & ~TIMER_CB;
3103 } else {
3104 lp->local_state++; /* Ensure media connected */
3105 next_tick = dc2114x_autoconf(dev);
3106 }
3107 break;
3108
3109 case 1:
3110 if (!lp->tx_enable) {
3111 if ((sts = ping_media(dev, 3000)) < 0) {
3112 next_tick = sts & ~TIMER_CB;
3113 } else {
3114 if (sts) {
3115 lp->local_state = 0;
3116 lp->tcount++;
3117 lp->media = INIT;
3118 } else {
3119 de4x5_init_connection(dev);
3120 }
3121 }
3122 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3123 lp->media = BNC_SUSPECT;
3124 next_tick = 3000;
3125 }
3126 break;
3127 }
3128 break;
3129
3130 case BNC_SUSPECT:
3131 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3132 break;
3133
3134 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3135 if (srom_map_media(dev) < 0) {
3136 lp->tcount++;
3137 lp->media = INIT;
3138 return next_tick;
3139 }
3140 if (lp->media == _100Mb) {
3141 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3142 lp->media = SPD_DET;
3143 return (slnk & ~TIMER_CB);
3144 }
3145 } else {
3146 if (wait_for_link(dev) < 0) {
3147 lp->media = SPD_DET;
3148 return PDET_LINK_WAIT;
3149 }
3150 }
3151 if (lp->media == ANS) { /* Do MII parallel detection */
3152 if (is_spd_100(dev)) {
3153 lp->media = _100Mb;
3154 } else {
3155 lp->media = _10Mb;
3156 }
3157 next_tick = dc2114x_autoconf(dev);
3158 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3159 (((lp->media == _10Mb) || (lp->media == TP) ||
3160 (lp->media == BNC) || (lp->media == AUI)) &&
3161 is_10_up(dev))) {
3162 next_tick = dc2114x_autoconf(dev);
3163 } else {
3164 lp->tcount++;
3165 lp->media = INIT;
3166 }
3167 break;
3168
3169 case _10Mb:
3170 next_tick = 3000;
3171 if (!lp->tx_enable) {
3172 SET_10Mb;
3173 de4x5_init_connection(dev);
3174 } else {
3175 if (!lp->linkOK && (lp->autosense == AUTO)) {
3176 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3177 lp->media = INIT;
3178 lp->tcount++;
3179 next_tick = DE4X5_AUTOSENSE_MS;
3180 }
3181 }
3182 }
3183 break;
3184
3185 case _100Mb:
3186 next_tick = 3000;
3187 if (!lp->tx_enable) {
3188 SET_100Mb;
3189 de4x5_init_connection(dev);
3190 } else {
3191 if (!lp->linkOK && (lp->autosense == AUTO)) {
3192 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3193 lp->media = INIT;
3194 lp->tcount++;
3195 next_tick = DE4X5_AUTOSENSE_MS;
3196 }
3197 }
3198 }
3199 break;
3200
3201 default:
3202 lp->tcount++;
3203 printk("Huh?: media:%02x\n", lp->media);
3204 lp->media = INIT;
3205 break;
3206 }
3207
3208 return next_tick;
3209 }
3210
3211 static int
3212 srom_autoconf(struct net_device *dev)
3213 {
3214 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3215
3216 return lp->infoleaf_fn(dev);
3217 }
3218
3219 /*
3220 ** This mapping keeps the original media codes and FDX flag unchanged.
3221 ** While it isn't strictly necessary, it helps me for the moment...
3222 ** The early return avoids a media state / SROM media space clash.
3223 */
3224 static int
3225 srom_map_media(struct net_device *dev)
3226 {
3227 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3228
3229 lp->fdx = 0;
3230 if (lp->infoblock_media == lp->media)
3231 return 0;
3232
3233 switch(lp->infoblock_media) {
3234 case SROM_10BASETF:
3235 if (!lp->params.fdx) return -1;
3236 lp->fdx = TRUE;
3237 case SROM_10BASET:
3238 if (lp->params.fdx && !lp->fdx) return -1;
3239 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3240 lp->media = _10Mb;
3241 } else {
3242 lp->media = TP;
3243 }
3244 break;
3245
3246 case SROM_10BASE2:
3247 lp->media = BNC;
3248 break;
3249
3250 case SROM_10BASE5:
3251 lp->media = AUI;
3252 break;
3253
3254 case SROM_100BASETF:
3255 if (!lp->params.fdx) return -1;
3256 lp->fdx = TRUE;
3257 case SROM_100BASET:
3258 if (lp->params.fdx && !lp->fdx) return -1;
3259 lp->media = _100Mb;
3260 break;
3261
3262 case SROM_100BASET4:
3263 lp->media = _100Mb;
3264 break;
3265
3266 case SROM_100BASEFF:
3267 if (!lp->params.fdx) return -1;
3268 lp->fdx = TRUE;
3269 case SROM_100BASEF:
3270 if (lp->params.fdx && !lp->fdx) return -1;
3271 lp->media = _100Mb;
3272 break;
3273
3274 case ANS:
3275 lp->media = ANS;
3276 lp->fdx = lp->params.fdx;
3277 break;
3278
3279 default:
3280 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3281 lp->infoblock_media);
3282 return -1;
3283 break;
3284 }
3285
3286 return 0;
3287 }
3288
3289 static void
3290 de4x5_init_connection(struct net_device *dev)
3291 {
3292 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3293 u_long iobase = dev->base_addr;
3294 u_long flags = 0;
3295
3296 if (lp->media != lp->c_media) {
3297 de4x5_dbg_media(dev);
3298 lp->c_media = lp->media; /* Stop scrolling media messages */
3299 }
3300
3301 spin_lock_irqsave(&lp->lock, flags);
3302 de4x5_rst_desc_ring(dev);
3303 de4x5_setup_intr(dev);
3304 lp->tx_enable = YES;
3305 spin_unlock_irqrestore(&lp->lock, flags);
3306 outl(POLL_DEMAND, DE4X5_TPD);
3307
3308 netif_wake_queue(dev);
3309
3310 return;
3311 }
3312
3313 /*
3314 ** General PHY reset function. Some MII devices don't reset correctly
3315 ** since their MII address pins can float at voltages that are dependent
3316 ** on the signal pin use. Do a double reset to ensure a reset.
3317 */
3318 static int
3319 de4x5_reset_phy(struct net_device *dev)
3320 {
3321 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3322 u_long iobase = dev->base_addr;
3323 int next_tick = 0;
3324
3325 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3326 if (lp->timeout < 0) {
3327 if (lp->useSROM) {
3328 if (lp->phy[lp->active].rst) {
3329 srom_exec(dev, lp->phy[lp->active].rst);
3330 srom_exec(dev, lp->phy[lp->active].rst);
3331 } else if (lp->rst) { /* Type 5 infoblock reset */
3332 srom_exec(dev, lp->rst);
3333 srom_exec(dev, lp->rst);
3334 }
3335 } else {
3336 PHY_HARD_RESET;
3337 }
3338 if (lp->useMII) {
3339 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3340 }
3341 }
3342 if (lp->useMII) {
3343 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3344 }
3345 } else if (lp->chipset == DC21140) {
3346 PHY_HARD_RESET;
3347 }
3348
3349 return next_tick;
3350 }
3351
3352 static int
3353 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3354 {
3355 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3356 u_long iobase = dev->base_addr;
3357 s32 sts, csr12;
3358
3359 if (lp->timeout < 0) {
3360 lp->timeout = msec/100;
3361 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3362 reset_init_sia(dev, csr13, csr14, csr15);
3363 }
3364
3365 /* set up the interrupt mask */
3366 outl(irq_mask, DE4X5_IMR);
3367
3368 /* clear all pending interrupts */
3369 sts = inl(DE4X5_STS);
3370 outl(sts, DE4X5_STS);
3371
3372 /* clear csr12 NRA and SRA bits */
3373 if ((lp->chipset == DC21041) || lp->useSROM) {
3374 csr12 = inl(DE4X5_SISR);
3375 outl(csr12, DE4X5_SISR);
3376 }
3377 }
3378
3379 sts = inl(DE4X5_STS) & ~TIMER_CB;
3380
3381 if (!(sts & irqs) && --lp->timeout) {
3382 sts = 100 | TIMER_CB;
3383 } else {
3384 lp->timeout = -1;
3385 }
3386
3387 return sts;
3388 }
3389
3390 static int
3391 test_tp(struct net_device *dev, s32 msec)
3392 {
3393 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3394 u_long iobase = dev->base_addr;
3395 int sisr;
3396
3397 if (lp->timeout < 0) {
3398 lp->timeout = msec/100;
3399 }
3400
3401 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3402
3403 if (sisr && --lp->timeout) {
3404 sisr = 100 | TIMER_CB;
3405 } else {
3406 lp->timeout = -1;
3407 }
3408
3409 return sisr;
3410 }
3411
3412 /*
3413 ** Samples the 100Mb Link State Signal. The sample interval is important
3414 ** because too fast a rate can give erroneous results and confuse the
3415 ** speed sense algorithm.
3416 */
3417 #define SAMPLE_INTERVAL 500 /* ms */
3418 #define SAMPLE_DELAY 2000 /* ms */
3419 static int
3420 test_for_100Mb(struct net_device *dev, int msec)
3421 {
3422 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3423 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3424
3425 if (lp->timeout < 0) {
3426 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3427 if (msec > SAMPLE_DELAY) {
3428 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3429 gep = SAMPLE_DELAY | TIMER_CB;
3430 return gep;
3431 } else {
3432 lp->timeout = msec/SAMPLE_INTERVAL;
3433 }
3434 }
3435
3436 if (lp->phy[lp->active].id || lp->useSROM) {
3437 gep = is_100_up(dev) | is_spd_100(dev);
3438 } else {
3439 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3440 }
3441 if (!(gep & ret) && --lp->timeout) {
3442 gep = SAMPLE_INTERVAL | TIMER_CB;
3443 } else {
3444 lp->timeout = -1;
3445 }
3446
3447 return gep;
3448 }
3449
3450 static int
3451 wait_for_link(struct net_device *dev)
3452 {
3453 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3454
3455 if (lp->timeout < 0) {
3456 lp->timeout = 1;
3457 }
3458
3459 if (lp->timeout--) {
3460 return TIMER_CB;
3461 } else {
3462 lp->timeout = -1;
3463 }
3464
3465 return 0;
3466 }
3467
3468 /*
3469 **
3470 **
3471 */
3472 static int
3473 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3474 {
3475 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3476 int test;
3477 u_long iobase = dev->base_addr;
3478
3479 if (lp->timeout < 0) {
3480 lp->timeout = msec/100;
3481 }
3482
3483 if (pol) pol = ~0;
3484 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3485 test = (reg ^ pol) & mask;
3486
3487 if (test && --lp->timeout) {
3488 reg = 100 | TIMER_CB;
3489 } else {
3490 lp->timeout = -1;
3491 }
3492
3493 return reg;
3494 }
3495
3496 static int
3497 is_spd_100(struct net_device *dev)
3498 {
3499 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3500 u_long iobase = dev->base_addr;
3501 int spd;
3502
3503 if (lp->useMII) {
3504 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3505 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3506 spd &= lp->phy[lp->active].spd.mask;
3507 } else if (!lp->useSROM) { /* de500-xa */
3508 spd = ((~gep_rd(dev)) & GEP_SLNK);
3509 } else {
3510 if ((lp->ibn == 2) || !lp->asBitValid)
3511 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3512
3513 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3514 (lp->linkOK & ~lp->asBitValid);
3515 }
3516
3517 return spd;
3518 }
3519
3520 static int
3521 is_100_up(struct net_device *dev)
3522 {
3523 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3524 u_long iobase = dev->base_addr;
3525
3526 if (lp->useMII) {
3527 /* Double read for sticky bits & temporary drops */
3528 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3529 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3530 } else if (!lp->useSROM) { /* de500-xa */
3531 return ((~gep_rd(dev)) & GEP_SLNK);
3532 } else {
3533 if ((lp->ibn == 2) || !lp->asBitValid)
3534 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3535
3536 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3537 (lp->linkOK & ~lp->asBitValid));
3538 }
3539 }
3540
3541 static int
3542 is_10_up(struct net_device *dev)
3543 {
3544 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3545 u_long iobase = dev->base_addr;
3546
3547 if (lp->useMII) {
3548 /* Double read for sticky bits & temporary drops */
3549 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3550 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3551 } else if (!lp->useSROM) { /* de500-xa */
3552 return ((~gep_rd(dev)) & GEP_LNP);
3553 } else {
3554 if ((lp->ibn == 2) || !lp->asBitValid)
3555 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3556 (~inl(DE4X5_SISR)&SISR_LS10):
3557 0);
3558
3559 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3560 (lp->linkOK & ~lp->asBitValid));
3561 }
3562 }
3563
3564 static int
3565 is_anc_capable(struct net_device *dev)
3566 {
3567 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3568 u_long iobase = dev->base_addr;
3569
3570 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3571 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3572 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3573 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3574 } else {
3575 return 0;
3576 }
3577 }
3578
3579 /*
3580 ** Send a packet onto the media and watch for send errors that indicate the
3581 ** media is bad or unconnected.
3582 */
3583 static int
3584 ping_media(struct net_device *dev, int msec)
3585 {
3586 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3587 u_long iobase = dev->base_addr;
3588 int sisr;
3589
3590 if (lp->timeout < 0) {
3591 lp->timeout = msec/100;
3592
3593 lp->tmp = lp->tx_new; /* Remember the ring position */
3594 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3595 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3596 outl(POLL_DEMAND, DE4X5_TPD);
3597 }
3598
3599 sisr = inl(DE4X5_SISR);
3600
3601 if ((!(sisr & SISR_NCR)) &&
3602 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3603 (--lp->timeout)) {
3604 sisr = 100 | TIMER_CB;
3605 } else {
3606 if ((!(sisr & SISR_NCR)) &&
3607 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3608 lp->timeout) {
3609 sisr = 0;
3610 } else {
3611 sisr = 1;
3612 }
3613 lp->timeout = -1;
3614 }
3615
3616 return sisr;
3617 }
3618
3619 /*
3620 ** This function does 2 things: on Intels it kmalloc's another buffer to
3621 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3622 ** into which the packet is copied.
3623 */
3624 static struct sk_buff *
3625 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3626 {
3627 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3628 struct sk_buff *p;
3629
3630 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3631 struct sk_buff *ret;
3632 u_long i=0, tmp;
3633
3634 p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3635 if (!p) return NULL;
3636
3637 p->dev = dev;
3638 tmp = virt_to_bus(p->data);
3639 i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3640 skb_reserve(p, i);
3641 lp->rx_ring[index].buf = tmp + i;
3642
3643 ret = lp->rx_skb[index];
3644 lp->rx_skb[index] = p;
3645
3646 if ((u_long) ret > 1) {
3647 skb_put(ret, len);
3648 }
3649
3650 return ret;
3651
3652 #else
3653 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3654
3655 p = dev_alloc_skb(len + 2);
3656 if (!p) return NULL;
3657
3658 p->dev = dev;
3659 skb_reserve(p, 2); /* Align */
3660 if (index < lp->rx_old) { /* Wrapped buffer */
3661 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3662 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3663 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3664 } else { /* Linear buffer */
3665 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3666 }
3667
3668 return p;
3669 #endif
3670 }
3671
3672 static void
3673 de4x5_free_rx_buffs(struct net_device *dev)
3674 {
3675 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3676 int i;
3677
3678 for (i=0; i<lp->rxRingSize; i++) {
3679 if ((u_long) lp->rx_skb[i] > 1) {
3680 dev_kfree_skb(lp->rx_skb[i]);
3681 }
3682 lp->rx_ring[i].status = 0;
3683 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3684 }
3685
3686 return;
3687 }
3688
3689 static void
3690 de4x5_free_tx_buffs(struct net_device *dev)
3691 {
3692 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3693 int i;
3694
3695 for (i=0; i<lp->txRingSize; i++) {
3696 if (lp->tx_skb[i])
3697 de4x5_free_tx_buff(lp, i);
3698 lp->tx_ring[i].status = 0;
3699 }
3700
3701 /* Unload the locally queued packets */
3702 while (lp->cache.skb) {
3703 dev_kfree_skb(de4x5_get_cache(dev));
3704 }
3705
3706 return;
3707 }
3708
3709 /*
3710 ** When a user pulls a connection, the DECchip can end up in a
3711 ** 'running - waiting for end of transmission' state. This means that we
3712 ** have to perform a chip soft reset to ensure that we can synchronize
3713 ** the hardware and software and make any media probes using a loopback
3714 ** packet meaningful.
3715 */
3716 static void
3717 de4x5_save_skbs(struct net_device *dev)
3718 {
3719 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3720 u_long iobase = dev->base_addr;
3721 s32 omr;
3722
3723 if (!lp->cache.save_cnt) {
3724 STOP_DE4X5;
3725 de4x5_tx(dev); /* Flush any sent skb's */
3726 de4x5_free_tx_buffs(dev);
3727 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3728 de4x5_sw_reset(dev);
3729 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3730 lp->cache.save_cnt++;
3731 START_DE4X5;
3732 }
3733
3734 return;
3735 }
3736
3737 static void
3738 de4x5_rst_desc_ring(struct net_device *dev)
3739 {
3740 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3741 u_long iobase = dev->base_addr;
3742 int i;
3743 s32 omr;
3744
3745 if (lp->cache.save_cnt) {
3746 STOP_DE4X5;
3747 outl(lp->dma_rings, DE4X5_RRBA);
3748 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3749 DE4X5_TRBA);
3750
3751 lp->rx_new = lp->rx_old = 0;
3752 lp->tx_new = lp->tx_old = 0;
3753
3754 for (i = 0; i < lp->rxRingSize; i++) {
3755 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3756 }
3757
3758 for (i = 0; i < lp->txRingSize; i++) {
3759 lp->tx_ring[i].status = cpu_to_le32(0);
3760 }
3761
3762 barrier();
3763 lp->cache.save_cnt--;
3764 START_DE4X5;
3765 }
3766
3767 return;
3768 }
3769
3770 static void
3771 de4x5_cache_state(struct net_device *dev, int flag)
3772 {
3773 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3774 u_long iobase = dev->base_addr;
3775
3776 switch(flag) {
3777 case DE4X5_SAVE_STATE:
3778 lp->cache.csr0 = inl(DE4X5_BMR);
3779 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3780 lp->cache.csr7 = inl(DE4X5_IMR);
3781 break;
3782
3783 case DE4X5_RESTORE_STATE:
3784 outl(lp->cache.csr0, DE4X5_BMR);
3785 outl(lp->cache.csr6, DE4X5_OMR);
3786 outl(lp->cache.csr7, DE4X5_IMR);
3787 if (lp->chipset == DC21140) {
3788 gep_wr(lp->cache.gepc, dev);
3789 gep_wr(lp->cache.gep, dev);
3790 } else {
3791 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3792 lp->cache.csr15);
3793 }
3794 break;
3795 }
3796
3797 return;
3798 }
3799
3800 static void
3801 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3802 {
3803 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3804 struct sk_buff *p;
3805
3806 if (lp->cache.skb) {
3807 for (p=lp->cache.skb; p->next; p=p->next);
3808 p->next = skb;
3809 } else {
3810 lp->cache.skb = skb;
3811 }
3812 skb->next = NULL;
3813
3814 return;
3815 }
3816
3817 static void
3818 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3819 {
3820 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3821 struct sk_buff *p = lp->cache.skb;
3822
3823 lp->cache.skb = skb;
3824 skb->next = p;
3825
3826 return;
3827 }
3828
3829 static struct sk_buff *
3830 de4x5_get_cache(struct net_device *dev)
3831 {
3832 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3833 struct sk_buff *p = lp->cache.skb;
3834
3835 if (p) {
3836 lp->cache.skb = p->next;
3837 p->next = NULL;
3838 }
3839
3840 return p;
3841 }
3842
3843 /*
3844 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3845 ** is received and the auto-negotiation status is NWAY OK.
3846 */
3847 static int
3848 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3849 {
3850 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3851 u_long iobase = dev->base_addr;
3852 s32 sts, ans;
3853
3854 if (lp->timeout < 0) {
3855 lp->timeout = msec/100;
3856 outl(irq_mask, DE4X5_IMR);
3857
3858 /* clear all pending interrupts */
3859 sts = inl(DE4X5_STS);
3860 outl(sts, DE4X5_STS);
3861 }
3862
3863 ans = inl(DE4X5_SISR) & SISR_ANS;
3864 sts = inl(DE4X5_STS) & ~TIMER_CB;
3865
3866 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3867 sts = 100 | TIMER_CB;
3868 } else {
3869 lp->timeout = -1;
3870 }
3871
3872 return sts;
3873 }
3874
3875 static void
3876 de4x5_setup_intr(struct net_device *dev)
3877 {
3878 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3879 u_long iobase = dev->base_addr;
3880 s32 imr, sts;
3881
3882 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3883 imr = 0;
3884 UNMASK_IRQs;
3885 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3886 outl(sts, DE4X5_STS);
3887 ENABLE_IRQs;
3888 }
3889
3890 return;
3891 }
3892
3893 /*
3894 **
3895 */
3896 static void
3897 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3898 {
3899 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3900 u_long iobase = dev->base_addr;
3901
3902 RESET_SIA;
3903 if (lp->useSROM) {
3904 if (lp->ibn == 3) {
3905 srom_exec(dev, lp->phy[lp->active].rst);
3906 srom_exec(dev, lp->phy[lp->active].gep);
3907 outl(1, DE4X5_SICR);
3908 return;
3909 } else {
3910 csr15 = lp->cache.csr15;
3911 csr14 = lp->cache.csr14;
3912 csr13 = lp->cache.csr13;
3913 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3914 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3915 }
3916 } else {
3917 outl(csr15, DE4X5_SIGR);
3918 }
3919 outl(csr14, DE4X5_STRR);
3920 outl(csr13, DE4X5_SICR);
3921
3922 de4x5_ms_delay(10);
3923
3924 return;
3925 }
3926
3927 /*
3928 ** Create a loopback ethernet packet
3929 */
3930 static void
3931 create_packet(struct net_device *dev, char *frame, int len)
3932 {
3933 int i;
3934 char *buf = frame;
3935
3936 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3937 *buf++ = dev->dev_addr[i];
3938 }
3939 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3940 *buf++ = dev->dev_addr[i];
3941 }
3942
3943 *buf++ = 0; /* Packet length (2 bytes) */
3944 *buf++ = 1;
3945
3946 return;
3947 }
3948
3949 /*
3950 ** Known delay in microseconds
3951 */
3952 static void
3953 de4x5_us_delay(u32 usec)
3954 {
3955 udelay(usec);
3956
3957 return;
3958 }
3959
3960 /*
3961 ** Known delay in milliseconds, in millisecond steps.
3962 */
3963 static void
3964 de4x5_ms_delay(u32 msec)
3965 {
3966 u_int i;
3967
3968 for (i=0; i<msec; i++) {
3969 de4x5_us_delay(1000);
3970 }
3971
3972 return;
3973 }
3974
3975
3976 /*
3977 ** Look for a particular board name in the EISA configuration space
3978 */
3979 static int
3980 EISA_signature(char *name, s32 eisa_id)
3981 {
3982 static c_char *signatures[] = DE4X5_SIGNATURE;
3983 char ManCode[DE4X5_STRLEN];
3984 union {
3985 s32 ID;
3986 char Id[4];
3987 } Eisa;
3988 int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3989
3990 *name = '\0';
3991 Eisa.ID = inl(eisa_id);
3992
3993 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3994 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3995 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3996 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3997 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3998 ManCode[5]='\0';
3999
4000 for (i=0;i<siglen;i++) {
4001 if (strstr(ManCode, signatures[i]) != NULL) {
4002 strcpy(name,ManCode);
4003 status = 1;
4004 break;
4005 }
4006 }
4007
4008 return status; /* return the device name string */
4009 }
4010
4011 /*
4012 ** Look for a particular board name in the PCI configuration space
4013 */
4014 static int
4015 PCI_signature(char *name, struct bus_type *lp)
4016 {
4017 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
4018 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
4019
4020 if (lp->chipset == DC21040) {
4021 strcpy(name, "DE434/5");
4022 return status;
4023 } else { /* Search for a DEC name in the SROM */
4024 int i = *((char *)&lp->srom + 19) * 3;
4025 strncpy(name, (char *)&lp->srom + 26 + i, 8);
4026 }
4027 name[8] = '\0';
4028 for (i=0; i<siglen; i++) {
4029 if (strstr(name,de4x5_signatures[i])!=NULL) break;
4030 }
4031 if (i == siglen) {
4032 if (dec_only) {
4033 *name = '\0';
4034 } else { /* Use chip name to avoid confusion */
4035 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
4036 ((lp->chipset == DC21041) ? "DC21041" :
4037 ((lp->chipset == DC21140) ? "DC21140" :
4038 ((lp->chipset == DC21142) ? "DC21142" :
4039 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4040 )))))));
4041 }
4042 if (lp->chipset != DC21041) {
4043 useSROM = TRUE; /* card is not recognisably DEC */
4044 }
4045 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4046 useSROM = TRUE;
4047 }
4048
4049 return status;
4050 }
4051
4052 /*
4053 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4054 ** the DC21040, else read the SROM for the other chips.
4055 ** The SROM may not be present in a multi-MAC card, so first read the
4056 ** MAC address and check for a bad address. If there is a bad one then exit
4057 ** immediately with the prior srom contents intact (the h/w address will
4058 ** be fixed up later).
4059 */
4060 static void
4061 DevicePresent(u_long aprom_addr)
4062 {
4063 int i, j=0;
4064 struct bus_type *lp = &bus;
4065
4066 if (lp->chipset == DC21040) {
4067 if (lp->bus == EISA) {
4068 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4069 } else {
4070 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4071 }
4072 } else { /* Read new srom */
4073 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4074 for (i=0; i<(ETH_ALEN>>1); i++) {
4075 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4076 *p = le16_to_cpu(tmp);
4077 j += *p++;
4078 }
4079 if ((j == 0) || (j == 0x2fffd)) {
4080 return;
4081 }
4082
4083 p=(short *)&lp->srom;
4084 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4085 tmp = srom_rd(aprom_addr, i);
4086 *p++ = le16_to_cpu(tmp);
4087 }
4088 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4089 }
4090
4091 return;
4092 }
4093
4094 /*
4095 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4096 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4097 ** it...from depca.c.
4098 */
4099 static void
4100 enet_addr_rst(u_long aprom_addr)
4101 {
4102 union {
4103 struct {
4104 u32 a;
4105 u32 b;
4106 } llsig;
4107 char Sig[sizeof(u32) << 1];
4108 } dev;
4109 short sigLength=0;
4110 s8 data;
4111 int i, j;
4112
4113 dev.llsig.a = ETH_PROM_SIG;
4114 dev.llsig.b = ETH_PROM_SIG;
4115 sigLength = sizeof(u32) << 1;
4116
4117 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4118 data = inb(aprom_addr);
4119 if (dev.Sig[j] == data) { /* track signature */
4120 j++;
4121 } else { /* lost signature; begin search again */
4122 if (data == dev.Sig[0]) { /* rare case.... */
4123 j=1;
4124 } else {
4125 j=0;
4126 }
4127 }
4128 }
4129
4130 return;
4131 }
4132
4133 /*
4134 ** For the bad status case and no SROM, then add one to the previous
4135 ** address. However, need to add one backwards in case we have 0xff
4136 ** as one or more of the bytes. Only the last 3 bytes should be checked
4137 ** as the first three are invariant - assigned to an organisation.
4138 */
4139 static int
4140 get_hw_addr(struct net_device *dev)
4141 {
4142 u_long iobase = dev->base_addr;
4143 int broken, i, k, tmp, status = 0;
4144 u_short j,chksum;
4145 struct bus_type *lp = &bus;
4146
4147 broken = de4x5_bad_srom(lp);
4148
4149 for (i=0,k=0,j=0;j<3;j++) {
4150 k <<= 1;
4151 if (k > 0xffff) k-=0xffff;
4152
4153 if (lp->bus == PCI) {
4154 if (lp->chipset == DC21040) {
4155 while ((tmp = inl(DE4X5_APROM)) < 0);
4156 k += (u_char) tmp;
4157 dev->dev_addr[i++] = (u_char) tmp;
4158 while ((tmp = inl(DE4X5_APROM)) < 0);
4159 k += (u_short) (tmp << 8);
4160 dev->dev_addr[i++] = (u_char) tmp;
4161 } else if (!broken) {
4162 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4163 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4164 } else if ((broken == SMC) || (broken == ACCTON)) {
4165 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4166 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4167 }
4168 } else {
4169 k += (u_char) (tmp = inb(EISA_APROM));
4170 dev->dev_addr[i++] = (u_char) tmp;
4171 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4172 dev->dev_addr[i++] = (u_char) tmp;
4173 }
4174
4175 if (k > 0xffff) k-=0xffff;
4176 }
4177 if (k == 0xffff) k=0;
4178
4179 if (lp->bus == PCI) {
4180 if (lp->chipset == DC21040) {
4181 while ((tmp = inl(DE4X5_APROM)) < 0);
4182 chksum = (u_char) tmp;
4183 while ((tmp = inl(DE4X5_APROM)) < 0);
4184 chksum |= (u_short) (tmp << 8);
4185 if ((k != chksum) && (dec_only)) status = -1;
4186 }
4187 } else {
4188 chksum = (u_char) inb(EISA_APROM);
4189 chksum |= (u_short) (inb(EISA_APROM) << 8);
4190 if ((k != chksum) && (dec_only)) status = -1;
4191 }
4192
4193 /* If possible, try to fix a broken card - SMC only so far */
4194 srom_repair(dev, broken);
4195
4196 #ifdef CONFIG_PPC
4197 /*
4198 ** If the address starts with 00 a0, we have to bit-reverse
4199 ** each byte of the address.
4200 */
4201 if ( (ppc_md.ppc_machine & _MACH_Pmac) &&
4202 (dev->dev_addr[0] == 0) &&
4203 (dev->dev_addr[1] == 0xa0) )
4204 {
4205 for (i = 0; i < ETH_ALEN; ++i)
4206 {
4207 int x = dev->dev_addr[i];
4208 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4209 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4210 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4211 }
4212 }
4213 #endif /* CONFIG_PPC */
4214
4215 /* Test for a bad enet address */
4216 status = test_bad_enet(dev, status);
4217
4218 return status;
4219 }
4220
4221 /*
4222 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4223 ** didn't seem to work here...?
4224 */
4225 static int
4226 de4x5_bad_srom(struct bus_type *lp)
4227 {
4228 int i, status = 0;
4229
4230 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4231 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4232 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4233 if (i == 0) {
4234 status = SMC;
4235 } else if (i == 1) {
4236 status = ACCTON;
4237 }
4238 break;
4239 }
4240 }
4241
4242 return status;
4243 }
4244
4245 static int
4246 de4x5_strncmp(char *a, char *b, int n)
4247 {
4248 int ret=0;
4249
4250 for (;n && !ret;n--) {
4251 ret = *a++ - *b++;
4252 }
4253
4254 return ret;
4255 }
4256
4257 static void
4258 srom_repair(struct net_device *dev, int card)
4259 {
4260 struct bus_type *lp = &bus;
4261
4262 switch(card) {
4263 case SMC:
4264 memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4265 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4266 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4267 useSROM = TRUE;
4268 break;
4269 }
4270
4271 return;
4272 }
4273
4274 /*
4275 ** Assume that the irq's do not follow the PCI spec - this is seems
4276 ** to be true so far (2 for 2).
4277 */
4278 static int
4279 test_bad_enet(struct net_device *dev, int status)
4280 {
4281 struct bus_type *lp = &bus;
4282 int i, tmp;
4283
4284 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4285 if ((tmp == 0) || (tmp == 0x5fa)) {
4286 if ((lp->chipset == last.chipset) &&
4287 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4288 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4289 for (i=ETH_ALEN-1; i>2; --i) {
4290 dev->dev_addr[i] += 1;
4291 if (dev->dev_addr[i] != 0) break;
4292 }
4293 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4294 if (!an_exception(lp)) {
4295 dev->irq = last.irq;
4296 }
4297
4298 status = 0;
4299 }
4300 } else if (!status) {
4301 last.chipset = lp->chipset;
4302 last.bus = lp->bus_num;
4303 last.irq = dev->irq;
4304 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4305 }
4306
4307 return status;
4308 }
4309
4310 /*
4311 ** List of board exceptions with correctly wired IRQs
4312 */
4313 static int
4314 an_exception(struct bus_type *lp)
4315 {
4316 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4317 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4318 return -1;
4319 }
4320
4321 return 0;
4322 }
4323
4324 /*
4325 ** SROM Read
4326 */
4327 static short
4328 srom_rd(u_long addr, u_char offset)
4329 {
4330 sendto_srom(SROM_RD | SROM_SR, addr);
4331
4332 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4333 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4334 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4335
4336 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4337 }
4338
4339 static void
4340 srom_latch(u_int command, u_long addr)
4341 {
4342 sendto_srom(command, addr);
4343 sendto_srom(command | DT_CLK, addr);
4344 sendto_srom(command, addr);
4345
4346 return;
4347 }
4348
4349 static void
4350 srom_command(u_int command, u_long addr)
4351 {
4352 srom_latch(command, addr);
4353 srom_latch(command, addr);
4354 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4355
4356 return;
4357 }
4358
4359 static void
4360 srom_address(u_int command, u_long addr, u_char offset)
4361 {
4362 int i, a;
4363
4364 a = offset << 2;
4365 for (i=0; i<6; i++, a <<= 1) {
4366 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4367 }
4368 de4x5_us_delay(1);
4369
4370 i = (getfrom_srom(addr) >> 3) & 0x01;
4371
4372 return;
4373 }
4374
4375 static short
4376 srom_data(u_int command, u_long addr)
4377 {
4378 int i;
4379 short word = 0;
4380 s32 tmp;
4381
4382 for (i=0; i<16; i++) {
4383 sendto_srom(command | DT_CLK, addr);
4384 tmp = getfrom_srom(addr);
4385 sendto_srom(command, addr);
4386
4387 word = (word << 1) | ((tmp >> 3) & 0x01);
4388 }
4389
4390 sendto_srom(command & 0x0000ff00, addr);
4391
4392 return word;
4393 }
4394
4395 /*
4396 static void
4397 srom_busy(u_int command, u_long addr)
4398 {
4399 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4400
4401 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4402 de4x5_ms_delay(1);
4403 }
4404
4405 sendto_srom(command & 0x0000ff00, addr);
4406
4407 return;
4408 }
4409 */
4410
4411 static void
4412 sendto_srom(u_int command, u_long addr)
4413 {
4414 outl(command, addr);
4415 udelay(1);
4416
4417 return;
4418 }
4419
4420 static int
4421 getfrom_srom(u_long addr)
4422 {
4423 s32 tmp;
4424
4425 tmp = inl(addr);
4426 udelay(1);
4427
4428 return tmp;
4429 }
4430
4431 static int
4432 srom_infoleaf_info(struct net_device *dev)
4433 {
4434 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4435 int i, count;
4436 u_char *p;
4437
4438 /* Find the infoleaf decoder function that matches this chipset */
4439 for (i=0; i<INFOLEAF_SIZE; i++) {
4440 if (lp->chipset == infoleaf_array[i].chipset) break;
4441 }
4442 if (i == INFOLEAF_SIZE) {
4443 lp->useSROM = FALSE;
4444 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4445 dev->name);
4446 return -ENXIO;
4447 }
4448
4449 lp->infoleaf_fn = infoleaf_array[i].fn;
4450
4451 /* Find the information offset that this function should use */
4452 count = *((u_char *)&lp->srom + 19);
4453 p = (u_char *)&lp->srom + 26;
4454
4455 if (count > 1) {
4456 for (i=count; i; --i, p+=3) {
4457 if (lp->device == *p) break;
4458 }
4459 if (i == 0) {
4460 lp->useSROM = FALSE;
4461 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4462 dev->name, lp->device);
4463 return -ENXIO;
4464 }
4465 }
4466
4467 lp->infoleaf_offset = TWIDDLE(p+1);
4468
4469 return 0;
4470 }
4471
4472 /*
4473 ** This routine loads any type 1 or 3 MII info into the mii device
4474 ** struct and executes any type 5 code to reset PHY devices for this
4475 ** controller.
4476 ** The info for the MII devices will be valid since the index used
4477 ** will follow the discovery process from MII address 1-31 then 0.
4478 */
4479 static void
4480 srom_init(struct net_device *dev)
4481 {
4482 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4483 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4484 u_char count;
4485
4486 p+=2;
4487 if (lp->chipset == DC21140) {
4488 lp->cache.gepc = (*p++ | GEP_CTRL);
4489 gep_wr(lp->cache.gepc, dev);
4490 }
4491
4492 /* Block count */
4493 count = *p++;
4494
4495 /* Jump the infoblocks to find types */
4496 for (;count; --count) {
4497 if (*p < 128) {
4498 p += COMPACT_LEN;
4499 } else if (*(p+1) == 5) {
4500 type5_infoblock(dev, 1, p);
4501 p += ((*p & BLOCK_LEN) + 1);
4502 } else if (*(p+1) == 4) {
4503 p += ((*p & BLOCK_LEN) + 1);
4504 } else if (*(p+1) == 3) {
4505 type3_infoblock(dev, 1, p);
4506 p += ((*p & BLOCK_LEN) + 1);
4507 } else if (*(p+1) == 2) {
4508 p += ((*p & BLOCK_LEN) + 1);
4509 } else if (*(p+1) == 1) {
4510 type1_infoblock(dev, 1, p);
4511 p += ((*p & BLOCK_LEN) + 1);
4512 } else {
4513 p += ((*p & BLOCK_LEN) + 1);
4514 }
4515 }
4516
4517 return;
4518 }
4519
4520 /*
4521 ** A generic routine that writes GEP control, data and reset information
4522 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4523 */
4524 static void
4525 srom_exec(struct net_device *dev, u_char *p)
4526 {
4527 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4528 u_long iobase = dev->base_addr;
4529 u_char count = (p ? *p++ : 0);
4530 u_short *w = (u_short *)p;
4531
4532 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4533
4534 if (lp->chipset != DC21140) RESET_SIA;
4535
4536 while (count--) {
4537 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4538 *p++ : TWIDDLE(w++)), dev);
4539 mdelay(2); /* 2ms per action */
4540 }
4541
4542 if (lp->chipset != DC21140) {
4543 outl(lp->cache.csr14, DE4X5_STRR);
4544 outl(lp->cache.csr13, DE4X5_SICR);
4545 }
4546
4547 return;
4548 }
4549
4550 /*
4551 ** Basically this function is a NOP since it will never be called,
4552 ** unless I implement the DC21041 SROM functions. There's no need
4553 ** since the existing code will be satisfactory for all boards.
4554 */
4555 static int
4556 dc21041_infoleaf(struct net_device *dev)
4557 {
4558 return DE4X5_AUTOSENSE_MS;
4559 }
4560
4561 static int
4562 dc21140_infoleaf(struct net_device *dev)
4563 {
4564 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4565 u_char count = 0;
4566 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4567 int next_tick = DE4X5_AUTOSENSE_MS;
4568
4569 /* Read the connection type */
4570 p+=2;
4571
4572 /* GEP control */
4573 lp->cache.gepc = (*p++ | GEP_CTRL);
4574
4575 /* Block count */
4576 count = *p++;
4577
4578 /* Recursively figure out the info blocks */
4579 if (*p < 128) {
4580 next_tick = dc_infoblock[COMPACT](dev, count, p);
4581 } else {
4582 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4583 }
4584
4585 if (lp->tcount == count) {
4586 lp->media = NC;
4587 if (lp->media != lp->c_media) {
4588 de4x5_dbg_media(dev);
4589 lp->c_media = lp->media;
4590 }
4591 lp->media = INIT;
4592 lp->tcount = 0;
4593 lp->tx_enable = FALSE;
4594 }
4595
4596 return next_tick & ~TIMER_CB;
4597 }
4598
4599 static int
4600 dc21142_infoleaf(struct net_device *dev)
4601 {
4602 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4603 u_char count = 0;
4604 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4605 int next_tick = DE4X5_AUTOSENSE_MS;
4606
4607 /* Read the connection type */
4608 p+=2;
4609
4610 /* Block count */
4611 count = *p++;
4612
4613 /* Recursively figure out the info blocks */
4614 if (*p < 128) {
4615 next_tick = dc_infoblock[COMPACT](dev, count, p);
4616 } else {
4617 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4618 }
4619
4620 if (lp->tcount == count) {
4621 lp->media = NC;
4622 if (lp->media != lp->c_media) {
4623 de4x5_dbg_media(dev);
4624 lp->c_media = lp->media;
4625 }
4626 lp->media = INIT;
4627 lp->tcount = 0;
4628 lp->tx_enable = FALSE;
4629 }
4630
4631 return next_tick & ~TIMER_CB;
4632 }
4633
4634 static int
4635 dc21143_infoleaf(struct net_device *dev)
4636 {
4637 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4638 u_char count = 0;
4639 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4640 int next_tick = DE4X5_AUTOSENSE_MS;
4641
4642 /* Read the connection type */
4643 p+=2;
4644
4645 /* Block count */
4646 count = *p++;
4647
4648 /* Recursively figure out the info blocks */
4649 if (*p < 128) {
4650 next_tick = dc_infoblock[COMPACT](dev, count, p);
4651 } else {
4652 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4653 }
4654 if (lp->tcount == count) {
4655 lp->media = NC;
4656 if (lp->media != lp->c_media) {
4657 de4x5_dbg_media(dev);
4658 lp->c_media = lp->media;
4659 }
4660 lp->media = INIT;
4661 lp->tcount = 0;
4662 lp->tx_enable = FALSE;
4663 }
4664
4665 return next_tick & ~TIMER_CB;
4666 }
4667
4668 /*
4669 ** The compact infoblock is only designed for DC21140[A] chips, so
4670 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4671 */
4672 static int
4673 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4674 {
4675 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4676 u_char flags, csr6;
4677
4678 /* Recursively figure out the info blocks */
4679 if (--count > lp->tcount) {
4680 if (*(p+COMPACT_LEN) < 128) {
4681 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4682 } else {
4683 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4684 }
4685 }
4686
4687 if ((lp->media == INIT) && (lp->timeout < 0)) {
4688 lp->ibn = COMPACT;
4689 lp->active = 0;
4690 gep_wr(lp->cache.gepc, dev);
4691 lp->infoblock_media = (*p++) & COMPACT_MC;
4692 lp->cache.gep = *p++;
4693 csr6 = *p++;
4694 flags = *p++;
4695
4696 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4697 lp->defMedium = (flags & 0x40) ? -1 : 0;
4698 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4699 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4700 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4701 lp->useMII = FALSE;
4702
4703 de4x5_switch_mac_port(dev);
4704 }
4705
4706 return dc21140m_autoconf(dev);
4707 }
4708
4709 /*
4710 ** This block describes non MII media for the DC21140[A] only.
4711 */
4712 static int
4713 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4714 {
4715 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4716 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4717
4718 /* Recursively figure out the info blocks */
4719 if (--count > lp->tcount) {
4720 if (*(p+len) < 128) {
4721 return dc_infoblock[COMPACT](dev, count, p+len);
4722 } else {
4723 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4724 }
4725 }
4726
4727 if ((lp->media == INIT) && (lp->timeout < 0)) {
4728 lp->ibn = 0;
4729 lp->active = 0;
4730 gep_wr(lp->cache.gepc, dev);
4731 p+=2;
4732 lp->infoblock_media = (*p++) & BLOCK0_MC;
4733 lp->cache.gep = *p++;
4734 csr6 = *p++;
4735 flags = *p++;
4736
4737 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4738 lp->defMedium = (flags & 0x40) ? -1 : 0;
4739 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4740 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4741 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4742 lp->useMII = FALSE;
4743
4744 de4x5_switch_mac_port(dev);
4745 }
4746
4747 return dc21140m_autoconf(dev);
4748 }
4749
4750 /* These functions are under construction! */
4751
4752 static int
4753 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4754 {
4755 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4756 u_char len = (*p & BLOCK_LEN)+1;
4757
4758 /* Recursively figure out the info blocks */
4759 if (--count > lp->tcount) {
4760 if (*(p+len) < 128) {
4761 return dc_infoblock[COMPACT](dev, count, p+len);
4762 } else {
4763 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4764 }
4765 }
4766
4767 p += 2;
4768 if (lp->state == INITIALISED) {
4769 lp->ibn = 1;
4770 lp->active = *p++;
4771 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4772 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4773 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4774 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4775 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4776 lp->phy[lp->active].ttm = TWIDDLE(p);
4777 return 0;
4778 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4779 lp->ibn = 1;
4780 lp->active = *p;
4781 lp->infoblock_csr6 = OMR_MII_100;
4782 lp->useMII = TRUE;
4783 lp->infoblock_media = ANS;
4784
4785 de4x5_switch_mac_port(dev);
4786 }
4787
4788 return dc21140m_autoconf(dev);
4789 }
4790
4791 static int
4792 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4793 {
4794 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4795 u_char len = (*p & BLOCK_LEN)+1;
4796
4797 /* Recursively figure out the info blocks */
4798 if (--count > lp->tcount) {
4799 if (*(p+len) < 128) {
4800 return dc_infoblock[COMPACT](dev, count, p+len);
4801 } else {
4802 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4803 }
4804 }
4805
4806 if ((lp->media == INIT) && (lp->timeout < 0)) {
4807 lp->ibn = 2;
4808 lp->active = 0;
4809 p += 2;
4810 lp->infoblock_media = (*p) & MEDIA_CODE;
4811
4812 if ((*p++) & EXT_FIELD) {
4813 lp->cache.csr13 = TWIDDLE(p); p += 2;
4814 lp->cache.csr14 = TWIDDLE(p); p += 2;
4815 lp->cache.csr15 = TWIDDLE(p); p += 2;
4816 } else {
4817 lp->cache.csr13 = CSR13;
4818 lp->cache.csr14 = CSR14;
4819 lp->cache.csr15 = CSR15;
4820 }
4821 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4822 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4823 lp->infoblock_csr6 = OMR_SIA;
4824 lp->useMII = FALSE;
4825
4826 de4x5_switch_mac_port(dev);
4827 }
4828
4829 return dc2114x_autoconf(dev);
4830 }
4831
4832 static int
4833 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4834 {
4835 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4836 u_char len = (*p & BLOCK_LEN)+1;
4837
4838 /* Recursively figure out the info blocks */
4839 if (--count > lp->tcount) {
4840 if (*(p+len) < 128) {
4841 return dc_infoblock[COMPACT](dev, count, p+len);
4842 } else {
4843 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4844 }
4845 }
4846
4847 p += 2;
4848 if (lp->state == INITIALISED) {
4849 lp->ibn = 3;
4850 lp->active = *p++;
4851 if (MOTO_SROM_BUG) lp->active = 0;
4852 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4853 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4854 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4855 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4856 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4857 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4858 lp->phy[lp->active].mci = *p;
4859 return 0;
4860 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4861 lp->ibn = 3;
4862 lp->active = *p;
4863 if (MOTO_SROM_BUG) lp->active = 0;
4864 lp->infoblock_csr6 = OMR_MII_100;
4865 lp->useMII = TRUE;
4866 lp->infoblock_media = ANS;
4867
4868 de4x5_switch_mac_port(dev);
4869 }
4870
4871 return dc2114x_autoconf(dev);
4872 }
4873
4874 static int
4875 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4876 {
4877 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4878 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4879
4880 /* Recursively figure out the info blocks */
4881 if (--count > lp->tcount) {
4882 if (*(p+len) < 128) {
4883 return dc_infoblock[COMPACT](dev, count, p+len);
4884 } else {
4885 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4886 }
4887 }
4888
4889 if ((lp->media == INIT) && (lp->timeout < 0)) {
4890 lp->ibn = 4;
4891 lp->active = 0;
4892 p+=2;
4893 lp->infoblock_media = (*p++) & MEDIA_CODE;
4894 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4895 lp->cache.csr14 = CSR14;
4896 lp->cache.csr15 = CSR15;
4897 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4898 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4899 csr6 = *p++;
4900 flags = *p++;
4901
4902 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4903 lp->defMedium = (flags & 0x40) ? -1 : 0;
4904 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4905 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4906 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4907 lp->useMII = FALSE;
4908
4909 de4x5_switch_mac_port(dev);
4910 }
4911
4912 return dc2114x_autoconf(dev);
4913 }
4914
4915 /*
4916 ** This block type provides information for resetting external devices
4917 ** (chips) through the General Purpose Register.
4918 */
4919 static int
4920 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4921 {
4922 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4923 u_char len = (*p & BLOCK_LEN)+1;
4924
4925 /* Recursively figure out the info blocks */
4926 if (--count > lp->tcount) {
4927 if (*(p+len) < 128) {
4928 return dc_infoblock[COMPACT](dev, count, p+len);
4929 } else {
4930 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4931 }
4932 }
4933
4934 /* Must be initializing to run this code */
4935 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4936 p+=2;
4937 lp->rst = p;
4938 srom_exec(dev, lp->rst);
4939 }
4940
4941 return DE4X5_AUTOSENSE_MS;
4942 }
4943
4944 /*
4945 ** MII Read/Write
4946 */
4947
4948 static int
4949 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4950 {
4951 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4952 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4953 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4954 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4955 mii_address(phyreg, ioaddr); /* PHY Register to read */
4956 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4957
4958 return mii_rdata(ioaddr); /* Read data */
4959 }
4960
4961 static void
4962 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4963 {
4964 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4965 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4966 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4967 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4968 mii_address(phyreg, ioaddr); /* PHY Register to write */
4969 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4970 data = mii_swap(data, 16); /* Swap data bit ordering */
4971 mii_wdata(data, 16, ioaddr); /* Write data */
4972
4973 return;
4974 }
4975
4976 static int
4977 mii_rdata(u_long ioaddr)
4978 {
4979 int i;
4980 s32 tmp = 0;
4981
4982 for (i=0; i<16; i++) {
4983 tmp <<= 1;
4984 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4985 }
4986
4987 return tmp;
4988 }
4989
4990 static void
4991 mii_wdata(int data, int len, u_long ioaddr)
4992 {
4993 int i;
4994
4995 for (i=0; i<len; i++) {
4996 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4997 data >>= 1;
4998 }
4999
5000 return;
5001 }
5002
5003 static void
5004 mii_address(u_char addr, u_long ioaddr)
5005 {
5006 int i;
5007
5008 addr = mii_swap(addr, 5);
5009 for (i=0; i<5; i++) {
5010 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
5011 addr >>= 1;
5012 }
5013
5014 return;
5015 }
5016
5017 static void
5018 mii_ta(u_long rw, u_long ioaddr)
5019 {
5020 if (rw == MII_STWR) {
5021 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
5022 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
5023 } else {
5024 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
5025 }
5026
5027 return;
5028 }
5029
5030 static int
5031 mii_swap(int data, int len)
5032 {
5033 int i, tmp = 0;
5034
5035 for (i=0; i<len; i++) {
5036 tmp <<= 1;
5037 tmp |= (data & 1);
5038 data >>= 1;
5039 }
5040
5041 return tmp;
5042 }
5043
5044 static void
5045 sendto_mii(u32 command, int data, u_long ioaddr)
5046 {
5047 u32 j;
5048
5049 j = (data & 1) << 17;
5050 outl(command | j, ioaddr);
5051 udelay(1);
5052 outl(command | MII_MDC | j, ioaddr);
5053 udelay(1);
5054
5055 return;
5056 }
5057
5058 static int
5059 getfrom_mii(u32 command, u_long ioaddr)
5060 {
5061 outl(command, ioaddr);
5062 udelay(1);
5063 outl(command | MII_MDC, ioaddr);
5064 udelay(1);
5065
5066 return ((inl(ioaddr) >> 19) & 1);
5067 }
5068
5069 /*
5070 ** Here's 3 ways to calculate the OUI from the ID registers.
5071 */
5072 static int
5073 mii_get_oui(u_char phyaddr, u_long ioaddr)
5074 {
5075 /*
5076 union {
5077 u_short reg;
5078 u_char breg[2];
5079 } a;
5080 int i, r2, r3, ret=0;*/
5081 int r2, r3;
5082
5083 /* Read r2 and r3 */
5084 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5085 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5086 /* SEEQ and Cypress way * /
5087 / * Shuffle r2 and r3 * /
5088 a.reg=0;
5089 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5090 r2 = ((r2>>2)&0x3fff);
5091
5092 / * Bit reverse r3 * /
5093 for (i=0;i<8;i++) {
5094 ret<<=1;
5095 ret |= (r3&1);
5096 r3>>=1;
5097 }
5098
5099 / * Bit reverse r2 * /
5100 for (i=0;i<16;i++) {
5101 a.reg<<=1;
5102 a.reg |= (r2&1);
5103 r2>>=1;
5104 }
5105
5106 / * Swap r2 bytes * /
5107 i=a.breg[0];
5108 a.breg[0]=a.breg[1];
5109 a.breg[1]=i;
5110
5111 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5112 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5113 return r2; /* (I did it) My way */
5114 }
5115
5116 /*
5117 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5118 */
5119 static int
5120 mii_get_phy(struct net_device *dev)
5121 {
5122 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5123 u_long iobase = dev->base_addr;
5124 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5125 int id;
5126
5127 lp->active = 0;
5128 lp->useMII = TRUE;
5129
5130 /* Search the MII address space for possible PHY devices */
5131 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5132 lp->phy[lp->active].addr = i;
5133 if (i==0) n++; /* Count cycles */
5134 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5135 id = mii_get_oui(i, DE4X5_MII);
5136 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5137 for (j=0; j<limit; j++) { /* Search PHY table */
5138 if (id != phy_info[j].id) continue; /* ID match? */
5139 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5140 if (k < DE4X5_MAX_PHY) {
5141 memcpy((char *)&lp->phy[k],
5142 (char *)&phy_info[j], sizeof(struct phy_table));
5143 lp->phy[k].addr = i;
5144 lp->mii_cnt++;
5145 lp->active++;
5146 } else {
5147 goto purgatory; /* Stop the search */
5148 }
5149 break;
5150 }
5151 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5152 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5153 lp->phy[k].addr = i;
5154 lp->phy[k].id = id;
5155 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5156 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5157 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5158 lp->mii_cnt++;
5159 lp->active++;
5160 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5161 j = de4x5_debug;
5162 de4x5_debug |= DEBUG_MII;
5163 de4x5_dbg_mii(dev, k);
5164 de4x5_debug = j;
5165 printk("\n");
5166 }
5167 }
5168 purgatory:
5169 lp->active = 0;
5170 if (lp->phy[0].id) { /* Reset the PHY devices */
5171 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5172 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5173 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5174
5175 de4x5_dbg_mii(dev, k);
5176 }
5177 }
5178 if (!lp->mii_cnt) lp->useMII = FALSE;
5179
5180 return lp->mii_cnt;
5181 }
5182
5183 static char *
5184 build_setup_frame(struct net_device *dev, int mode)
5185 {
5186 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5187 int i;
5188 char *pa = lp->setup_frame;
5189
5190 /* Initialise the setup frame */
5191 if (mode == ALL) {
5192 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5193 }
5194
5195 if (lp->setup_f == HASH_PERF) {
5196 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5197 *(pa + i) = dev->dev_addr[i]; /* Host address */
5198 if (i & 0x01) pa += 2;
5199 }
5200 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5201 } else {
5202 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5203 *(pa + (i&1)) = dev->dev_addr[i];
5204 if (i & 0x01) pa += 4;
5205 }
5206 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5207 *(pa + (i&1)) = (char) 0xff;
5208 if (i & 0x01) pa += 4;
5209 }
5210 }
5211
5212 return pa; /* Points to the next entry */
5213 }
5214
5215 static void
5216 enable_ast(struct net_device *dev, u32 time_out)
5217 {
5218 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5219
5220 return;
5221 }
5222
5223 static void
5224 disable_ast(struct net_device *dev)
5225 {
5226 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5227
5228 del_timer(&lp->timer);
5229
5230 return;
5231 }
5232
5233 static long
5234 de4x5_switch_mac_port(struct net_device *dev)
5235 {
5236 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5237 u_long iobase = dev->base_addr;
5238 s32 omr;
5239
5240 STOP_DE4X5;
5241
5242 /* Assert the OMR_PS bit in CSR6 */
5243 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5244 OMR_FDX));
5245 omr |= lp->infoblock_csr6;
5246 if (omr & OMR_PS) omr |= OMR_HBD;
5247 outl(omr, DE4X5_OMR);
5248
5249 /* Soft Reset */
5250 RESET_DE4X5;
5251
5252 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5253 if (lp->chipset == DC21140) {
5254 gep_wr(lp->cache.gepc, dev);
5255 gep_wr(lp->cache.gep, dev);
5256 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5257 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5258 }
5259
5260 /* Restore CSR6 */
5261 outl(omr, DE4X5_OMR);
5262
5263 /* Reset CSR8 */
5264 inl(DE4X5_MFC);
5265
5266 return omr;
5267 }
5268
5269 static void
5270 gep_wr(s32 data, struct net_device *dev)
5271 {
5272 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5273 u_long iobase = dev->base_addr;
5274
5275 if (lp->chipset == DC21140) {
5276 outl(data, DE4X5_GEP);
5277 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5278 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5279 }
5280
5281 return;
5282 }
5283
5284 static int
5285 gep_rd(struct net_device *dev)
5286 {
5287 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5288 u_long iobase = dev->base_addr;
5289
5290 if (lp->chipset == DC21140) {
5291 return inl(DE4X5_GEP);
5292 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5293 return (inl(DE4X5_SIGR) & 0x000fffff);
5294 }
5295
5296 return 0;
5297 }
5298
5299 static void
5300 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5301 {
5302 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5303 int dt;
5304
5305 /* First, cancel any pending timer events */
5306 del_timer(&lp->timer);
5307
5308 /* Convert msec to ticks */
5309 dt = (msec * HZ) / 1000;
5310 if (dt==0) dt=1;
5311
5312 /* Set up timer */
5313 lp->timer.expires = jiffies + dt;
5314 lp->timer.function = fn;
5315 lp->timer.data = data;
5316 add_timer(&lp->timer);
5317
5318 return;
5319 }
5320
5321 static void
5322 yawn(struct net_device *dev, int state)
5323 {
5324 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5325 u_long iobase = dev->base_addr;
5326
5327 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5328
5329 if(lp->bus == EISA) {
5330 switch(state) {
5331 case WAKEUP:
5332 outb(WAKEUP, PCI_CFPM);
5333 de4x5_ms_delay(10);
5334 break;
5335
5336 case SNOOZE:
5337 outb(SNOOZE, PCI_CFPM);
5338 break;
5339
5340 case SLEEP:
5341 outl(0, DE4X5_SICR);
5342 outb(SLEEP, PCI_CFPM);
5343 break;
5344 }
5345 } else {
5346 switch(state) {
5347 case WAKEUP:
5348 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5349 PCI_CFDA_PSM, WAKEUP);
5350 de4x5_ms_delay(10);
5351 break;
5352
5353 case SNOOZE:
5354 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5355 PCI_CFDA_PSM, SNOOZE);
5356 break;
5357
5358 case SLEEP:
5359 outl(0, DE4X5_SICR);
5360 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5361 PCI_CFDA_PSM, SLEEP);
5362 break;
5363 }
5364 }
5365
5366 return;
5367 }
5368
5369 static void
5370 de4x5_parse_params(struct net_device *dev)
5371 {
5372 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5373 char *p, *q, t;
5374
5375 lp->params.fdx = 0;
5376 lp->params.autosense = AUTO;
5377
5378 if (args == NULL) return;
5379
5380 if ((p = strstr(args, dev->name))) {
5381 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5382 t = *q;
5383 *q = '\0';
5384
5385 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5386 if (strstr(p, "force_eisa") || strstr(p, "FORCE_EISA")) forceEISA = 1;
5387 #endif
5388 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5389
5390 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5391 if (strstr(p, "TP")) {
5392 lp->params.autosense = TP;
5393 } else if (strstr(p, "TP_NW")) {
5394 lp->params.autosense = TP_NW;
5395 } else if (strstr(p, "BNC")) {
5396 lp->params.autosense = BNC;
5397 } else if (strstr(p, "AUI")) {
5398 lp->params.autosense = AUI;
5399 } else if (strstr(p, "BNC_AUI")) {
5400 lp->params.autosense = BNC;
5401 } else if (strstr(p, "10Mb")) {
5402 lp->params.autosense = _10Mb;
5403 } else if (strstr(p, "100Mb")) {
5404 lp->params.autosense = _100Mb;
5405 } else if (strstr(p, "AUTO")) {
5406 lp->params.autosense = AUTO;
5407 }
5408 }
5409 *q = t;
5410 }
5411
5412 return;
5413 }
5414
5415 static void
5416 de4x5_dbg_open(struct net_device *dev)
5417 {
5418 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5419 int i;
5420
5421 if (de4x5_debug & DEBUG_OPEN) {
5422 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5423 printk("\tphysical address: ");
5424 for (i=0;i<6;i++) {
5425 printk("%2.2x:",(short)dev->dev_addr[i]);
5426 }
5427 printk("\n");
5428 printk("Descriptor head addresses:\n");
5429 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5430 printk("Descriptor addresses:\nRX: ");
5431 for (i=0;i<lp->rxRingSize-1;i++){
5432 if (i < 3) {
5433 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5434 }
5435 }
5436 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5437 printk("TX: ");
5438 for (i=0;i<lp->txRingSize-1;i++){
5439 if (i < 3) {
5440 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5441 }
5442 }
5443 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5444 printk("Descriptor buffers:\nRX: ");
5445 for (i=0;i<lp->rxRingSize-1;i++){
5446 if (i < 3) {
5447 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5448 }
5449 }
5450 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5451 printk("TX: ");
5452 for (i=0;i<lp->txRingSize-1;i++){
5453 if (i < 3) {
5454 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5455 }
5456 }
5457 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5458 printk("Ring size: \nRX: %d\nTX: %d\n",
5459 (short)lp->rxRingSize,
5460 (short)lp->txRingSize);
5461 }
5462
5463 return;
5464 }
5465
5466 static void
5467 de4x5_dbg_mii(struct net_device *dev, int k)
5468 {
5469 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5470 u_long iobase = dev->base_addr;
5471
5472 if (de4x5_debug & DEBUG_MII) {
5473 printk("\nMII device address: %d\n", lp->phy[k].addr);
5474 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5475 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5476 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5477 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5478 if (lp->phy[k].id != BROADCOM_T4) {
5479 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5480 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5481 }
5482 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5483 if (lp->phy[k].id != BROADCOM_T4) {
5484 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5485 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5486 } else {
5487 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5488 }
5489 }
5490
5491 return;
5492 }
5493
5494 static void
5495 de4x5_dbg_media(struct net_device *dev)
5496 {
5497 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5498
5499 if (lp->media != lp->c_media) {
5500 if (de4x5_debug & DEBUG_MEDIA) {
5501 printk("%s: media is %s%s\n", dev->name,
5502 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5503 (lp->media == TP ? "TP" :
5504 (lp->media == ANS ? "TP/Nway" :
5505 (lp->media == BNC ? "BNC" :
5506 (lp->media == AUI ? "AUI" :
5507 (lp->media == BNC_AUI ? "BNC/AUI" :
5508 (lp->media == EXT_SIA ? "EXT SIA" :
5509 (lp->media == _100Mb ? "100Mb/s" :
5510 (lp->media == _10Mb ? "10Mb/s" :
5511 "???"
5512 ))))))))), (lp->fdx?" full duplex.":"."));
5513 }
5514 lp->c_media = lp->media;
5515 }
5516
5517 return;
5518 }
5519
5520 static void
5521 de4x5_dbg_srom(struct de4x5_srom *p)
5522 {
5523 int i;
5524
5525 if (de4x5_debug & DEBUG_SROM) {
5526 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5527 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5528 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5529 printk("SROM version: %02x\n", (u_char)(p->version));
5530 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5531
5532 printk("Hardware Address: ");
5533 for (i=0;i<ETH_ALEN-1;i++) {
5534 printk("%02x:", (u_char)*(p->ieee_addr+i));
5535 }
5536 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5537 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5538 for (i=0; i<64; i++) {
5539 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5540 }
5541 }
5542
5543 return;
5544 }
5545
5546 static void
5547 de4x5_dbg_rx(struct sk_buff *skb, int len)
5548 {
5549 int i, j;
5550
5551 if (de4x5_debug & DEBUG_RX) {
5552 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5553 (u_char)skb->data[0],
5554 (u_char)skb->data[1],
5555 (u_char)skb->data[2],
5556 (u_char)skb->data[3],
5557 (u_char)skb->data[4],
5558 (u_char)skb->data[5],
5559 (u_char)skb->data[6],
5560 (u_char)skb->data[7],
5561 (u_char)skb->data[8],
5562 (u_char)skb->data[9],
5563 (u_char)skb->data[10],
5564 (u_char)skb->data[11],
5565 (u_char)skb->data[12],
5566 (u_char)skb->data[13],
5567 len);
5568 for (j=0; len>0;j+=16, len-=16) {
5569 printk(" %03x: ",j);
5570 for (i=0; i<16 && i<len; i++) {
5571 printk("%02x ",(u_char)skb->data[i+j]);
5572 }
5573 printk("\n");
5574 }
5575 }
5576
5577 return;
5578 }
5579
5580 /*
5581 ** Perform IOCTL call functions here. Some are privileged operations and the
5582 ** effective uid is checked in those cases. In the normal course of events
5583 ** this function is only used for my testing.
5584 */
5585 static int
5586 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5587 {
5588 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5589 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5590 u_long iobase = dev->base_addr;
5591 int i, j, status = 0;
5592 s32 omr;
5593 union {
5594 u8 addr[144];
5595 u16 sval[72];
5596 u32 lval[36];
5597 } tmp;
5598 u_long flags = 0;
5599
5600 switch(ioc->cmd) {
5601 case DE4X5_GET_HWADDR: /* Get the hardware address */
5602 ioc->len = ETH_ALEN;
5603 for (i=0; i<ETH_ALEN; i++) {
5604 tmp.addr[i] = dev->dev_addr[i];
5605 }
5606 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5607 break;
5608
5609 case DE4X5_SET_HWADDR: /* Set the hardware address */
5610 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5611 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5612 if (netif_queue_stopped(dev))
5613 return -EBUSY;
5614 netif_stop_queue(dev);
5615 for (i=0; i<ETH_ALEN; i++) {
5616 dev->dev_addr[i] = tmp.addr[i];
5617 }
5618 build_setup_frame(dev, PHYS_ADDR_ONLY);
5619 /* Set up the descriptor and give ownership to the card */
5620 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5621 SETUP_FRAME_LEN, (struct sk_buff *)1);
5622 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5623 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5624 netif_wake_queue(dev); /* Unlock the TX ring */
5625 break;
5626
5627 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5628 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5629 omr = inl(DE4X5_OMR);
5630 omr |= OMR_PR;
5631 outl(omr, DE4X5_OMR);
5632 dev->flags |= IFF_PROMISC;
5633 break;
5634
5635 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5636 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5637 omr = inl(DE4X5_OMR);
5638 omr &= ~OMR_PR;
5639 outb(omr, DE4X5_OMR);
5640 dev->flags &= ~IFF_PROMISC;
5641 break;
5642
5643 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5644 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5645 printk("%s: Boo!\n", dev->name);
5646 break;
5647
5648 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5649 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5650 omr = inl(DE4X5_OMR);
5651 omr |= OMR_PM;
5652 outl(omr, DE4X5_OMR);
5653 break;
5654
5655 case DE4X5_GET_STATS: /* Get the driver statistics */
5656 {
5657 struct pkt_stats statbuf;
5658 ioc->len = sizeof(statbuf);
5659 spin_lock_irqsave(&lp->lock, flags);
5660 memcpy(&statbuf, &lp->pktStats, ioc->len);
5661 spin_unlock_irqrestore(&lp->lock, flags);
5662 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5663 return -EFAULT;
5664 break;
5665 }
5666 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5667 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5668 spin_lock_irqsave(&lp->lock, flags);
5669 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5670 spin_unlock_irqrestore(&lp->lock, flags);
5671 break;
5672
5673 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5674 tmp.addr[0] = inl(DE4X5_OMR);
5675 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5676 break;
5677
5678 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5679 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5680 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5681 outl(tmp.addr[0], DE4X5_OMR);
5682 break;
5683
5684 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5685 j = 0;
5686 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5687 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5688 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5689 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5690 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5691 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5692 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5693 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5694 ioc->len = j;
5695 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5696 break;
5697
5698 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5699 /*
5700 case DE4X5_DUMP:
5701 j = 0;
5702 tmp.addr[j++] = dev->irq;
5703 for (i=0; i<ETH_ALEN; i++) {
5704 tmp.addr[j++] = dev->dev_addr[i];
5705 }
5706 tmp.addr[j++] = lp->rxRingSize;
5707 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5708 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5709
5710 for (i=0;i<lp->rxRingSize-1;i++){
5711 if (i < 3) {
5712 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5713 }
5714 }
5715 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5716 for (i=0;i<lp->txRingSize-1;i++){
5717 if (i < 3) {
5718 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5719 }
5720 }
5721 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5722
5723 for (i=0;i<lp->rxRingSize-1;i++){
5724 if (i < 3) {
5725 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5726 }
5727 }
5728 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5729 for (i=0;i<lp->txRingSize-1;i++){
5730 if (i < 3) {
5731 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5732 }
5733 }
5734 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5735
5736 for (i=0;i<lp->rxRingSize;i++){
5737 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5738 }
5739 for (i=0;i<lp->txRingSize;i++){
5740 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5741 }
5742
5743 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5744 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5745 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5746 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5747 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5748 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5749 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5750 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5751 tmp.lval[j>>2] = lp->chipset; j+=4;
5752 if (lp->chipset == DC21140) {
5753 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5754 } else {
5755 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5756 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5757 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5758 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5759 }
5760 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5761 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5762 tmp.lval[j>>2] = lp->active; j+=4;
5763 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5764 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5765 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5766 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5767 if (lp->phy[lp->active].id != BROADCOM_T4) {
5768 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5769 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5770 }
5771 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5772 if (lp->phy[lp->active].id != BROADCOM_T4) {
5773 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5774 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5775 } else {
5776 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5777 }
5778 }
5779
5780 tmp.addr[j++] = lp->txRingSize;
5781 tmp.addr[j++] = netif_queue_stopped(dev);
5782
5783 ioc->len = j;
5784 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5785 break;
5786
5787 */
5788 default:
5789 return -EOPNOTSUPP;
5790 }
5791
5792 return status;
5793 }
5794
5795 #ifdef MODULE
5796 /*
5797 ** Note now that module autoprobing is allowed under EISA and PCI. The
5798 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5799 ** to "do the right thing".
5800 */
5801 #define LP(a) ((struct de4x5_private *)(a))
5802 static struct net_device *mdev = NULL;
5803 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5804 MODULE_PARM(io, "i");
5805
5806 int
5807 init_module(void)
5808 {
5809 int i, num, status = -EIO;
5810 struct net_device *p;
5811
5812 num = count_adapters();
5813
5814 for (i=0; i<num; i++) {
5815 if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5816 return -ENOMEM;
5817
5818 if (!mdev) mdev = p;
5819
5820 if (register_netdev(p) != 0) {
5821 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5822 if (lp) {
5823 release_region(p->base_addr, (lp->bus == PCI ?
5824 DE4X5_PCI_TOTAL_SIZE :
5825 DE4X5_EISA_TOTAL_SIZE));
5826 if (lp->cache.priv) { /* Private area allocated? */
5827 kfree(lp->cache.priv); /* Free the private area */
5828 }
5829 if (lp->rx_ring) {
5830 pci_free_consistent(lp->pdev, lp->dma_size, lp->rx_ring,
5831 lp->dma_rings);
5832 }
5833 }
5834 kfree(p);
5835 } else {
5836 status = 0; /* At least one adapter will work */
5837 lastModule = p;
5838 }
5839 }
5840
5841 return status;
5842 }
5843
5844 void
5845 cleanup_module(void)
5846 {
5847 while (mdev != NULL) {
5848 mdev = unlink_modules(mdev);
5849 }
5850
5851 return;
5852 }
5853
5854 static struct net_device *
5855 unlink_modules(struct net_device *p)
5856 {
5857 struct net_device *next = NULL;
5858
5859 if (p->priv) { /* Private areas allocated? */
5860 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5861
5862 next = lp->next_module;
5863 if (lp->rx_ring) {
5864 pci_free_consistent(lp->pdev, lp->dma_size, lp->rx_ring,
5865 lp->dma_rings);
5866 }
5867 release_region(p->base_addr, (lp->bus == PCI ?
5868 DE4X5_PCI_TOTAL_SIZE :
5869 DE4X5_EISA_TOTAL_SIZE));
5870 kfree(lp->cache.priv); /* Free the private area */
5871 }
5872 unregister_netdev(p);
5873 kfree(p); /* Free the device structure */
5874
5875 return next;
5876 }
5877
5878 static int
5879 count_adapters(void)
5880 {
5881 int i, j=0;
5882 u_short vendor;
5883 u_int class = DE4X5_CLASS_CODE;
5884 u_int device;
5885
5886 #if !defined(__sparc_v9__) && !defined(__powerpc__) && !defined(__alpha__)
5887 char name[DE4X5_STRLEN];
5888 u_long iobase = 0x1000;
5889
5890 for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5891 if (EISA_signature(name, EISA_ID)) j++;
5892 }
5893 #endif
5894 if (!pcibios_present()) return j;
5895
5896 for (i=0; (pdev=pci_find_class(class, pdev))!= NULL; i++) {
5897 vendor = pdev->vendor;
5898 device = pdev->device << 8;
5899 if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5900 }
5901
5902 return j;
5903 }
5904
5905 /*
5906 ** If at end of eth device list and can't use current entry, malloc
5907 ** one up. If memory could not be allocated, print an error message.
5908 */
5909 static struct net_device * __init
5910 insert_device(struct net_device *dev, u_long iobase, int (*init)(struct net_device *))
5911 {
5912 struct net_device *new;
5913
5914 new = (struct net_device *)kmalloc(sizeof(struct net_device), GFP_KERNEL);
5915 if (new == NULL) {
5916 printk("de4x5.c: Device not initialised, insufficient memory\n");
5917 return NULL;
5918 } else {
5919 memset((char *)new, 0, sizeof(struct net_device));
5920 new->base_addr = iobase; /* assign the io address */
5921 new->init = init; /* initialisation routine */
5922 }
5923
5924 return new;
5925 }
5926
5927 #endif /* MODULE */
5928
5929 \f
5930 /*
5931 * Local variables:
5932 *
5933 * Delete -DMODVERSIONS below if you didn't define this in your kernel
5934 *
5935 * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -DMODVERSIONS -include /linux/include/linux/modversions.h -c de4x5.c"
5936 * End:
5937 */
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