Import 2.3.10pre5
[davej-history.git] / drivers / isdn / hisax / hfc_2bds0.h
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1 /* $Id: hfc_2bds0.h,v 1.2 1998/02/02 13:26:15 keil Exp $
3 * specific defines for CCD's HFC 2BDS0
5 * Author Karsten Keil (keil@temic-ech.spacenet.de)
8 * $Log: hfc_2bds0.h,v $
9 * Revision 1.2 1998/02/02 13:26:15 keil
10 * New
16 #define HFCD_CIRM 0x18
17 #define HFCD_CTMT 0x19
18 #define HFCD_INT_M1 0x1A
19 #define HFCD_INT_M2 0x1B
20 #define HFCD_INT_S1 0x1E
21 #define HFCD_STAT 0x1C
22 #define HFCD_STAT_DISB 0x1D
23 #define HFCD_STATES 0x30
24 #define HFCD_SCTRL 0x31
25 #define HFCD_TEST 0x32
26 #define HFCD_SQ 0x34
27 #define HFCD_CLKDEL 0x37
28 #define HFCD_MST_MODE 0x2E
29 #define HFCD_CONN 0x2F
31 #define HFCD_FIFO 0x80
32 #define HFCD_Z1 0x10
33 #define HFCD_Z2 0x18
34 #define HFCD_Z_LOW 0x00
35 #define HFCD_Z_HIGH 0x04
36 #define HFCD_F1_INC 0x12
37 #define HFCD_FIFO_IN 0x16
38 #define HFCD_F1 0x1a
39 #define HFCD_F2 0x1e
40 #define HFCD_F2_INC 0x22
41 #define HFCD_FIFO_OUT 0x26
42 #define HFCD_REC 0x01
43 #define HFCD_SEND 0x00
45 #define HFCB_FIFO 0x80
46 #define HFCB_Z1 0x00
47 #define HFCB_Z2 0x08
48 #define HFCB_Z_LOW 0x00
49 #define HFCB_Z_HIGH 0x04
50 #define HFCB_F1_INC 0x28
51 #define HFCB_FIFO_IN 0x2c
52 #define HFCB_F1 0x30
53 #define HFCB_F2 0x34
54 #define HFCB_F2_INC 0x38
55 #define HFCB_FIFO_OUT 0x3c
56 #define HFCB_REC 0x01
57 #define HFCB_SEND 0x00
58 #define HFCB_B1 0x00
59 #define HFCB_B2 0x02
60 #define HFCB_CHANNEL(ch) (ch ? HFCB_B2 : HFCB_B1)
62 #define HFCD_STATUS 0
63 #define HFCD_DATA 1
64 #define HFCD_DATA_NODEB 2
66 /* Status (READ) */
67 #define HFCD_BUSY 0x01
68 #define HFCD_BUSY_NBUSY 0x04
69 #define HFCD_TIMER_ELAP 0x10
70 #define HFCD_STATINT 0x20
71 #define HFCD_FRAMEINT 0x40
72 #define HFCD_ANYINT 0x80
74 /* CTMT (Write) */
75 #define HFCD_CLTIMER 0x80
76 #define HFCD_TIM25 0x00
77 #define HFCD_TIM50 0x08
78 #define HFCD_TIM400 0x10
79 #define HFCD_TIM800 0x18
80 #define HFCD_AUTO_TIMER 0x20
81 #define HFCD_TRANSB2 0x02
82 #define HFCD_TRANSB1 0x01
84 /* CIRM (Write) */
85 #define HFCD_RESET 0x08
86 #define HFCD_MEM8K 0x10
87 #define HFCD_INTA 0x01
88 #define HFCD_INTB 0x02
89 #define HFCD_INTC 0x03
90 #define HFCD_INTD 0x04
91 #define HFCD_INTE 0x05
92 #define HFCD_INTF 0x06
94 /* INT_M1;INT_S1 */
95 #define HFCD_INTS_B1TRANS 0x01
96 #define HFCD_INTS_B2TRANS 0x02
97 #define HFCD_INTS_DTRANS 0x04
98 #define HFCD_INTS_B1REC 0x08
99 #define HFCD_INTS_B2REC 0x10
100 #define HFCD_INTS_DREC 0x20
101 #define HFCD_INTS_L1STATE 0x40
102 #define HFCD_INTS_TIMER 0x80
104 /* INT_M2 */
105 #define HFCD_IRQ_ENABLE 0x08
107 /* STATES */
108 #define HFCD_LOAD_STATE 0x10
109 #define HFCD_ACTIVATE 0x20
110 #define HFCD_DO_ACTION 0x40
112 /* HFCD_MST_MODE */
113 #define HFCD_MASTER 0x01
115 /* HFCD_SCTRL */
116 #define SCTRL_B1_ENA 0x01
117 #define SCTRL_B2_ENA 0x02
118 #define SCTRL_LOW_PRIO 0x08
119 #define SCTRL_SQ_ENA 0x10
120 #define SCTRL_TEST 0x20
121 #define SCTRL_NONE_CAP 0x40
122 #define SCTRL_PWR_DOWN 0x80
124 /* HFCD_TEST */
125 #define HFCD_AUTO_AWAKE 0x01
127 extern void main_irq_2bds0(struct BCState *bcs);
128 extern void init2bds0(struct IsdnCardState *cs);
129 extern void release2bds0(struct IsdnCardState *cs);
130 extern void hfc2bds0_interrupt(struct IsdnCardState *cs, u_char val);
131 extern void set_cs_func(struct IsdnCardState *cs);