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Import 2.3.99pre2-1
[davej-history.git] / drivers / net / sunhme.c
blobd4f6e5b191c0ec6c483db77ec58ba855e2d14d61
1 /* $Id: sunhme.c,v 1.94 2000/03/15 06:47:04 davem Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 *
6 * Copyright (C) 1996, 1998, 1999 David S. Miller (davem@redhat.com)
7 */
8
9 static char *version =
10 "sunhme.c:v1.99 12/Sep/99 David S. Miller (davem@redhat.com)\n";
11
12 #include <linux/module.h>
13
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/types.h>
18 #include <linux/fcntl.h>
19 #include <linux/interrupt.h>
20 #include <linux/ptrace.h>
21 #include <linux/ioport.h>
22 #include <linux/in.h>
23 #include <linux/malloc.h>
24 #include <linux/string.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <asm/system.h>
28 #include <asm/bitops.h>
29 #include <asm/io.h>
30 #include <asm/dma.h>
31 #include <linux/errno.h>
32 #include <asm/byteorder.h>
33
34 #include <asm/idprom.h>
35 #include <asm/sbus.h>
36 #include <asm/openprom.h>
37 #include <asm/oplib.h>
38 #include <asm/auxio.h>
39 #include <asm/pgtable.h>
40 #include <asm/irq.h>
41 #ifndef __sparc_v9__
42 #include <asm/io-unit.h>
43 #endif
44 #include <asm/ethtool.h>
45 #include <asm/uaccess.h>
46
47 #include <linux/netdevice.h>
48 #include <linux/etherdevice.h>
49 #include <linux/skbuff.h>
50
51 #ifdef CONFIG_PCI
52 #include <linux/pci.h>
53 #include <asm/pbm.h>
54 #endif
55
56 #include "sunhme.h"
57
58 #ifdef MODULE
59 static struct happy_meal *root_happy_dev = NULL;
60 #endif
61
62 static struct quattro *qfe_sbus_list = NULL;
63 #ifdef CONFIG_PCI
64 static struct quattro *qfe_pci_list = NULL;
65 #endif
66
67 #undef HMEDEBUG
68 #undef SXDEBUG
69 #undef RXDEBUG
70 #undef TXDEBUG
71 #undef TXLOGGING
72
73 #ifdef TXLOGGING
74 struct hme_tx_logent {
75 unsigned int tstamp;
76 int tx_new, tx_old;
77 unsigned int action;
78 #define TXLOG_ACTION_IRQ 0x01
79 #define TXLOG_ACTION_TXMIT 0x02
80 #define TXLOG_ACTION_TBUSY 0x04
81 #define TXLOG_ACTION_NBUFS 0x08
82 unsigned int status;
83 };
84 #define TX_LOG_LEN 128
85 static struct hme_tx_logent tx_log[TX_LOG_LEN];
86 static int txlog_cur_entry = 0;
87 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
88 {
89 struct hme_tx_logent *tlp;
90 unsigned long flags;
91
92 save_and_cli(flags);
93 tlp = &tx_log[txlog_cur_entry];
94 tlp->tstamp = (unsigned int)jiffies;
95 tlp->tx_new = hp->tx_new;
96 tlp->tx_old = hp->tx_old;
97 tlp->action = a;
98 tlp->status = s;
99 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
100 restore_flags(flags);
101 }
102 static __inline__ void tx_dump_log(void)
103 {
104 int i, this;
105
106 this = txlog_cur_entry;
107 for (i = 0; i < TX_LOG_LEN; i++) {
108 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
109 tx_log[this].tstamp,
110 tx_log[this].tx_new, tx_log[this].tx_old,
111 tx_log[this].action, tx_log[this].status);
112 this = (this + 1) & (TX_LOG_LEN - 1);
113 }
114 }
115 static __inline__ void tx_dump_ring(struct happy_meal *hp)
116 {
117 struct hmeal_init_block *hb = hp->happy_block;
118 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
119 int i;
120
121 for (i = 0; i < TX_RING_SIZE; i+=4) {
122 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
123 i, i + 4,
124 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
125 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
126 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
127 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
128 }
129 }
130 #else
131 #define tx_add_log(hp, a, s) do { } while(0)
132 #define tx_dump_log() do { } while(0)
133 #define tx_dump_ring(hp) do { } while(0)
134 #endif
135
136 #ifdef HMEDEBUG
137 #define HMD(x) printk x
138 #else
139 #define HMD(x)
140 #endif
141
142 /* #define AUTO_SWITCH_DEBUG */
143
144 #ifdef AUTO_SWITCH_DEBUG
145 #define ASD(x) printk x
146 #else
147 #define ASD(x)
148 #endif
149
150 #define DEFAULT_IPG0 16 /* For lance-mode only */
151 #define DEFAULT_IPG1 8 /* For all modes */
152 #define DEFAULT_IPG2 4 /* For all modes */
153 #define DEFAULT_JAMSIZE 4 /* Toe jam */
154
155 /* NOTE: In the descriptor writes one _must_ write the address
156 * member _first_. The card must not be allowed to see
157 * the updated descriptor flags until the address is
158 * correct. I've added a write memory barrier between
159 * the two stores so that I can sleep well at night... -DaveM
160 */
161
162 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
163 static void sbus_hme_write32(unsigned long reg, u32 val)
164 {
165 sbus_writel(val, reg);
166 }
167
168 static u32 sbus_hme_read32(unsigned long reg)
169 {
170 return sbus_readl(reg);
171 }
172
173 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
174 {
175 rxd->rx_addr = addr;
176 wmb();
177 rxd->rx_flags = flags;
178 }
179
180 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
181 {
182 txd->tx_addr = addr;
183 wmb();
184 txd->tx_flags = flags;
185 }
186
187 static u32 sbus_hme_read_desc32(u32 *p)
188 {
189 return *p;
190 }
191
192 static void pci_hme_write32(unsigned long reg, u32 val)
193 {
194 writel(val, reg);
195 }
196
197 static u32 pci_hme_read32(unsigned long reg)
198 {
199 return readl(reg);
200 }
201
202 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
203 {
204 rxd->rx_addr = cpu_to_le32(addr);
205 wmb();
206 rxd->rx_flags = cpu_to_le32(flags);
207 }
208
209 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
210 {
211 txd->tx_addr = cpu_to_le32(addr);
212 wmb();
213 txd->tx_flags = cpu_to_le32(flags);
214 }
215
216 static u32 pci_hme_read_desc32(u32 *p)
217 {
218 return cpu_to_le32p(p);
219 }
220
221 #define hme_write32(__hp, __reg, __val) \
222 ((__hp)->write32((__reg), (__val)))
223 #define hme_read32(__hp, __reg) \
224 ((__hp)->read32(__reg))
225 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
226 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
227 #define hme_write_txd(__hp, __txd, __flags, __addr) \
228 ((__hp)->write_txd((__txd), (__flags), (__addr)))
229 #define hme_read_desc32(__hp, __p) \
230 ((__hp)->read_desc32(__p))
231 #define hme_dma_map(__hp, __ptr, __size, __dir) \
232 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
233 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
234 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
235 #define hme_dma_sync(__hp, __addr, __size, __dir) \
236 ((__hp)->dma_sync((__hp)->happy_dev, (__addr), (__size), (__dir)))
237 #else
238 #ifdef CONFIG_SBUS
239 /* SBUS only compilation */
240 #define hme_write32(__hp, __reg, __val) \
241 sbus_writel((__val), (__reg))
242 #define hme_read32(__hp, __reg) \
243 sbus_readl(__reg)
244 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
245 do { (__rxd)->rx_addr = (__addr); \
246 wmb(); \
247 (__rxd)->rx_flags = (__flags); \
248 } while(0)
249 #define hme_write_txd(__hp, __txd, __flags, __addr) \
250 do { (__txd)->tx_addr = (__addr); \
251 wmb(); \
252 (__txd)->tx_flags = (__flags); \
253 } while(0)
254 #define hme_read_desc32(__hp, __p) (*(__p))
255 #define hme_dma_map(__hp, __ptr, __size, __dir) \
256 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
257 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
258 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
259 #define hme_dma_sync(__hp, __addr, __size, __dir) \
260 sbus_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
261 #else
262 /* PCI only compilation */
263 #define hme_write32(__hp, __reg, __val) \
264 writel((__val), (__reg))
265 #define hme_read32(__hp, __reg) \
266 readl(__reg)
267 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
268 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
269 wmb(); \
270 (__rxd)->rx_flags = cpu_to_le32(__flags); \
271 } while(0)
272 #define hme_write_txd(__hp, __txd, __flags, __addr) \
273 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
274 wmb(); \
275 (__txd)->tx_flags = cpu_to_le32(__flags); \
276 } while(0)
277 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
278 #define hme_dma_map(__hp, __ptr, __size, __dir) \
279 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
280 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
281 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
282 #define hme_dma_sync(__hp, __addr, __size, __dir) \
283 pci_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
284 #endif
285 #endif
286
287 #define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
288 #define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
289 #define DMA_TODEVICE SBUS_DMA_TODEVICE
290
291 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
292 static void BB_PUT_BIT(struct happy_meal *hp, unsigned long tregs, int bit)
293 {
294 hme_write32(hp, tregs + TCVR_BBDATA, bit);
295 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
296 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
297 }
298
299 #if 0
300 static u32 BB_GET_BIT(struct happy_meal *hp, unsigned long tregs, int internal)
301 {
302 u32 ret;
303
304 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
305 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
306 ret = hme_read32(hp, tregs + TCVR_CFG);
307 if (internal)
308 ret &= TCV_CFG_MDIO0;
309 else
310 ret &= TCV_CFG_MDIO1;
311
312 return ret;
313 }
314 #endif
315
316 static u32 BB_GET_BIT2(struct happy_meal *hp, unsigned long tregs, int internal)
317 {
318 u32 retval;
319
320 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
321 udelay(1);
322 retval = hme_read32(hp, tregs + TCVR_CFG);
323 if (internal)
324 retval &= TCV_CFG_MDIO0;
325 else
326 retval &= TCV_CFG_MDIO1;
327 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
328
329 return retval;
330 }
331
332 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
333
334 static int happy_meal_bb_read(struct happy_meal *hp,
335 unsigned long tregs, int reg)
336 {
337 u32 tmp;
338 int retval = 0;
339 int i;
340
341 ASD(("happy_meal_bb_read: reg=%d ", reg));
342
343 /* Enable the MIF BitBang outputs. */
344 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
345
346 /* Force BitBang into the idle state. */
347 for (i = 0; i < 32; i++)
348 BB_PUT_BIT(hp, tregs, 1);
349
350 /* Give it the read sequence. */
351 BB_PUT_BIT(hp, tregs, 0);
352 BB_PUT_BIT(hp, tregs, 1);
353 BB_PUT_BIT(hp, tregs, 1);
354 BB_PUT_BIT(hp, tregs, 0);
355
356 /* Give it the PHY address. */
357 tmp = hp->paddr & 0xff;
358 for (i = 4; i >= 0; i--)
359 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
360
361 /* Tell it what register we want to read. */
362 tmp = (reg & 0xff);
363 for (i = 4; i >= 0; i--)
364 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
365
366 /* Close down the MIF BitBang outputs. */
367 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
368
369 /* Now read in the value. */
370 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
371 for (i = 15; i >= 0; i--)
372 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
373 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
374 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
375 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
376 ASD(("value=%x\n", retval));
377 return retval;
378 }
379
380 static void happy_meal_bb_write(struct happy_meal *hp,
381 unsigned long tregs, int reg,
382 unsigned short value)
383 {
384 u32 tmp;
385 int i;
386
387 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
388
389 /* Enable the MIF BitBang outputs. */
390 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
391
392 /* Force BitBang into the idle state. */
393 for (i = 0; i < 32; i++)
394 BB_PUT_BIT(hp, tregs, 1);
395
396 /* Give it write sequence. */
397 BB_PUT_BIT(hp, tregs, 0);
398 BB_PUT_BIT(hp, tregs, 1);
399 BB_PUT_BIT(hp, tregs, 0);
400 BB_PUT_BIT(hp, tregs, 1);
401
402 /* Give it the PHY address. */
403 tmp = (hp->paddr & 0xff);
404 for (i = 4; i >= 0; i--)
405 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
406
407 /* Tell it what register we will be writing. */
408 tmp = (reg & 0xff);
409 for (i = 4; i >= 0; i--)
410 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
411
412 /* Tell it to become ready for the bits. */
413 BB_PUT_BIT(hp, tregs, 1);
414 BB_PUT_BIT(hp, tregs, 0);
415
416 for (i = 15; i >= 0; i--)
417 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
418
419 /* Close down the MIF BitBang outputs. */
420 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
421 }
422
423 #define TCVR_READ_TRIES 16
424
425 static int happy_meal_tcvr_read(struct happy_meal *hp,
426 unsigned long tregs, int reg)
427 {
428 int tries = TCVR_READ_TRIES;
429 int retval;
430
431 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
432 if (hp->tcvr_type == none) {
433 ASD(("no transceiver, value=TCVR_FAILURE\n"));
434 return TCVR_FAILURE;
435 }
436
437 if (!(hp->happy_flags & HFLAG_FENABLE)) {
438 ASD(("doing bit bang\n"));
439 return happy_meal_bb_read(hp, tregs, reg);
440 }
441
442 hme_write32(hp, tregs + TCVR_FRAME,
443 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
444 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
445 udelay(20);
446 if (!tries) {
447 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
448 return TCVR_FAILURE;
449 }
450 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
451 ASD(("value=%04x\n", retval));
452 return retval;
453 }
454
455 #define TCVR_WRITE_TRIES 16
456
457 static void happy_meal_tcvr_write(struct happy_meal *hp,
458 unsigned long tregs, int reg,
459 unsigned short value)
460 {
461 int tries = TCVR_WRITE_TRIES;
462
463 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
464
465 /* Welcome to Sun Microsystems, can I take your order please? */
466 if (!hp->happy_flags & HFLAG_FENABLE)
467 return happy_meal_bb_write(hp, tregs, reg, value);
468
469 /* Would you like fries with that? */
470 hme_write32(hp, tregs + TCVR_FRAME,
471 (FRAME_WRITE | (hp->paddr << 23) |
472 ((reg & 0xff) << 18) | (value & 0xffff)));
473 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
474 udelay(20);
475
476 /* Anything else? */
477 if (!tries)
478 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
479
480 /* Fifty-two cents is your change, have a nice day. */
481 }
482
483 /* Auto negotiation. The scheme is very simple. We have a timer routine
484 * that keeps watching the auto negotiation process as it progresses.
485 * The DP83840 is first told to start doing it's thing, we set up the time
486 * and place the timer state machine in it's initial state.
487 *
488 * Here the timer peeks at the DP83840 status registers at each click to see
489 * if the auto negotiation has completed, we assume here that the DP83840 PHY
490 * will time out at some point and just tell us what (didn't) happen. For
491 * complete coverage we only allow so many of the ticks at this level to run,
492 * when this has expired we print a warning message and try another strategy.
493 * This "other" strategy is to force the interface into various speed/duplex
494 * configurations and we stop when we see a link-up condition before the
495 * maximum number of "peek" ticks have occurred.
496 *
497 * Once a valid link status has been detected we configure the BigMAC and
498 * the rest of the Happy Meal to speak the most efficient protocol we could
499 * get a clean link for. The priority for link configurations, highest first
500 * is:
501 * 100 Base-T Full Duplex
502 * 100 Base-T Half Duplex
503 * 10 Base-T Full Duplex
504 * 10 Base-T Half Duplex
505 *
506 * We start a new timer now, after a successful auto negotiation status has
507 * been detected. This timer just waits for the link-up bit to get set in
508 * the BMCR of the DP83840. When this occurs we print a kernel log message
509 * describing the link type in use and the fact that it is up.
510 *
511 * If a fatal error of some sort is signalled and detected in the interrupt
512 * service routine, and the chip is reset, or the link is ifconfig'd down
513 * and then back up, this entire process repeats itself all over again.
514 */
515 static int try_next_permutation(struct happy_meal *hp, unsigned long tregs)
516 {
517 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
518
519 /* Downgrade from full to half duplex. Only possible
520 * via ethtool.
521 */
522 if (hp->sw_bmcr & BMCR_FULLDPLX) {
523 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
524 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
525 return 0;
526 }
527
528 /* Downgrade from 100 to 10. */
529 if (hp->sw_bmcr & BMCR_SPEED100) {
530 hp->sw_bmcr &= ~(BMCR_SPEED100);
531 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
532 return 0;
533 }
534
535 /* We've tried everything. */
536 return -1;
537 }
538
539 static void display_link_mode(struct happy_meal *hp, unsigned long tregs)
540 {
541 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
542 if (hp->tcvr_type == external)
543 printk("external ");
544 else
545 printk("internal ");
546 printk("transceiver at ");
547 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, DP83840_LPA);
548 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
549 if (hp->sw_lpa & LPA_100FULL)
550 printk("100Mb/s, Full Duplex.\n");
551 else
552 printk("100Mb/s, Half Duplex.\n");
553 } else {
554 if (hp->sw_lpa & LPA_10FULL)
555 printk("10Mb/s, Full Duplex.\n");
556 else
557 printk("10Mb/s, Half Duplex.\n");
558 }
559 }
560
561 static void display_forced_link_mode(struct happy_meal *hp, unsigned long tregs)
562 {
563 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
564 if (hp->tcvr_type == external)
565 printk("external ");
566 else
567 printk("internal ");
568 printk("transceiver at ");
569 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
570 if (hp->sw_bmcr & BMCR_SPEED100)
571 printk("100Mb/s, ");
572 else
573 printk("10Mb/s, ");
574 if (hp->sw_bmcr & BMCR_FULLDPLX)
575 printk("Full Duplex.\n");
576 else
577 printk("Half Duplex.\n");
578 }
579
580 static int set_happy_link_modes(struct happy_meal *hp, unsigned long tregs)
581 {
582 int full;
583
584 /* All we care about is making sure the bigmac tx_cfg has a
585 * proper duplex setting.
586 */
587 if (hp->timer_state == arbwait) {
588 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, DP83840_LPA);
589 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
590 goto no_response;
591 if (hp->sw_lpa & LPA_100FULL)
592 full = 1;
593 else if (hp->sw_lpa & LPA_100HALF)
594 full = 0;
595 else if (hp->sw_lpa & LPA_10FULL)
596 full = 1;
597 else
598 full = 0;
599 } else {
600 /* Forcing a link mode. */
601 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
602 if (hp->sw_bmcr & BMCR_FULLDPLX)
603 full = 1;
604 else
605 full = 0;
606 }
607
608 /* Before changing other bits in the tx_cfg register, and in
609 * general any of other the TX config registers too, you
610 * must:
611 * 1) Clear Enable
612 * 2) Poll with reads until that bit reads back as zero
613 * 3) Make TX configuration changes
614 * 4) Set Enable once more
615 */
616 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
617 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
618 ~(BIGMAC_TXCFG_ENABLE));
619 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
620 barrier();
621 if (full) {
622 hp->happy_flags |= HFLAG_FULL;
623 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
624 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
625 BIGMAC_TXCFG_FULLDPLX);
626 } else {
627 hp->happy_flags &= ~(HFLAG_FULL);
628 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
629 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
630 ~(BIGMAC_TXCFG_FULLDPLX));
631 }
632 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
633 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
634 BIGMAC_TXCFG_ENABLE);
635 return 0;
636 no_response:
637 return 1;
638 }
639
640 static int happy_meal_init(struct happy_meal *hp, int from_irq);
641
642 static int is_lucent_phy(struct happy_meal *hp)
643 {
644 unsigned long tregs = hp->tcvregs;
645 unsigned short mr2, mr3;
646 int ret = 0;
647
648 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
649 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
650 if ((mr2 & 0xffff) == 0x0180 &&
651 ((mr3 & 0xffff) >> 10) == 0x1d) {
652 #if 0
653 printk("HMEDEBUG: Lucent PHY detected.\n");
654 #endif
655 ret = 1;
656 }
657
658 return ret;
659 }
660
661 static void happy_meal_timer(unsigned long data)
662 {
663 struct happy_meal *hp = (struct happy_meal *) data;
664 unsigned long tregs = hp->tcvregs;
665 int restart_timer = 0;
666
667 hp->timer_ticks++;
668 switch(hp->timer_state) {
669 case arbwait:
670 /* Only allow for 5 ticks, thats 10 seconds and much too
671 * long to wait for arbitration to complete.
672 */
673 if (hp->timer_ticks >= 10) {
674 /* Enter force mode. */
675 do_force_mode:
676 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
677 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
678 hp->dev->name);
679 hp->sw_bmcr = BMCR_SPEED100;
680 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
681
682 if (!is_lucent_phy(hp)) {
683 /* OK, seems we need do disable the transceiver for the first
684 * tick to make sure we get an accurate link state at the
685 * second tick.
686 */
687 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
688 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
689 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
690 }
691 hp->timer_state = ltrywait;
692 hp->timer_ticks = 0;
693 restart_timer = 1;
694 } else {
695 /* Anything interesting happen? */
696 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
697 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
698 int ret;
699
700 /* Just what we've been waiting for... */
701 ret = set_happy_link_modes(hp, tregs);
702 if (ret) {
703 /* Ooops, something bad happened, go to force
704 * mode.
705 *
706 * XXX Broken hubs which don't support 802.3u
707 * XXX auto-negotiation make this happen as well.
708 */
709 goto do_force_mode;
710 }
711
712 /* Success, at least so far, advance our state engine. */
713 hp->timer_state = lupwait;
714 restart_timer = 1;
715 } else {
716 restart_timer = 1;
717 }
718 }
719 break;
720
721 case lupwait:
722 /* Auto negotiation was successful and we are awaiting a
723 * link up status. I have decided to let this timer run
724 * forever until some sort of error is signalled, reporting
725 * a message to the user at 10 second intervals.
726 */
727 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
728 if (hp->sw_bmsr & BMSR_LSTATUS) {
729 /* Wheee, it's up, display the link mode in use and put
730 * the timer to sleep.
731 */
732 display_link_mode(hp, tregs);
733 hp->timer_state = asleep;
734 restart_timer = 0;
735 } else {
736 if (hp->timer_ticks >= 10) {
737 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
738 "not completely up.\n", hp->dev->name);
739 hp->timer_ticks = 0;
740 restart_timer = 1;
741 } else {
742 restart_timer = 1;
743 }
744 }
745 break;
746
747 case ltrywait:
748 /* Making the timeout here too long can make it take
749 * annoyingly long to attempt all of the link mode
750 * permutations, but then again this is essentially
751 * error recovery code for the most part.
752 */
753 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
754 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
755 if (hp->timer_ticks == 1) {
756 if (!is_lucent_phy(hp)) {
757 /* Re-enable transceiver, we'll re-enable the transceiver next
758 * tick, then check link state on the following tick.
759 */
760 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
761 happy_meal_tcvr_write(hp, tregs,
762 DP83840_CSCONFIG, hp->sw_csconfig);
763 }
764 restart_timer = 1;
765 break;
766 }
767 if (hp->timer_ticks == 2) {
768 if (!is_lucent_phy(hp)) {
769 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
770 happy_meal_tcvr_write(hp, tregs,
771 DP83840_CSCONFIG, hp->sw_csconfig);
772 }
773 restart_timer = 1;
774 break;
775 }
776 if (hp->sw_bmsr & BMSR_LSTATUS) {
777 /* Force mode selection success. */
778 display_forced_link_mode(hp, tregs);
779 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
780 hp->timer_state = asleep;
781 restart_timer = 0;
782 } else {
783 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
784 int ret;
785
786 ret = try_next_permutation(hp, tregs);
787 if (ret == -1) {
788 /* Aieee, tried them all, reset the
789 * chip and try all over again.
790 */
791
792 /* Let the user know... */
793 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
794 hp->dev->name);
795
796 ret = happy_meal_init(hp, 0);
797 if (ret) {
798 /* ho hum... */
799 printk(KERN_ERR "%s: Error, cannot re-init the "
800 "Happy Meal.\n", hp->dev->name);
801 }
802 return;
803 }
804 if (!is_lucent_phy(hp)) {
805 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
806 DP83840_CSCONFIG);
807 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
808 happy_meal_tcvr_write(hp, tregs,
809 DP83840_CSCONFIG, hp->sw_csconfig);
810 }
811 hp->timer_ticks = 0;
812 restart_timer = 1;
813 } else {
814 restart_timer = 1;
815 }
816 }
817 break;
818
819 case asleep:
820 default:
821 /* Can't happens.... */
822 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
823 hp->dev->name);
824 restart_timer = 0;
825 hp->timer_ticks = 0;
826 hp->timer_state = asleep; /* foo on you */
827 break;
828 };
829
830 if (restart_timer) {
831 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
832 add_timer(&hp->happy_timer);
833 }
834 }
835
836 #define TX_RESET_TRIES 32
837 #define RX_RESET_TRIES 32
838
839 static void happy_meal_tx_reset(struct happy_meal *hp, unsigned long bregs)
840 {
841 int tries = TX_RESET_TRIES;
842
843 HMD(("happy_meal_tx_reset: reset, "));
844
845 /* Would you like to try our SMCC Delux? */
846 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
847 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
848 udelay(20);
849
850 /* Lettuce, tomato, buggy hardware (no extra charge)? */
851 if (!tries)
852 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
853
854 /* Take care. */
855 HMD(("done\n"));
856 }
857
858 static void happy_meal_rx_reset(struct happy_meal *hp, unsigned long bregs)
859 {
860 int tries = RX_RESET_TRIES;
861
862 HMD(("happy_meal_rx_reset: reset, "));
863
864 /* We have a special on GNU/Viking hardware bugs today. */
865 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
866 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
867 udelay(20);
868
869 /* Will that be all? */
870 if (!tries)
871 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
872
873 /* Don't forget your vik_1137125_wa. Have a nice day. */
874 HMD(("done\n"));
875 }
876
877 #define STOP_TRIES 16
878
879 static void happy_meal_stop(struct happy_meal *hp, unsigned long gregs)
880 {
881 int tries = STOP_TRIES;
882
883 HMD(("happy_meal_stop: reset, "));
884
885 /* We're consolidating our STB products, it's your lucky day. */
886 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
887 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
888 udelay(20);
889
890 /* Come back next week when we are "Sun Microelectronics". */
891 if (!tries)
892 printk(KERN_ERR "happy meal: Fry guys.");
893
894 /* Remember: "Different name, same old buggy as shit hardware." */
895 HMD(("done\n"));
896 }
897
898 static void happy_meal_get_counters(struct happy_meal *hp, unsigned long bregs)
899 {
900 struct net_device_stats *stats = &hp->net_stats;
901
902 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
903 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
904
905 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
906 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
907
908 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
909 hme_write32(hp, bregs + BMAC_GLECTR, 0);
910
911 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
912
913 stats->collisions +=
914 (hme_read32(hp, bregs + BMAC_EXCTR) +
915 hme_read32(hp, bregs + BMAC_LTCTR));
916 hme_write32(hp, bregs + BMAC_EXCTR, 0);
917 hme_write32(hp, bregs + BMAC_LTCTR, 0);
918 }
919
920 #if 0
921 static void happy_meal_poll_start(struct happy_meal *hp, unsigned long tregs)
922 {
923 u32 tmp;
924 int speed;
925
926 ASD(("happy_meal_poll_start: "));
927 if (!(hp->happy_flags & HFLAG_POLLENABLE)) {
928 HMD(("polling disabled, return\n"));
929 return;
930 }
931
932 /* Start the MIF polling on the external transceiver. */
933 ASD(("polling on, "));
934 tmp = hme_read32(hp, tregs + TCVR_CFG);
935 tmp &= ~(TCV_CFG_PDADDR | TCV_CFG_PREGADDR);
936 tmp |= ((hp->paddr & 0x1f) << 10);
937 tmp |= (TCV_PADDR_ETX << 3);
938 tmp |= TCV_CFG_PENABLE;
939 hme_write32(hp, tregs + TCVR_CFG, tmp);
940
941 /* Let the bits set. */
942 udelay(200);
943
944 /* We are polling now. */
945 ASD(("now polling, "));
946 hp->happy_flags |= HFLAG_POLL;
947
948 /* Clear the poll flags, get the basic status as of now. */
949 hp->poll_flag = 0;
950 hp->poll_data = hme_read32(hp, tregs + TCVR_STATUS) >> 16;
951
952 if (hp->happy_flags & HFLAG_AUTO)
953 speed = hp->auto_speed;
954 else
955 speed = hp->forced_speed;
956
957 /* Listen only for the MIF interrupts we want to hear. */
958 ASD(("mif ints on, "));
959 if (speed == 100)
960 hme_write32(hp, tregs + TCVR_IMASK, 0xfffb);
961 else
962 hme_write32(hp, tregs + TCVR_IMASK, 0xfff9);
963 ASD(("done\n"));
964 }
965 #endif
966
967 static void happy_meal_poll_stop(struct happy_meal *hp, unsigned long tregs)
968 {
969 ASD(("happy_meal_poll_stop: "));
970
971 /* If polling disabled or not polling already, nothing to do. */
972 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
973 (HFLAG_POLLENABLE | HFLAG_POLL)) {
974 HMD(("not polling, return\n"));
975 return;
976 }
977
978 /* Shut up the MIF. */
979 ASD(("were polling, mif ints off, "));
980 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
981
982 /* Turn off polling. */
983 ASD(("polling off, "));
984 hme_write32(hp, tregs + TCVR_CFG,
985 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
986
987 /* We are no longer polling. */
988 hp->happy_flags &= ~(HFLAG_POLL);
989
990 /* Let the bits set. */
991 udelay(200);
992 ASD(("done\n"));
993 }
994
995 /* Only Sun can take such nice parts and fuck up the programming interface
996 * like this. Good job guys...
997 */
998 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
999 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1000
1001 static int happy_meal_tcvr_reset(struct happy_meal *hp, unsigned long tregs)
1002 {
1003 u32 tconfig;
1004 int result, tries = TCVR_RESET_TRIES;
1005
1006 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1007 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1008 if (hp->tcvr_type == external) {
1009 ASD(("external<"));
1010 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1011 hp->tcvr_type = internal;
1012 hp->paddr = TCV_PADDR_ITX;
1013 ASD(("ISOLATE,"));
1014 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR,
1015 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1016 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1017 if (result == TCVR_FAILURE) {
1018 ASD(("phyread_fail>\n"));
1019 return -1;
1020 }
1021 ASD(("phyread_ok,PSELECT>"));
1022 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1023 hp->tcvr_type = external;
1024 hp->paddr = TCV_PADDR_ETX;
1025 } else {
1026 if (tconfig & TCV_CFG_MDIO1) {
1027 ASD(("internal<PSELECT,"));
1028 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1029 ASD(("ISOLATE,"));
1030 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR,
1031 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1032 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1033 if (result == TCVR_FAILURE) {
1034 ASD(("phyread_fail>\n"));
1035 return -1;
1036 }
1037 ASD(("phyread_ok,~PSELECT>"));
1038 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1039 hp->tcvr_type = internal;
1040 hp->paddr = TCV_PADDR_ITX;
1041 }
1042 }
1043
1044 ASD(("BMCR_RESET "));
1045 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, BMCR_RESET);
1046
1047 while (--tries) {
1048 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1049 if (result == TCVR_FAILURE)
1050 return -1;
1051 hp->sw_bmcr = result;
1052 if (!(result & BMCR_RESET))
1053 break;
1054 udelay(20);
1055 }
1056 if (!tries) {
1057 ASD(("BMCR RESET FAILED!\n"));
1058 return -1;
1059 }
1060 ASD(("RESET_OK\n"));
1061
1062 /* Get fresh copies of the PHY registers. */
1063 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
1064 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID1);
1065 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID2);
1066 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, DP83840_ADVERTISE);
1067
1068 ASD(("UNISOLATE"));
1069 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1070 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1071
1072 tries = TCVR_UNISOLATE_TRIES;
1073 while (--tries) {
1074 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1075 if (result == TCVR_FAILURE)
1076 return -1;
1077 if (!(result & BMCR_ISOLATE))
1078 break;
1079 udelay(20);
1080 }
1081 if (!tries) {
1082 ASD((" FAILED!\n"));
1083 return -1;
1084 }
1085 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1086 if (!is_lucent_phy(hp)) {
1087 result = happy_meal_tcvr_read(hp, tregs,
1088 DP83840_CSCONFIG);
1089 happy_meal_tcvr_write(hp, tregs,
1090 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1091 }
1092 return 0;
1093 }
1094
1095 /* Figure out whether we have an internal or external transceiver. */
1096 static void happy_meal_transceiver_check(struct happy_meal *hp, unsigned long tregs)
1097 {
1098 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1099
1100 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1101 if (hp->happy_flags & HFLAG_POLL) {
1102 /* If we are polling, we must stop to get the transceiver type. */
1103 ASD(("<polling> "));
1104 if (hp->tcvr_type == internal) {
1105 if (tconfig & TCV_CFG_MDIO1) {
1106 ASD(("<internal> <poll stop> "));
1107 happy_meal_poll_stop(hp, tregs);
1108 hp->paddr = TCV_PADDR_ETX;
1109 hp->tcvr_type = external;
1110 ASD(("<external>\n"));
1111 tconfig &= ~(TCV_CFG_PENABLE);
1112 tconfig |= TCV_CFG_PSELECT;
1113 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1114 }
1115 } else {
1116 if (hp->tcvr_type == external) {
1117 ASD(("<external> "));
1118 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1119 ASD(("<poll stop> "));
1120 happy_meal_poll_stop(hp, tregs);
1121 hp->paddr = TCV_PADDR_ITX;
1122 hp->tcvr_type = internal;
1123 ASD(("<internal>\n"));
1124 hme_write32(hp, tregs + TCVR_CFG,
1125 hme_read32(hp, tregs + TCVR_CFG) &
1126 ~(TCV_CFG_PSELECT));
1127 }
1128 ASD(("\n"));
1129 } else {
1130 ASD(("<none>\n"));
1131 }
1132 }
1133 } else {
1134 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1135
1136 /* Else we can just work off of the MDIO bits. */
1137 ASD(("<not polling> "));
1138 if (reread & TCV_CFG_MDIO1) {
1139 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1140 hp->paddr = TCV_PADDR_ETX;
1141 hp->tcvr_type = external;
1142 ASD(("<external>\n"));
1143 } else {
1144 if (reread & TCV_CFG_MDIO0) {
1145 hme_write32(hp, tregs + TCVR_CFG,
1146 tconfig & ~(TCV_CFG_PSELECT));
1147 hp->paddr = TCV_PADDR_ITX;
1148 hp->tcvr_type = internal;
1149 ASD(("<internal>\n"));
1150 } else {
1151 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1152 hp->tcvr_type = none; /* Grrr... */
1153 ASD(("<none>\n"));
1154 }
1155 }
1156 }
1157 }
1158
1159 /* The receive ring buffers are a bit tricky to get right. Here goes...
1160 *
1161 * The buffers we dma into must be 64 byte aligned. So we use a special
1162 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1163 * we really need.
1164 *
1165 * We use skb_reserve() to align the data block we get in the skb. We
1166 * also program the etxregs->cfg register to use an offset of 2. This
1167 * imperical constant plus the ethernet header size will always leave
1168 * us with a nicely aligned ip header once we pass things up to the
1169 * protocol layers.
1170 *
1171 * The numbers work out to:
1172 *
1173 * Max ethernet frame size 1518
1174 * Ethernet header size 14
1175 * Happy Meal base offset 2
1176 *
1177 * Say a skb data area is at 0xf001b010, and its size alloced is
1178 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1179 *
1180 * First our alloc_skb() routine aligns the data base to a 64 byte
1181 * boundry. We now have 0xf001b040 as our skb data address. We
1182 * plug this into the receive descriptor address.
1183 *
1184 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1185 * So now the data we will end up looking at starts at 0xf001b042. When
1186 * the packet arrives, we will check out the size received and subtract
1187 * this from the skb->length. Then we just pass the packet up to the
1188 * protocols as is, and allocate a new skb to replace this slot we have
1189 * just received from.
1190 *
1191 * The ethernet layer will strip the ether header from the front of the
1192 * skb we just sent to it, this leaves us with the ip header sitting
1193 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1194 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1195 * bit checksum is obtained from the low bits of the receive descriptor
1196 * flags, thus:
1197 *
1198 * skb->csum = rxd->rx_flags & 0xffff;
1199 * skb->ip_summed = CHECKSUM_HW;
1200 *
1201 * before sending off the skb to the protocols, and we are good as gold.
1202 */
1203 static void happy_meal_clean_rings(struct happy_meal *hp)
1204 {
1205 int i;
1206
1207 for (i = 0; i < RX_RING_SIZE; i++) {
1208 if (hp->rx_skbs[i] != NULL) {
1209 struct sk_buff *skb = hp->rx_skbs[i];
1210 struct happy_meal_rxd *rxd;
1211 u32 dma_addr;
1212
1213 rxd = &hp->happy_block->happy_meal_rxd[i];
1214 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1215 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1216 dev_kfree_skb_any(skb);
1217 hp->rx_skbs[i] = NULL;
1218 }
1219 }
1220
1221 for (i = 0; i < TX_RING_SIZE; i++) {
1222 if (hp->tx_skbs[i] != NULL) {
1223 struct sk_buff *skb = hp->tx_skbs[i];
1224 struct happy_meal_txd *txd;
1225 u32 dma_addr;
1226
1227 txd = &hp->happy_block->happy_meal_txd[i];
1228 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1229 hme_dma_unmap(hp, dma_addr, skb->len, DMA_TODEVICE);
1230 dev_kfree_skb_any(skb);
1231 hp->tx_skbs[i] = NULL;
1232 }
1233 }
1234 }
1235
1236 static void happy_meal_init_rings(struct happy_meal *hp, int from_irq)
1237 {
1238 struct hmeal_init_block *hb = hp->happy_block;
1239 struct net_device *dev = hp->dev;
1240 int i, gfp_flags = GFP_KERNEL;
1241
1242 if (from_irq || in_interrupt())
1243 gfp_flags = GFP_ATOMIC;
1244
1245 HMD(("happy_meal_init_rings: counters to zero, "));
1246 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1247
1248 /* Free any skippy bufs left around in the rings. */
1249 HMD(("clean, "));
1250 happy_meal_clean_rings(hp);
1251
1252 /* Now get new skippy bufs for the receive ring. */
1253 HMD(("init rxring, "));
1254 for (i = 0; i < RX_RING_SIZE; i++) {
1255 struct sk_buff *skb;
1256
1257 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
1258 if (!skb) {
1259 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1260 continue;
1261 }
1262 hp->rx_skbs[i] = skb;
1263 skb->dev = dev;
1264
1265 /* Because we reserve afterwards. */
1266 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1267 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1268 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1269 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1270 skb_reserve(skb, RX_OFFSET);
1271 }
1272
1273 HMD(("init txring, "));
1274 for (i = 0; i < TX_RING_SIZE; i++)
1275 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1276
1277 HMD(("done\n"));
1278 }
1279
1280 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1281 unsigned long tregs,
1282 struct ethtool_cmd *ep)
1283 {
1284 int timeout;
1285
1286 /* Read all of the registers we are interested in now. */
1287 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
1288 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1289 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID1);
1290 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID2);
1291
1292 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1293
1294 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, DP83840_ADVERTISE);
1295 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1296 /* Advertise everything we can support. */
1297 if (hp->sw_bmsr & BMSR_10HALF)
1298 hp->sw_advertise |= (ADVERTISE_10HALF);
1299 else
1300 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1301
1302 if (hp->sw_bmsr & BMSR_10FULL)
1303 hp->sw_advertise |= (ADVERTISE_10FULL);
1304 else
1305 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1306 if (hp->sw_bmsr & BMSR_100HALF)
1307 hp->sw_advertise |= (ADVERTISE_100HALF);
1308 else
1309 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1310 if (hp->sw_bmsr & BMSR_100FULL)
1311 hp->sw_advertise |= (ADVERTISE_100FULL);
1312 else
1313 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1314 happy_meal_tcvr_write(hp, tregs, DP83840_ADVERTISE, hp->sw_advertise);
1315
1316 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1317 * XXX and this is because the DP83840 does not support it, changes
1318 * XXX would need to be made to the tx/rx logic in the driver as well
1319 * XXX so I completely skip checking for it in the BMSR for now.
1320 */
1321
1322 #ifdef AUTO_SWITCH_DEBUG
1323 ASD(("%s: Advertising [ ", hp->dev->name));
1324 if (hp->sw_advertise & ADVERTISE_10HALF)
1325 ASD(("10H "));
1326 if (hp->sw_advertise & ADVERTISE_10FULL)
1327 ASD(("10F "));
1328 if (hp->sw_advertise & ADVERTISE_100HALF)
1329 ASD(("100H "));
1330 if (hp->sw_advertise & ADVERTISE_100FULL)
1331 ASD(("100F "));
1332 #endif
1333
1334 /* Enable Auto-Negotiation, this is usually on already... */
1335 hp->sw_bmcr |= BMCR_ANENABLE;
1336 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1337
1338 /* Restart it to make sure it is going. */
1339 hp->sw_bmcr |= BMCR_ANRESTART;
1340 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1341
1342 /* BMCR_ANRESTART self clears when the process has begun. */
1343
1344 timeout = 64; /* More than enough. */
1345 while (--timeout) {
1346 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1347 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1348 break; /* got it. */
1349 udelay(10);
1350 }
1351 if (!timeout) {
1352 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1353 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1354 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1355 hp->dev->name);
1356 goto force_link;
1357 } else {
1358 hp->timer_state = arbwait;
1359 }
1360 } else {
1361 force_link:
1362 /* Force the link up, trying first a particular mode.
1363 * Either we are here at the request of ethtool or
1364 * because the Happy Meal would not start to autoneg.
1365 */
1366
1367 /* Disable auto-negotiation in BMCR, enable the duplex and
1368 * speed setting, init the timer state machine, and fire it off.
1369 */
1370 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1371 hp->sw_bmcr = BMCR_SPEED100;
1372 } else {
1373 if (ep->speed == SPEED_100)
1374 hp->sw_bmcr = BMCR_SPEED100;
1375 else
1376 hp->sw_bmcr = 0;
1377 if (ep->duplex == DUPLEX_FULL)
1378 hp->sw_bmcr |= BMCR_FULLDPLX;
1379 }
1380 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1381
1382 if (!is_lucent_phy(hp)) {
1383 /* OK, seems we need do disable the transceiver for the first
1384 * tick to make sure we get an accurate link state at the
1385 * second tick.
1386 */
1387 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1388 DP83840_CSCONFIG);
1389 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1390 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1391 hp->sw_csconfig);
1392 }
1393 hp->timer_state = ltrywait;
1394 }
1395
1396 hp->timer_ticks = 0;
1397 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1398 hp->happy_timer.data = (unsigned long) hp;
1399 hp->happy_timer.function = &happy_meal_timer;
1400 add_timer(&hp->happy_timer);
1401 }
1402
1403 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
1404 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
1405
1406 static int happy_meal_init(struct happy_meal *hp, int from_irq)
1407 {
1408 unsigned long gregs = hp->gregs;
1409 unsigned long etxregs = hp->etxregs;
1410 unsigned long erxregs = hp->erxregs;
1411 unsigned long bregs = hp->bigmacregs;
1412 unsigned long tregs = hp->tcvregs;
1413 u32 regtmp, rxcfg;
1414 unsigned char *e = &hp->dev->dev_addr[0];
1415
1416 /* If auto-negotiation timer is running, kill it. */
1417 del_timer(&hp->happy_timer);
1418
1419 HMD(("happy_meal_init: happy_flags[%08x] ",
1420 hp->happy_flags));
1421 if (!(hp->happy_flags & HFLAG_INIT)) {
1422 HMD(("set HFLAG_INIT, "));
1423 hp->happy_flags |= HFLAG_INIT;
1424 happy_meal_get_counters(hp, bregs);
1425 }
1426
1427 /* Stop polling. */
1428 HMD(("to happy_meal_poll_stop\n"));
1429 happy_meal_poll_stop(hp, tregs);
1430
1431 /* Stop transmitter and receiver. */
1432 HMD(("happy_meal_init: to happy_meal_stop\n"));
1433 happy_meal_stop(hp, gregs);
1434
1435 /* Alloc and reset the tx/rx descriptor chains. */
1436 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1437 happy_meal_init_rings(hp, from_irq);
1438
1439 /* Shut up the MIF. */
1440 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1441 hme_read32(hp, &tregs->int_mask)));
1442 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1443
1444 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1445 if (hp->happy_flags & HFLAG_FENABLE) {
1446 HMD(("use frame old[%08x], ",
1447 hme_read32(hp, &tregs->cfg)));
1448 hme_write32(hp, tregs + TCVR_CFG,
1449 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1450 } else {
1451 HMD(("use bitbang old[%08x], ",
1452 hme_read32(hp, &tregs->cfg)));
1453 hme_write32(hp, tregs + TCVR_CFG,
1454 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1455 }
1456
1457 /* Check the state of the transceiver. */
1458 HMD(("to happy_meal_transceiver_check\n"));
1459 happy_meal_transceiver_check(hp, tregs);
1460
1461 /* Put the Big Mac into a sane state. */
1462 HMD(("happy_meal_init: "));
1463 switch(hp->tcvr_type) {
1464 case none:
1465 /* Cannot operate if we don't know the transceiver type! */
1466 HMD(("AAIEEE no transceiver type, EAGAIN"));
1467 return -EAGAIN;
1468
1469 case internal:
1470 /* Using the MII buffers. */
1471 HMD(("internal, using MII, "));
1472 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1473 break;
1474
1475 case external:
1476 /* Not using the MII, disable it. */
1477 HMD(("external, disable MII, "));
1478 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1479 break;
1480 };
1481
1482 if (happy_meal_tcvr_reset(hp, tregs))
1483 return -EAGAIN;
1484
1485 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1486 HMD(("tx/rx reset, "));
1487 happy_meal_tx_reset(hp, bregs);
1488 happy_meal_rx_reset(hp, bregs);
1489
1490 /* Set jam size and inter-packet gaps to reasonable defaults. */
1491 HMD(("jsize/ipg1/ipg2, "));
1492 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1493 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1494 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1495
1496 /* Load up the MAC address and random seed. */
1497 HMD(("rseed/macaddr, "));
1498
1499 /* The docs recommend to use the 10LSB of our MAC here. */
1500 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1501
1502 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1503 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1504 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1505
1506 HMD(("htable, "));
1507 if ((hp->dev->flags & IFF_ALLMULTI) ||
1508 (hp->dev->mc_count > 64)) {
1509 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1510 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1511 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1512 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1513 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1514 u16 hash_table[4];
1515 struct dev_mc_list *dmi = hp->dev->mc_list;
1516 char *addrs;
1517 int i, j, bit, byte;
1518 u32 crc, poly = CRC_POLYNOMIAL_LE;
1519
1520 for (i = 0; i < 4; i++)
1521 hash_table[i] = 0;
1522
1523 for (i = 0; i < hp->dev->mc_count; i++) {
1524 addrs = dmi->dmi_addr;
1525 dmi = dmi->next;
1526
1527 if (!(*addrs & 1))
1528 continue;
1529
1530 crc = 0xffffffffU;
1531 for (byte = 0; byte < 6; byte++) {
1532 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1533 int test;
1534
1535 test = ((bit ^ crc) & 0x01);
1536 crc >>= 1;
1537 if (test)
1538 crc = crc ^ poly;
1539 }
1540 }
1541 crc >>= 26;
1542 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1543 }
1544 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1545 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1546 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1547 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1548 } else {
1549 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1550 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1551 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1552 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1553 }
1554
1555 /* Set the RX and TX ring ptrs. */
1556 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1557 (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1558 (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1559 hme_write32(hp, erxregs + ERX_RING,
1560 (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1561 hme_write32(hp, etxregs + ETX_RING,
1562 (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1563
1564 /* Set the supported burst sizes. */
1565 HMD(("happy_meal_init: old[%08x] bursts<",
1566 hme_read32(hp, gregs + GREG_CFG)));
1567
1568 if ((hp->happy_bursts & DMA_BURST64) &&
1569 ((hp->happy_flags & HFLAG_PCI) != 0
1570 #ifdef CONFIG_SBUS
1571 || sbus_can_burst64(hp->happy_dev)
1572 #endif
1573 || 0)) {
1574 u32 gcfg = GREG_CFG_BURST64;
1575
1576 /* I have no idea if I should set the extended
1577 * transfer mode bit for Cheerio, so for now I
1578 * do not. -DaveM
1579 */
1580 #ifdef CONFIG_SBUS
1581 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1582 sbus_can_dma_64bit(hp->happy_dev)) {
1583 sbus_set_sbus64(hp->happy_dev,
1584 hp->happy_bursts);
1585 gcfg |= GREG_CFG_64BIT;
1586 }
1587 #endif
1588
1589 HMD(("64>"));
1590 hme_write32(hp, gregs + GREG_CFG, gcfg);
1591 } else if (hp->happy_bursts & DMA_BURST32) {
1592 HMD(("32>"));
1593 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1594 } else if (hp->happy_bursts & DMA_BURST16) {
1595 HMD(("16>"));
1596 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1597 } else {
1598 HMD(("XXX>"));
1599 hme_write32(hp, gregs + GREG_CFG, 0);
1600 }
1601
1602 /* Turn off interrupts we do not want to hear. */
1603 HMD((", enable global interrupts, "));
1604 hme_write32(hp, gregs + GREG_IMASK,
1605 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1606 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1607
1608 /* Set the transmit ring buffer size. */
1609 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1610 hme_read32(hp, etxregs + ETX_RSIZE)));
1611 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1612
1613 /* Enable transmitter DVMA. */
1614 HMD(("tx dma enable old[%08x], ",
1615 hme_read32(hp, etxregs + ETX_CFG)));
1616 hme_write32(hp, etxregs + ETX_CFG,
1617 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1618
1619 /* This chip really rots, for the receiver sometimes when you
1620 * write to it's control registers not all the bits get there
1621 * properly. I cannot think of a sane way to provide complete
1622 * coverage for this hardware bug yet.
1623 */
1624 HMD(("erx regs bug old[%08x]\n",
1625 hme_read32(hp, erxregs + ERX_CFG)));
1626 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1627 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1628 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1629 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1630 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1631 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1632 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1633 /* XXX Should return failure here... */
1634 }
1635
1636 /* Enable Big Mac hash table filter. */
1637 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1638 hme_read32(hp, bregs + BMAC_RXCFG)));
1639 rxcfg = BIGMAC_RXCFG_HENABLE;
1640 if (hp->dev->flags & IFF_PROMISC)
1641 rxcfg |= BIGMAC_RXCFG_PMISC;
1642 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1643
1644 /* Let the bits settle in the chip. */
1645 udelay(10);
1646
1647 /* Ok, configure the Big Mac transmitter. */
1648 HMD(("BIGMAC init, "));
1649 regtmp = 0;
1650 if (hp->happy_flags & HFLAG_FULL)
1651 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1652 hme_write32(hp, bregs + BMAC_TXCFG, regtmp | BIGMAC_TXCFG_DGIVEUP);
1653
1654 /* Enable the output drivers no matter what. */
1655 regtmp = BIGMAC_XCFG_ODENABLE;
1656
1657 /* If card can do lance mode, enable it. */
1658 if (hp->happy_flags & HFLAG_LANCE)
1659 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1660
1661 /* Disable the MII buffers if using external transceiver. */
1662 if (hp->tcvr_type == external)
1663 regtmp |= BIGMAC_XCFG_MIIDISAB;
1664
1665 HMD(("XIF config old[%08x], ",
1666 hme_read32(hp, bregs + BMAC_XIFCFG)));
1667 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1668
1669 /* Start things up. */
1670 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1671 hme_read32(hp, bregs + BMAC_TXCFG),
1672 hme_read32(hp, bregs + BMAC_RXCFG)));
1673 hme_write32(hp, bregs + BMAC_TXCFG,
1674 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1675 hme_write32(hp, bregs + BMAC_RXCFG,
1676 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1677
1678 /* Get the autonegotiation started, and the watch timer ticking. */
1679 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1680
1681 /* Success. */
1682 return 0;
1683 }
1684
1685 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1686 {
1687 unsigned long tregs = hp->tcvregs;
1688 unsigned long bregs = hp->bigmacregs;
1689 unsigned long gregs = hp->gregs;
1690
1691 happy_meal_stop(hp, gregs);
1692 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1693 if (hp->happy_flags & HFLAG_FENABLE)
1694 hme_write32(hp, tregs + TCVR_CFG,
1695 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1696 else
1697 hme_write32(hp, tregs + TCVR_CFG,
1698 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1699 happy_meal_transceiver_check(hp, tregs);
1700 switch(hp->tcvr_type) {
1701 case none:
1702 return;
1703 case internal:
1704 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1705 break;
1706 case external:
1707 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1708 break;
1709 };
1710 if (happy_meal_tcvr_reset(hp, tregs))
1711 return;
1712
1713 /* Latch PHY registers as of now. */
1714 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
1715 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, DP83840_ADVERTISE);
1716
1717 /* Advertise everything we can support. */
1718 if (hp->sw_bmsr & BMSR_10HALF)
1719 hp->sw_advertise |= (ADVERTISE_10HALF);
1720 else
1721 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1722
1723 if (hp->sw_bmsr & BMSR_10FULL)
1724 hp->sw_advertise |= (ADVERTISE_10FULL);
1725 else
1726 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1727 if (hp->sw_bmsr & BMSR_100HALF)
1728 hp->sw_advertise |= (ADVERTISE_100HALF);
1729 else
1730 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1731 if (hp->sw_bmsr & BMSR_100FULL)
1732 hp->sw_advertise |= (ADVERTISE_100FULL);
1733 else
1734 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1735
1736 /* Update the PHY advertisement register. */
1737 happy_meal_tcvr_write(hp, tregs, DP83840_ADVERTISE, hp->sw_advertise);
1738 }
1739
1740 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1741 * the hardware, so we cannot re-read it and get a correct value.
1742 */
1743 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1744 {
1745 int reset = 0;
1746
1747 /* Only print messages for non-counter related interrupts. */
1748 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1749 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1750 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1751 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1752 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1753 GREG_STAT_SLVPERR))
1754 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1755 hp->dev->name, status);
1756
1757 if (status & GREG_STAT_RFIFOVF) {
1758 /* Receive FIFO overflow is harmless and the hardware will take
1759 care of it, just some packets are lost. Who cares. */
1760 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1761 }
1762
1763 if (status & GREG_STAT_STSTERR) {
1764 /* BigMAC SQE link test failed. */
1765 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1766 reset = 1;
1767 }
1768
1769 if (status & GREG_STAT_TFIFO_UND) {
1770 /* Transmit FIFO underrun, again DMA error likely. */
1771 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1772 hp->dev->name);
1773 reset = 1;
1774 }
1775
1776 if (status & GREG_STAT_MAXPKTERR) {
1777 /* Driver error, tried to transmit something larger
1778 * than ethernet max mtu.
1779 */
1780 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1781 reset = 1;
1782 }
1783
1784 if (status & GREG_STAT_NORXD) {
1785 /* This is harmless, it just means the system is
1786 * quite loaded and the incomming packet rate was
1787 * faster than the interrupt handler could keep up
1788 * with.
1789 */
1790 printk(KERN_INFO "%s: Happy Meal out of receive "
1791 "descriptors, packet dropped.\n",
1792 hp->dev->name);
1793 }
1794
1795 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1796 /* All sorts of DMA receive errors. */
1797 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1798 if (status & GREG_STAT_RXERR)
1799 printk("GenericError ");
1800 if (status & GREG_STAT_RXPERR)
1801 printk("ParityError ");
1802 if (status & GREG_STAT_RXTERR)
1803 printk("RxTagBotch ");
1804 printk("]\n");
1805 reset = 1;
1806 }
1807
1808 if (status & GREG_STAT_EOPERR) {
1809 /* Driver bug, didn't set EOP bit in tx descriptor given
1810 * to the happy meal.
1811 */
1812 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1813 hp->dev->name);
1814 reset = 1;
1815 }
1816
1817 if (status & GREG_STAT_MIFIRQ) {
1818 /* MIF signalled an interrupt, were we polling it? */
1819 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1820 }
1821
1822 if (status &
1823 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1824 /* All sorts of transmit DMA errors. */
1825 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1826 if (status & GREG_STAT_TXEACK)
1827 printk("GenericError ");
1828 if (status & GREG_STAT_TXLERR)
1829 printk("LateError ");
1830 if (status & GREG_STAT_TXPERR)
1831 printk("ParityErro ");
1832 if (status & GREG_STAT_TXTERR)
1833 printk("TagBotch ");
1834 printk("]\n");
1835 reset = 1;
1836 }
1837
1838 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1839 /* Bus or parity error when cpu accessed happy meal registers
1840 * or it's internal FIFO's. Should never see this.
1841 */
1842 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1843 hp->dev->name,
1844 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1845 reset = 1;
1846 }
1847
1848 if (reset) {
1849 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1850 happy_meal_init(hp, 1);
1851 return 1;
1852 }
1853 return 0;
1854 }
1855
1856 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1857 {
1858 unsigned long tregs = hp->tcvregs;
1859
1860 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1861 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1862 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, DP83840_LPA);
1863
1864 /* Use the fastest transmission protocol possible. */
1865 if (hp->sw_lpa & LPA_100FULL) {
1866 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1867 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1868 } else if (hp->sw_lpa & LPA_100HALF) {
1869 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1870 hp->sw_bmcr |= BMCR_SPEED100;
1871 } else if (hp->sw_lpa & LPA_10FULL) {
1872 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1873 hp->sw_bmcr |= BMCR_FULLDPLX;
1874 } else {
1875 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1876 }
1877 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1878
1879 /* Finally stop polling and shut up the MIF. */
1880 happy_meal_poll_stop(hp, tregs);
1881 }
1882
1883 #ifdef TXDEBUG
1884 #define TXD(x) printk x
1885 #else
1886 #define TXD(x)
1887 #endif
1888
1889 static void happy_meal_tx(struct happy_meal *hp)
1890 {
1891 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1892 struct happy_meal_txd *this;
1893 struct net_device *dev = hp->dev;
1894 int elem;
1895
1896 spin_lock(&hp->happy_lock);
1897
1898 elem = hp->tx_old;
1899 TXD(("TX<"));
1900 while (elem != hp->tx_new) {
1901 struct sk_buff *skb;
1902 u32 flags, dma_addr;
1903
1904 TXD(("[%d]", elem));
1905 this = &txbase[elem];
1906 flags = hme_read_desc32(hp, &this->tx_flags);
1907 if (flags & TXFLAG_OWN)
1908 break;
1909 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1910 skb = hp->tx_skbs[elem];
1911 hme_dma_unmap(hp, dma_addr, skb->len, DMA_TODEVICE);
1912 hp->tx_skbs[elem] = NULL;
1913 hp->net_stats.tx_bytes += skb->len;
1914
1915 dev_kfree_skb_irq(skb);
1916
1917 hp->net_stats.tx_packets++;
1918 elem = NEXT_TX(elem);
1919 }
1920 hp->tx_old = elem;
1921 TXD((">"));
1922
1923 if (netif_queue_stopped(dev) &&
1924 TX_BUFFS_AVAIL(hp) > 0)
1925 netif_wake_queue(dev);
1926
1927 spin_unlock(&hp->happy_lock);
1928 }
1929
1930 #ifdef RXDEBUG
1931 #define RXD(x) printk x
1932 #else
1933 #define RXD(x)
1934 #endif
1935
1936 /* Originally I used to handle the allocation failure by just giving back just
1937 * that one ring buffer to the happy meal. Problem is that usually when that
1938 * condition is triggered, the happy meal expects you to do something reasonable
1939 * with all of the packets it has DMA'd in. So now I just drop the entire
1940 * ring when we cannot get a new skb and give them all back to the happy meal,
1941 * maybe things will be "happier" now.
1942 */
1943 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1944 {
1945 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1946 struct happy_meal_rxd *this;
1947 int elem = hp->rx_new, drops = 0;
1948 u32 flags;
1949
1950 RXD(("RX<"));
1951 this = &rxbase[elem];
1952 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1953 struct sk_buff *skb;
1954 int len = flags >> 16;
1955 u16 csum = flags & RXFLAG_CSUM;
1956 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
1957
1958 RXD(("[%d ", elem));
1959
1960 /* Check for errors. */
1961 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
1962 RXD(("ERR(%08x)]", flags));
1963 hp->net_stats.rx_errors++;
1964 if (len < ETH_ZLEN)
1965 hp->net_stats.rx_length_errors++;
1966 if (len & (RXFLAG_OVERFLOW >> 16)) {
1967 hp->net_stats.rx_over_errors++;
1968 hp->net_stats.rx_fifo_errors++;
1969 }
1970
1971 /* Return it to the Happy meal. */
1972 drop_it:
1973 hp->net_stats.rx_dropped++;
1974 hme_write_rxd(hp, this,
1975 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
1976 dma_addr);
1977 goto next;
1978 }
1979 skb = hp->rx_skbs[elem];
1980 if (len > RX_COPY_THRESHOLD) {
1981 struct sk_buff *new_skb;
1982
1983 /* Now refill the entry, if we can. */
1984 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1985 if (new_skb == NULL) {
1986 drops++;
1987 goto drop_it;
1988 }
1989 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1990 hp->rx_skbs[elem] = new_skb;
1991 new_skb->dev = dev;
1992 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
1993 hme_write_rxd(hp, this,
1994 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
1995 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1996 skb_reserve(new_skb, RX_OFFSET);
1997
1998 /* Trim the original skb for the netif. */
1999 skb_trim(skb, len);
2000 } else {
2001 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2002
2003 if (copy_skb == NULL) {
2004 drops++;
2005 goto drop_it;
2006 }
2007
2008 copy_skb->dev = dev;
2009 skb_reserve(copy_skb, 2);
2010 skb_put(copy_skb, len);
2011 hme_dma_sync(hp, dma_addr, len, DMA_FROMDEVICE);
2012 memcpy(copy_skb->data, skb->data, len);
2013
2014 /* Reuse original ring buffer. */
2015 hme_write_rxd(hp, this,
2016 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2017 dma_addr);
2018
2019 skb = copy_skb;
2020 }
2021
2022 /* This card is _fucking_ hot... */
2023 if (!(csum ^ 0xffff))
2024 skb->ip_summed = CHECKSUM_UNNECESSARY;
2025 else
2026 skb->ip_summed = CHECKSUM_NONE;
2027
2028 RXD(("len=%d csum=%4x]", len, csum));
2029 skb->protocol = eth_type_trans(skb, dev);
2030 netif_rx(skb);
2031
2032 hp->net_stats.rx_packets++;
2033 hp->net_stats.rx_bytes += len;
2034 next:
2035 elem = NEXT_RX(elem);
2036 this = &rxbase[elem];
2037 }
2038 hp->rx_new = elem;
2039 if (drops)
2040 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2041 RXD((">"));
2042 }
2043
2044 static void happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2045 {
2046 struct net_device *dev = (struct net_device *) dev_id;
2047 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2048 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2049
2050 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2051
2052 if (happy_status & GREG_STAT_ERRORS) {
2053 HMD(("ERRORS "));
2054 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2055 return;
2056 }
2057
2058 if (happy_status & GREG_STAT_MIFIRQ) {
2059 HMD(("MIFIRQ "));
2060 happy_meal_mif_interrupt(hp);
2061 }
2062
2063 if (happy_status & GREG_STAT_TXALL) {
2064 HMD(("TXALL "));
2065 happy_meal_tx(hp);
2066 }
2067
2068 if (happy_status & GREG_STAT_RXTOHOST) {
2069 HMD(("RXTOHOST "));
2070 happy_meal_rx(hp, dev);
2071 }
2072
2073 HMD(("done\n"));
2074 }
2075
2076 static void quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2077 {
2078 struct quattro *qp = (struct quattro *) cookie;
2079 int i;
2080
2081 for (i = 0; i < 4; i++) {
2082 struct net_device *dev = qp->happy_meals[i];
2083 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2084 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2085
2086 HMD(("quattro_interrupt: status=%08x ", happy_status));
2087
2088 if (!(happy_status & (GREG_STAT_ERRORS |
2089 GREG_STAT_MIFIRQ |
2090 GREG_STAT_TXALL |
2091 GREG_STAT_RXTOHOST)))
2092 continue;
2093
2094 if (happy_status & GREG_STAT_ERRORS) {
2095 HMD(("ERRORS "));
2096 if (happy_meal_is_not_so_happy(hp, happy_status))
2097 break;
2098 }
2099
2100 if (happy_status & GREG_STAT_MIFIRQ) {
2101 HMD(("MIFIRQ "));
2102 happy_meal_mif_interrupt(hp);
2103 }
2104
2105 if (happy_status & GREG_STAT_TXALL) {
2106 HMD(("TXALL "));
2107 happy_meal_tx(hp);
2108 }
2109
2110 if (happy_status & GREG_STAT_RXTOHOST) {
2111 HMD(("RXTOHOST "));
2112 happy_meal_rx(hp, dev);
2113 }
2114 }
2115 HMD(("done\n"));
2116 }
2117
2118 static int happy_meal_open(struct net_device *dev)
2119 {
2120 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2121 int res;
2122
2123 HMD(("happy_meal_open: "));
2124
2125 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2126 * into a single source which we register handling at probe time.
2127 */
2128 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2129 if (request_irq(dev->irq, &happy_meal_interrupt,
2130 SA_SHIRQ, "HAPPY MEAL", (void *)dev)) {
2131 HMD(("EAGAIN\n"));
2132 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %s to go.\n",
2133 __irq_itoa(dev->irq));
2134 return -EAGAIN;
2135 }
2136 }
2137
2138 HMD(("to happy_meal_init\n"));
2139 res = happy_meal_init(hp, 0);
2140 if (!res) {
2141 MOD_INC_USE_COUNT;
2142 }
2143 return res;
2144 }
2145
2146 static int happy_meal_close(struct net_device *dev)
2147 {
2148 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2149
2150 happy_meal_stop(hp, hp->gregs);
2151 happy_meal_clean_rings(hp);
2152
2153 /* If auto-negotiation timer is running, kill it. */
2154 del_timer(&hp->happy_timer);
2155
2156 /* On Quattro QFE cards, all hme interrupts are concentrated
2157 * into a single source which we register handling at probe
2158 * time and never unregister.
2159 */
2160 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2161 free_irq(dev->irq, (void *)dev);
2162
2163 MOD_DEC_USE_COUNT;
2164 return 0;
2165 }
2166
2167 #ifdef SXDEBUG
2168 #define SXD(x) printk x
2169 #else
2170 #define SXD(x)
2171 #endif
2172
2173 static void happy_meal_tx_timeout(struct net_device *dev)
2174 {
2175 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2176
2177 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2178 tx_dump_log();
2179 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2180 hme_read32(hp, hp->gregs + GREG_STAT),
2181 hme_read32(hp, hp->etxregs + ETX_CFG),
2182 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2183 happy_meal_init(hp, 0);
2184 netif_wake_queue(dev);
2185 }
2186
2187 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2188 {
2189 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2190 int len, entry;
2191 u32 mapping;
2192
2193 len = skb->len;
2194 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2195
2196 spin_lock_irq(&hp->happy_lock);
2197
2198 entry = hp->tx_new;
2199 SXD(("SX<l[%d]e[%d]>", len, entry));
2200 hp->tx_skbs[entry] = skb;
2201 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2202 (TXFLAG_OWN | TXFLAG_SOP | TXFLAG_EOP | (len & TXFLAG_SIZE)),
2203 mapping);
2204 hp->tx_new = NEXT_TX(entry);
2205 if (TX_BUFFS_AVAIL(hp) <= 0)
2206 netif_stop_queue(dev);
2207
2208 /* Get it going. */
2209 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2210
2211 spin_unlock_irq(&hp->happy_lock);
2212
2213 dev->trans_start = jiffies;
2214
2215 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2216 return 0;
2217 }
2218
2219 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2220 {
2221 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2222
2223 happy_meal_get_counters(hp, hp->bigmacregs);
2224 return &hp->net_stats;
2225 }
2226
2227 static void happy_meal_set_multicast(struct net_device *dev)
2228 {
2229 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2230 unsigned long bregs = hp->bigmacregs;
2231 struct dev_mc_list *dmi = dev->mc_list;
2232 char *addrs;
2233 int i, j, bit, byte;
2234 u32 crc, poly = CRC_POLYNOMIAL_LE;
2235
2236 /* Lock out others. */
2237 netif_stop_queue(dev);
2238
2239 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2240 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2241 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2242 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2243 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2244 } else if (dev->flags & IFF_PROMISC) {
2245 hme_write32(hp, bregs + BMAC_RXCFG,
2246 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2247 } else {
2248 u16 hash_table[4];
2249
2250 for (i = 0; i < 4; i++)
2251 hash_table[i] = 0;
2252
2253 for (i = 0; i < dev->mc_count; i++) {
2254 addrs = dmi->dmi_addr;
2255 dmi = dmi->next;
2256
2257 if (!(*addrs & 1))
2258 continue;
2259
2260 crc = 0xffffffffU;
2261 for (byte = 0; byte < 6; byte++) {
2262 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
2263 int test;
2264
2265 test = ((bit ^ crc) & 0x01);
2266 crc >>= 1;
2267 if (test)
2268 crc = crc ^ poly;
2269 }
2270 }
2271 crc >>= 26;
2272 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2273 }
2274 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2275 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2276 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2277 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2278 }
2279
2280 /* Let us get going again. */
2281 netif_wake_queue(dev);
2282 }
2283
2284 /* Ethtool support... */
2285 static int happy_meal_ioctl(struct net_device *dev,
2286 struct ifreq *rq, int cmd)
2287 {
2288 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2289 struct ethtool_cmd *ep_user = (struct ethtool_cmd *) rq->ifr_data;
2290 struct ethtool_cmd ecmd;
2291
2292 if (cmd != SIOCETHTOOL)
2293 return -EOPNOTSUPP;
2294 if (copy_from_user(&ecmd, ep_user, sizeof(ecmd)))
2295 return -EFAULT;
2296
2297 if (ecmd.cmd == SPARC_ETH_GSET) {
2298 ecmd.supported =
2299 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2300 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2301 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2302
2303 /* XXX hardcoded stuff for now */
2304 ecmd.port = PORT_TP; /* XXX no MII support */
2305 ecmd.transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2306 ecmd.phy_address = 0; /* XXX fixed PHYAD */
2307
2308 /* Record PHY settings. */
2309 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, DP83840_BMCR);
2310 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, DP83840_LPA);
2311 if (hp->sw_bmcr & BMCR_ANENABLE) {
2312 ecmd.autoneg = AUTONEG_ENABLE;
2313 ecmd.speed =
2314 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2315 SPEED_100 : SPEED_10;
2316 if (ecmd.speed == SPEED_100)
2317 ecmd.duplex =
2318 (hp->sw_lpa & (LPA_100FULL)) ?
2319 DUPLEX_FULL : DUPLEX_HALF;
2320 else
2321 ecmd.duplex =
2322 (hp->sw_lpa & (LPA_10FULL)) ?
2323 DUPLEX_FULL : DUPLEX_HALF;
2324 } else {
2325 ecmd.autoneg = AUTONEG_DISABLE;
2326 ecmd.speed =
2327 (hp->sw_bmcr & BMCR_SPEED100) ?
2328 SPEED_100 : SPEED_10;
2329 ecmd.duplex =
2330 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2331 DUPLEX_FULL : DUPLEX_HALF;
2332 }
2333 if (copy_to_user(ep_user, &ecmd, sizeof(ecmd)))
2334 return -EFAULT;
2335 return 0;
2336 } else if (ecmd.cmd == SPARC_ETH_SSET) {
2337 if (!capable(CAP_NET_ADMIN))
2338 return -EPERM;
2339
2340 /* Verify the settings we care about. */
2341 if (ecmd.autoneg != AUTONEG_ENABLE &&
2342 ecmd.autoneg != AUTONEG_DISABLE)
2343 return -EINVAL;
2344 if (ecmd.autoneg == AUTONEG_DISABLE &&
2345 ((ecmd.speed != SPEED_100 &&
2346 ecmd.speed != SPEED_10) ||
2347 (ecmd.duplex != DUPLEX_HALF &&
2348 ecmd.duplex != DUPLEX_FULL)))
2349 return -EINVAL;
2350
2351 /* Ok, do it to it. */
2352 del_timer(&hp->happy_timer);
2353 happy_meal_begin_auto_negotiation(hp,
2354 hp->tcvregs,
2355 &ecmd);
2356
2357 return 0;
2358 } else
2359 return -EOPNOTSUPP;
2360 }
2361
2362 static int hme_version_printed = 0;
2363
2364 #ifdef CONFIG_SBUS
2365 void __init quattro_get_ranges(struct quattro *qp)
2366 {
2367 struct sbus_dev *sdev = qp->quattro_dev;
2368 int err;
2369
2370 err = prom_getproperty(sdev->prom_node,
2371 "ranges",
2372 (char *)&qp->ranges[0],
2373 sizeof(qp->ranges));
2374 if (err == 0 || err == -1) {
2375 qp->nranges = 0;
2376 return;
2377 }
2378 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2379 }
2380
2381 static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2382 {
2383 struct sbus_dev *sdev = hp->happy_dev;
2384 int rng;
2385
2386 for (rng = 0; rng < qp->nranges; rng++) {
2387 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2388 int reg;
2389
2390 for (reg = 0; reg < 5; reg++) {
2391 if (sdev->reg_addrs[reg].which_io ==
2392 rngp->ot_child_space)
2393 break;
2394 }
2395 if (reg == 5)
2396 continue;
2397
2398 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2399 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2400 }
2401 }
2402
2403 /* Given a happy meal sbus device, find it's quattro parent.
2404 * If none exist, allocate and return a new one.
2405 *
2406 * Return NULL on failure.
2407 */
2408 static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2409 {
2410 struct sbus_bus *sbus;
2411 struct sbus_dev *sdev;
2412 struct quattro *qp;
2413
2414 if (qfe_sbus_list == NULL)
2415 goto found;
2416
2417 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2418 for (sdev = qp->quattro_dev;
2419 sdev != NULL;
2420 sdev = sdev->next) {
2421 if (sdev == goal_sdev)
2422 return qp;
2423 }
2424 }
2425 for_each_sbus(sbus) {
2426 for_each_sbusdev(sdev, sbus) {
2427 if (sdev->child != NULL) {
2428 struct sbus_dev *p;
2429
2430 for (p = sdev->child; p != NULL; p = p->next)
2431 if (p == goal_sdev)
2432 goto found;
2433 }
2434 }
2435 }
2436
2437 /* Cannot find quattro parent, fail. */
2438 return NULL;
2439
2440 found:
2441 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2442 if (qp != NULL) {
2443 int i;
2444
2445 for (i = 0; i < 4; i++)
2446 qp->happy_meals[i] = NULL;
2447
2448 qp->quattro_dev = goal_sdev;
2449 qp->next = qfe_sbus_list;
2450 qfe_sbus_list = qp;
2451 quattro_get_ranges(qp);
2452 }
2453 return qp;
2454 }
2455
2456 /* After all quattro cards have been probed, we call these functions
2457 * to register the IRQ handlers.
2458 */
2459 static void __init quattro_sbus_register_irqs(void)
2460 {
2461 struct quattro *qp;
2462
2463 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2464 struct sbus_dev *sdev = qp->quattro_dev;
2465 int err;
2466
2467 err = request_irq(sdev->irqs[0],
2468 quattro_sbus_interrupt,
2469 SA_SHIRQ, "Quattro",
2470 qp);
2471 if (err != 0) {
2472 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2473 panic("QFE request irq");
2474 }
2475 }
2476 }
2477 #endif /* CONFIG_SBUS */
2478
2479 #ifdef CONFIG_PCI
2480 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2481 {
2482 struct pci_dev *bdev = pdev->bus->self;
2483 struct quattro *qp;
2484
2485 if (!bdev) return NULL;
2486 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2487 struct pci_dev *qpdev = qp->quattro_dev;
2488
2489 if (qpdev == bdev)
2490 return qp;
2491 }
2492 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2493 if (qp != NULL) {
2494 int i;
2495
2496 for (i = 0; i < 4; i++)
2497 qp->happy_meals[i] = NULL;
2498
2499 qp->quattro_dev = bdev;
2500 qp->next = qfe_pci_list;
2501 qfe_pci_list = qp;
2502
2503 /* No range tricks necessary on PCI. */
2504 qp->nranges = 0;
2505 }
2506 return qp;
2507 }
2508 #endif /* CONFIG_PCI */
2509
2510 #ifdef CONFIG_SBUS
2511 static int __init happy_meal_sbus_init(struct net_device *dev,
2512 struct sbus_dev *sdev,
2513 int is_qfe)
2514 {
2515 struct quattro *qp = NULL;
2516 struct happy_meal *hp;
2517 int i, qfe_slot = -1;
2518
2519 if (is_qfe) {
2520 qp = quattro_sbus_find(sdev);
2521 if (qp == NULL)
2522 return ENODEV;
2523 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2524 if (qp->happy_meals[qfe_slot] == NULL)
2525 break;
2526 if (qfe_slot == 4)
2527 return ENODEV;
2528 }
2529 if (dev == NULL) {
2530 dev = init_etherdev(0, sizeof(struct happy_meal));
2531 } else {
2532 dev->priv = kmalloc(sizeof(struct happy_meal), GFP_KERNEL);
2533 if (dev->priv == NULL)
2534 return -ENOMEM;
2535 }
2536 if (hme_version_printed++ == 0)
2537 printk(KERN_INFO "%s", version);
2538
2539 if (qfe_slot != -1)
2540 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2541 dev->name, qfe_slot);
2542 else
2543 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2544 dev->name);
2545
2546 /* Quattro local-mac-address... */
2547 if (qfe_slot != -1 && prom_getproplen(sdev->prom_node,"local-mac-address")==6)
2548 prom_getproperty(sdev->prom_node,"local-mac-address",dev->dev_addr,6);
2549 else
2550 memcpy(dev->dev_addr,idprom->id_ethaddr,6);
2551 for (i = 0; i < 6; i++)
2552 printk("%2.2x%c",
2553 dev->dev_addr[i], i == 5 ? ' ' : ':');
2554 printk("\n");
2555
2556 hp = (struct happy_meal *) dev->priv;
2557 memset(hp, 0, sizeof(*hp));
2558
2559 hp->happy_dev = sdev;
2560
2561 spin_lock_init(&hp->happy_lock);
2562
2563 if (sdev->num_registers != 5) {
2564 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2565 sdev->num_registers);
2566 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2567 return ENODEV;
2568 }
2569
2570 if (qp != NULL) {
2571 hp->qfe_parent = qp;
2572 hp->qfe_ent = qfe_slot;
2573 qp->happy_meals[qfe_slot] = dev;
2574 quattro_apply_ranges(qp, hp);
2575 }
2576
2577 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2578 GREG_REG_SIZE, "HME Global Regs");
2579 if (!hp->gregs) {
2580 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2581 return ENODEV;
2582 }
2583
2584 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2585 ETX_REG_SIZE, "HME TX Regs");
2586 if (!hp->etxregs) {
2587 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2588 return ENODEV;
2589 }
2590
2591 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2592 ERX_REG_SIZE, "HME RX Regs");
2593 if (!hp->erxregs) {
2594 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2595 return ENODEV;
2596 }
2597
2598 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2599 BMAC_REG_SIZE, "HME BIGMAC Regs");
2600 if (!hp->bigmacregs) {
2601 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2602 return ENODEV;
2603 }
2604
2605 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2606 TCVR_REG_SIZE, "HME Tranceiver Regs");
2607 if (!hp->tcvregs) {
2608 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2609 return ENODEV;
2610 }
2611
2612 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2613 if (hp->hm_revision == 0xff)
2614 hp->hm_revision = 0xa0;
2615
2616 /* Now enable the feature flags we can. */
2617 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2618 hp->happy_flags = HFLAG_20_21;
2619 else if (hp->hm_revision != 0xa0)
2620 hp->happy_flags = HFLAG_NOT_A0;
2621
2622 if (qp != NULL)
2623 hp->happy_flags |= HFLAG_QUATTRO;
2624
2625 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2626 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2627 "burst-sizes", 0x00);
2628
2629 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2630 PAGE_SIZE,
2631 &hp->hblock_dvma);
2632
2633 /* Force check of the link first time we are brought up. */
2634 hp->linkcheck = 0;
2635
2636 /* Force timer state to 'asleep' with count of zero. */
2637 hp->timer_state = asleep;
2638 hp->timer_ticks = 0;
2639
2640 init_timer(&hp->happy_timer);
2641
2642 hp->dev = dev;
2643 dev->open = &happy_meal_open;
2644 dev->stop = &happy_meal_close;
2645 dev->hard_start_xmit = &happy_meal_start_xmit;
2646 dev->get_stats = &happy_meal_get_stats;
2647 dev->set_multicast_list = &happy_meal_set_multicast;
2648 dev->tx_timeout = &happy_meal_tx_timeout;
2649 dev->watchdog_timeo = 5*HZ;
2650 dev->do_ioctl = &happy_meal_ioctl;
2651
2652 dev->irq = sdev->irqs[0];
2653
2654 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2655 /* Hook up PCI register/dma accessors. */
2656 hp->read_desc32 = sbus_hme_read_desc32;
2657 hp->write_txd = sbus_hme_write_txd;
2658 hp->write_rxd = sbus_hme_write_rxd;
2659 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2660 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2661 hp->dma_sync = (void (*)(void *, u32, long, int))sbus_dma_sync_single;
2662 hp->read32 = sbus_hme_read32;
2663 hp->write32 = sbus_hme_write32;
2664 #endif
2665
2666 /* Grrr, Happy Meal comes up by default not advertising
2667 * full duplex 100baseT capabilities, fix this.
2668 */
2669 happy_meal_set_initial_advertisement(hp);
2670
2671 ether_setup(dev);
2672 #ifdef MODULE
2673 /* We are home free at this point, link us in to the happy
2674 * module device list.
2675 */
2676 dev->ifindex = dev_new_index();
2677 hp->next_module = root_happy_dev;
2678 root_happy_dev = hp;
2679 #endif
2680 return 0;
2681 }
2682 #endif
2683
2684 #ifdef CONFIG_PCI
2685 static int __init happy_meal_pci_init(struct net_device *dev, struct pci_dev *pdev)
2686 {
2687 struct quattro *qp = NULL;
2688 struct pcidev_cookie *pcp;
2689 struct happy_meal *hp;
2690 unsigned long hpreg_base;
2691 unsigned short pci_command;
2692 int i, node, qfe_slot = -1;
2693 char prom_name[64];
2694
2695 /* Now make sure pci_dev cookie is there. */
2696 pcp = pdev->sysdata;
2697 if (pcp == NULL || pcp->prom_node == -1) {
2698 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
2699 return ENODEV;
2700 }
2701 node = pcp->prom_node;
2702
2703 prom_getstring(node, "name", prom_name, sizeof(prom_name));
2704 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2705 qp = quattro_pci_find(pdev);
2706 if (qp == NULL)
2707 return ENODEV;
2708 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2709 if (qp->happy_meals[qfe_slot] == NULL)
2710 break;
2711 if (qfe_slot == 4)
2712 return ENODEV;
2713 }
2714 if (dev == NULL) {
2715 dev = init_etherdev(0, sizeof(struct happy_meal));
2716 } else {
2717 dev->priv = kmalloc(sizeof(struct happy_meal), GFP_KERNEL);
2718 if (dev->priv == NULL)
2719 return -ENOMEM;
2720 }
2721 if (hme_version_printed++ == 0)
2722 printk(KERN_INFO "%s", version);
2723
2724 if (!qfe_slot) {
2725 struct pci_dev *qpdev = qp->quattro_dev;
2726
2727 prom_name[0] = 0;
2728 if (!strncmp(dev->name, "eth", 3)) {
2729 int i = simple_strtoul(dev->name + 3, NULL, 10);
2730 sprintf(prom_name, "-%d", i + 3);
2731 }
2732 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
2733 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
2734 qpdev->device == PCI_DEVICE_ID_DEC_21153)
2735 printk("DEC 21153 PCI Bridge\n");
2736 else
2737 printk("unknown bridge %04x.%04x\n",
2738 qpdev->vendor, qpdev->device);
2739 }
2740 if (qfe_slot != -1)
2741 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
2742 dev->name, qfe_slot);
2743 else
2744 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
2745 dev->name);
2746
2747 dev->base_addr = (long) pdev;
2748
2749 hp = (struct happy_meal *)dev->priv;
2750 memset(hp, 0, sizeof(*hp));
2751
2752 hp->happy_dev = pdev;
2753
2754 spin_lock_init(&hp->happy_lock);
2755
2756 if (qp != NULL) {
2757 hp->qfe_parent = qp;
2758 hp->qfe_ent = qfe_slot;
2759 qp->happy_meals[qfe_slot] = dev;
2760 }
2761
2762 hpreg_base = pdev->resource[0].start;
2763 if ((pdev->resource[0].flags & IORESOURCE_IO) != 0) {
2764 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
2765 return ENODEV;
2766 }
2767 hpreg_base &= PCI_BASE_ADDRESS_MEM_MASK;
2768 hpreg_base = (unsigned long) ioremap(hpreg_base, 0x8000);
2769
2770 if (qfe_slot != -1 && prom_getproplen(node, "local-mac-address") == 6)
2771 prom_getproperty(node, "local-mac-address", dev->dev_addr, 6);
2772 else
2773 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2774 for (i = 0; i < 6; i++)
2775 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
2776
2777 printk("\n");
2778
2779 /* Layout registers. */
2780 hp->gregs = (hpreg_base + 0x0000UL);
2781 hp->etxregs = (hpreg_base + 0x2000UL);
2782 hp->erxregs = (hpreg_base + 0x4000UL);
2783 hp->bigmacregs = (hpreg_base + 0x6000UL);
2784 hp->tcvregs = (hpreg_base + 0x7000UL);
2785
2786 hp->hm_revision = prom_getintdefault(node, "hm-rev", 0xff);
2787 if (hp->hm_revision == 0xff)
2788 hp->hm_revision = 0xa0;
2789
2790 /* Now enable the feature flags we can. */
2791 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2792 hp->happy_flags = HFLAG_20_21;
2793 else if (hp->hm_revision != 0xa0)
2794 hp->happy_flags = HFLAG_NOT_A0;
2795
2796 if (qp != NULL)
2797 hp->happy_flags |= HFLAG_QUATTRO;
2798
2799 /* And of course, indicate this is PCI. */
2800 hp->happy_flags |= HFLAG_PCI;
2801
2802 /* Assume PCI happy meals can handle all burst sizes. */
2803 hp->happy_bursts = DMA_BURSTBITS;
2804
2805 hp->happy_block = (struct hmeal_init_block *)
2806 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
2807
2808 if (!hp->happy_block) {
2809 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
2810 return ENODEV;
2811 }
2812
2813 hp->linkcheck = 0;
2814 hp->timer_state = asleep;
2815 hp->timer_ticks = 0;
2816
2817 init_timer(&hp->happy_timer);
2818
2819 hp->dev = dev;
2820 dev->open = &happy_meal_open;
2821 dev->stop = &happy_meal_close;
2822 dev->hard_start_xmit = &happy_meal_start_xmit;
2823 dev->get_stats = &happy_meal_get_stats;
2824 dev->set_multicast_list = &happy_meal_set_multicast;
2825 dev->do_ioctl = &happy_meal_ioctl;
2826 dev->irq = pdev->irq;
2827 dev->dma = 0;
2828
2829 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2830 /* Hook up PCI register/dma accessors. */
2831 hp->read_desc32 = pci_hme_read_desc32;
2832 hp->write_txd = pci_hme_write_txd;
2833 hp->write_rxd = pci_hme_write_rxd;
2834 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
2835 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
2836 hp->dma_sync = (void (*)(void *, u32, long, int))pci_dma_sync_single;
2837 hp->read32 = pci_hme_read32;
2838 hp->write32 = pci_hme_write32;
2839 #endif
2840
2841 /* Grrr, Happy Meal comes up by default not advertising
2842 * full duplex 100baseT capabilities, fix this.
2843 */
2844 happy_meal_set_initial_advertisement(hp);
2845
2846 ether_setup(dev);
2847
2848 /* If we don't do this, nothing works. */
2849 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2850 pci_command |= PCI_COMMAND_MASTER;
2851 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
2852
2853 /* Set the latency timer and cache line size as well,
2854 * PROM leaves it at zero.
2855 */
2856 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
2857 #ifdef __sparc_v9__
2858 /* NOTE: Cache line size is in 32-bit word units. */
2859 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x10);
2860 #endif
2861
2862 #ifdef MODULE
2863 /* We are home free at this point, link us in to the happy
2864 * module device list.
2865 */
2866 dev->ifindex = dev_new_index();
2867 hp->next_module = root_happy_dev;
2868 root_happy_dev = hp;
2869 #endif
2870 return 0;
2871 }
2872 #endif
2873
2874 #ifdef CONFIG_SBUS
2875 static int __init happy_meal_sbus_probe(struct net_device *dev)
2876 {
2877 struct sbus_bus *sbus;
2878 struct sbus_dev *sdev;
2879 int cards = 0;
2880
2881 for_each_sbus(sbus) {
2882 for_each_sbusdev(sdev, sbus) {
2883 char *name = sdev->prom_name;
2884
2885 if (cards)
2886 dev = NULL;
2887 if (!strcmp(name, "SUNW,hme")) {
2888 cards++;
2889 happy_meal_sbus_init(dev, sdev, 0);
2890 } else if (!strcmp(name, "qfe") ||
2891 !strcmp(name, "SUNW,qfe")) {
2892 cards++;
2893 happy_meal_sbus_init(dev, sdev, 1);
2894 }
2895 }
2896 }
2897 if (cards != 0)
2898 quattro_sbus_register_irqs();
2899 return cards;
2900 }
2901 #endif
2902
2903 #ifdef CONFIG_PCI
2904 static int __init happy_meal_pci_probe(struct net_device *dev)
2905 {
2906 int cards = 0;
2907
2908 if (pci_present()) {
2909 struct pci_dev *pdev;
2910
2911 pdev = pci_find_device(PCI_VENDOR_ID_SUN,
2912 PCI_DEVICE_ID_SUN_HAPPYMEAL, 0);
2913 while (pdev != NULL) {
2914 if (cards)
2915 dev = NULL;
2916 cards++;
2917 happy_meal_pci_init(dev, pdev);
2918 pdev = pci_find_device(PCI_VENDOR_ID_SUN,
2919 PCI_DEVICE_ID_SUN_HAPPYMEAL,
2920 pdev);
2921 }
2922 }
2923 return cards;
2924 }
2925 #endif
2926
2927 static int __init happy_meal_probe(void)
2928 {
2929 struct net_device *dev = NULL;
2930 static int called = 0;
2931 int cards;
2932
2933 #ifdef MODULE
2934 root_happy_dev = NULL;
2935 #endif
2936
2937 if (called)
2938 return ENODEV;
2939 called++;
2940
2941 cards = 0;
2942 #ifdef CONFIG_SBUS
2943 cards += happy_meal_sbus_probe(dev);
2944 if (cards != 0)
2945 dev = NULL;
2946 #endif
2947 #ifdef CONFIG_PCI
2948 cards += happy_meal_pci_probe(dev);
2949 #endif
2950 if (!cards)
2951 return ENODEV;
2952 return 0;
2953 }
2954
2955
2956 static void __exit happy_meal_cleanup_module(void)
2957 {
2958 #ifdef MODULE
2959 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
2960 while (root_happy_dev) {
2961 struct happy_meal *hp = root_happy_dev;
2962 struct happy_meal *next = root_happy_dev->next_module;
2963
2964 #ifdef CONFIG_SBUS
2965 if (!(hp->happy_flags & HFLAG_PCI)) {
2966 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2967 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2968 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2969 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2970 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2971 sbus_free_consistent(hp->happy_dev,
2972 PAGE_SIZE,
2973 hp->happy_block,
2974 hp->hblock_dvma);
2975 }
2976 #endif
2977 #ifdef CONFIG_PCI
2978 if ((hp->happy_flags & HFLAG_PCI)) {
2979 pci_free_consistent(hp->happy_dev,
2980 PAGE_SIZE,
2981 hp->happy_block,
2982 hp->hblock_dvma);
2983 }
2984 #endif
2985 unregister_netdev(hp->dev);
2986 kfree(hp->dev);
2987 root_happy_dev = next;
2988 }
2989 #endif /* MODULE */
2990 }
2991
2992 module_init(happy_meal_probe);
2993 module_exit(happy_meal_cleanup_module);
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