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Ok. I didn't make 2.4.0 in 2000. Tough. I tried, but we had some
[davej-history.git] / drivers / net / sunhme.c
blobba436a12b77c0541a331774c6b46ea069d8b2394
1 /* $Id: sunhme.c,v 1.105 2000/12/05 02:00:36 anton Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 *
6 * Copyright (C) 1996, 1998, 1999 David S. Miller (davem@redhat.com)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
16 static char *version =
17 "sunhme.c:v1.99 12/Sep/99 David S. Miller (davem@redhat.com)\n";
18
19 #include <linux/module.h>
20
21 #include <linux/config.h>
22 #include <linux/kernel.h>
23 #include <linux/sched.h>
24 #include <linux/types.h>
25 #include <linux/fcntl.h>
26 #include <linux/interrupt.h>
27 #include <linux/ptrace.h>
28 #include <linux/ioport.h>
29 #include <linux/in.h>
30 #include <linux/malloc.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33 #include <linux/init.h>
34 #include <linux/ethtool.h>
35 #include <asm/system.h>
36 #include <asm/bitops.h>
37 #include <asm/io.h>
38 #include <asm/dma.h>
39 #include <linux/errno.h>
40 #include <asm/byteorder.h>
41
42 #ifdef __sparc__
43 #include <asm/idprom.h>
44 #include <asm/sbus.h>
45 #include <asm/openprom.h>
46 #include <asm/oplib.h>
47 #include <asm/auxio.h>
48 #ifndef __sparc_v9__
49 #include <asm/io-unit.h>
50 #endif
51 #endif
52 #include <asm/uaccess.h>
53
54 #include <asm/pgtable.h>
55 #include <asm/irq.h>
56
57 #include <linux/netdevice.h>
58 #include <linux/etherdevice.h>
59 #include <linux/skbuff.h>
60
61 #ifdef CONFIG_PCI
62 #include <linux/pci.h>
63 #ifdef __sparc__
64 #include <asm/pbm.h>
65 #endif
66 #endif
67
68 #include "sunhme.h"
69
70
71 static int macaddr[6];
72
73 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
74 MODULE_PARM(macaddr, "6i");
75
76 static struct happy_meal *root_happy_dev = NULL;
77
78 #ifdef CONFIG_SBUS
79 static struct quattro *qfe_sbus_list = NULL;
80 #endif
81
82 #ifdef CONFIG_PCI
83 static struct quattro *qfe_pci_list = NULL;
84 #endif
85
86 #undef HMEDEBUG
87 #undef SXDEBUG
88 #undef RXDEBUG
89 #undef TXDEBUG
90 #undef TXLOGGING
91
92 #ifdef TXLOGGING
93 struct hme_tx_logent {
94 unsigned int tstamp;
95 int tx_new, tx_old;
96 unsigned int action;
97 #define TXLOG_ACTION_IRQ 0x01
98 #define TXLOG_ACTION_TXMIT 0x02
99 #define TXLOG_ACTION_TBUSY 0x04
100 #define TXLOG_ACTION_NBUFS 0x08
101 unsigned int status;
102 };
103 #define TX_LOG_LEN 128
104 static struct hme_tx_logent tx_log[TX_LOG_LEN];
105 static int txlog_cur_entry = 0;
106 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
107 {
108 struct hme_tx_logent *tlp;
109 unsigned long flags;
110
111 save_and_cli(flags);
112 tlp = &tx_log[txlog_cur_entry];
113 tlp->tstamp = (unsigned int)jiffies;
114 tlp->tx_new = hp->tx_new;
115 tlp->tx_old = hp->tx_old;
116 tlp->action = a;
117 tlp->status = s;
118 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
119 restore_flags(flags);
120 }
121 static __inline__ void tx_dump_log(void)
122 {
123 int i, this;
124
125 this = txlog_cur_entry;
126 for (i = 0; i < TX_LOG_LEN; i++) {
127 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
128 tx_log[this].tstamp,
129 tx_log[this].tx_new, tx_log[this].tx_old,
130 tx_log[this].action, tx_log[this].status);
131 this = (this + 1) & (TX_LOG_LEN - 1);
132 }
133 }
134 static __inline__ void tx_dump_ring(struct happy_meal *hp)
135 {
136 struct hmeal_init_block *hb = hp->happy_block;
137 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
138 int i;
139
140 for (i = 0; i < TX_RING_SIZE; i+=4) {
141 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
142 i, i + 4,
143 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
144 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
145 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
146 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
147 }
148 }
149 #else
150 #define tx_add_log(hp, a, s) do { } while(0)
151 #define tx_dump_log() do { } while(0)
152 #define tx_dump_ring(hp) do { } while(0)
153 #endif
154
155 #ifdef HMEDEBUG
156 #define HMD(x) printk x
157 #else
158 #define HMD(x)
159 #endif
160
161 /* #define AUTO_SWITCH_DEBUG */
162
163 #ifdef AUTO_SWITCH_DEBUG
164 #define ASD(x) printk x
165 #else
166 #define ASD(x)
167 #endif
168
169 #define DEFAULT_IPG0 16 /* For lance-mode only */
170 #define DEFAULT_IPG1 8 /* For all modes */
171 #define DEFAULT_IPG2 4 /* For all modes */
172 #define DEFAULT_JAMSIZE 4 /* Toe jam */
173
174 #ifdef CONFIG_PCI
175 /* This happy_pci_ids is declared __initdata because it is only used
176 as an advisory to depmod. If this is ported to the new PCI interface
177 where it could be referenced at any time due to hot plugging,
178 it should be changed to __devinitdata. */
179
180 struct pci_device_id happymeal_pci_ids[] __initdata = {
181 {
182 vendor: PCI_VENDOR_ID_SUN,
183 device: PCI_DEVICE_ID_SUN_HAPPYMEAL,
184 subvendor: PCI_ANY_ID,
185 subdevice: PCI_ANY_ID,
186 },
187 { } /* Terminating entry */
188 };
189
190 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
191 #endif
192
193 /* NOTE: In the descriptor writes one _must_ write the address
194 * member _first_. The card must not be allowed to see
195 * the updated descriptor flags until the address is
196 * correct. I've added a write memory barrier between
197 * the two stores so that I can sleep well at night... -DaveM
198 */
199
200 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
201 static void sbus_hme_write32(unsigned long reg, u32 val)
202 {
203 sbus_writel(val, reg);
204 }
205
206 static u32 sbus_hme_read32(unsigned long reg)
207 {
208 return sbus_readl(reg);
209 }
210
211 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
212 {
213 rxd->rx_addr = addr;
214 wmb();
215 rxd->rx_flags = flags;
216 }
217
218 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
219 {
220 txd->tx_addr = addr;
221 wmb();
222 txd->tx_flags = flags;
223 }
224
225 static u32 sbus_hme_read_desc32(u32 *p)
226 {
227 return *p;
228 }
229
230 static void pci_hme_write32(unsigned long reg, u32 val)
231 {
232 writel(val, reg);
233 }
234
235 static u32 pci_hme_read32(unsigned long reg)
236 {
237 return readl(reg);
238 }
239
240 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
241 {
242 rxd->rx_addr = cpu_to_le32(addr);
243 wmb();
244 rxd->rx_flags = cpu_to_le32(flags);
245 }
246
247 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
248 {
249 txd->tx_addr = cpu_to_le32(addr);
250 wmb();
251 txd->tx_flags = cpu_to_le32(flags);
252 }
253
254 static u32 pci_hme_read_desc32(u32 *p)
255 {
256 return cpu_to_le32p(p);
257 }
258
259 #define hme_write32(__hp, __reg, __val) \
260 ((__hp)->write32((__reg), (__val)))
261 #define hme_read32(__hp, __reg) \
262 ((__hp)->read32(__reg))
263 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
264 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
265 #define hme_write_txd(__hp, __txd, __flags, __addr) \
266 ((__hp)->write_txd((__txd), (__flags), (__addr)))
267 #define hme_read_desc32(__hp, __p) \
268 ((__hp)->read_desc32(__p))
269 #define hme_dma_map(__hp, __ptr, __size, __dir) \
270 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
271 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
272 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
273 #define hme_dma_sync(__hp, __addr, __size, __dir) \
274 ((__hp)->dma_sync((__hp)->happy_dev, (__addr), (__size), (__dir)))
275 #else
276 #ifdef CONFIG_SBUS
277 /* SBUS only compilation */
278 #define hme_write32(__hp, __reg, __val) \
279 sbus_writel((__val), (__reg))
280 #define hme_read32(__hp, __reg) \
281 sbus_readl(__reg)
282 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
283 do { (__rxd)->rx_addr = (__addr); \
284 wmb(); \
285 (__rxd)->rx_flags = (__flags); \
286 } while(0)
287 #define hme_write_txd(__hp, __txd, __flags, __addr) \
288 do { (__txd)->tx_addr = (__addr); \
289 wmb(); \
290 (__txd)->tx_flags = (__flags); \
291 } while(0)
292 #define hme_read_desc32(__hp, __p) (*(__p))
293 #define hme_dma_map(__hp, __ptr, __size, __dir) \
294 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
295 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
296 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
297 #define hme_dma_sync(__hp, __addr, __size, __dir) \
298 sbus_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
299 #else
300 /* PCI only compilation */
301 #define hme_write32(__hp, __reg, __val) \
302 writel((__val), (__reg))
303 #define hme_read32(__hp, __reg) \
304 readl(__reg)
305 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
306 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
307 wmb(); \
308 (__rxd)->rx_flags = cpu_to_le32(__flags); \
309 } while(0)
310 #define hme_write_txd(__hp, __txd, __flags, __addr) \
311 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
312 wmb(); \
313 (__txd)->tx_flags = cpu_to_le32(__flags); \
314 } while(0)
315 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
316 #define hme_dma_map(__hp, __ptr, __size, __dir) \
317 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
318 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
319 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
320 #define hme_dma_sync(__hp, __addr, __size, __dir) \
321 pci_dma_sync_single((__hp)->happy_dev, (__addr), (__size), (__dir))
322 #endif
323 #endif
324
325
326 #ifdef SBUS_DMA_BIDIRECTIONAL
327 # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
328 #else
329 # define DMA_BIDIRECTIONAL 0
330 #endif
331
332 #ifdef SBUS_DMA_FROMDEVICE
333 # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
334 #else
335 # define DMA_TODEVICE 1
336 #endif
337
338 #ifdef SBUS_DMA_TODEVICE
339 # define DMA_TODEVICE SBUS_DMA_TODEVICE
340 #else
341 # define DMA_FROMDEVICE 2
342 #endif
343
344
345 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
346 static void BB_PUT_BIT(struct happy_meal *hp, unsigned long tregs, int bit)
347 {
348 hme_write32(hp, tregs + TCVR_BBDATA, bit);
349 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
350 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
351 }
352
353 #if 0
354 static u32 BB_GET_BIT(struct happy_meal *hp, unsigned long tregs, int internal)
355 {
356 u32 ret;
357
358 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
359 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
360 ret = hme_read32(hp, tregs + TCVR_CFG);
361 if (internal)
362 ret &= TCV_CFG_MDIO0;
363 else
364 ret &= TCV_CFG_MDIO1;
365
366 return ret;
367 }
368 #endif
369
370 static u32 BB_GET_BIT2(struct happy_meal *hp, unsigned long tregs, int internal)
371 {
372 u32 retval;
373
374 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
375 udelay(1);
376 retval = hme_read32(hp, tregs + TCVR_CFG);
377 if (internal)
378 retval &= TCV_CFG_MDIO0;
379 else
380 retval &= TCV_CFG_MDIO1;
381 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
382
383 return retval;
384 }
385
386 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
387
388 static int happy_meal_bb_read(struct happy_meal *hp,
389 unsigned long tregs, int reg)
390 {
391 u32 tmp;
392 int retval = 0;
393 int i;
394
395 ASD(("happy_meal_bb_read: reg=%d ", reg));
396
397 /* Enable the MIF BitBang outputs. */
398 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
399
400 /* Force BitBang into the idle state. */
401 for (i = 0; i < 32; i++)
402 BB_PUT_BIT(hp, tregs, 1);
403
404 /* Give it the read sequence. */
405 BB_PUT_BIT(hp, tregs, 0);
406 BB_PUT_BIT(hp, tregs, 1);
407 BB_PUT_BIT(hp, tregs, 1);
408 BB_PUT_BIT(hp, tregs, 0);
409
410 /* Give it the PHY address. */
411 tmp = hp->paddr & 0xff;
412 for (i = 4; i >= 0; i--)
413 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
414
415 /* Tell it what register we want to read. */
416 tmp = (reg & 0xff);
417 for (i = 4; i >= 0; i--)
418 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
419
420 /* Close down the MIF BitBang outputs. */
421 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
422
423 /* Now read in the value. */
424 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
425 for (i = 15; i >= 0; i--)
426 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
427 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
428 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
429 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
430 ASD(("value=%x\n", retval));
431 return retval;
432 }
433
434 static void happy_meal_bb_write(struct happy_meal *hp,
435 unsigned long tregs, int reg,
436 unsigned short value)
437 {
438 u32 tmp;
439 int i;
440
441 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
442
443 /* Enable the MIF BitBang outputs. */
444 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
445
446 /* Force BitBang into the idle state. */
447 for (i = 0; i < 32; i++)
448 BB_PUT_BIT(hp, tregs, 1);
449
450 /* Give it write sequence. */
451 BB_PUT_BIT(hp, tregs, 0);
452 BB_PUT_BIT(hp, tregs, 1);
453 BB_PUT_BIT(hp, tregs, 0);
454 BB_PUT_BIT(hp, tregs, 1);
455
456 /* Give it the PHY address. */
457 tmp = (hp->paddr & 0xff);
458 for (i = 4; i >= 0; i--)
459 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
460
461 /* Tell it what register we will be writing. */
462 tmp = (reg & 0xff);
463 for (i = 4; i >= 0; i--)
464 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
465
466 /* Tell it to become ready for the bits. */
467 BB_PUT_BIT(hp, tregs, 1);
468 BB_PUT_BIT(hp, tregs, 0);
469
470 for (i = 15; i >= 0; i--)
471 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
472
473 /* Close down the MIF BitBang outputs. */
474 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
475 }
476
477 #define TCVR_READ_TRIES 16
478
479 static int happy_meal_tcvr_read(struct happy_meal *hp,
480 unsigned long tregs, int reg)
481 {
482 int tries = TCVR_READ_TRIES;
483 int retval;
484
485 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
486 if (hp->tcvr_type == none) {
487 ASD(("no transceiver, value=TCVR_FAILURE\n"));
488 return TCVR_FAILURE;
489 }
490
491 if (!(hp->happy_flags & HFLAG_FENABLE)) {
492 ASD(("doing bit bang\n"));
493 return happy_meal_bb_read(hp, tregs, reg);
494 }
495
496 hme_write32(hp, tregs + TCVR_FRAME,
497 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
498 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
499 udelay(20);
500 if (!tries) {
501 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
502 return TCVR_FAILURE;
503 }
504 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
505 ASD(("value=%04x\n", retval));
506 return retval;
507 }
508
509 #define TCVR_WRITE_TRIES 16
510
511 static void happy_meal_tcvr_write(struct happy_meal *hp,
512 unsigned long tregs, int reg,
513 unsigned short value)
514 {
515 int tries = TCVR_WRITE_TRIES;
516
517 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
518
519 /* Welcome to Sun Microsystems, can I take your order please? */
520 if (!hp->happy_flags & HFLAG_FENABLE)
521 return happy_meal_bb_write(hp, tregs, reg, value);
522
523 /* Would you like fries with that? */
524 hme_write32(hp, tregs + TCVR_FRAME,
525 (FRAME_WRITE | (hp->paddr << 23) |
526 ((reg & 0xff) << 18) | (value & 0xffff)));
527 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
528 udelay(20);
529
530 /* Anything else? */
531 if (!tries)
532 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
533
534 /* Fifty-two cents is your change, have a nice day. */
535 }
536
537 /* Auto negotiation. The scheme is very simple. We have a timer routine
538 * that keeps watching the auto negotiation process as it progresses.
539 * The DP83840 is first told to start doing it's thing, we set up the time
540 * and place the timer state machine in it's initial state.
541 *
542 * Here the timer peeks at the DP83840 status registers at each click to see
543 * if the auto negotiation has completed, we assume here that the DP83840 PHY
544 * will time out at some point and just tell us what (didn't) happen. For
545 * complete coverage we only allow so many of the ticks at this level to run,
546 * when this has expired we print a warning message and try another strategy.
547 * This "other" strategy is to force the interface into various speed/duplex
548 * configurations and we stop when we see a link-up condition before the
549 * maximum number of "peek" ticks have occurred.
550 *
551 * Once a valid link status has been detected we configure the BigMAC and
552 * the rest of the Happy Meal to speak the most efficient protocol we could
553 * get a clean link for. The priority for link configurations, highest first
554 * is:
555 * 100 Base-T Full Duplex
556 * 100 Base-T Half Duplex
557 * 10 Base-T Full Duplex
558 * 10 Base-T Half Duplex
559 *
560 * We start a new timer now, after a successful auto negotiation status has
561 * been detected. This timer just waits for the link-up bit to get set in
562 * the BMCR of the DP83840. When this occurs we print a kernel log message
563 * describing the link type in use and the fact that it is up.
564 *
565 * If a fatal error of some sort is signalled and detected in the interrupt
566 * service routine, and the chip is reset, or the link is ifconfig'd down
567 * and then back up, this entire process repeats itself all over again.
568 */
569 static int try_next_permutation(struct happy_meal *hp, unsigned long tregs)
570 {
571 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
572
573 /* Downgrade from full to half duplex. Only possible
574 * via ethtool.
575 */
576 if (hp->sw_bmcr & BMCR_FULLDPLX) {
577 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
578 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
579 return 0;
580 }
581
582 /* Downgrade from 100 to 10. */
583 if (hp->sw_bmcr & BMCR_SPEED100) {
584 hp->sw_bmcr &= ~(BMCR_SPEED100);
585 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
586 return 0;
587 }
588
589 /* We've tried everything. */
590 return -1;
591 }
592
593 static void display_link_mode(struct happy_meal *hp, unsigned long tregs)
594 {
595 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
596 if (hp->tcvr_type == external)
597 printk("external ");
598 else
599 printk("internal ");
600 printk("transceiver at ");
601 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, DP83840_LPA);
602 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
603 if (hp->sw_lpa & LPA_100FULL)
604 printk("100Mb/s, Full Duplex.\n");
605 else
606 printk("100Mb/s, Half Duplex.\n");
607 } else {
608 if (hp->sw_lpa & LPA_10FULL)
609 printk("10Mb/s, Full Duplex.\n");
610 else
611 printk("10Mb/s, Half Duplex.\n");
612 }
613 }
614
615 static void display_forced_link_mode(struct happy_meal *hp, unsigned long tregs)
616 {
617 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
618 if (hp->tcvr_type == external)
619 printk("external ");
620 else
621 printk("internal ");
622 printk("transceiver at ");
623 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
624 if (hp->sw_bmcr & BMCR_SPEED100)
625 printk("100Mb/s, ");
626 else
627 printk("10Mb/s, ");
628 if (hp->sw_bmcr & BMCR_FULLDPLX)
629 printk("Full Duplex.\n");
630 else
631 printk("Half Duplex.\n");
632 }
633
634 static int set_happy_link_modes(struct happy_meal *hp, unsigned long tregs)
635 {
636 int full;
637
638 /* All we care about is making sure the bigmac tx_cfg has a
639 * proper duplex setting.
640 */
641 if (hp->timer_state == arbwait) {
642 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, DP83840_LPA);
643 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
644 goto no_response;
645 if (hp->sw_lpa & LPA_100FULL)
646 full = 1;
647 else if (hp->sw_lpa & LPA_100HALF)
648 full = 0;
649 else if (hp->sw_lpa & LPA_10FULL)
650 full = 1;
651 else
652 full = 0;
653 } else {
654 /* Forcing a link mode. */
655 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
656 if (hp->sw_bmcr & BMCR_FULLDPLX)
657 full = 1;
658 else
659 full = 0;
660 }
661
662 /* Before changing other bits in the tx_cfg register, and in
663 * general any of other the TX config registers too, you
664 * must:
665 * 1) Clear Enable
666 * 2) Poll with reads until that bit reads back as zero
667 * 3) Make TX configuration changes
668 * 4) Set Enable once more
669 */
670 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
671 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
672 ~(BIGMAC_TXCFG_ENABLE));
673 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
674 barrier();
675 if (full) {
676 hp->happy_flags |= HFLAG_FULL;
677 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
678 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
679 BIGMAC_TXCFG_FULLDPLX);
680 } else {
681 hp->happy_flags &= ~(HFLAG_FULL);
682 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
683 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
684 ~(BIGMAC_TXCFG_FULLDPLX));
685 }
686 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
687 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
688 BIGMAC_TXCFG_ENABLE);
689 return 0;
690 no_response:
691 return 1;
692 }
693
694 static int happy_meal_init(struct happy_meal *hp, int from_irq);
695
696 static int is_lucent_phy(struct happy_meal *hp)
697 {
698 unsigned long tregs = hp->tcvregs;
699 unsigned short mr2, mr3;
700 int ret = 0;
701
702 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
703 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
704 if ((mr2 & 0xffff) == 0x0180 &&
705 ((mr3 & 0xffff) >> 10) == 0x1d) {
706 #if 0
707 printk("HMEDEBUG: Lucent PHY detected.\n");
708 #endif
709 ret = 1;
710 }
711
712 return ret;
713 }
714
715 static void happy_meal_timer(unsigned long data)
716 {
717 struct happy_meal *hp = (struct happy_meal *) data;
718 unsigned long tregs = hp->tcvregs;
719 int restart_timer = 0;
720
721 hp->timer_ticks++;
722 switch(hp->timer_state) {
723 case arbwait:
724 /* Only allow for 5 ticks, thats 10 seconds and much too
725 * long to wait for arbitration to complete.
726 */
727 if (hp->timer_ticks >= 10) {
728 /* Enter force mode. */
729 do_force_mode:
730 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
731 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
732 hp->dev->name);
733 hp->sw_bmcr = BMCR_SPEED100;
734 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
735
736 if (!is_lucent_phy(hp)) {
737 /* OK, seems we need do disable the transceiver for the first
738 * tick to make sure we get an accurate link state at the
739 * second tick.
740 */
741 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
742 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
743 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
744 }
745 hp->timer_state = ltrywait;
746 hp->timer_ticks = 0;
747 restart_timer = 1;
748 } else {
749 /* Anything interesting happen? */
750 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
751 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
752 int ret;
753
754 /* Just what we've been waiting for... */
755 ret = set_happy_link_modes(hp, tregs);
756 if (ret) {
757 /* Ooops, something bad happened, go to force
758 * mode.
759 *
760 * XXX Broken hubs which don't support 802.3u
761 * XXX auto-negotiation make this happen as well.
762 */
763 goto do_force_mode;
764 }
765
766 /* Success, at least so far, advance our state engine. */
767 hp->timer_state = lupwait;
768 restart_timer = 1;
769 } else {
770 restart_timer = 1;
771 }
772 }
773 break;
774
775 case lupwait:
776 /* Auto negotiation was successful and we are awaiting a
777 * link up status. I have decided to let this timer run
778 * forever until some sort of error is signalled, reporting
779 * a message to the user at 10 second intervals.
780 */
781 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
782 if (hp->sw_bmsr & BMSR_LSTATUS) {
783 /* Wheee, it's up, display the link mode in use and put
784 * the timer to sleep.
785 */
786 display_link_mode(hp, tregs);
787 hp->timer_state = asleep;
788 restart_timer = 0;
789 } else {
790 if (hp->timer_ticks >= 10) {
791 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
792 "not completely up.\n", hp->dev->name);
793 hp->timer_ticks = 0;
794 restart_timer = 1;
795 } else {
796 restart_timer = 1;
797 }
798 }
799 break;
800
801 case ltrywait:
802 /* Making the timeout here too long can make it take
803 * annoyingly long to attempt all of the link mode
804 * permutations, but then again this is essentially
805 * error recovery code for the most part.
806 */
807 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
808 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
809 if (hp->timer_ticks == 1) {
810 if (!is_lucent_phy(hp)) {
811 /* Re-enable transceiver, we'll re-enable the transceiver next
812 * tick, then check link state on the following tick.
813 */
814 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
815 happy_meal_tcvr_write(hp, tregs,
816 DP83840_CSCONFIG, hp->sw_csconfig);
817 }
818 restart_timer = 1;
819 break;
820 }
821 if (hp->timer_ticks == 2) {
822 if (!is_lucent_phy(hp)) {
823 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
824 happy_meal_tcvr_write(hp, tregs,
825 DP83840_CSCONFIG, hp->sw_csconfig);
826 }
827 restart_timer = 1;
828 break;
829 }
830 if (hp->sw_bmsr & BMSR_LSTATUS) {
831 /* Force mode selection success. */
832 display_forced_link_mode(hp, tregs);
833 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
834 hp->timer_state = asleep;
835 restart_timer = 0;
836 } else {
837 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
838 int ret;
839
840 ret = try_next_permutation(hp, tregs);
841 if (ret == -1) {
842 /* Aieee, tried them all, reset the
843 * chip and try all over again.
844 */
845
846 /* Let the user know... */
847 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
848 hp->dev->name);
849
850 ret = happy_meal_init(hp, 0);
851 if (ret) {
852 /* ho hum... */
853 printk(KERN_ERR "%s: Error, cannot re-init the "
854 "Happy Meal.\n", hp->dev->name);
855 }
856 return;
857 }
858 if (!is_lucent_phy(hp)) {
859 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
860 DP83840_CSCONFIG);
861 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
862 happy_meal_tcvr_write(hp, tregs,
863 DP83840_CSCONFIG, hp->sw_csconfig);
864 }
865 hp->timer_ticks = 0;
866 restart_timer = 1;
867 } else {
868 restart_timer = 1;
869 }
870 }
871 break;
872
873 case asleep:
874 default:
875 /* Can't happens.... */
876 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
877 hp->dev->name);
878 restart_timer = 0;
879 hp->timer_ticks = 0;
880 hp->timer_state = asleep; /* foo on you */
881 break;
882 };
883
884 if (restart_timer) {
885 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
886 add_timer(&hp->happy_timer);
887 }
888 }
889
890 #define TX_RESET_TRIES 32
891 #define RX_RESET_TRIES 32
892
893 static void happy_meal_tx_reset(struct happy_meal *hp, unsigned long bregs)
894 {
895 int tries = TX_RESET_TRIES;
896
897 HMD(("happy_meal_tx_reset: reset, "));
898
899 /* Would you like to try our SMCC Delux? */
900 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
901 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
902 udelay(20);
903
904 /* Lettuce, tomato, buggy hardware (no extra charge)? */
905 if (!tries)
906 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
907
908 /* Take care. */
909 HMD(("done\n"));
910 }
911
912 static void happy_meal_rx_reset(struct happy_meal *hp, unsigned long bregs)
913 {
914 int tries = RX_RESET_TRIES;
915
916 HMD(("happy_meal_rx_reset: reset, "));
917
918 /* We have a special on GNU/Viking hardware bugs today. */
919 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
920 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
921 udelay(20);
922
923 /* Will that be all? */
924 if (!tries)
925 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
926
927 /* Don't forget your vik_1137125_wa. Have a nice day. */
928 HMD(("done\n"));
929 }
930
931 #define STOP_TRIES 16
932
933 static void happy_meal_stop(struct happy_meal *hp, unsigned long gregs)
934 {
935 int tries = STOP_TRIES;
936
937 HMD(("happy_meal_stop: reset, "));
938
939 /* We're consolidating our STB products, it's your lucky day. */
940 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
941 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
942 udelay(20);
943
944 /* Come back next week when we are "Sun Microelectronics". */
945 if (!tries)
946 printk(KERN_ERR "happy meal: Fry guys.");
947
948 /* Remember: "Different name, same old buggy as shit hardware." */
949 HMD(("done\n"));
950 }
951
952 static void happy_meal_get_counters(struct happy_meal *hp, unsigned long bregs)
953 {
954 struct net_device_stats *stats = &hp->net_stats;
955
956 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
957 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
958
959 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
960 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
961
962 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
963 hme_write32(hp, bregs + BMAC_GLECTR, 0);
964
965 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
966
967 stats->collisions +=
968 (hme_read32(hp, bregs + BMAC_EXCTR) +
969 hme_read32(hp, bregs + BMAC_LTCTR));
970 hme_write32(hp, bregs + BMAC_EXCTR, 0);
971 hme_write32(hp, bregs + BMAC_LTCTR, 0);
972 }
973
974 #if 0
975 static void happy_meal_poll_start(struct happy_meal *hp, unsigned long tregs)
976 {
977 u32 tmp;
978 int speed;
979
980 ASD(("happy_meal_poll_start: "));
981 if (!(hp->happy_flags & HFLAG_POLLENABLE)) {
982 HMD(("polling disabled, return\n"));
983 return;
984 }
985
986 /* Start the MIF polling on the external transceiver. */
987 ASD(("polling on, "));
988 tmp = hme_read32(hp, tregs + TCVR_CFG);
989 tmp &= ~(TCV_CFG_PDADDR | TCV_CFG_PREGADDR);
990 tmp |= ((hp->paddr & 0x1f) << 10);
991 tmp |= (TCV_PADDR_ETX << 3);
992 tmp |= TCV_CFG_PENABLE;
993 hme_write32(hp, tregs + TCVR_CFG, tmp);
994
995 /* Let the bits set. */
996 udelay(200);
997
998 /* We are polling now. */
999 ASD(("now polling, "));
1000 hp->happy_flags |= HFLAG_POLL;
1001
1002 /* Clear the poll flags, get the basic status as of now. */
1003 hp->poll_flag = 0;
1004 hp->poll_data = hme_read32(hp, tregs + TCVR_STATUS) >> 16;
1005
1006 if (hp->happy_flags & HFLAG_AUTO)
1007 speed = hp->auto_speed;
1008 else
1009 speed = hp->forced_speed;
1010
1011 /* Listen only for the MIF interrupts we want to hear. */
1012 ASD(("mif ints on, "));
1013 if (speed == 100)
1014 hme_write32(hp, tregs + TCVR_IMASK, 0xfffb);
1015 else
1016 hme_write32(hp, tregs + TCVR_IMASK, 0xfff9);
1017 ASD(("done\n"));
1018 }
1019 #endif
1020
1021 static void happy_meal_poll_stop(struct happy_meal *hp, unsigned long tregs)
1022 {
1023 ASD(("happy_meal_poll_stop: "));
1024
1025 /* If polling disabled or not polling already, nothing to do. */
1026 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
1027 (HFLAG_POLLENABLE | HFLAG_POLL)) {
1028 HMD(("not polling, return\n"));
1029 return;
1030 }
1031
1032 /* Shut up the MIF. */
1033 ASD(("were polling, mif ints off, "));
1034 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1035
1036 /* Turn off polling. */
1037 ASD(("polling off, "));
1038 hme_write32(hp, tregs + TCVR_CFG,
1039 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
1040
1041 /* We are no longer polling. */
1042 hp->happy_flags &= ~(HFLAG_POLL);
1043
1044 /* Let the bits set. */
1045 udelay(200);
1046 ASD(("done\n"));
1047 }
1048
1049 /* Only Sun can take such nice parts and fuck up the programming interface
1050 * like this. Good job guys...
1051 */
1052 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
1053 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1054
1055 static int happy_meal_tcvr_reset(struct happy_meal *hp, unsigned long tregs)
1056 {
1057 u32 tconfig;
1058 int result, tries = TCVR_RESET_TRIES;
1059
1060 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1061 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1062 if (hp->tcvr_type == external) {
1063 ASD(("external<"));
1064 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1065 hp->tcvr_type = internal;
1066 hp->paddr = TCV_PADDR_ITX;
1067 ASD(("ISOLATE,"));
1068 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR,
1069 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1070 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1071 if (result == TCVR_FAILURE) {
1072 ASD(("phyread_fail>\n"));
1073 return -1;
1074 }
1075 ASD(("phyread_ok,PSELECT>"));
1076 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1077 hp->tcvr_type = external;
1078 hp->paddr = TCV_PADDR_ETX;
1079 } else {
1080 if (tconfig & TCV_CFG_MDIO1) {
1081 ASD(("internal<PSELECT,"));
1082 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1083 ASD(("ISOLATE,"));
1084 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR,
1085 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1086 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1087 if (result == TCVR_FAILURE) {
1088 ASD(("phyread_fail>\n"));
1089 return -1;
1090 }
1091 ASD(("phyread_ok,~PSELECT>"));
1092 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1093 hp->tcvr_type = internal;
1094 hp->paddr = TCV_PADDR_ITX;
1095 }
1096 }
1097
1098 ASD(("BMCR_RESET "));
1099 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, BMCR_RESET);
1100
1101 while (--tries) {
1102 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1103 if (result == TCVR_FAILURE)
1104 return -1;
1105 hp->sw_bmcr = result;
1106 if (!(result & BMCR_RESET))
1107 break;
1108 udelay(20);
1109 }
1110 if (!tries) {
1111 ASD(("BMCR RESET FAILED!\n"));
1112 return -1;
1113 }
1114 ASD(("RESET_OK\n"));
1115
1116 /* Get fresh copies of the PHY registers. */
1117 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
1118 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID1);
1119 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID2);
1120 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, DP83840_ADVERTISE);
1121
1122 ASD(("UNISOLATE"));
1123 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1124 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1125
1126 tries = TCVR_UNISOLATE_TRIES;
1127 while (--tries) {
1128 result = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1129 if (result == TCVR_FAILURE)
1130 return -1;
1131 if (!(result & BMCR_ISOLATE))
1132 break;
1133 udelay(20);
1134 }
1135 if (!tries) {
1136 ASD((" FAILED!\n"));
1137 return -1;
1138 }
1139 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1140 if (!is_lucent_phy(hp)) {
1141 result = happy_meal_tcvr_read(hp, tregs,
1142 DP83840_CSCONFIG);
1143 happy_meal_tcvr_write(hp, tregs,
1144 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1145 }
1146 return 0;
1147 }
1148
1149 /* Figure out whether we have an internal or external transceiver. */
1150 static void happy_meal_transceiver_check(struct happy_meal *hp, unsigned long tregs)
1151 {
1152 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1153
1154 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1155 if (hp->happy_flags & HFLAG_POLL) {
1156 /* If we are polling, we must stop to get the transceiver type. */
1157 ASD(("<polling> "));
1158 if (hp->tcvr_type == internal) {
1159 if (tconfig & TCV_CFG_MDIO1) {
1160 ASD(("<internal> <poll stop> "));
1161 happy_meal_poll_stop(hp, tregs);
1162 hp->paddr = TCV_PADDR_ETX;
1163 hp->tcvr_type = external;
1164 ASD(("<external>\n"));
1165 tconfig &= ~(TCV_CFG_PENABLE);
1166 tconfig |= TCV_CFG_PSELECT;
1167 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1168 }
1169 } else {
1170 if (hp->tcvr_type == external) {
1171 ASD(("<external> "));
1172 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1173 ASD(("<poll stop> "));
1174 happy_meal_poll_stop(hp, tregs);
1175 hp->paddr = TCV_PADDR_ITX;
1176 hp->tcvr_type = internal;
1177 ASD(("<internal>\n"));
1178 hme_write32(hp, tregs + TCVR_CFG,
1179 hme_read32(hp, tregs + TCVR_CFG) &
1180 ~(TCV_CFG_PSELECT));
1181 }
1182 ASD(("\n"));
1183 } else {
1184 ASD(("<none>\n"));
1185 }
1186 }
1187 } else {
1188 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1189
1190 /* Else we can just work off of the MDIO bits. */
1191 ASD(("<not polling> "));
1192 if (reread & TCV_CFG_MDIO1) {
1193 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1194 hp->paddr = TCV_PADDR_ETX;
1195 hp->tcvr_type = external;
1196 ASD(("<external>\n"));
1197 } else {
1198 if (reread & TCV_CFG_MDIO0) {
1199 hme_write32(hp, tregs + TCVR_CFG,
1200 tconfig & ~(TCV_CFG_PSELECT));
1201 hp->paddr = TCV_PADDR_ITX;
1202 hp->tcvr_type = internal;
1203 ASD(("<internal>\n"));
1204 } else {
1205 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1206 hp->tcvr_type = none; /* Grrr... */
1207 ASD(("<none>\n"));
1208 }
1209 }
1210 }
1211 }
1212
1213 /* The receive ring buffers are a bit tricky to get right. Here goes...
1214 *
1215 * The buffers we dma into must be 64 byte aligned. So we use a special
1216 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1217 * we really need.
1218 *
1219 * We use skb_reserve() to align the data block we get in the skb. We
1220 * also program the etxregs->cfg register to use an offset of 2. This
1221 * imperical constant plus the ethernet header size will always leave
1222 * us with a nicely aligned ip header once we pass things up to the
1223 * protocol layers.
1224 *
1225 * The numbers work out to:
1226 *
1227 * Max ethernet frame size 1518
1228 * Ethernet header size 14
1229 * Happy Meal base offset 2
1230 *
1231 * Say a skb data area is at 0xf001b010, and its size alloced is
1232 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1233 *
1234 * First our alloc_skb() routine aligns the data base to a 64 byte
1235 * boundry. We now have 0xf001b040 as our skb data address. We
1236 * plug this into the receive descriptor address.
1237 *
1238 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1239 * So now the data we will end up looking at starts at 0xf001b042. When
1240 * the packet arrives, we will check out the size received and subtract
1241 * this from the skb->length. Then we just pass the packet up to the
1242 * protocols as is, and allocate a new skb to replace this slot we have
1243 * just received from.
1244 *
1245 * The ethernet layer will strip the ether header from the front of the
1246 * skb we just sent to it, this leaves us with the ip header sitting
1247 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1248 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1249 * bit checksum is obtained from the low bits of the receive descriptor
1250 * flags, thus:
1251 *
1252 * skb->csum = rxd->rx_flags & 0xffff;
1253 * skb->ip_summed = CHECKSUM_HW;
1254 *
1255 * before sending off the skb to the protocols, and we are good as gold.
1256 */
1257 static void happy_meal_clean_rings(struct happy_meal *hp)
1258 {
1259 int i;
1260
1261 for (i = 0; i < RX_RING_SIZE; i++) {
1262 if (hp->rx_skbs[i] != NULL) {
1263 struct sk_buff *skb = hp->rx_skbs[i];
1264 struct happy_meal_rxd *rxd;
1265 u32 dma_addr;
1266
1267 rxd = &hp->happy_block->happy_meal_rxd[i];
1268 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1269 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1270 dev_kfree_skb_any(skb);
1271 hp->rx_skbs[i] = NULL;
1272 }
1273 }
1274
1275 for (i = 0; i < TX_RING_SIZE; i++) {
1276 if (hp->tx_skbs[i] != NULL) {
1277 struct sk_buff *skb = hp->tx_skbs[i];
1278 struct happy_meal_txd *txd;
1279 u32 dma_addr;
1280
1281 txd = &hp->happy_block->happy_meal_txd[i];
1282 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1283 hme_dma_unmap(hp, dma_addr, skb->len, DMA_TODEVICE);
1284 dev_kfree_skb_any(skb);
1285 hp->tx_skbs[i] = NULL;
1286 }
1287 }
1288 }
1289
1290 static void happy_meal_init_rings(struct happy_meal *hp, int from_irq)
1291 {
1292 struct hmeal_init_block *hb = hp->happy_block;
1293 struct net_device *dev = hp->dev;
1294 int i, gfp_flags = GFP_KERNEL;
1295
1296 if (from_irq || in_interrupt())
1297 gfp_flags = GFP_ATOMIC;
1298
1299 HMD(("happy_meal_init_rings: counters to zero, "));
1300 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1301
1302 /* Free any skippy bufs left around in the rings. */
1303 HMD(("clean, "));
1304 happy_meal_clean_rings(hp);
1305
1306 /* Now get new skippy bufs for the receive ring. */
1307 HMD(("init rxring, "));
1308 for (i = 0; i < RX_RING_SIZE; i++) {
1309 struct sk_buff *skb;
1310
1311 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
1312 if (!skb) {
1313 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1314 continue;
1315 }
1316 hp->rx_skbs[i] = skb;
1317 skb->dev = dev;
1318
1319 /* Because we reserve afterwards. */
1320 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1321 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1322 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1323 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1324 skb_reserve(skb, RX_OFFSET);
1325 }
1326
1327 HMD(("init txring, "));
1328 for (i = 0; i < TX_RING_SIZE; i++)
1329 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1330
1331 HMD(("done\n"));
1332 }
1333
1334 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1335 unsigned long tregs,
1336 struct ethtool_cmd *ep)
1337 {
1338 int timeout;
1339
1340 /* Read all of the registers we are interested in now. */
1341 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
1342 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1343 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID1);
1344 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, DP83840_PHYSID2);
1345
1346 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1347
1348 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, DP83840_ADVERTISE);
1349 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1350 /* Advertise everything we can support. */
1351 if (hp->sw_bmsr & BMSR_10HALF)
1352 hp->sw_advertise |= (ADVERTISE_10HALF);
1353 else
1354 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1355
1356 if (hp->sw_bmsr & BMSR_10FULL)
1357 hp->sw_advertise |= (ADVERTISE_10FULL);
1358 else
1359 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1360 if (hp->sw_bmsr & BMSR_100HALF)
1361 hp->sw_advertise |= (ADVERTISE_100HALF);
1362 else
1363 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1364 if (hp->sw_bmsr & BMSR_100FULL)
1365 hp->sw_advertise |= (ADVERTISE_100FULL);
1366 else
1367 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1368 happy_meal_tcvr_write(hp, tregs, DP83840_ADVERTISE, hp->sw_advertise);
1369
1370 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1371 * XXX and this is because the DP83840 does not support it, changes
1372 * XXX would need to be made to the tx/rx logic in the driver as well
1373 * XXX so I completely skip checking for it in the BMSR for now.
1374 */
1375
1376 #ifdef AUTO_SWITCH_DEBUG
1377 ASD(("%s: Advertising [ ", hp->dev->name));
1378 if (hp->sw_advertise & ADVERTISE_10HALF)
1379 ASD(("10H "));
1380 if (hp->sw_advertise & ADVERTISE_10FULL)
1381 ASD(("10F "));
1382 if (hp->sw_advertise & ADVERTISE_100HALF)
1383 ASD(("100H "));
1384 if (hp->sw_advertise & ADVERTISE_100FULL)
1385 ASD(("100F "));
1386 #endif
1387
1388 /* Enable Auto-Negotiation, this is usually on already... */
1389 hp->sw_bmcr |= BMCR_ANENABLE;
1390 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1391
1392 /* Restart it to make sure it is going. */
1393 hp->sw_bmcr |= BMCR_ANRESTART;
1394 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1395
1396 /* BMCR_ANRESTART self clears when the process has begun. */
1397
1398 timeout = 64; /* More than enough. */
1399 while (--timeout) {
1400 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1401 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1402 break; /* got it. */
1403 udelay(10);
1404 }
1405 if (!timeout) {
1406 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1407 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1408 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1409 hp->dev->name);
1410 goto force_link;
1411 } else {
1412 hp->timer_state = arbwait;
1413 }
1414 } else {
1415 force_link:
1416 /* Force the link up, trying first a particular mode.
1417 * Either we are here at the request of ethtool or
1418 * because the Happy Meal would not start to autoneg.
1419 */
1420
1421 /* Disable auto-negotiation in BMCR, enable the duplex and
1422 * speed setting, init the timer state machine, and fire it off.
1423 */
1424 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1425 hp->sw_bmcr = BMCR_SPEED100;
1426 } else {
1427 if (ep->speed == SPEED_100)
1428 hp->sw_bmcr = BMCR_SPEED100;
1429 else
1430 hp->sw_bmcr = 0;
1431 if (ep->duplex == DUPLEX_FULL)
1432 hp->sw_bmcr |= BMCR_FULLDPLX;
1433 }
1434 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1435
1436 if (!is_lucent_phy(hp)) {
1437 /* OK, seems we need do disable the transceiver for the first
1438 * tick to make sure we get an accurate link state at the
1439 * second tick.
1440 */
1441 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1442 DP83840_CSCONFIG);
1443 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1444 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1445 hp->sw_csconfig);
1446 }
1447 hp->timer_state = ltrywait;
1448 }
1449
1450 hp->timer_ticks = 0;
1451 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1452 hp->happy_timer.data = (unsigned long) hp;
1453 hp->happy_timer.function = &happy_meal_timer;
1454 add_timer(&hp->happy_timer);
1455 }
1456
1457 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
1458 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
1459
1460 static int happy_meal_init(struct happy_meal *hp, int from_irq)
1461 {
1462 unsigned long gregs = hp->gregs;
1463 unsigned long etxregs = hp->etxregs;
1464 unsigned long erxregs = hp->erxregs;
1465 unsigned long bregs = hp->bigmacregs;
1466 unsigned long tregs = hp->tcvregs;
1467 u32 regtmp, rxcfg;
1468 unsigned char *e = &hp->dev->dev_addr[0];
1469
1470 /* If auto-negotiation timer is running, kill it. */
1471 del_timer(&hp->happy_timer);
1472
1473 HMD(("happy_meal_init: happy_flags[%08x] ",
1474 hp->happy_flags));
1475 if (!(hp->happy_flags & HFLAG_INIT)) {
1476 HMD(("set HFLAG_INIT, "));
1477 hp->happy_flags |= HFLAG_INIT;
1478 happy_meal_get_counters(hp, bregs);
1479 }
1480
1481 /* Stop polling. */
1482 HMD(("to happy_meal_poll_stop\n"));
1483 happy_meal_poll_stop(hp, tregs);
1484
1485 /* Stop transmitter and receiver. */
1486 HMD(("happy_meal_init: to happy_meal_stop\n"));
1487 happy_meal_stop(hp, gregs);
1488
1489 /* Alloc and reset the tx/rx descriptor chains. */
1490 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1491 happy_meal_init_rings(hp, from_irq);
1492
1493 /* Shut up the MIF. */
1494 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1495 hme_read32(hp, tregs + TCVR_IMASK)));
1496 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1497
1498 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1499 if (hp->happy_flags & HFLAG_FENABLE) {
1500 HMD(("use frame old[%08x], ",
1501 hme_read32(hp, tregs + TCVR_CFG)));
1502 hme_write32(hp, tregs + TCVR_CFG,
1503 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1504 } else {
1505 HMD(("use bitbang old[%08x], ",
1506 hme_read32(hp, tregs + TCVR_CFG)));
1507 hme_write32(hp, tregs + TCVR_CFG,
1508 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1509 }
1510
1511 /* Check the state of the transceiver. */
1512 HMD(("to happy_meal_transceiver_check\n"));
1513 happy_meal_transceiver_check(hp, tregs);
1514
1515 /* Put the Big Mac into a sane state. */
1516 HMD(("happy_meal_init: "));
1517 switch(hp->tcvr_type) {
1518 case none:
1519 /* Cannot operate if we don't know the transceiver type! */
1520 HMD(("AAIEEE no transceiver type, EAGAIN"));
1521 return -EAGAIN;
1522
1523 case internal:
1524 /* Using the MII buffers. */
1525 HMD(("internal, using MII, "));
1526 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1527 break;
1528
1529 case external:
1530 /* Not using the MII, disable it. */
1531 HMD(("external, disable MII, "));
1532 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1533 break;
1534 };
1535
1536 if (happy_meal_tcvr_reset(hp, tregs))
1537 return -EAGAIN;
1538
1539 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1540 HMD(("tx/rx reset, "));
1541 happy_meal_tx_reset(hp, bregs);
1542 happy_meal_rx_reset(hp, bregs);
1543
1544 /* Set jam size and inter-packet gaps to reasonable defaults. */
1545 HMD(("jsize/ipg1/ipg2, "));
1546 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1547 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1548 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1549
1550 /* Load up the MAC address and random seed. */
1551 HMD(("rseed/macaddr, "));
1552
1553 /* The docs recommend to use the 10LSB of our MAC here. */
1554 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1555
1556 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1557 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1558 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1559
1560 HMD(("htable, "));
1561 if ((hp->dev->flags & IFF_ALLMULTI) ||
1562 (hp->dev->mc_count > 64)) {
1563 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1564 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1565 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1566 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1567 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1568 u16 hash_table[4];
1569 struct dev_mc_list *dmi = hp->dev->mc_list;
1570 char *addrs;
1571 int i, j, bit, byte;
1572 u32 crc, poly = CRC_POLYNOMIAL_LE;
1573
1574 for (i = 0; i < 4; i++)
1575 hash_table[i] = 0;
1576
1577 for (i = 0; i < hp->dev->mc_count; i++) {
1578 addrs = dmi->dmi_addr;
1579 dmi = dmi->next;
1580
1581 if (!(*addrs & 1))
1582 continue;
1583
1584 crc = 0xffffffffU;
1585 for (byte = 0; byte < 6; byte++) {
1586 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
1587 int test;
1588
1589 test = ((bit ^ crc) & 0x01);
1590 crc >>= 1;
1591 if (test)
1592 crc = crc ^ poly;
1593 }
1594 }
1595 crc >>= 26;
1596 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1597 }
1598 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1599 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1600 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1601 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1602 } else {
1603 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1604 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1605 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1606 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1607 }
1608
1609 /* Set the RX and TX ring ptrs. */
1610 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1611 (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1612 (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1613 hme_write32(hp, erxregs + ERX_RING,
1614 (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1615 hme_write32(hp, etxregs + ETX_RING,
1616 (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1617
1618 /* Set the supported burst sizes. */
1619 HMD(("happy_meal_init: old[%08x] bursts<",
1620 hme_read32(hp, gregs + GREG_CFG)));
1621
1622 #ifndef __sparc__
1623 /* It is always PCI and can handle 64byte bursts. */
1624 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1625 #else
1626 if ((hp->happy_bursts & DMA_BURST64) &&
1627 ((hp->happy_flags & HFLAG_PCI) != 0
1628 #ifdef CONFIG_SBUS
1629 || sbus_can_burst64(hp->happy_dev)
1630 #endif
1631 || 0)) {
1632 u32 gcfg = GREG_CFG_BURST64;
1633
1634 /* I have no idea if I should set the extended
1635 * transfer mode bit for Cheerio, so for now I
1636 * do not. -DaveM
1637 */
1638 #ifdef CONFIG_SBUS
1639 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1640 sbus_can_dma_64bit(hp->happy_dev)) {
1641 sbus_set_sbus64(hp->happy_dev,
1642 hp->happy_bursts);
1643 gcfg |= GREG_CFG_64BIT;
1644 }
1645 #endif
1646
1647 HMD(("64>"));
1648 hme_write32(hp, gregs + GREG_CFG, gcfg);
1649 } else if (hp->happy_bursts & DMA_BURST32) {
1650 HMD(("32>"));
1651 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1652 } else if (hp->happy_bursts & DMA_BURST16) {
1653 HMD(("16>"));
1654 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1655 } else {
1656 HMD(("XXX>"));
1657 hme_write32(hp, gregs + GREG_CFG, 0);
1658 }
1659 #endif /* __sparc__ */
1660
1661 /* Turn off interrupts we do not want to hear. */
1662 HMD((", enable global interrupts, "));
1663 hme_write32(hp, gregs + GREG_IMASK,
1664 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1665 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1666
1667 /* Set the transmit ring buffer size. */
1668 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1669 hme_read32(hp, etxregs + ETX_RSIZE)));
1670 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1671
1672 /* Enable transmitter DVMA. */
1673 HMD(("tx dma enable old[%08x], ",
1674 hme_read32(hp, etxregs + ETX_CFG)));
1675 hme_write32(hp, etxregs + ETX_CFG,
1676 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1677
1678 /* This chip really rots, for the receiver sometimes when you
1679 * write to it's control registers not all the bits get there
1680 * properly. I cannot think of a sane way to provide complete
1681 * coverage for this hardware bug yet.
1682 */
1683 HMD(("erx regs bug old[%08x]\n",
1684 hme_read32(hp, erxregs + ERX_CFG)));
1685 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1686 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1687 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1688 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1689 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1690 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1691 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1692 /* XXX Should return failure here... */
1693 }
1694
1695 /* Enable Big Mac hash table filter. */
1696 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1697 hme_read32(hp, bregs + BMAC_RXCFG)));
1698 rxcfg = BIGMAC_RXCFG_HENABLE;
1699 if (hp->dev->flags & IFF_PROMISC)
1700 rxcfg |= BIGMAC_RXCFG_PMISC;
1701 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1702
1703 /* Let the bits settle in the chip. */
1704 udelay(10);
1705
1706 /* Ok, configure the Big Mac transmitter. */
1707 HMD(("BIGMAC init, "));
1708 regtmp = 0;
1709 if (hp->happy_flags & HFLAG_FULL)
1710 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1711 hme_write32(hp, bregs + BMAC_TXCFG, regtmp | BIGMAC_TXCFG_DGIVEUP);
1712
1713 /* Enable the output drivers no matter what. */
1714 regtmp = BIGMAC_XCFG_ODENABLE;
1715
1716 /* If card can do lance mode, enable it. */
1717 if (hp->happy_flags & HFLAG_LANCE)
1718 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1719
1720 /* Disable the MII buffers if using external transceiver. */
1721 if (hp->tcvr_type == external)
1722 regtmp |= BIGMAC_XCFG_MIIDISAB;
1723
1724 HMD(("XIF config old[%08x], ",
1725 hme_read32(hp, bregs + BMAC_XIFCFG)));
1726 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1727
1728 /* Start things up. */
1729 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1730 hme_read32(hp, bregs + BMAC_TXCFG),
1731 hme_read32(hp, bregs + BMAC_RXCFG)));
1732 hme_write32(hp, bregs + BMAC_TXCFG,
1733 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1734 hme_write32(hp, bregs + BMAC_RXCFG,
1735 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1736
1737 /* Get the autonegotiation started, and the watch timer ticking. */
1738 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1739
1740 /* Success. */
1741 return 0;
1742 }
1743
1744 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1745 {
1746 unsigned long tregs = hp->tcvregs;
1747 unsigned long bregs = hp->bigmacregs;
1748 unsigned long gregs = hp->gregs;
1749
1750 happy_meal_stop(hp, gregs);
1751 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1752 if (hp->happy_flags & HFLAG_FENABLE)
1753 hme_write32(hp, tregs + TCVR_CFG,
1754 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1755 else
1756 hme_write32(hp, tregs + TCVR_CFG,
1757 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1758 happy_meal_transceiver_check(hp, tregs);
1759 switch(hp->tcvr_type) {
1760 case none:
1761 return;
1762 case internal:
1763 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1764 break;
1765 case external:
1766 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1767 break;
1768 };
1769 if (happy_meal_tcvr_reset(hp, tregs))
1770 return;
1771
1772 /* Latch PHY registers as of now. */
1773 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, DP83840_BMSR);
1774 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, DP83840_ADVERTISE);
1775
1776 /* Advertise everything we can support. */
1777 if (hp->sw_bmsr & BMSR_10HALF)
1778 hp->sw_advertise |= (ADVERTISE_10HALF);
1779 else
1780 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1781
1782 if (hp->sw_bmsr & BMSR_10FULL)
1783 hp->sw_advertise |= (ADVERTISE_10FULL);
1784 else
1785 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1786 if (hp->sw_bmsr & BMSR_100HALF)
1787 hp->sw_advertise |= (ADVERTISE_100HALF);
1788 else
1789 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1790 if (hp->sw_bmsr & BMSR_100FULL)
1791 hp->sw_advertise |= (ADVERTISE_100FULL);
1792 else
1793 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1794
1795 /* Update the PHY advertisement register. */
1796 happy_meal_tcvr_write(hp, tregs, DP83840_ADVERTISE, hp->sw_advertise);
1797 }
1798
1799 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1800 * the hardware, so we cannot re-read it and get a correct value.
1801 */
1802 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1803 {
1804 int reset = 0;
1805
1806 /* Only print messages for non-counter related interrupts. */
1807 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1808 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1809 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1810 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1811 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1812 GREG_STAT_SLVPERR))
1813 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1814 hp->dev->name, status);
1815
1816 if (status & GREG_STAT_RFIFOVF) {
1817 /* Receive FIFO overflow is harmless and the hardware will take
1818 care of it, just some packets are lost. Who cares. */
1819 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1820 }
1821
1822 if (status & GREG_STAT_STSTERR) {
1823 /* BigMAC SQE link test failed. */
1824 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1825 reset = 1;
1826 }
1827
1828 if (status & GREG_STAT_TFIFO_UND) {
1829 /* Transmit FIFO underrun, again DMA error likely. */
1830 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1831 hp->dev->name);
1832 reset = 1;
1833 }
1834
1835 if (status & GREG_STAT_MAXPKTERR) {
1836 /* Driver error, tried to transmit something larger
1837 * than ethernet max mtu.
1838 */
1839 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1840 reset = 1;
1841 }
1842
1843 if (status & GREG_STAT_NORXD) {
1844 /* This is harmless, it just means the system is
1845 * quite loaded and the incomming packet rate was
1846 * faster than the interrupt handler could keep up
1847 * with.
1848 */
1849 printk(KERN_INFO "%s: Happy Meal out of receive "
1850 "descriptors, packet dropped.\n",
1851 hp->dev->name);
1852 }
1853
1854 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1855 /* All sorts of DMA receive errors. */
1856 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1857 if (status & GREG_STAT_RXERR)
1858 printk("GenericError ");
1859 if (status & GREG_STAT_RXPERR)
1860 printk("ParityError ");
1861 if (status & GREG_STAT_RXTERR)
1862 printk("RxTagBotch ");
1863 printk("]\n");
1864 reset = 1;
1865 }
1866
1867 if (status & GREG_STAT_EOPERR) {
1868 /* Driver bug, didn't set EOP bit in tx descriptor given
1869 * to the happy meal.
1870 */
1871 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1872 hp->dev->name);
1873 reset = 1;
1874 }
1875
1876 if (status & GREG_STAT_MIFIRQ) {
1877 /* MIF signalled an interrupt, were we polling it? */
1878 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1879 }
1880
1881 if (status &
1882 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1883 /* All sorts of transmit DMA errors. */
1884 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1885 if (status & GREG_STAT_TXEACK)
1886 printk("GenericError ");
1887 if (status & GREG_STAT_TXLERR)
1888 printk("LateError ");
1889 if (status & GREG_STAT_TXPERR)
1890 printk("ParityErro ");
1891 if (status & GREG_STAT_TXTERR)
1892 printk("TagBotch ");
1893 printk("]\n");
1894 reset = 1;
1895 }
1896
1897 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1898 /* Bus or parity error when cpu accessed happy meal registers
1899 * or it's internal FIFO's. Should never see this.
1900 */
1901 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1902 hp->dev->name,
1903 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1904 reset = 1;
1905 }
1906
1907 if (reset) {
1908 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1909 happy_meal_init(hp, 1);
1910 return 1;
1911 }
1912 return 0;
1913 }
1914
1915 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1916 {
1917 unsigned long tregs = hp->tcvregs;
1918
1919 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1920 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, DP83840_BMCR);
1921 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, DP83840_LPA);
1922
1923 /* Use the fastest transmission protocol possible. */
1924 if (hp->sw_lpa & LPA_100FULL) {
1925 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1926 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1927 } else if (hp->sw_lpa & LPA_100HALF) {
1928 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1929 hp->sw_bmcr |= BMCR_SPEED100;
1930 } else if (hp->sw_lpa & LPA_10FULL) {
1931 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1932 hp->sw_bmcr |= BMCR_FULLDPLX;
1933 } else {
1934 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1935 }
1936 happy_meal_tcvr_write(hp, tregs, DP83840_BMCR, hp->sw_bmcr);
1937
1938 /* Finally stop polling and shut up the MIF. */
1939 happy_meal_poll_stop(hp, tregs);
1940 }
1941
1942 #ifdef TXDEBUG
1943 #define TXD(x) printk x
1944 #else
1945 #define TXD(x)
1946 #endif
1947
1948 static void happy_meal_tx(struct happy_meal *hp)
1949 {
1950 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1951 struct happy_meal_txd *this;
1952 struct net_device *dev = hp->dev;
1953 int elem;
1954
1955 spin_lock(&hp->happy_lock);
1956
1957 elem = hp->tx_old;
1958 TXD(("TX<"));
1959 while (elem != hp->tx_new) {
1960 struct sk_buff *skb;
1961 u32 flags, dma_addr;
1962
1963 TXD(("[%d]", elem));
1964 this = &txbase[elem];
1965 flags = hme_read_desc32(hp, &this->tx_flags);
1966 if (flags & TXFLAG_OWN)
1967 break;
1968 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1969 skb = hp->tx_skbs[elem];
1970 hme_dma_unmap(hp, dma_addr, skb->len, DMA_TODEVICE);
1971 hp->tx_skbs[elem] = NULL;
1972 hp->net_stats.tx_bytes += skb->len;
1973
1974 dev_kfree_skb_irq(skb);
1975
1976 hp->net_stats.tx_packets++;
1977 elem = NEXT_TX(elem);
1978 }
1979 hp->tx_old = elem;
1980 TXD((">"));
1981
1982 if (netif_queue_stopped(dev) &&
1983 TX_BUFFS_AVAIL(hp) > 0)
1984 netif_wake_queue(dev);
1985
1986 spin_unlock(&hp->happy_lock);
1987 }
1988
1989 #ifdef RXDEBUG
1990 #define RXD(x) printk x
1991 #else
1992 #define RXD(x)
1993 #endif
1994
1995 /* Originally I used to handle the allocation failure by just giving back just
1996 * that one ring buffer to the happy meal. Problem is that usually when that
1997 * condition is triggered, the happy meal expects you to do something reasonable
1998 * with all of the packets it has DMA'd in. So now I just drop the entire
1999 * ring when we cannot get a new skb and give them all back to the happy meal,
2000 * maybe things will be "happier" now.
2001 */
2002 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
2003 {
2004 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2005 struct happy_meal_rxd *this;
2006 int elem = hp->rx_new, drops = 0;
2007 u32 flags;
2008
2009 RXD(("RX<"));
2010 this = &rxbase[elem];
2011 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2012 struct sk_buff *skb;
2013 int len = flags >> 16;
2014 u16 csum = flags & RXFLAG_CSUM;
2015 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2016
2017 RXD(("[%d ", elem));
2018
2019 /* Check for errors. */
2020 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2021 RXD(("ERR(%08x)]", flags));
2022 hp->net_stats.rx_errors++;
2023 if (len < ETH_ZLEN)
2024 hp->net_stats.rx_length_errors++;
2025 if (len & (RXFLAG_OVERFLOW >> 16)) {
2026 hp->net_stats.rx_over_errors++;
2027 hp->net_stats.rx_fifo_errors++;
2028 }
2029
2030 /* Return it to the Happy meal. */
2031 drop_it:
2032 hp->net_stats.rx_dropped++;
2033 hme_write_rxd(hp, this,
2034 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2035 dma_addr);
2036 goto next;
2037 }
2038 skb = hp->rx_skbs[elem];
2039 if (len > RX_COPY_THRESHOLD) {
2040 struct sk_buff *new_skb;
2041
2042 /* Now refill the entry, if we can. */
2043 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2044 if (new_skb == NULL) {
2045 drops++;
2046 goto drop_it;
2047 }
2048 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2049 hp->rx_skbs[elem] = new_skb;
2050 new_skb->dev = dev;
2051 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2052 hme_write_rxd(hp, this,
2053 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2054 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2055 skb_reserve(new_skb, RX_OFFSET);
2056
2057 /* Trim the original skb for the netif. */
2058 skb_trim(skb, len);
2059 } else {
2060 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2061
2062 if (copy_skb == NULL) {
2063 drops++;
2064 goto drop_it;
2065 }
2066
2067 copy_skb->dev = dev;
2068 skb_reserve(copy_skb, 2);
2069 skb_put(copy_skb, len);
2070 hme_dma_sync(hp, dma_addr, len, DMA_FROMDEVICE);
2071 memcpy(copy_skb->data, skb->data, len);
2072
2073 /* Reuse original ring buffer. */
2074 hme_write_rxd(hp, this,
2075 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2076 dma_addr);
2077
2078 skb = copy_skb;
2079 }
2080
2081 /* This card is _fucking_ hot... */
2082 if (!(csum ^ 0xffff))
2083 skb->ip_summed = CHECKSUM_UNNECESSARY;
2084 else
2085 skb->ip_summed = CHECKSUM_NONE;
2086
2087 RXD(("len=%d csum=%4x]", len, csum));
2088 skb->protocol = eth_type_trans(skb, dev);
2089 netif_rx(skb);
2090
2091 hp->net_stats.rx_packets++;
2092 hp->net_stats.rx_bytes += len;
2093 next:
2094 elem = NEXT_RX(elem);
2095 this = &rxbase[elem];
2096 }
2097 hp->rx_new = elem;
2098 if (drops)
2099 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2100 RXD((">"));
2101 }
2102
2103 static void happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2104 {
2105 struct net_device *dev = (struct net_device *) dev_id;
2106 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2107 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2108
2109 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2110
2111 if (happy_status & GREG_STAT_ERRORS) {
2112 HMD(("ERRORS "));
2113 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2114 return;
2115 }
2116
2117 if (happy_status & GREG_STAT_MIFIRQ) {
2118 HMD(("MIFIRQ "));
2119 happy_meal_mif_interrupt(hp);
2120 }
2121
2122 if (happy_status & GREG_STAT_TXALL) {
2123 HMD(("TXALL "));
2124 happy_meal_tx(hp);
2125 }
2126
2127 if (happy_status & GREG_STAT_RXTOHOST) {
2128 HMD(("RXTOHOST "));
2129 happy_meal_rx(hp, dev);
2130 }
2131
2132 HMD(("done\n"));
2133 }
2134
2135 #ifdef CONFIG_SBUS
2136 static void quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2137 {
2138 struct quattro *qp = (struct quattro *) cookie;
2139 int i;
2140
2141 for (i = 0; i < 4; i++) {
2142 struct net_device *dev = qp->happy_meals[i];
2143 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2144 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2145
2146 HMD(("quattro_interrupt: status=%08x ", happy_status));
2147
2148 if (!(happy_status & (GREG_STAT_ERRORS |
2149 GREG_STAT_MIFIRQ |
2150 GREG_STAT_TXALL |
2151 GREG_STAT_RXTOHOST)))
2152 continue;
2153
2154 if (happy_status & GREG_STAT_ERRORS) {
2155 HMD(("ERRORS "));
2156 if (happy_meal_is_not_so_happy(hp, happy_status))
2157 break;
2158 }
2159
2160 if (happy_status & GREG_STAT_MIFIRQ) {
2161 HMD(("MIFIRQ "));
2162 happy_meal_mif_interrupt(hp);
2163 }
2164
2165 if (happy_status & GREG_STAT_TXALL) {
2166 HMD(("TXALL "));
2167 happy_meal_tx(hp);
2168 }
2169
2170 if (happy_status & GREG_STAT_RXTOHOST) {
2171 HMD(("RXTOHOST "));
2172 happy_meal_rx(hp, dev);
2173 }
2174 }
2175 HMD(("done\n"));
2176 }
2177 #endif
2178
2179 static int happy_meal_open(struct net_device *dev)
2180 {
2181 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2182 int res;
2183
2184 HMD(("happy_meal_open: "));
2185
2186 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2187 * into a single source which we register handling at probe time.
2188 */
2189 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2190 if (request_irq(dev->irq, &happy_meal_interrupt,
2191 SA_SHIRQ, "HAPPY MEAL", (void *)dev)) {
2192 HMD(("EAGAIN\n"));
2193 #ifdef __sparc__
2194 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %s to go.\n",
2195 __irq_itoa(dev->irq));
2196 #else
2197 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2198 dev->irq);
2199 #endif
2200
2201 return -EAGAIN;
2202 }
2203 }
2204
2205 HMD(("to happy_meal_init\n"));
2206 res = happy_meal_init(hp, 0);
2207 if (!res) {
2208 MOD_INC_USE_COUNT;
2209 }
2210 return res;
2211 }
2212
2213 static int happy_meal_close(struct net_device *dev)
2214 {
2215 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2216
2217 happy_meal_stop(hp, hp->gregs);
2218 happy_meal_clean_rings(hp);
2219
2220 /* If auto-negotiation timer is running, kill it. */
2221 del_timer(&hp->happy_timer);
2222
2223 /* On Quattro QFE cards, all hme interrupts are concentrated
2224 * into a single source which we register handling at probe
2225 * time and never unregister.
2226 */
2227 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2228 free_irq(dev->irq, (void *)dev);
2229
2230 MOD_DEC_USE_COUNT;
2231 return 0;
2232 }
2233
2234 #ifdef SXDEBUG
2235 #define SXD(x) printk x
2236 #else
2237 #define SXD(x)
2238 #endif
2239
2240 #ifdef CONFIG_SBUS
2241 static void happy_meal_tx_timeout(struct net_device *dev)
2242 {
2243 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2244
2245 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2246 tx_dump_log();
2247 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2248 hme_read32(hp, hp->gregs + GREG_STAT),
2249 hme_read32(hp, hp->etxregs + ETX_CFG),
2250 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2251 happy_meal_init(hp, 0);
2252 netif_wake_queue(dev);
2253 }
2254 #endif
2255
2256 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2257 {
2258 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2259 int len, entry;
2260 u32 mapping;
2261
2262 len = skb->len;
2263 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2264
2265 spin_lock_irq(&hp->happy_lock);
2266
2267 entry = hp->tx_new;
2268 SXD(("SX<l[%d]e[%d]>", len, entry));
2269 hp->tx_skbs[entry] = skb;
2270 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2271 (TXFLAG_OWN | TXFLAG_SOP | TXFLAG_EOP | (len & TXFLAG_SIZE)),
2272 mapping);
2273 hp->tx_new = NEXT_TX(entry);
2274 if (TX_BUFFS_AVAIL(hp) <= 0)
2275 netif_stop_queue(dev);
2276
2277 /* Get it going. */
2278 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2279
2280 spin_unlock_irq(&hp->happy_lock);
2281
2282 dev->trans_start = jiffies;
2283
2284 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2285 return 0;
2286 }
2287
2288 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2289 {
2290 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2291
2292 happy_meal_get_counters(hp, hp->bigmacregs);
2293 return &hp->net_stats;
2294 }
2295
2296 static void happy_meal_set_multicast(struct net_device *dev)
2297 {
2298 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2299 unsigned long bregs = hp->bigmacregs;
2300 struct dev_mc_list *dmi = dev->mc_list;
2301 char *addrs;
2302 int i, j, bit, byte;
2303 u32 crc, poly = CRC_POLYNOMIAL_LE;
2304
2305 /* Lock out others. */
2306 netif_stop_queue(dev);
2307
2308 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2309 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2310 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2311 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2312 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2313 } else if (dev->flags & IFF_PROMISC) {
2314 hme_write32(hp, bregs + BMAC_RXCFG,
2315 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2316 } else {
2317 u16 hash_table[4];
2318
2319 for (i = 0; i < 4; i++)
2320 hash_table[i] = 0;
2321
2322 for (i = 0; i < dev->mc_count; i++) {
2323 addrs = dmi->dmi_addr;
2324 dmi = dmi->next;
2325
2326 if (!(*addrs & 1))
2327 continue;
2328
2329 crc = 0xffffffffU;
2330 for (byte = 0; byte < 6; byte++) {
2331 for (bit = *addrs++, j = 0; j < 8; j++, bit >>= 1) {
2332 int test;
2333
2334 test = ((bit ^ crc) & 0x01);
2335 crc >>= 1;
2336 if (test)
2337 crc = crc ^ poly;
2338 }
2339 }
2340 crc >>= 26;
2341 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2342 }
2343 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2344 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2345 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2346 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2347 }
2348
2349 /* Let us get going again. */
2350 netif_wake_queue(dev);
2351 }
2352
2353 /* Ethtool support... */
2354 static int happy_meal_ioctl(struct net_device *dev,
2355 struct ifreq *rq, int cmd)
2356 {
2357 struct happy_meal *hp = (struct happy_meal *) dev->priv;
2358 struct ethtool_cmd *ep_user = (struct ethtool_cmd *) rq->ifr_data;
2359 struct ethtool_cmd ecmd;
2360
2361 if (cmd != SIOCETHTOOL)
2362 return -EOPNOTSUPP;
2363 if (copy_from_user(&ecmd, ep_user, sizeof(ecmd)))
2364 return -EFAULT;
2365
2366 if (ecmd.cmd == SPARC_ETH_GSET) {
2367 ecmd.supported =
2368 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2369 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2370 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2371
2372 /* XXX hardcoded stuff for now */
2373 ecmd.port = PORT_TP; /* XXX no MII support */
2374 ecmd.transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2375 ecmd.phy_address = 0; /* XXX fixed PHYAD */
2376
2377 /* Record PHY settings. */
2378 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, DP83840_BMCR);
2379 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, DP83840_LPA);
2380 if (hp->sw_bmcr & BMCR_ANENABLE) {
2381 ecmd.autoneg = AUTONEG_ENABLE;
2382 ecmd.speed =
2383 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2384 SPEED_100 : SPEED_10;
2385 if (ecmd.speed == SPEED_100)
2386 ecmd.duplex =
2387 (hp->sw_lpa & (LPA_100FULL)) ?
2388 DUPLEX_FULL : DUPLEX_HALF;
2389 else
2390 ecmd.duplex =
2391 (hp->sw_lpa & (LPA_10FULL)) ?
2392 DUPLEX_FULL : DUPLEX_HALF;
2393 } else {
2394 ecmd.autoneg = AUTONEG_DISABLE;
2395 ecmd.speed =
2396 (hp->sw_bmcr & BMCR_SPEED100) ?
2397 SPEED_100 : SPEED_10;
2398 ecmd.duplex =
2399 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2400 DUPLEX_FULL : DUPLEX_HALF;
2401 }
2402 if (copy_to_user(ep_user, &ecmd, sizeof(ecmd)))
2403 return -EFAULT;
2404 return 0;
2405 } else if (ecmd.cmd == SPARC_ETH_SSET) {
2406 if (!capable(CAP_NET_ADMIN))
2407 return -EPERM;
2408
2409 /* Verify the settings we care about. */
2410 if (ecmd.autoneg != AUTONEG_ENABLE &&
2411 ecmd.autoneg != AUTONEG_DISABLE)
2412 return -EINVAL;
2413 if (ecmd.autoneg == AUTONEG_DISABLE &&
2414 ((ecmd.speed != SPEED_100 &&
2415 ecmd.speed != SPEED_10) ||
2416 (ecmd.duplex != DUPLEX_HALF &&
2417 ecmd.duplex != DUPLEX_FULL)))
2418 return -EINVAL;
2419
2420 /* Ok, do it to it. */
2421 del_timer(&hp->happy_timer);
2422 happy_meal_begin_auto_negotiation(hp,
2423 hp->tcvregs,
2424 &ecmd);
2425
2426 return 0;
2427 } else
2428 return -EOPNOTSUPP;
2429 }
2430
2431 static int hme_version_printed = 0;
2432
2433 #ifdef CONFIG_SBUS
2434 void __init quattro_get_ranges(struct quattro *qp)
2435 {
2436 struct sbus_dev *sdev = qp->quattro_dev;
2437 int err;
2438
2439 err = prom_getproperty(sdev->prom_node,
2440 "ranges",
2441 (char *)&qp->ranges[0],
2442 sizeof(qp->ranges));
2443 if (err == 0 || err == -1) {
2444 qp->nranges = 0;
2445 return;
2446 }
2447 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2448 }
2449
2450 static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2451 {
2452 struct sbus_dev *sdev = hp->happy_dev;
2453 int rng;
2454
2455 for (rng = 0; rng < qp->nranges; rng++) {
2456 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2457 int reg;
2458
2459 for (reg = 0; reg < 5; reg++) {
2460 if (sdev->reg_addrs[reg].which_io ==
2461 rngp->ot_child_space)
2462 break;
2463 }
2464 if (reg == 5)
2465 continue;
2466
2467 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2468 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2469 }
2470 }
2471
2472 /* Given a happy meal sbus device, find it's quattro parent.
2473 * If none exist, allocate and return a new one.
2474 *
2475 * Return NULL on failure.
2476 */
2477 static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2478 {
2479 struct sbus_bus *sbus;
2480 struct sbus_dev *sdev;
2481 struct quattro *qp;
2482
2483 if (qfe_sbus_list == NULL)
2484 goto found;
2485
2486 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2487 for (sdev = qp->quattro_dev;
2488 sdev != NULL;
2489 sdev = sdev->next) {
2490 if (sdev == goal_sdev)
2491 return qp;
2492 }
2493 }
2494 for_each_sbus(sbus) {
2495 for_each_sbusdev(sdev, sbus) {
2496 if (sdev->child != NULL) {
2497 struct sbus_dev *p;
2498
2499 for (p = sdev->child; p != NULL; p = p->next)
2500 if (p == goal_sdev)
2501 goto found;
2502 }
2503 }
2504 }
2505
2506 /* Cannot find quattro parent, fail. */
2507 return NULL;
2508
2509 found:
2510 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2511 if (qp != NULL) {
2512 int i;
2513
2514 for (i = 0; i < 4; i++)
2515 qp->happy_meals[i] = NULL;
2516
2517 qp->quattro_dev = goal_sdev;
2518 qp->next = qfe_sbus_list;
2519 qfe_sbus_list = qp;
2520 quattro_get_ranges(qp);
2521 }
2522 return qp;
2523 }
2524
2525 /* After all quattro cards have been probed, we call these functions
2526 * to register the IRQ handlers.
2527 */
2528 static void __init quattro_sbus_register_irqs(void)
2529 {
2530 struct quattro *qp;
2531
2532 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2533 struct sbus_dev *sdev = qp->quattro_dev;
2534 int err;
2535
2536 err = request_irq(sdev->irqs[0],
2537 quattro_sbus_interrupt,
2538 SA_SHIRQ, "Quattro",
2539 qp);
2540 if (err != 0) {
2541 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2542 panic("QFE request irq");
2543 }
2544 }
2545 }
2546 #endif /* CONFIG_SBUS */
2547
2548 #ifdef CONFIG_PCI
2549 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2550 {
2551 struct pci_dev *bdev = pdev->bus->self;
2552 struct quattro *qp;
2553
2554 if (!bdev) return NULL;
2555 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2556 struct pci_dev *qpdev = qp->quattro_dev;
2557
2558 if (qpdev == bdev)
2559 return qp;
2560 }
2561 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2562 if (qp != NULL) {
2563 int i;
2564
2565 for (i = 0; i < 4; i++)
2566 qp->happy_meals[i] = NULL;
2567
2568 qp->quattro_dev = bdev;
2569 qp->next = qfe_pci_list;
2570 qfe_pci_list = qp;
2571
2572 /* No range tricks necessary on PCI. */
2573 qp->nranges = 0;
2574 }
2575 return qp;
2576 }
2577 #endif /* CONFIG_PCI */
2578
2579 #ifdef CONFIG_SBUS
2580 static int __init happy_meal_sbus_init(struct net_device *dev,
2581 struct sbus_dev *sdev,
2582 int is_qfe)
2583 {
2584 struct quattro *qp = NULL;
2585 struct happy_meal *hp;
2586 int i, qfe_slot = -1;
2587
2588 if (is_qfe) {
2589 qp = quattro_sbus_find(sdev);
2590 if (qp == NULL)
2591 return -ENODEV;
2592 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2593 if (qp->happy_meals[qfe_slot] == NULL)
2594 break;
2595 if (qfe_slot == 4)
2596 return -ENODEV;
2597 }
2598 if (dev == NULL) {
2599 dev = init_etherdev(0, sizeof(struct happy_meal));
2600 } else {
2601 dev->priv = kmalloc(sizeof(struct happy_meal), GFP_KERNEL);
2602 if (dev->priv == NULL)
2603 return -ENOMEM;
2604 }
2605 if (hme_version_printed++ == 0)
2606 printk(KERN_INFO "%s", version);
2607
2608 if (qfe_slot != -1)
2609 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2610 dev->name, qfe_slot);
2611 else
2612 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2613 dev->name);
2614
2615 /* If user did not specify a MAC address specifically, use
2616 * the Quattro local-mac-address property...
2617 */
2618 for (i = 0; i < 6; i++) {
2619 if (macaddr[i] != 0)
2620 break;
2621 }
2622 if (i < 6) { /* a mac address was given */
2623 for (i = 0; i < 6; i++)
2624 dev->dev_addr[i] = macaddr[i];
2625 } else if (qfe_slot != -1 &&
2626 prom_getproplen(sdev->prom_node,
2627 "local-mac-address") == 6) {
2628 prom_getproperty(sdev->prom_node, "local-mac-address",
2629 dev->dev_addr, 6);
2630 } else {
2631 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2632 }
2633
2634 for (i = 0; i < 6; i++)
2635 printk("%2.2x%c",
2636 dev->dev_addr[i], i == 5 ? ' ' : ':');
2637 printk("\n");
2638
2639 hp = (struct happy_meal *) dev->priv;
2640 memset(hp, 0, sizeof(*hp));
2641
2642 hp->happy_dev = sdev;
2643
2644 spin_lock_init(&hp->happy_lock);
2645
2646 if (sdev->num_registers != 5) {
2647 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2648 sdev->num_registers);
2649 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2650 return -ENODEV;
2651 }
2652
2653 if (qp != NULL) {
2654 hp->qfe_parent = qp;
2655 hp->qfe_ent = qfe_slot;
2656 qp->happy_meals[qfe_slot] = dev;
2657 quattro_apply_ranges(qp, hp);
2658 }
2659
2660 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2661 GREG_REG_SIZE, "HME Global Regs");
2662 if (!hp->gregs) {
2663 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2664 return -ENODEV;
2665 }
2666
2667 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2668 ETX_REG_SIZE, "HME TX Regs");
2669 if (!hp->etxregs) {
2670 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2671 return -ENODEV;
2672 }
2673
2674 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2675 ERX_REG_SIZE, "HME RX Regs");
2676 if (!hp->erxregs) {
2677 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2678 return -ENODEV;
2679 }
2680
2681 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2682 BMAC_REG_SIZE, "HME BIGMAC Regs");
2683 if (!hp->bigmacregs) {
2684 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2685 return -ENODEV;
2686 }
2687
2688 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2689 TCVR_REG_SIZE, "HME Tranceiver Regs");
2690 if (!hp->tcvregs) {
2691 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2692 return -ENODEV;
2693 }
2694
2695 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2696 if (hp->hm_revision == 0xff)
2697 hp->hm_revision = 0xa0;
2698
2699 /* Now enable the feature flags we can. */
2700 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2701 hp->happy_flags = HFLAG_20_21;
2702 else if (hp->hm_revision != 0xa0)
2703 hp->happy_flags = HFLAG_NOT_A0;
2704
2705 if (qp != NULL)
2706 hp->happy_flags |= HFLAG_QUATTRO;
2707
2708 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2709 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2710 "burst-sizes", 0x00);
2711
2712 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2713 PAGE_SIZE,
2714 &hp->hblock_dvma);
2715
2716 /* Force check of the link first time we are brought up. */
2717 hp->linkcheck = 0;
2718
2719 /* Force timer state to 'asleep' with count of zero. */
2720 hp->timer_state = asleep;
2721 hp->timer_ticks = 0;
2722
2723 init_timer(&hp->happy_timer);
2724
2725 hp->dev = dev;
2726 dev->open = &happy_meal_open;
2727 dev->stop = &happy_meal_close;
2728 dev->hard_start_xmit = &happy_meal_start_xmit;
2729 dev->get_stats = &happy_meal_get_stats;
2730 dev->set_multicast_list = &happy_meal_set_multicast;
2731 dev->tx_timeout = &happy_meal_tx_timeout;
2732 dev->watchdog_timeo = 5*HZ;
2733 dev->do_ioctl = &happy_meal_ioctl;
2734
2735 dev->irq = sdev->irqs[0];
2736
2737 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2738 /* Hook up PCI register/dma accessors. */
2739 hp->read_desc32 = sbus_hme_read_desc32;
2740 hp->write_txd = sbus_hme_write_txd;
2741 hp->write_rxd = sbus_hme_write_rxd;
2742 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2743 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2744 hp->dma_sync = (void (*)(void *, u32, long, int))sbus_dma_sync_single;
2745 hp->read32 = sbus_hme_read32;
2746 hp->write32 = sbus_hme_write32;
2747 #endif
2748
2749 /* Grrr, Happy Meal comes up by default not advertising
2750 * full duplex 100baseT capabilities, fix this.
2751 */
2752 happy_meal_set_initial_advertisement(hp);
2753
2754 ether_setup(dev);
2755
2756 /* We are home free at this point, link us in to the happy
2757 * device list.
2758 */
2759 dev->ifindex = dev_new_index();
2760 hp->next_module = root_happy_dev;
2761 root_happy_dev = hp;
2762
2763 return 0;
2764 }
2765 #endif
2766
2767 #ifdef CONFIG_PCI
2768 static int __init happy_meal_pci_init(struct net_device *dev, struct pci_dev *pdev)
2769 {
2770 struct quattro *qp = NULL;
2771 #ifdef __sparc__
2772 struct pcidev_cookie *pcp;
2773 int node;
2774 #endif
2775 struct happy_meal *hp;
2776 unsigned long hpreg_base;
2777 int i, qfe_slot = -1;
2778 char prom_name[64];
2779
2780 /* Now make sure pci_dev cookie is there. */
2781 #ifdef __sparc__
2782 pcp = pdev->sysdata;
2783 if (pcp == NULL || pcp->prom_node == -1) {
2784 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
2785 return -ENODEV;
2786 }
2787 node = pcp->prom_node;
2788
2789 prom_getstring(node, "name", prom_name, sizeof(prom_name));
2790 #else
2791 #warning This needs to be corrected... -DaveM
2792 strcpy(prom_name, "qfe");
2793 #endif
2794
2795 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2796 qp = quattro_pci_find(pdev);
2797 if (qp == NULL)
2798 return -ENODEV;
2799 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2800 if (qp->happy_meals[qfe_slot] == NULL)
2801 break;
2802 if (qfe_slot == 4)
2803 return -ENODEV;
2804 }
2805 if (dev == NULL) {
2806 dev = init_etherdev(0, sizeof(struct happy_meal));
2807 } else {
2808 dev->priv = kmalloc(sizeof(struct happy_meal), GFP_KERNEL);
2809 if (dev->priv == NULL)
2810 return -ENOMEM;
2811 }
2812 if (hme_version_printed++ == 0)
2813 printk(KERN_INFO "%s", version);
2814
2815 if (!qfe_slot) {
2816 struct pci_dev *qpdev = qp->quattro_dev;
2817
2818 prom_name[0] = 0;
2819 if (!strncmp(dev->name, "eth", 3)) {
2820 int i = simple_strtoul(dev->name + 3, NULL, 10);
2821 sprintf(prom_name, "-%d", i + 3);
2822 }
2823 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
2824 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
2825 qpdev->device == PCI_DEVICE_ID_DEC_21153)
2826 printk("DEC 21153 PCI Bridge\n");
2827 else
2828 printk("unknown bridge %04x.%04x\n",
2829 qpdev->vendor, qpdev->device);
2830 }
2831 if (qfe_slot != -1)
2832 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
2833 dev->name, qfe_slot);
2834 else
2835 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
2836 dev->name);
2837
2838 dev->base_addr = (long) pdev;
2839
2840 hp = (struct happy_meal *)dev->priv;
2841 memset(hp, 0, sizeof(*hp));
2842
2843 hp->happy_dev = pdev;
2844
2845 spin_lock_init(&hp->happy_lock);
2846
2847 if (qp != NULL) {
2848 hp->qfe_parent = qp;
2849 hp->qfe_ent = qfe_slot;
2850 qp->happy_meals[qfe_slot] = dev;
2851 }
2852
2853 hpreg_base = pci_resource_start(pdev, 0);
2854 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2855 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
2856 return -ENODEV;
2857 }
2858 hpreg_base = (unsigned long) ioremap(hpreg_base, 0x8000);
2859
2860 for (i = 0; i < 6; i++) {
2861 if (macaddr[i] != 0)
2862 break;
2863 }
2864 if (i < 6) { /* a mac address was given */
2865 for (i = 0; i < 6; i++)
2866 dev->dev_addr[i] = macaddr[i];
2867 } else {
2868 #ifdef __sparc__
2869 if (qfe_slot != -1 &&
2870 prom_getproplen(node, "local-mac-address") == 6) {
2871 prom_getproperty(node, "local-mac-address",
2872 dev->dev_addr, 6);
2873 } else {
2874 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2875 }
2876 #else
2877 memset(dev->dev_addr, 0, 6);
2878 #endif
2879 }
2880
2881 for (i = 0; i < 6; i++)
2882 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
2883
2884 printk("\n");
2885
2886 /* Layout registers. */
2887 hp->gregs = (hpreg_base + 0x0000UL);
2888 hp->etxregs = (hpreg_base + 0x2000UL);
2889 hp->erxregs = (hpreg_base + 0x4000UL);
2890 hp->bigmacregs = (hpreg_base + 0x6000UL);
2891 hp->tcvregs = (hpreg_base + 0x7000UL);
2892
2893 #ifdef __sparc__
2894 hp->hm_revision = prom_getintdefault(node, "hm-rev", 0xff);
2895 if (hp->hm_revision == 0xff)
2896 hp->hm_revision = 0xa0;
2897 #else
2898 /* works with this on non-sparc hosts */
2899 hp->hm_revision = 0x20;
2900 #endif
2901
2902 /* Now enable the feature flags we can. */
2903 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2904 hp->happy_flags = HFLAG_20_21;
2905 else if (hp->hm_revision != 0xa0)
2906 hp->happy_flags = HFLAG_NOT_A0;
2907
2908 if (qp != NULL)
2909 hp->happy_flags |= HFLAG_QUATTRO;
2910
2911 /* And of course, indicate this is PCI. */
2912 hp->happy_flags |= HFLAG_PCI;
2913
2914 #ifdef __sparc__
2915 /* Assume PCI happy meals can handle all burst sizes. */
2916 hp->happy_bursts = DMA_BURSTBITS;
2917 #endif
2918
2919 hp->happy_block = (struct hmeal_init_block *)
2920 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
2921
2922 if (!hp->happy_block) {
2923 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
2924 return -ENODEV;
2925 }
2926
2927 hp->linkcheck = 0;
2928 hp->timer_state = asleep;
2929 hp->timer_ticks = 0;
2930
2931 init_timer(&hp->happy_timer);
2932
2933 hp->dev = dev;
2934 dev->open = &happy_meal_open;
2935 dev->stop = &happy_meal_close;
2936 dev->hard_start_xmit = &happy_meal_start_xmit;
2937 dev->get_stats = &happy_meal_get_stats;
2938 dev->set_multicast_list = &happy_meal_set_multicast;
2939 dev->do_ioctl = &happy_meal_ioctl;
2940 dev->irq = pdev->irq;
2941 dev->dma = 0;
2942
2943 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2944 /* Hook up PCI register/dma accessors. */
2945 hp->read_desc32 = pci_hme_read_desc32;
2946 hp->write_txd = pci_hme_write_txd;
2947 hp->write_rxd = pci_hme_write_rxd;
2948 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
2949 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
2950 hp->dma_sync = (void (*)(void *, u32, long, int))pci_dma_sync_single;
2951 hp->read32 = pci_hme_read32;
2952 hp->write32 = pci_hme_write32;
2953 #endif
2954
2955 /* Grrr, Happy Meal comes up by default not advertising
2956 * full duplex 100baseT capabilities, fix this.
2957 */
2958 happy_meal_set_initial_advertisement(hp);
2959
2960 ether_setup(dev);
2961
2962 /* We are home free at this point, link us in to the happy
2963 * device list.
2964 */
2965 dev->ifindex = dev_new_index();
2966 hp->next_module = root_happy_dev;
2967 root_happy_dev = hp;
2968
2969 return 0;
2970 }
2971 #endif
2972
2973 #ifdef CONFIG_SBUS
2974 static int __init happy_meal_sbus_probe(struct net_device *dev)
2975 {
2976 struct sbus_bus *sbus;
2977 struct sbus_dev *sdev;
2978 int cards = 0;
2979
2980 for_each_sbus(sbus) {
2981 for_each_sbusdev(sdev, sbus) {
2982 char *name = sdev->prom_name;
2983
2984 if (cards)
2985 dev = NULL;
2986 if (!strcmp(name, "SUNW,hme")) {
2987 cards++;
2988 happy_meal_sbus_init(dev, sdev, 0);
2989 } else if (!strcmp(name, "qfe") ||
2990 !strcmp(name, "SUNW,qfe")) {
2991 cards++;
2992 happy_meal_sbus_init(dev, sdev, 1);
2993 }
2994 }
2995 }
2996 if (cards != 0)
2997 quattro_sbus_register_irqs();
2998 return cards;
2999 }
3000 #endif
3001
3002 #ifdef CONFIG_PCI
3003 static int __init happy_meal_pci_probe(struct net_device *dev)
3004 {
3005 struct pci_dev *pdev = NULL;
3006 int cards = 0;
3007
3008 while ((pdev = pci_find_device(PCI_VENDOR_ID_SUN,
3009 PCI_DEVICE_ID_SUN_HAPPYMEAL, pdev)) != NULL) {
3010 if (pci_enable_device(pdev))
3011 continue;
3012 if (cards)
3013 dev = NULL;
3014 cards++;
3015 happy_meal_pci_init(dev, pdev);
3016 }
3017 return cards;
3018 }
3019 #endif
3020
3021 static int __init happy_meal_probe(void)
3022 {
3023 struct net_device *dev = NULL;
3024 static int called = 0;
3025 int cards;
3026
3027 root_happy_dev = NULL;
3028
3029 if (called)
3030 return -ENODEV;
3031 called++;
3032
3033 cards = 0;
3034 #ifdef CONFIG_SBUS
3035 cards += happy_meal_sbus_probe(dev);
3036 if (cards != 0)
3037 dev = NULL;
3038 #endif
3039 #ifdef CONFIG_PCI
3040 cards += happy_meal_pci_probe(dev);
3041 #endif
3042 if (!cards)
3043 return -ENODEV;
3044 return 0;
3045 }
3046
3047
3048 static void __exit happy_meal_cleanup_module(void)
3049 {
3050 while (root_happy_dev) {
3051 struct happy_meal *hp = root_happy_dev;
3052 struct happy_meal *next = root_happy_dev->next_module;
3053
3054 #ifdef CONFIG_SBUS
3055 if (!(hp->happy_flags & HFLAG_PCI)) {
3056 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3057 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3058 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3059 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3060 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3061 sbus_free_consistent(hp->happy_dev,
3062 PAGE_SIZE,
3063 hp->happy_block,
3064 hp->hblock_dvma);
3065 }
3066 #endif
3067 #ifdef CONFIG_PCI
3068 if ((hp->happy_flags & HFLAG_PCI)) {
3069 pci_free_consistent(hp->happy_dev,
3070 PAGE_SIZE,
3071 hp->happy_block,
3072 hp->hblock_dvma);
3073 }
3074 #endif
3075 unregister_netdev(hp->dev);
3076 kfree(hp->dev);
3077 root_happy_dev = next;
3078 }
3079 }
3080
3081 module_init(happy_meal_probe);
3082 module_exit(happy_meal_cleanup_module);
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