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Linux 2.4.0-test10pre4
[davej-history.git] / drivers / sbus / char / bpp.c
blob4579404e310e5c70e867df408902c8397c583914
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/version.h>
16 #include <linux/fs.h>
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/smp_lock.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23 #include <linux/devfs_fs_kernel.h>
24
25 #include <asm/uaccess.h>
26 #include <asm/io.h>
27
28 #if defined(__i386__)
29 # include <asm/system.h>
30 # include <asm/segment.h>
31 #endif
32
33 #if defined(__sparc__)
34 # include <linux/init.h>
35 # include <linux/delay.h> /* udelay() */
36
37 # include <asm/oplib.h> /* OpenProm Library */
38 # include <asm/sbus.h>
39 #endif
40
41 #include <asm/bpp.h>
42
43 #define BPP_PROBE_CODE 0x55
44 #define BPP_DELAY 100
45
46 static const unsigned BPP_MAJOR = LP_MAJOR;
47 static const char* dev_name = "bpp";
48
49 /* When switching from compatibility to a mode where I can read, try
50 the following mode first. */
51
52 /* const unsigned char DEFAULT_ECP = 0x10; */
53 static const unsigned char DEFAULT_ECP = 0x30;
54 static const unsigned char DEFAULT_NIBBLE = 0x00;
55
56 /*
57 * These are 1284 time constraints, in units of jiffies.
58 */
59
60 static const unsigned long TIME_PSetup = 1;
61 static const unsigned long TIME_PResponse = 6;
62 static const unsigned long TIME_IDLE_LIMIT = 2000;
63
64 /*
65 * One instance per supported subdevice...
66 */
67 # define BPP_NO 3
68
69 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
70
71 struct inst {
72 unsigned present : 1; /* True if the hardware exists */
73 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
74 unsigned opened : 1; /* True if the device is opened already */
75 unsigned run_flag : 1; /* True if waiting for a repeate byte */
76
77 unsigned char direction; /* 0 --> out, 0x20 --> IN */
78 unsigned char pp_state; /* State of host controlled pins. */
79 enum IEEE_Mode mode;
80
81 unsigned char run_length;
82 unsigned char repeat_byte;
83
84 /* These members manage timeouts for programmed delays */
85 wait_queue_head_t wait_queue;
86 struct timer_list timer_list;
87 };
88
89 static struct inst instances[BPP_NO];
90
91 #if defined(__i386__)
92
93 const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
94
95 /*
96 * These are for data access.
97 * Control lines accesses are hidden in set_bits() and get_bits().
98 * The exeption is the probe procedure, which is system-dependent.
99 */
100 #define bpp_outb_p(data, base) outb_p((data), (base))
101 #define bpp_inb(base) inb(base)
102 #define bpp_inb_p(base) inb_p(base)
103
104 /*
105 * This method takes the pin values mask and sets the hardware pins to
106 * the requested value: 1 == high voltage, 0 == low voltage. This
107 * burries the annoying PC bit inversion and preserves the direction
108 * flag.
109 */
110 static void set_pins(unsigned short pins, unsigned minor)
111 {
112 unsigned char bits = instances[minor].direction; /* == 0x20 */
113
114 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
115 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
116 if ( pins & BPP_PP_nInit) bits |= 4;
117 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
118
119 instances[minor].pp_state = bits;
120
121 outb_p(bits, base_addrs[minor]+2);
122 }
123
124 static unsigned short get_pins(unsigned minor)
125 {
126 unsigned short bits = 0;
127
128 unsigned value = instances[minor].pp_state;
129 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
130 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
131 if (value & 0x04) bits |= BPP_PP_nInit;
132 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
133
134 value = inb_p(base_addrs[minor]+1);
135 if (value & 0x08) bits |= BPP_GP_nFault;
136 if (value & 0x10) bits |= BPP_GP_Select;
137 if (value & 0x20) bits |= BPP_GP_PError;
138 if (value & 0x40) bits |= BPP_GP_nAck;
139 if (! (value & 0x80)) bits |= BPP_GP_Busy;
140
141 return bits;
142 }
143
144 #endif /* __i386__ */
145
146 #if defined(__sparc__)
147
148 /*
149 * Register block
150 */
151 /* DMA registers */
152 #define BPP_CSR 0x00
153 #define BPP_ADDR 0x04
154 #define BPP_BCNT 0x08
155 #define BPP_TST_CSR 0x0C
156 /* Parallel Port registers */
157 #define BPP_HCR 0x10
158 #define BPP_OCR 0x12
159 #define BPP_DR 0x14
160 #define BPP_TCR 0x15
161 #define BPP_OR 0x16
162 #define BPP_IR 0x17
163 #define BPP_ICR 0x18
164 #define BPP_SIZE 0x1A
165
166 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
167 #define P_DEV_ID_MASK 0xf0000000 /* R */
168 #define P_DEV_ID_ZEBRA 0x40000000
169 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
170 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
171 #define P_A_LOADED 0x04000000 /* R */
172 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
173 #define P_EN_NEXT 0x01000000 /* RW */
174 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
175 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
176 of P-FIFO on loading of P_ADDR*/
177 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
178 #define P_BURST_8 0x00000000
179 #define P_BURST_4 0x00040000
180 #define P_BURST_1 0x00080000 /* "No burst" write */
181 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
182 P_EN_NEXT=1 */
183 #define P_EN_CNT 0x00002000 /* RW */
184 #define P_EN_DMA 0x00000200 /* RW */
185 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
186 #define P_RESET 0x00000080 /* RW */
187 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
188 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
189 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
190 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
191 #define P_ERR_PEND 0x00000002 /* R */
192 #define P_INT_PEND 0x00000001 /* R */
193
194 /* BPP_HCR. Time is in increments of SBus clock. */
195 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
196 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
197 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
198
199 /* BPP_OCR. */
200 #define P_OCR_MEM_CLR 0x8000
201 #define P_OCR_DATA_SRC 0x4000 /* ) */
202 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
203 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
204 #define P_OCR_ACK_DSEL 0x0800 /* ) */
205 #define P_OCR_EN_DIAG 0x0400
206 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
207 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
208 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
209 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
210 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
211 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
212
213 /* BPP_TCR */
214 #define P_TCR_DIR 0x08
215 #define P_TCR_BUSY 0x04
216 #define P_TCR_ACK 0x02
217 #define P_TCR_DS 0x01 /* Strobe */
218
219 /* BPP_OR */
220 #define P_OR_V3 0x20 /* ) */
221 #define P_OR_V2 0x10 /* ) on Zebra only */
222 #define P_OR_V1 0x08 /* ) */
223 #define P_OR_INIT 0x04
224 #define P_OR_AFXN 0x02 /* Auto Feed */
225 #define P_OR_SLCT_IN 0x01
226
227 /* BPP_IR */
228 #define P_IR_PE 0x04
229 #define P_IR_SLCT 0x02
230 #define P_IR_ERR 0x01
231
232 /* BPP_ICR */
233 #define P_DS_IRQ 0x8000 /* RW1 */
234 #define P_ACK_IRQ 0x4000 /* RW1 */
235 #define P_BUSY_IRQ 0x2000 /* RW1 */
236 #define P_PE_IRQ 0x1000 /* RW1 */
237 #define P_SLCT_IRQ 0x0800 /* RW1 */
238 #define P_ERR_IRQ 0x0400 /* RW1 */
239 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
240 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
241 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
242 #define P_BUSY_IRQ_EN 0x0040 /* RW */
243 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
244 #define P_PE_IRQ_EN 0x0010 /* RW */
245 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
246 #define P_SLCT_IRQ_EN 0x0004 /* RW */
247 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
248 #define P_ERR_IRQ_EN 0x0001 /* RW */
249
250 unsigned long base_addrs[BPP_NO];
251
252 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
253 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
254 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
255
256 static void set_pins(unsigned short pins, unsigned minor)
257 {
258 unsigned long base = base_addrs[minor];
259 unsigned char bits_tcr = 0, bits_or = 0;
260
261 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
262 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
263
264 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
265 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
266 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
267
268 sbus_writeb(bits_or, base + BPP_OR);
269 sbus_writeb(bits_tcr, base + BPP_TCR);
270 }
271
272 /*
273 * i386 people read output pins from a software image.
274 * We may get them back from hardware.
275 * Again, inversion of pins must he buried here.
276 */
277 static unsigned short get_pins(unsigned minor)
278 {
279 unsigned long base = base_addrs[minor];
280 unsigned short bits = 0;
281 unsigned value_tcr = sbus_readb(base + BPP_TCR);
282 unsigned value_ir = sbus_readb(base + BPP_IR);
283 unsigned value_or = sbus_readb(base + BPP_OR);
284
285 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
286 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
287 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
288 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
289
290 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
291 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
292 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
293 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
294 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
295
296 return bits;
297 }
298
299 #endif /* __sparc__ */
300
301 static void bpp_wake_up(unsigned long val)
302 { wake_up(&instances[val].wait_queue); }
303
304 static void snooze(unsigned long snooze_time, unsigned minor)
305 {
306 instances[minor].timer_list.expires = jiffies + snooze_time + 1;
307 instances[minor].timer_list.data = minor;
308 add_timer(&instances[minor].timer_list);
309 sleep_on (&instances[minor].wait_queue);
310 }
311
312 static int wait_for(unsigned short set, unsigned short clr,
313 unsigned long delay, unsigned minor)
314 {
315 unsigned short pins = get_pins(minor);
316
317 unsigned long extime = 0;
318
319 /*
320 * Try a real fast scan for the first jiffy, in case the device
321 * responds real good. The first while loop guesses an expire
322 * time accounting for possible wraparound of jiffies.
323 */
324 while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
325 while ( (time_before(jiffies, extime))
326 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
327 pins = get_pins(minor);
328 }
329
330 delay -= 1;
331
332 /*
333 * If my delay expired or the pins are still not where I want
334 * them, then resort to using the timer and greatly reduce my
335 * sample rate. If the peripheral is going to be slow, this will
336 * give the CPU up to some more worthy process.
337 */
338 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
339
340 snooze(1, minor);
341 pins = get_pins(minor);
342 delay -= 1;
343 }
344
345 if (delay == 0) return -1;
346 else return pins;
347 }
348
349 /*
350 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
351 * errno means something broke, and I do not yet know how to fix it.
352 */
353 static int negotiate(unsigned char mode, unsigned minor)
354 {
355 int rc;
356 unsigned short pins = get_pins(minor);
357 if (pins & BPP_PP_nSelectIn) return -EIO;
358
359
360 /* Event 0: Write the mode to the data lines */
361 bpp_outb_p(mode, base_addrs[minor]);
362
363 snooze(TIME_PSetup, minor);
364
365 /* Event 1: Strobe the mode code into the peripheral */
366 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
367
368 /* Wait for Event 2: Peripheral responds as a 1284 device. */
369 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
370 BPP_GP_nAck,
371 TIME_PResponse,
372 minor);
373
374 if (rc == -1) return -ETIMEDOUT;
375
376 /* Event 3: latch extensibility request */
377 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
378
379 /* ... quick nap while peripheral ponders the byte i'm sending...*/
380 snooze(1, minor);
381
382 /* Event 4: restore strobe, to ACK peripheral's response. */
383 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
384
385 /* Wait for Event 6: Peripheral latches response bits */
386 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
387 if (rc == -1) return -EIO;
388
389 /* A 1284 device cannot refuse nibble mode */
390 if (mode == DEFAULT_NIBBLE) return 0;
391
392 if (pins & BPP_GP_Select) return 0;
393
394 return -EPROTONOSUPPORT;
395 }
396
397 static int terminate(unsigned minor)
398 {
399 int rc;
400
401 /* Event 22: Request termination of 1284 mode */
402 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
403
404 /* Wait for Events 23 and 24: ACK termination request. */
405 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
406 BPP_GP_nAck,
407 TIME_PSetup+TIME_PResponse,
408 minor);
409
410 instances[minor].direction = 0;
411 instances[minor].mode = COMPATIBILITY;
412
413 if (rc == -1) {
414 return -EIO;
415 }
416
417 /* Event 25: Handshake by lowering nAutoFd */
418 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
419
420 /* Event 26: Peripheral wiggles lines... */
421
422 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
423 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
424 if (rc == -1) {
425 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
426 return -EIO;
427 }
428
429 /* Event 28: Finish phase by raising nAutoFd */
430 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
431
432 return 0;
433 }
434
435
436 /*
437 * Allow only one process to open the device at a time.
438 */
439 static int bpp_open(struct inode *inode, struct file *f)
440 {
441 unsigned minor = MINOR(inode->i_rdev);
442 if (minor >= BPP_NO) return -ENODEV;
443 if (! instances[minor].present) return -ENODEV;
444 if (instances[minor].opened) return -EBUSY;
445
446 instances[minor].opened = 1;
447
448 return 0;
449 }
450
451 /*
452 * When the process closes the device, this method is called to clean
453 * up and reset the hardware. Always leave the device in compatibility
454 * mode as this is a reasonable place to clean up from messes made by
455 * ioctls, or other mayhem.
456 */
457 static int bpp_release(struct inode *inode, struct file *f)
458 {
459 unsigned minor = MINOR(inode->i_rdev);
460
461 lock_kernel();
462 instances[minor].opened = 0;
463
464 if (instances[minor].mode != COMPATIBILITY)
465 terminate(minor);
466 unlock_kernel();
467 return 0;
468 }
469
470 static long read_nibble(unsigned minor, char *c, unsigned long cnt)
471 {
472 unsigned long remaining = cnt;
473 long rc;
474
475 while (remaining > 0) {
476 unsigned char byte = 0;
477 int pins;
478
479 /* Event 7: request nibble */
480 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
481
482 /* Wait for event 9: Peripher strobes first nibble */
483 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
484 if (pins == -1) return -ETIMEDOUT;
485
486 /* Event 10: I handshake nibble */
487 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
488 if (pins & BPP_GP_nFault) byte |= 0x01;
489 if (pins & BPP_GP_Select) byte |= 0x02;
490 if (pins & BPP_GP_PError) byte |= 0x04;
491 if (pins & BPP_GP_Busy) byte |= 0x08;
492
493 /* Wait for event 11: Peripheral handshakes nibble */
494 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
495
496 /* Event 7: request nibble */
497 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
498
499 /* Wait for event 9: Peripher strobes first nibble */
500 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
501 if (rc == -1) return -ETIMEDOUT;
502
503 /* Event 10: I handshake nibble */
504 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
505 if (pins & BPP_GP_nFault) byte |= 0x10;
506 if (pins & BPP_GP_Select) byte |= 0x20;
507 if (pins & BPP_GP_PError) byte |= 0x40;
508 if (pins & BPP_GP_Busy) byte |= 0x80;
509
510 if (put_user(byte, c))
511 return -EFAULT;
512 c += 1;
513 remaining -= 1;
514
515 /* Wait for event 11: Peripheral handshakes nibble */
516 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
517 if (rc == -1) return -EIO;
518 }
519
520 return cnt - remaining;
521 }
522
523 static long read_ecp(unsigned minor, char *c, unsigned long cnt)
524 {
525 unsigned long remaining;
526 long rc;
527
528 /* Turn ECP mode from forward to reverse if needed. */
529 if (! instances[minor].direction) {
530 unsigned short pins = get_pins(minor);
531
532 /* Event 38: Turn the bus around */
533 instances[minor].direction = 0x20;
534 pins &= ~BPP_PP_nAutoFd;
535 set_pins(pins, minor);
536
537 /* Event 39: Set pins for reverse mode. */
538 snooze(TIME_PSetup, minor);
539 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
540
541 /* Wait for event 40: Peripheral ready to be strobed */
542 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
543 if (rc == -1) return -ETIMEDOUT;
544 }
545
546 remaining = cnt;
547
548 while (remaining > 0) {
549
550 /* If there is a run length for a repeated byte, repeat */
551 /* that byte a few times. */
552 if (instances[minor].run_length && !instances[minor].run_flag) {
553
554 char buffer[128];
555 unsigned idx;
556 unsigned repeat = remaining < instances[minor].run_length
557 ? remaining
558 : instances[minor].run_length;
559
560 for (idx = 0 ; idx < repeat ; idx += 1)
561 buffer[idx] = instances[minor].repeat_byte;
562
563 if (copy_to_user(c, buffer, repeat))
564 return -EFAULT;
565 remaining -= repeat;
566 c += repeat;
567 instances[minor].run_length -= repeat;
568 }
569
570 if (remaining == 0) break;
571
572
573 /* Wait for Event 43: Data active on the bus. */
574 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
575 if (rc == -1) break;
576
577 if (rc & BPP_GP_Busy) {
578 /* OK, this is data. read it in. */
579 unsigned char byte = bpp_inb(base_addrs[minor]);
580 if (put_user(byte, c))
581 return -EFAULT;
582 c += 1;
583 remaining -= 1;
584
585 if (instances[minor].run_flag) {
586 instances[minor].repeat_byte = byte;
587 instances[minor].run_flag = 0;
588 }
589
590 } else {
591 unsigned char byte = bpp_inb(base_addrs[minor]);
592 if (byte & 0x80) {
593 printk("bpp%d: "
594 "Ignoring ECP channel %u from device.\n",
595 minor, byte & 0x7f);
596 } else {
597 instances[minor].run_length = byte;
598 instances[minor].run_flag = 1;
599 }
600 }
601
602 /* Event 44: I got it. */
603 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
604
605 /* Wait for event 45: peripheral handshake */
606 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
607 if (rc == -1) return -ETIMEDOUT;
608
609 /* Event 46: Finish handshake */
610 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
611
612 }
613
614
615 return cnt - remaining;
616 }
617
618 static ssize_t bpp_read(struct file *f, char *c, size_t cnt, loff_t * ppos)
619 {
620 long rc;
621 const unsigned minor = MINOR(f->f_dentry->d_inode->i_rdev);
622 if (minor >= BPP_NO) return -ENODEV;
623 if (!instances[minor].present) return -ENODEV;
624
625 switch (instances[minor].mode) {
626
627 default:
628 if (instances[minor].mode != COMPATIBILITY)
629 terminate(minor);
630
631 if (instances[minor].enhanced) {
632 /* For now, do all reads with ECP-RLE mode */
633 unsigned short pins;
634
635 rc = negotiate(DEFAULT_ECP, minor);
636 if (rc < 0) break;
637
638 instances[minor].mode = ECP_RLE;
639
640 /* Event 30: set nAutoFd low to setup for ECP mode */
641 pins = get_pins(minor);
642 pins &= ~BPP_PP_nAutoFd;
643 set_pins(pins, minor);
644
645 /* Wait for Event 31: peripheral ready */
646 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
647 if (rc == -1) return -ETIMEDOUT;
648
649 rc = read_ecp(minor, c, cnt);
650
651 } else {
652 rc = negotiate(DEFAULT_NIBBLE, minor);
653 if (rc < 0) break;
654
655 instances[minor].mode = NIBBLE;
656
657 rc = read_nibble(minor, c, cnt);
658 }
659 break;
660
661 case NIBBLE:
662 rc = read_nibble(minor, c, cnt);
663 break;
664
665 case ECP:
666 case ECP_RLE:
667 rc = read_ecp(minor, c, cnt);
668 break;
669
670 }
671
672
673 return rc;
674 }
675
676 /*
677 * Compatibility mode handshaking is a matter of writing data,
678 * strobing it, and waiting for the printer to stop being busy.
679 */
680 static long write_compat(unsigned minor, const char *c, unsigned long cnt)
681 {
682 long rc;
683 unsigned short pins = get_pins(minor);
684
685 unsigned long remaining = cnt;
686
687
688 while (remaining > 0) {
689 unsigned char byte;
690
691 if (get_user(byte, c))
692 return -EFAULT;
693 c += 1;
694
695 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
696 if (rc == -1) return -ETIMEDOUT;
697
698 bpp_outb_p(byte, base_addrs[minor]);
699 remaining -= 1;
700 /* snooze(1, minor); */
701
702 pins &= ~BPP_PP_nStrobe;
703 set_pins(pins, minor);
704
705 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
706
707 pins |= BPP_PP_nStrobe;
708 set_pins(pins, minor);
709 }
710
711 return cnt - remaining;
712 }
713
714 /*
715 * Write data using ECP mode. Watch out that the port may be set up
716 * for reading. If so, turn the port around.
717 */
718 static long write_ecp(unsigned minor, const char *c, unsigned long cnt)
719 {
720 unsigned short pins = get_pins(minor);
721 unsigned long remaining = cnt;
722
723 if (instances[minor].direction) {
724 int rc;
725
726 /* Event 47 Request bus be turned around */
727 pins |= BPP_PP_nInit;
728 set_pins(pins, minor);
729
730 /* Wait for Event 49: Peripheral relinquished bus */
731 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
732
733 pins |= BPP_PP_nAutoFd;
734 instances[minor].direction = 0;
735 set_pins(pins, minor);
736 }
737
738 while (remaining > 0) {
739 unsigned char byte;
740 int rc;
741
742 if (get_user(byte, c))
743 return -EFAULT;
744
745 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
746 if (rc == -1) return -ETIMEDOUT;
747
748 c += 1;
749
750 bpp_outb_p(byte, base_addrs[minor]);
751
752 pins &= ~BPP_PP_nStrobe;
753 set_pins(pins, minor);
754
755 pins |= BPP_PP_nStrobe;
756 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
757 if (rc == -1) return -EIO;
758
759 set_pins(pins, minor);
760 }
761
762 return cnt - remaining;
763 }
764
765 /*
766 * Write to the peripheral. Be sensitive of the current mode. If I'm
767 * in a mode that can be turned around (ECP) then just do
768 * that. Otherwise, terminate and do my writing in compat mode. This
769 * is the safest course as any device can handle it.
770 */
771 static ssize_t bpp_write(struct file *f, const char *c, size_t cnt, loff_t * ppos)
772 {
773 long errno = 0;
774 const unsigned minor = MINOR(f->f_dentry->d_inode->i_rdev);
775 if (minor >= BPP_NO) return -ENODEV;
776 if (!instances[minor].present) return -ENODEV;
777
778 switch (instances[minor].mode) {
779
780 case ECP:
781 case ECP_RLE:
782 errno = write_ecp(minor, c, cnt);
783 break;
784 case COMPATIBILITY:
785 errno = write_compat(minor, c, cnt);
786 break;
787 default:
788 terminate(minor);
789 errno = write_compat(minor, c, cnt);
790 }
791
792 return errno;
793 }
794
795 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
796 unsigned long arg)
797 {
798 int errno = 0;
799
800 unsigned minor = MINOR(inode->i_rdev);
801 if (minor >= BPP_NO) return -ENODEV;
802 if (!instances[minor].present) return -ENODEV;
803
804
805 switch (cmd) {
806
807 case BPP_PUT_PINS:
808 set_pins(arg, minor);
809 break;
810
811 case BPP_GET_PINS:
812 errno = get_pins(minor);
813 break;
814
815 case BPP_PUT_DATA:
816 bpp_outb_p(arg, base_addrs[minor]);
817 break;
818
819 case BPP_GET_DATA:
820 errno = bpp_inb_p(base_addrs[minor]);
821 break;
822
823 case BPP_SET_INPUT:
824 if (arg)
825 if (instances[minor].enhanced) {
826 unsigned short bits = get_pins(minor);
827 instances[minor].direction = 0x20;
828 set_pins(bits, minor);
829 } else {
830 errno = -ENOTTY;
831 }
832 else {
833 unsigned short bits = get_pins(minor);
834 instances[minor].direction = 0x00;
835 set_pins(bits, minor);
836 }
837 break;
838
839 default:
840 errno = -EINVAL;
841 }
842
843 return errno;
844 }
845
846 static struct file_operations bpp_fops = {
847 owner: THIS_MODULE,
848 read: bpp_read,
849 write: bpp_write,
850 ioctl: bpp_ioctl,
851 open: bpp_open,
852 release: bpp_release,
853 };
854
855 #if defined(__i386__)
856
857 #define collectLptPorts() {}
858
859 static void probeLptPort(unsigned idx)
860 {
861 unsigned int testvalue;
862 const unsigned short lpAddr = base_addrs[idx];
863
864 instances[idx].present = 0;
865 instances[idx].enhanced = 0;
866 instances[idx].direction = 0;
867 instances[idx].mode = COMPATIBILITY;
868 instances[idx].wait_queue = 0;
869 instances[idx].run_length = 0;
870 instances[idx].run_flag = 0;
871 init_timer(&instances[idx].timer_list);
872 instances[idx].timer_list.function = bpp_wake_up;
873 if (check_region(lpAddr,3)) return;
874
875 /*
876 * First, make sure the instance exists. Do this by writing to
877 * the data latch and reading the value back. If the port *is*
878 * present, test to see if it supports extended-mode
879 * operation. This will be required for IEEE1284 reverse
880 * transfers.
881 */
882
883 outb_p(BPP_PROBE_CODE, lpAddr);
884 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
885 ;
886 testvalue = inb_p(lpAddr);
887 if (testvalue == BPP_PROBE_CODE) {
888 unsigned save;
889 instances[idx].present = 1;
890
891 request_region(lpAddr,3, dev_name);
892 save = inb_p(lpAddr+2);
893 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
894 ;
895 outb_p(save|0x20, lpAddr+2);
896 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
897 ;
898 outb_p(~BPP_PROBE_CODE, lpAddr);
899 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
900 ;
901 testvalue = inb_p(lpAddr);
902 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
903 instances[idx].enhanced = 0;
904 else
905 instances[idx].enhanced = 1;
906 outb_p(save, lpAddr+2);
907 }
908
909 /*
910 * Leave the port in compat idle mode.
911 */
912 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
913
914 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
915 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
916 }
917
918 static inline void freeLptPort(int idx)
919 {
920 release_region(base_addrs[idx], 3);
921 }
922
923 #endif
924
925 #if defined(__sparc__)
926
927 static unsigned long map_bpp(struct sbus_dev *dev, int idx)
928 {
929 return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
930 }
931
932 static int collectLptPorts(void)
933 {
934 struct sbus_bus *bus;
935 struct sbus_dev *dev;
936 int count;
937
938 count = 0;
939 for_all_sbusdev(dev, bus) {
940 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
941 if (count >= BPP_NO) {
942 printk(KERN_NOTICE
943 "bpp: More than %d bpp ports,"
944 " rest is ignored\n", BPP_NO);
945 return count;
946 }
947 base_addrs[count] = map_bpp(dev, count);
948 count++;
949 }
950 }
951 return count;
952 }
953
954 static void probeLptPort(unsigned idx)
955 {
956 unsigned long rp = base_addrs[idx];
957 __u32 csr;
958 char *brand;
959
960 instances[idx].present = 0;
961 instances[idx].enhanced = 0;
962 instances[idx].direction = 0;
963 instances[idx].mode = COMPATIBILITY;
964 init_waitqueue_head(&instances[idx].wait_queue);
965 instances[idx].run_length = 0;
966 instances[idx].run_flag = 0;
967 init_timer(&instances[idx].timer_list);
968 instances[idx].timer_list.function = bpp_wake_up;
969
970 if (rp == 0) return;
971
972 instances[idx].present = 1;
973 instances[idx].enhanced = 1; /* Sure */
974
975 csr = sbus_readl(rp + BPP_CSR);
976 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
977 udelay(20);
978 csr = sbus_readl(rp + BPP_CSR);
979 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
980 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
981 }
982 }
983 printk("bpp%d: reset with 0x%08x ..", idx, csr);
984 sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
985 udelay(500);
986 sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
987 csr = sbus_readl(rp + BPP_CSR);
988 printk(" done with csr=0x%08x ocr=0x%04x\n",
989 csr, sbus_readw(rp + BPP_OCR));
990
991 switch (csr & P_DEV_ID_MASK) {
992 case P_DEV_ID_ZEBRA:
993 brand = "Zebra";
994 break;
995 case P_DEV_ID_L64854:
996 brand = "DMA2";
997 break;
998 default:
999 brand = "Unknown";
1000 }
1001 printk("bpp%d: %s at 0x%lx\n", idx, brand, rp);
1002
1003 /*
1004 * Leave the port in compat idle mode.
1005 */
1006 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1007
1008 return;
1009 }
1010
1011 static inline void freeLptPort(int idx)
1012 {
1013 sbus_iounmap(base_addrs[idx], BPP_SIZE);
1014 }
1015
1016 #endif
1017
1018 static devfs_handle_t devfs_handle;
1019
1020 #ifdef MODULE
1021 int init_module(void)
1022 #else
1023 int __init bpp_init(void)
1024 #endif
1025 {
1026 int rc;
1027 unsigned idx;
1028
1029 rc = collectLptPorts();
1030 if (rc == 0)
1031 return -ENODEV;
1032
1033 rc = devfs_register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1034 if (rc < 0)
1035 return rc;
1036
1037 for (idx = 0; idx < BPP_NO; idx += 1) {
1038 instances[idx].opened = 0;
1039 probeLptPort(idx);
1040 }
1041 devfs_handle = devfs_mk_dir (NULL, "bpp", NULL);
1042 devfs_register_series (devfs_handle, "%u", BPP_NO, DEVFS_FL_DEFAULT,
1043 BPP_MAJOR, 0, S_IFCHR | S_IRUSR | S_IWUSR,
1044 &bpp_fops, NULL);
1045
1046 return 0;
1047 }
1048
1049 #ifdef MODULE
1050 void cleanup_module(void)
1051 {
1052 unsigned idx;
1053
1054 devfs_unregister (devfs_handle);
1055 devfs_unregister_chrdev(BPP_MAJOR, dev_name);
1056
1057 for (idx = 0 ; idx < BPP_NO ; idx += 1) {
1058 if (instances[idx].present)
1059 freeLptPort(idx);
1060 }
1061 }
1062 #endif
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