2 * drivers/sbus/char/bpp.c
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/version.h>
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/smp_lock.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23 #include <linux/devfs_fs_kernel.h>
25 #include <asm/uaccess.h>
29 # include <asm/system.h>
30 # include <asm/segment.h>
33 #if defined(__sparc__)
34 # include <linux/init.h>
35 # include <linux/delay.h> /* udelay() */
37 # include <asm/oplib.h> /* OpenProm Library */
38 # include <asm/sbus.h>
43 #define BPP_PROBE_CODE 0x55
46 static const unsigned BPP_MAJOR
= LP_MAJOR
;
47 static const char* dev_name
= "bpp";
49 /* When switching from compatibility to a mode where I can read, try
50 the following mode first. */
52 /* const unsigned char DEFAULT_ECP = 0x10; */
53 static const unsigned char DEFAULT_ECP
= 0x30;
54 static const unsigned char DEFAULT_NIBBLE
= 0x00;
57 * These are 1284 time constraints, in units of jiffies.
60 static const unsigned long TIME_PSetup
= 1;
61 static const unsigned long TIME_PResponse
= 6;
62 static const unsigned long TIME_IDLE_LIMIT
= 2000;
65 * One instance per supported subdevice...
69 enum IEEE_Mode
{ COMPATIBILITY
, NIBBLE
, ECP
, ECP_RLE
, EPP
};
72 unsigned present
: 1; /* True if the hardware exists */
73 unsigned enhanced
: 1; /* True if the hardware in "enhanced" */
74 unsigned opened
: 1; /* True if the device is opened already */
75 unsigned run_flag
: 1; /* True if waiting for a repeate byte */
77 unsigned char direction
; /* 0 --> out, 0x20 --> IN */
78 unsigned char pp_state
; /* State of host controlled pins. */
81 unsigned char run_length
;
82 unsigned char repeat_byte
;
84 /* These members manage timeouts for programmed delays */
85 wait_queue_head_t wait_queue
;
86 struct timer_list timer_list
;
89 static struct inst instances
[BPP_NO
];
93 const unsigned short base_addrs
[BPP_NO
] = { 0x278, 0x378, 0x3bc };
96 * These are for data access.
97 * Control lines accesses are hidden in set_bits() and get_bits().
98 * The exeption is the probe procedure, which is system-dependent.
100 #define bpp_outb_p(data, base) outb_p((data), (base))
101 #define bpp_inb(base) inb(base)
102 #define bpp_inb_p(base) inb_p(base)
105 * This method takes the pin values mask and sets the hardware pins to
106 * the requested value: 1 == high voltage, 0 == low voltage. This
107 * burries the annoying PC bit inversion and preserves the direction
110 static void set_pins(unsigned short pins
, unsigned minor
)
112 unsigned char bits
= instances
[minor
].direction
; /* == 0x20 */
114 if (! (pins
& BPP_PP_nStrobe
)) bits
|= 1;
115 if (! (pins
& BPP_PP_nAutoFd
)) bits
|= 2;
116 if ( pins
& BPP_PP_nInit
) bits
|= 4;
117 if (! (pins
& BPP_PP_nSelectIn
)) bits
|= 8;
119 instances
[minor
].pp_state
= bits
;
121 outb_p(bits
, base_addrs
[minor
]+2);
124 static unsigned short get_pins(unsigned minor
)
126 unsigned short bits
= 0;
128 unsigned value
= instances
[minor
].pp_state
;
129 if (! (value
& 0x01)) bits
|= BPP_PP_nStrobe
;
130 if (! (value
& 0x02)) bits
|= BPP_PP_nAutoFd
;
131 if (value
& 0x04) bits
|= BPP_PP_nInit
;
132 if (! (value
& 0x08)) bits
|= BPP_PP_nSelectIn
;
134 value
= inb_p(base_addrs
[minor
]+1);
135 if (value
& 0x08) bits
|= BPP_GP_nFault
;
136 if (value
& 0x10) bits
|= BPP_GP_Select
;
137 if (value
& 0x20) bits
|= BPP_GP_PError
;
138 if (value
& 0x40) bits
|= BPP_GP_nAck
;
139 if (! (value
& 0x80)) bits
|= BPP_GP_Busy
;
144 #endif /* __i386__ */
146 #if defined(__sparc__)
153 #define BPP_ADDR 0x04
154 #define BPP_BCNT 0x08
155 #define BPP_TST_CSR 0x0C
156 /* Parallel Port registers */
164 #define BPP_SIZE 0x1A
166 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
167 #define P_DEV_ID_MASK 0xf0000000 /* R */
168 #define P_DEV_ID_ZEBRA 0x40000000
169 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
170 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
171 #define P_A_LOADED 0x04000000 /* R */
172 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
173 #define P_EN_NEXT 0x01000000 /* RW */
174 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
175 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
176 of P-FIFO on loading of P_ADDR*/
177 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
178 #define P_BURST_8 0x00000000
179 #define P_BURST_4 0x00040000
180 #define P_BURST_1 0x00080000 /* "No burst" write */
181 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
183 #define P_EN_CNT 0x00002000 /* RW */
184 #define P_EN_DMA 0x00000200 /* RW */
185 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
186 #define P_RESET 0x00000080 /* RW */
187 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
188 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
189 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
190 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
191 #define P_ERR_PEND 0x00000002 /* R */
192 #define P_INT_PEND 0x00000001 /* R */
194 /* BPP_HCR. Time is in increments of SBus clock. */
195 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
196 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
197 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
200 #define P_OCR_MEM_CLR 0x8000
201 #define P_OCR_DATA_SRC 0x4000 /* ) */
202 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
203 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
204 #define P_OCR_ACK_DSEL 0x0800 /* ) */
205 #define P_OCR_EN_DIAG 0x0400
206 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
207 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
208 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
209 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
210 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
211 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
214 #define P_TCR_DIR 0x08
215 #define P_TCR_BUSY 0x04
216 #define P_TCR_ACK 0x02
217 #define P_TCR_DS 0x01 /* Strobe */
220 #define P_OR_V3 0x20 /* ) */
221 #define P_OR_V2 0x10 /* ) on Zebra only */
222 #define P_OR_V1 0x08 /* ) */
223 #define P_OR_INIT 0x04
224 #define P_OR_AFXN 0x02 /* Auto Feed */
225 #define P_OR_SLCT_IN 0x01
229 #define P_IR_SLCT 0x02
230 #define P_IR_ERR 0x01
233 #define P_DS_IRQ 0x8000 /* RW1 */
234 #define P_ACK_IRQ 0x4000 /* RW1 */
235 #define P_BUSY_IRQ 0x2000 /* RW1 */
236 #define P_PE_IRQ 0x1000 /* RW1 */
237 #define P_SLCT_IRQ 0x0800 /* RW1 */
238 #define P_ERR_IRQ 0x0400 /* RW1 */
239 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
240 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
241 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
242 #define P_BUSY_IRQ_EN 0x0040 /* RW */
243 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
244 #define P_PE_IRQ_EN 0x0010 /* RW */
245 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
246 #define P_SLCT_IRQ_EN 0x0004 /* RW */
247 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
248 #define P_ERR_IRQ_EN 0x0001 /* RW */
250 unsigned long base_addrs
[BPP_NO
];
252 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
253 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
254 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
256 static void set_pins(unsigned short pins
, unsigned minor
)
258 unsigned long base
= base_addrs
[minor
];
259 unsigned char bits_tcr
= 0, bits_or
= 0;
261 if (instances
[minor
].direction
& 0x20) bits_tcr
|= P_TCR_DIR
;
262 if ( pins
& BPP_PP_nStrobe
) bits_tcr
|= P_TCR_DS
;
264 if ( pins
& BPP_PP_nAutoFd
) bits_or
|= P_OR_AFXN
;
265 if (! (pins
& BPP_PP_nInit
)) bits_or
|= P_OR_INIT
;
266 if (! (pins
& BPP_PP_nSelectIn
)) bits_or
|= P_OR_SLCT_IN
;
268 sbus_writeb(bits_or
, base
+ BPP_OR
);
269 sbus_writeb(bits_tcr
, base
+ BPP_TCR
);
273 * i386 people read output pins from a software image.
274 * We may get them back from hardware.
275 * Again, inversion of pins must he buried here.
277 static unsigned short get_pins(unsigned minor
)
279 unsigned long base
= base_addrs
[minor
];
280 unsigned short bits
= 0;
281 unsigned value_tcr
= sbus_readb(base
+ BPP_TCR
);
282 unsigned value_ir
= sbus_readb(base
+ BPP_IR
);
283 unsigned value_or
= sbus_readb(base
+ BPP_OR
);
285 if (value_tcr
& P_TCR_DS
) bits
|= BPP_PP_nStrobe
;
286 if (value_or
& P_OR_AFXN
) bits
|= BPP_PP_nAutoFd
;
287 if (! (value_or
& P_OR_INIT
)) bits
|= BPP_PP_nInit
;
288 if (! (value_or
& P_OR_SLCT_IN
)) bits
|= BPP_PP_nSelectIn
;
290 if (value_ir
& P_IR_ERR
) bits
|= BPP_GP_nFault
;
291 if (! (value_ir
& P_IR_SLCT
)) bits
|= BPP_GP_Select
;
292 if (! (value_ir
& P_IR_PE
)) bits
|= BPP_GP_PError
;
293 if (! (value_tcr
& P_TCR_ACK
)) bits
|= BPP_GP_nAck
;
294 if (value_tcr
& P_TCR_BUSY
) bits
|= BPP_GP_Busy
;
299 #endif /* __sparc__ */
301 static void bpp_wake_up(unsigned long val
)
302 { wake_up(&instances
[val
].wait_queue
); }
304 static void snooze(unsigned long snooze_time
, unsigned minor
)
306 instances
[minor
].timer_list
.expires
= jiffies
+ snooze_time
+ 1;
307 instances
[minor
].timer_list
.data
= minor
;
308 add_timer(&instances
[minor
].timer_list
);
309 sleep_on (&instances
[minor
].wait_queue
);
312 static int wait_for(unsigned short set
, unsigned short clr
,
313 unsigned long delay
, unsigned minor
)
315 unsigned short pins
= get_pins(minor
);
317 unsigned long extime
= 0;
320 * Try a real fast scan for the first jiffy, in case the device
321 * responds real good. The first while loop guesses an expire
322 * time accounting for possible wraparound of jiffies.
324 while (time_after_eq(jiffies
, extime
)) extime
= jiffies
+ 1;
325 while ( (time_before(jiffies
, extime
))
326 && (((pins
& set
) != set
) || ((pins
& clr
) != 0)) ) {
327 pins
= get_pins(minor
);
333 * If my delay expired or the pins are still not where I want
334 * them, then resort to using the timer and greatly reduce my
335 * sample rate. If the peripheral is going to be slow, this will
336 * give the CPU up to some more worthy process.
338 while ( delay
&& (((pins
& set
) != set
) || ((pins
& clr
) != 0)) ) {
341 pins
= get_pins(minor
);
345 if (delay
== 0) return -1;
350 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
351 * errno means something broke, and I do not yet know how to fix it.
353 static int negotiate(unsigned char mode
, unsigned minor
)
356 unsigned short pins
= get_pins(minor
);
357 if (pins
& BPP_PP_nSelectIn
) return -EIO
;
360 /* Event 0: Write the mode to the data lines */
361 bpp_outb_p(mode
, base_addrs
[minor
]);
363 snooze(TIME_PSetup
, minor
);
365 /* Event 1: Strobe the mode code into the peripheral */
366 set_pins(BPP_PP_nSelectIn
|BPP_PP_nStrobe
|BPP_PP_nInit
, minor
);
368 /* Wait for Event 2: Peripheral responds as a 1284 device. */
369 rc
= wait_for(BPP_GP_PError
|BPP_GP_Select
|BPP_GP_nFault
,
374 if (rc
== -1) return -ETIMEDOUT
;
376 /* Event 3: latch extensibility request */
377 set_pins(BPP_PP_nSelectIn
|BPP_PP_nInit
, minor
);
379 /* ... quick nap while peripheral ponders the byte i'm sending...*/
382 /* Event 4: restore strobe, to ACK peripheral's response. */
383 set_pins(BPP_PP_nSelectIn
|BPP_PP_nAutoFd
|BPP_PP_nStrobe
|BPP_PP_nInit
, minor
);
385 /* Wait for Event 6: Peripheral latches response bits */
386 rc
= wait_for(BPP_GP_nAck
, 0, TIME_PSetup
+TIME_PResponse
, minor
);
387 if (rc
== -1) return -EIO
;
389 /* A 1284 device cannot refuse nibble mode */
390 if (mode
== DEFAULT_NIBBLE
) return 0;
392 if (pins
& BPP_GP_Select
) return 0;
394 return -EPROTONOSUPPORT
;
397 static int terminate(unsigned minor
)
401 /* Event 22: Request termination of 1284 mode */
402 set_pins(BPP_PP_nAutoFd
|BPP_PP_nStrobe
|BPP_PP_nInit
, minor
);
404 /* Wait for Events 23 and 24: ACK termination request. */
405 rc
= wait_for(BPP_GP_Busy
|BPP_GP_nFault
,
407 TIME_PSetup
+TIME_PResponse
,
410 instances
[minor
].direction
= 0;
411 instances
[minor
].mode
= COMPATIBILITY
;
417 /* Event 25: Handshake by lowering nAutoFd */
418 set_pins(BPP_PP_nStrobe
|BPP_PP_nInit
, minor
);
420 /* Event 26: Peripheral wiggles lines... */
422 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
423 rc
= wait_for(BPP_GP_nAck
, 0, TIME_PResponse
, minor
);
425 set_pins(BPP_PP_nAutoFd
|BPP_PP_nStrobe
|BPP_PP_nInit
, minor
);
429 /* Event 28: Finish phase by raising nAutoFd */
430 set_pins(BPP_PP_nAutoFd
|BPP_PP_nStrobe
|BPP_PP_nInit
, minor
);
437 * Allow only one process to open the device at a time.
439 static int bpp_open(struct inode
*inode
, struct file
*f
)
441 unsigned minor
= MINOR(inode
->i_rdev
);
442 if (minor
>= BPP_NO
) return -ENODEV
;
443 if (! instances
[minor
].present
) return -ENODEV
;
444 if (instances
[minor
].opened
) return -EBUSY
;
446 instances
[minor
].opened
= 1;
452 * When the process closes the device, this method is called to clean
453 * up and reset the hardware. Always leave the device in compatibility
454 * mode as this is a reasonable place to clean up from messes made by
455 * ioctls, or other mayhem.
457 static int bpp_release(struct inode
*inode
, struct file
*f
)
459 unsigned minor
= MINOR(inode
->i_rdev
);
462 instances
[minor
].opened
= 0;
464 if (instances
[minor
].mode
!= COMPATIBILITY
)
470 static long read_nibble(unsigned minor
, char *c
, unsigned long cnt
)
472 unsigned long remaining
= cnt
;
475 while (remaining
> 0) {
476 unsigned char byte
= 0;
479 /* Event 7: request nibble */
480 set_pins(BPP_PP_nSelectIn
|BPP_PP_nStrobe
, minor
);
482 /* Wait for event 9: Peripher strobes first nibble */
483 pins
= wait_for(0, BPP_GP_nAck
, TIME_IDLE_LIMIT
, minor
);
484 if (pins
== -1) return -ETIMEDOUT
;
486 /* Event 10: I handshake nibble */
487 set_pins(BPP_PP_nSelectIn
|BPP_PP_nStrobe
|BPP_PP_nAutoFd
, minor
);
488 if (pins
& BPP_GP_nFault
) byte
|= 0x01;
489 if (pins
& BPP_GP_Select
) byte
|= 0x02;
490 if (pins
& BPP_GP_PError
) byte
|= 0x04;
491 if (pins
& BPP_GP_Busy
) byte
|= 0x08;
493 /* Wait for event 11: Peripheral handshakes nibble */
494 rc
= wait_for(BPP_GP_nAck
, 0, TIME_PResponse
, minor
);
496 /* Event 7: request nibble */
497 set_pins(BPP_PP_nSelectIn
|BPP_PP_nStrobe
, minor
);
499 /* Wait for event 9: Peripher strobes first nibble */
500 pins
= wait_for(0, BPP_GP_nAck
, TIME_PResponse
, minor
);
501 if (rc
== -1) return -ETIMEDOUT
;
503 /* Event 10: I handshake nibble */
504 set_pins(BPP_PP_nSelectIn
|BPP_PP_nStrobe
|BPP_PP_nAutoFd
, minor
);
505 if (pins
& BPP_GP_nFault
) byte
|= 0x10;
506 if (pins
& BPP_GP_Select
) byte
|= 0x20;
507 if (pins
& BPP_GP_PError
) byte
|= 0x40;
508 if (pins
& BPP_GP_Busy
) byte
|= 0x80;
510 if (put_user(byte
, c
))
515 /* Wait for event 11: Peripheral handshakes nibble */
516 rc
= wait_for(BPP_GP_nAck
, 0, TIME_PResponse
, minor
);
517 if (rc
== -1) return -EIO
;
520 return cnt
- remaining
;
523 static long read_ecp(unsigned minor
, char *c
, unsigned long cnt
)
525 unsigned long remaining
;
528 /* Turn ECP mode from forward to reverse if needed. */
529 if (! instances
[minor
].direction
) {
530 unsigned short pins
= get_pins(minor
);
532 /* Event 38: Turn the bus around */
533 instances
[minor
].direction
= 0x20;
534 pins
&= ~BPP_PP_nAutoFd
;
535 set_pins(pins
, minor
);
537 /* Event 39: Set pins for reverse mode. */
538 snooze(TIME_PSetup
, minor
);
539 set_pins(BPP_PP_nStrobe
|BPP_PP_nSelectIn
, minor
);
541 /* Wait for event 40: Peripheral ready to be strobed */
542 rc
= wait_for(0, BPP_GP_PError
, TIME_PResponse
, minor
);
543 if (rc
== -1) return -ETIMEDOUT
;
548 while (remaining
> 0) {
550 /* If there is a run length for a repeated byte, repeat */
551 /* that byte a few times. */
552 if (instances
[minor
].run_length
&& !instances
[minor
].run_flag
) {
556 unsigned repeat
= remaining
< instances
[minor
].run_length
558 : instances
[minor
].run_length
;
560 for (idx
= 0 ; idx
< repeat
; idx
+= 1)
561 buffer
[idx
] = instances
[minor
].repeat_byte
;
563 if (copy_to_user(c
, buffer
, repeat
))
567 instances
[minor
].run_length
-= repeat
;
570 if (remaining
== 0) break;
573 /* Wait for Event 43: Data active on the bus. */
574 rc
= wait_for(0, BPP_GP_nAck
, TIME_IDLE_LIMIT
, minor
);
577 if (rc
& BPP_GP_Busy
) {
578 /* OK, this is data. read it in. */
579 unsigned char byte
= bpp_inb(base_addrs
[minor
]);
580 if (put_user(byte
, c
))
585 if (instances
[minor
].run_flag
) {
586 instances
[minor
].repeat_byte
= byte
;
587 instances
[minor
].run_flag
= 0;
591 unsigned char byte
= bpp_inb(base_addrs
[minor
]);
594 "Ignoring ECP channel %u from device.\n",
597 instances
[minor
].run_length
= byte
;
598 instances
[minor
].run_flag
= 1;
602 /* Event 44: I got it. */
603 set_pins(BPP_PP_nStrobe
|BPP_PP_nAutoFd
|BPP_PP_nSelectIn
, minor
);
605 /* Wait for event 45: peripheral handshake */
606 rc
= wait_for(BPP_GP_nAck
, 0, TIME_PResponse
, minor
);
607 if (rc
== -1) return -ETIMEDOUT
;
609 /* Event 46: Finish handshake */
610 set_pins(BPP_PP_nStrobe
|BPP_PP_nSelectIn
, minor
);
615 return cnt
- remaining
;
618 static ssize_t
bpp_read(struct file
*f
, char *c
, size_t cnt
, loff_t
* ppos
)
621 const unsigned minor
= MINOR(f
->f_dentry
->d_inode
->i_rdev
);
622 if (minor
>= BPP_NO
) return -ENODEV
;
623 if (!instances
[minor
].present
) return -ENODEV
;
625 switch (instances
[minor
].mode
) {
628 if (instances
[minor
].mode
!= COMPATIBILITY
)
631 if (instances
[minor
].enhanced
) {
632 /* For now, do all reads with ECP-RLE mode */
635 rc
= negotiate(DEFAULT_ECP
, minor
);
638 instances
[minor
].mode
= ECP_RLE
;
640 /* Event 30: set nAutoFd low to setup for ECP mode */
641 pins
= get_pins(minor
);
642 pins
&= ~BPP_PP_nAutoFd
;
643 set_pins(pins
, minor
);
645 /* Wait for Event 31: peripheral ready */
646 rc
= wait_for(BPP_GP_PError
, 0, TIME_PResponse
, minor
);
647 if (rc
== -1) return -ETIMEDOUT
;
649 rc
= read_ecp(minor
, c
, cnt
);
652 rc
= negotiate(DEFAULT_NIBBLE
, minor
);
655 instances
[minor
].mode
= NIBBLE
;
657 rc
= read_nibble(minor
, c
, cnt
);
662 rc
= read_nibble(minor
, c
, cnt
);
667 rc
= read_ecp(minor
, c
, cnt
);
677 * Compatibility mode handshaking is a matter of writing data,
678 * strobing it, and waiting for the printer to stop being busy.
680 static long write_compat(unsigned minor
, const char *c
, unsigned long cnt
)
683 unsigned short pins
= get_pins(minor
);
685 unsigned long remaining
= cnt
;
688 while (remaining
> 0) {
691 if (get_user(byte
, c
))
695 rc
= wait_for(BPP_GP_nAck
, BPP_GP_Busy
, TIME_IDLE_LIMIT
, minor
);
696 if (rc
== -1) return -ETIMEDOUT
;
698 bpp_outb_p(byte
, base_addrs
[minor
]);
700 /* snooze(1, minor); */
702 pins
&= ~BPP_PP_nStrobe
;
703 set_pins(pins
, minor
);
705 rc
= wait_for(BPP_GP_Busy
, 0, TIME_PResponse
, minor
);
707 pins
|= BPP_PP_nStrobe
;
708 set_pins(pins
, minor
);
711 return cnt
- remaining
;
715 * Write data using ECP mode. Watch out that the port may be set up
716 * for reading. If so, turn the port around.
718 static long write_ecp(unsigned minor
, const char *c
, unsigned long cnt
)
720 unsigned short pins
= get_pins(minor
);
721 unsigned long remaining
= cnt
;
723 if (instances
[minor
].direction
) {
726 /* Event 47 Request bus be turned around */
727 pins
|= BPP_PP_nInit
;
728 set_pins(pins
, minor
);
730 /* Wait for Event 49: Peripheral relinquished bus */
731 rc
= wait_for(BPP_GP_PError
, 0, TIME_PResponse
, minor
);
733 pins
|= BPP_PP_nAutoFd
;
734 instances
[minor
].direction
= 0;
735 set_pins(pins
, minor
);
738 while (remaining
> 0) {
742 if (get_user(byte
, c
))
745 rc
= wait_for(0, BPP_GP_Busy
, TIME_PResponse
, minor
);
746 if (rc
== -1) return -ETIMEDOUT
;
750 bpp_outb_p(byte
, base_addrs
[minor
]);
752 pins
&= ~BPP_PP_nStrobe
;
753 set_pins(pins
, minor
);
755 pins
|= BPP_PP_nStrobe
;
756 rc
= wait_for(BPP_GP_Busy
, 0, TIME_PResponse
, minor
);
757 if (rc
== -1) return -EIO
;
759 set_pins(pins
, minor
);
762 return cnt
- remaining
;
766 * Write to the peripheral. Be sensitive of the current mode. If I'm
767 * in a mode that can be turned around (ECP) then just do
768 * that. Otherwise, terminate and do my writing in compat mode. This
769 * is the safest course as any device can handle it.
771 static ssize_t
bpp_write(struct file
*f
, const char *c
, size_t cnt
, loff_t
* ppos
)
774 const unsigned minor
= MINOR(f
->f_dentry
->d_inode
->i_rdev
);
775 if (minor
>= BPP_NO
) return -ENODEV
;
776 if (!instances
[minor
].present
) return -ENODEV
;
778 switch (instances
[minor
].mode
) {
782 errno
= write_ecp(minor
, c
, cnt
);
785 errno
= write_compat(minor
, c
, cnt
);
789 errno
= write_compat(minor
, c
, cnt
);
795 static int bpp_ioctl(struct inode
*inode
, struct file
*f
, unsigned int cmd
,
800 unsigned minor
= MINOR(inode
->i_rdev
);
801 if (minor
>= BPP_NO
) return -ENODEV
;
802 if (!instances
[minor
].present
) return -ENODEV
;
808 set_pins(arg
, minor
);
812 errno
= get_pins(minor
);
816 bpp_outb_p(arg
, base_addrs
[minor
]);
820 errno
= bpp_inb_p(base_addrs
[minor
]);
825 if (instances
[minor
].enhanced
) {
826 unsigned short bits
= get_pins(minor
);
827 instances
[minor
].direction
= 0x20;
828 set_pins(bits
, minor
);
833 unsigned short bits
= get_pins(minor
);
834 instances
[minor
].direction
= 0x00;
835 set_pins(bits
, minor
);
846 static struct file_operations bpp_fops
= {
852 release
: bpp_release
,
855 #if defined(__i386__)
857 #define collectLptPorts() {}
859 static void probeLptPort(unsigned idx
)
861 unsigned int testvalue
;
862 const unsigned short lpAddr
= base_addrs
[idx
];
864 instances
[idx
].present
= 0;
865 instances
[idx
].enhanced
= 0;
866 instances
[idx
].direction
= 0;
867 instances
[idx
].mode
= COMPATIBILITY
;
868 instances
[idx
].wait_queue
= 0;
869 instances
[idx
].run_length
= 0;
870 instances
[idx
].run_flag
= 0;
871 init_timer(&instances
[idx
].timer_list
);
872 instances
[idx
].timer_list
.function
= bpp_wake_up
;
873 if (check_region(lpAddr
,3)) return;
876 * First, make sure the instance exists. Do this by writing to
877 * the data latch and reading the value back. If the port *is*
878 * present, test to see if it supports extended-mode
879 * operation. This will be required for IEEE1284 reverse
883 outb_p(BPP_PROBE_CODE
, lpAddr
);
884 for (testvalue
=0; testvalue
<BPP_DELAY
; testvalue
++)
886 testvalue
= inb_p(lpAddr
);
887 if (testvalue
== BPP_PROBE_CODE
) {
889 instances
[idx
].present
= 1;
891 request_region(lpAddr
,3, dev_name
);
892 save
= inb_p(lpAddr
+2);
893 for (testvalue
=0; testvalue
<BPP_DELAY
; testvalue
++)
895 outb_p(save
|0x20, lpAddr
+2);
896 for (testvalue
=0; testvalue
<BPP_DELAY
; testvalue
++)
898 outb_p(~BPP_PROBE_CODE
, lpAddr
);
899 for (testvalue
=0; testvalue
<BPP_DELAY
; testvalue
++)
901 testvalue
= inb_p(lpAddr
);
902 if ((testvalue
&0xff) == (0xff&~BPP_PROBE_CODE
))
903 instances
[idx
].enhanced
= 0;
905 instances
[idx
].enhanced
= 1;
906 outb_p(save
, lpAddr
+2);
910 * Leave the port in compat idle mode.
912 set_pins(BPP_PP_nAutoFd
|BPP_PP_nStrobe
|BPP_PP_nInit
, idx
);
914 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx
, base_addrs
[idx
],
915 instances
[idx
].enhanced
? "SUPPORTED" : "UNAVAILABLE");
918 static inline void freeLptPort(int idx
)
920 release_region(base_addrs
[idx
], 3);
925 #if defined(__sparc__)
927 static unsigned long map_bpp(struct sbus_dev
*dev
, int idx
)
929 return sbus_ioremap(&dev
->resource
[0], 0, BPP_SIZE
, "bpp");
932 static int collectLptPorts(void)
934 struct sbus_bus
*bus
;
935 struct sbus_dev
*dev
;
939 for_all_sbusdev(dev
, bus
) {
940 if (strcmp(dev
->prom_name
, "SUNW,bpp") == 0) {
941 if (count
>= BPP_NO
) {
943 "bpp: More than %d bpp ports,"
944 " rest is ignored\n", BPP_NO
);
947 base_addrs
[count
] = map_bpp(dev
, count
);
954 static void probeLptPort(unsigned idx
)
956 unsigned long rp
= base_addrs
[idx
];
960 instances
[idx
].present
= 0;
961 instances
[idx
].enhanced
= 0;
962 instances
[idx
].direction
= 0;
963 instances
[idx
].mode
= COMPATIBILITY
;
964 init_waitqueue_head(&instances
[idx
].wait_queue
);
965 instances
[idx
].run_length
= 0;
966 instances
[idx
].run_flag
= 0;
967 init_timer(&instances
[idx
].timer_list
);
968 instances
[idx
].timer_list
.function
= bpp_wake_up
;
972 instances
[idx
].present
= 1;
973 instances
[idx
].enhanced
= 1; /* Sure */
975 csr
= sbus_readl(rp
+ BPP_CSR
);
976 if ((csr
& P_DRAINING
) != 0 && (csr
& P_ERR_PEND
) == 0) {
978 csr
= sbus_readl(rp
+ BPP_CSR
);
979 if ((csr
& P_DRAINING
) != 0 && (csr
& P_ERR_PEND
) == 0) {
980 printk("bpp%d: DRAINING still active (0x%08x)\n", idx
, csr
);
983 printk("bpp%d: reset with 0x%08x ..", idx
, csr
);
984 sbus_writel((csr
| P_RESET
) & ~P_INT_EN
, rp
+ BPP_CSR
);
986 sbus_writel(sbus_readl(rp
+ BPP_CSR
) & ~P_RESET
, rp
+ BPP_CSR
);
987 csr
= sbus_readl(rp
+ BPP_CSR
);
988 printk(" done with csr=0x%08x ocr=0x%04x\n",
989 csr
, sbus_readw(rp
+ BPP_OCR
));
991 switch (csr
& P_DEV_ID_MASK
) {
995 case P_DEV_ID_L64854
:
1001 printk("bpp%d: %s at 0x%lx\n", idx
, brand
, rp
);
1004 * Leave the port in compat idle mode.
1006 set_pins(BPP_PP_nAutoFd
|BPP_PP_nStrobe
|BPP_PP_nInit
, idx
);
1011 static inline void freeLptPort(int idx
)
1013 sbus_iounmap(base_addrs
[idx
], BPP_SIZE
);
1018 static devfs_handle_t devfs_handle
;
1020 static int __init
bpp_init(void)
1025 rc
= collectLptPorts();
1029 rc
= devfs_register_chrdev(BPP_MAJOR
, dev_name
, &bpp_fops
);
1033 for (idx
= 0; idx
< BPP_NO
; idx
+= 1) {
1034 instances
[idx
].opened
= 0;
1037 devfs_handle
= devfs_mk_dir (NULL
, "bpp", NULL
);
1038 devfs_register_series (devfs_handle
, "%u", BPP_NO
, DEVFS_FL_DEFAULT
,
1039 BPP_MAJOR
, 0, S_IFCHR
| S_IRUSR
| S_IWUSR
,
1045 static void __exit
bpp_cleanup(void)
1049 devfs_unregister (devfs_handle
);
1050 devfs_unregister_chrdev(BPP_MAJOR
, dev_name
);
1052 for (idx
= 0 ; idx
< BPP_NO
; idx
+= 1) {
1053 if (instances
[idx
].present
)
1058 module_init(bpp_init
);
1059 module_exit(bpp_cleanup
);