2 ** PCI Lower Bus Adapter (LBA) manager
4 ** (c) Copyright 1999,2000 Grant Grundler
5 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
13 ** This module primarily provides access to PCI bus (config/IOport
14 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
15 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
17 ** LBA driver isn't as simple as the Dino driver because:
18 ** (a) this chip has substantial bug fixes between revisions
19 ** (Only one Dino bug has a software workaround :^( )
20 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
21 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
22 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
23 ** (dino only deals with "Legacy" PDC)
25 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
26 ** (I/O SAPIC is integratd in the LBA chip).
28 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
29 ** FIXME: Add support for PCI card hot-plug (OLARD).
32 #include <linux/config.h>
33 #include <linux/delay.h>
34 #include <linux/types.h>
35 #include <linux/kernel.h>
36 #include <linux/spinlock.h>
37 #include <linux/init.h> /* for __init and __devinit */
38 #include <linux/pci.h>
39 #include <linux/ioport.h>
40 #include <linux/malloc.h>
41 #include <linux/smp_lock.h>
43 #include <asm/byteorder.h>
44 #include <asm/irq.h> /* for struct irq_region support */
46 #include <asm/pdcpat.h>
48 #include <asm/segment.h>
49 #include <asm/system.h>
51 #include <asm/hardware.h> /* for register_driver() stuff */
52 #include <asm/iosapic.h> /* for iosapic_register() */
53 #include <asm/gsc.h> /* gsc_read/write stuff */
58 #define FALSE (1 == 0)
61 #undef DEBUG_LBA /* general stuff */
62 #undef DEBUG_LBA_PORT /* debug I/O Port access */
63 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
64 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
67 #define DBG(x...) printk(x)
73 #define DBG_PORT(x...) printk(x)
75 #define DBG_PORT(x...)
79 #define DBG_CFG(x...) printk(x)
85 #define DBG_PAT(x...) printk(x)
91 ** Config accessor functions only pass in the 8-bit bus number and not
92 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
93 ** number based on what firmware wrote into the scratch register.
95 ** The "secondary" bus number is set to this before calling
96 ** pci_register_ops(). If any PPB's are present, the scan will
97 ** discover them and update the "secondary" and "subordinate"
98 ** fields in the pci_bus structure.
100 ** Changes in the configuration *may* result in a different
101 ** bus number for each LBA depending on what firmware does.
104 #define MODULE_NAME "lba"
106 static int lba_driver_callback(struct hp_device
*, struct pa_iodc_driver
*);
109 static struct pa_iodc_driver lba_drivers_for
[]= {
111 {HPHW_BRIDGE
, 0x782, 0x0, 0xa, 0,0,
112 DRIVER_CHECK_HVERSION
+
113 DRIVER_CHECK_SVERSION
+ DRIVER_CHECK_HWTYPE
,
114 MODULE_NAME
, "tbd", (void *) lba_driver_callback
},
118 (char *) NULL
, (char *) NULL
, (void *) NULL
}
122 #define LBA_FUNC_ID 0x0000 /* function id */
123 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
124 #define LBA_CAPABLE 0x0030 /* capabilities register */
126 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
127 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
129 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
130 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
131 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
133 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
134 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
135 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
136 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
138 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
140 #define LBA_STAT_CTL 0x0108 /* Status & Control */
141 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
143 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
144 #define LBA_LMMIO_MASK 0x0208
146 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
147 #define LBA_GMMIO_MASK 0x0218
149 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
150 #define LBA_WLMMIO_MASK 0x0228
152 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
153 #define LBA_WGMMIO_MASK 0x0238
155 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
156 #define LBA_IOS_MASK 0x0248
158 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
159 #define LBA_ELMMIO_MASK 0x0258
161 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
162 #define LBA_EIOS_MASK 0x0268
164 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
166 /* RESET: ignore DMA stuff until we can measure performance */
167 #define LBA_IBASE 0x0300 /* DMA support */
168 #define LBA_IMASK 0x0308
169 #define LBA_HINT_CFG 0x0310
170 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
172 /* ERROR regs are needed for config cycle kluges */
173 #define LBA_ERROR_CONFIG 0x0680
174 #define LBA_ERROR_STATUS 0x0688
176 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
178 /* non-postable I/O port space, densely packed */
180 #define LBA_ASTRO_PORT_BASE (0xfffffffffee00000UL)
182 #define LBA_ASTRO_PORT_BASE (0xfee00000UL)
187 ** lba_device: Per instance Elroy data structure
190 struct pci_hba_data hba
;
196 unsigned long lmmio_base
; /* PA_VIEW - fixup MEM addresses */
197 unsigned long gmmio_base
; /* PA_VIEW - Not used (yet) */
198 unsigned long iop_base
; /* PA_VIEW - for IO port accessor funcs */
201 int flags
; /* state/functionality enabled */
202 int hw_rev
; /* HW revision of chip */
211 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
212 #define LBA_FLAG_SKIP_PROBE 0x10
214 /* Tape Release 4 == hw_rev 5 */
215 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
216 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
217 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
220 /* Looks nice and keeps the compiler happy */
221 #define LBA_DEV(d) ((struct lba_device *) (d))
225 ** Only allow 8 subsidiary busses per LBA
226 ** Problem is the PCI bus numbering is globally shared.
228 #define LBA_MAX_NUM_BUSES 8
230 /************************************
231 * LBA register read and write support
233 * BE WARNED: register writes are posted.
234 * (ie follow writes which must reach HW with a read)
236 #define READ_U8(addr) gsc_readb(addr)
237 #define READ_U16(addr) gsc_readw((u16 *) (addr))
238 #define READ_U32(addr) gsc_readl((u32 *) (addr))
239 #define WRITE_U8(value, addr) gsc_writeb(value, addr)
240 #define WRITE_U16(value, addr) gsc_writew(value, (u16 *) (addr))
241 #define WRITE_U32(value, addr) gsc_writel(value, (u32 *) (addr))
243 #define READ_REG8(addr) gsc_readb(addr)
244 #define READ_REG16(addr) le16_to_cpu(gsc_readw((u16 *) (addr)))
245 #define READ_REG32(addr) le32_to_cpu(gsc_readl((u32 *) (addr)))
246 #define WRITE_REG8(value, addr) gsc_writeb(value, addr)
247 #define WRITE_REG16(value, addr) gsc_writew(cpu_to_le16(value), (u16 *) (addr))
248 #define WRITE_REG32(value, addr) gsc_writel(cpu_to_le32(value), (u32 *) (addr))
251 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
252 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
253 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
254 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
258 /* Extract LBA (Rope) number from HPA */
259 #define LBA_NUM(x) ((((uintptr_t) x) >> 13) & 0xf)
260 #endif /* DEBUG_LBA */
264 static unsigned long pdc_result
[32] __attribute__ ((aligned (8))) = {0,0,0,0};
268 ** One time initialization to let the world know the LBA was found.
269 ** This is the only routine which is NOT static.
270 ** Must be called exactly once before pci_init().
272 void __init
lba_init(void)
274 register_driver(lba_drivers_for
);
279 lba_dump_res(struct resource
*r
, int d
)
286 printk("(%p)", r
->parent
);
287 for (i
= d
; i
; --i
) printk(" ");
288 printk("%p [%lx,%lx]/%x\n", r
, r
->start
, r
->end
, (int) r
->flags
);
289 lba_dump_res(r
->child
, d
+2);
290 lba_dump_res(r
->sibling
, d
);
295 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
296 ** workaround for cfg cycles:
297 ** -- preserve LBA state
298 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
299 ** -- turn on smart mode
300 ** -- probe with config writes before doing config reads
301 ** -- check ERROR_STATUS
302 ** -- clear ERROR_STATUS
303 ** -- restore LBA state
305 ** The workaround is only used for device discovery.
309 lba_device_present( u8 bus
, u8 dfn
, struct lba_device
*d
)
311 u8 first_bus
= d
->hba
.hba_bus
->secondary
;
312 u8 last_sub_bus
= d
->hba
.hba_bus
->subordinate
;
314 /* FIXME - see below in this function */
315 u8 dev
= PCI_SLOT(dfn
);
316 u8 func
= PCI_FUNC(dfn
);
319 ASSERT(bus
>= first_bus
);
320 ASSERT(bus
<= last_sub_bus
);
321 ASSERT((bus
- first_bus
) < LBA_MAX_NUM_BUSES
);
323 if ((bus
< first_bus
) ||
324 (bus
> last_sub_bus
) ||
325 ((bus
- first_bus
) >= LBA_MAX_NUM_BUSES
))
327 /* devices that fall into any of these cases won't get claimed */
333 ** FIXME: Need to implement code to fill the devices bitmap based
334 ** on contents of the local pci_bus tree "data base".
335 ** pci_register_ops() walks the bus for us and builds the tree.
336 ** For now, always do the config cycle.
340 return (((d
->devices
[bus
][dev
]) >> func
) & 0x1);
348 #define LBA_CFG_SETUP(d, tok) { \
349 /* Save contents of error config register. */ \
350 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
352 /* Save contents of status control register. */ \
353 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
355 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
356 ** arbitration for full bus walks. \
358 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
359 /* Save contents of arb mask register. */ \
360 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
363 * Turn off all device arbitration bits (i.e. everything \
364 * except arbitration enable bit). \
366 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
370 * Set the smart mode bit so that master aborts don't cause \
371 * LBA to go into PCI fatal mode (required). \
373 WRITE_REG32(error_config | 0x20, d->hba.base_addr + LBA_ERROR_CONFIG); \
377 #define LBA_CFG_PROBE(d, tok) { \
379 * Setup Vendor ID write and read back the address register \
380 * to make sure that LBA is the bus master. \
382 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
384 * Read address register to ensure that LBA is the bus master, \
385 * which implies that DMA traffic has stopped when DMA arb is off. \
387 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
389 * Generate a cfg write cycle (will have no affect on \
390 * Vendor ID register since read-only). \
392 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
394 * Make sure write has completed before proceeding further, \
395 * i.e. before setting clear enable. \
397 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
403 * -- Can't tell if config cycle got the error.
405 * OV bit is broken until rev 4.0, so can't use OV bit and
406 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
408 * As of rev 4.0, no longer need the error check.
410 * -- Even if we could tell, we still want to return -1
411 * for **ANY** error (not just master abort).
413 * -- Only clear non-fatal errors (we don't want to bring
414 * LBA out of pci-fatal mode).
416 * Actually, there is still a race in which
417 * we could be clearing a fatal error. We will
418 * live with this during our real mode bus walk
419 * until rev 4.0 (no driver activity during
420 * real mode bus walk). The real mode bus walk
421 * has race conditions concerning the use of
422 * smart mode as well.
425 #define LBA_MASTER_ABORT_ERROR 0xc
426 #define LBA_FATAL_ERROR 0x10
428 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
429 u32 error_status = 0; \
431 * Set clear enable (CE) bit. Unset by HW when new \
432 * errors are logged -- LBA HW ERS section 14.3.3). \
434 WRITE_REG32(status_control | 0x20, base + LBA_STAT_CTL); \
435 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
436 if ((error_status & 0x1f) != 0) { \
438 * Fail the config read request. \
441 if ((error_status & LBA_FATAL_ERROR) == 0) { \
443 * Clear error status (if fatal bit not set) by setting \
444 * clear error log bit (CL). \
446 WRITE_REG32(status_control | 0x10, base + LBA_STAT_CTL); \
451 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
452 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR)
454 #define LBA_CFG_ADDR_SETUP(d, addr) { \
455 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
458 * -- Potentially could skip this once DMA bug fixed. \
460 * Read address register to ensure that LBA is the bus master, \
461 * which implies that DMA traffic has stopped when DMA arb is off. \
463 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
467 #define LBA_CFG_RESTORE(d, base) { \
469 * Restore status control register (turn off clear enable). \
471 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
473 * Restore error config register (turn off smart mode). \
475 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
476 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
478 * Restore arb mask register (reenables DMA arbitration). \
480 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
487 lba_rd_cfg( struct lba_device
*d
, u32 tok
, u8 reg
, u32 size
)
491 u32 arb_mask
= 0; /* used by LBA_CFG_SETUP/RESTORE */
492 u32 error_config
= 0; /* used by LBA_CFG_SETUP/RESTORE */
493 u32 status_control
= 0; /* used by LBA_CFG_SETUP/RESTORE */
495 ASSERT((size
== sizeof(u8
)) ||
496 (size
== sizeof(u16
)) ||
497 (size
== sizeof(u32
)));
499 if ((size
!= sizeof(u8
)) &&
500 (size
!= sizeof(u16
)) &&
501 (size
!= sizeof(u32
))) {
505 LBA_CFG_SETUP(d
, tok
);
506 LBA_CFG_PROBE(d
, tok
);
507 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
509 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
512 data
= (u32
) READ_REG8(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
& 3));
515 data
= (u32
) READ_REG16(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
& 2));
518 data
= READ_REG32(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
521 break; /* leave data as -1 */
524 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
530 #define LBA_CFG_RD(size, mask) \
531 static int lba_cfg_read##size (struct pci_dev *dev, int pos, u##size *data) \
533 struct lba_device *d = LBA_DEV(dev->bus->sysdata); \
534 u32 local_bus = (dev->bus->parent == NULL) ? 0 : dev->bus->secondary; \
535 u32 tok = LBA_CFG_TOK(local_bus,dev->devfn); \
537 if ((!LBA_TR4PLUS(d)) && (!LBA_SKIP_PROBE(d))) { \
538 /* original - Generate config cycle on broken elroy \
539 with risk we will miss PCI bus errors. */ \
540 *data = (u##size) lba_rd_cfg(d, tok, pos, sizeof(u##size)); \
541 DBG_CFG(KERN_DEBUG "%s(%s+%2x) -> 0x%x (a)\n", __FUNCTION__, dev->slot_name, pos, *data); \
542 return(*data == (u##size) -1); \
545 if (LBA_SKIP_PROBE(d) && (!lba_device_present(dev->bus->secondary, dev->devfn, d))) \
547 DBG_CFG(KERN_DEBUG "%s(%s+%2x) -> -1 (b)\n", __FUNCTION__, dev->slot_name, pos, *data); \
548 /* either don't want to look or know device isn't present. */ \
549 *data = (u##size) -1; \
554 ** Should only get here on fully working LBA rev. \
555 ** This is how simple the code should have been. \
557 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); \
558 *data = READ_REG##size(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & mask));\
559 DBG_CFG(KERN_DEBUG "%s(%s+%2x) -> 0x%x (c)\n", __FUNCTION__, dev->slot_name, pos, *data);\
560 return(*data == (u##size) -1); \
570 lba_wr_cfg( struct lba_device
*d
, u32 tok
, u8 reg
, u32 data
, u32 size
)
574 u32 error_config
= 0;
575 u32 status_control
= 0;
577 ASSERT((size
== sizeof(u8
)) ||
578 (size
== sizeof(u16
)) ||
579 (size
== sizeof(u32
)));
581 if ((size
!= sizeof(u8
)) &&
582 (size
!= sizeof(u16
)) &&
583 (size
!= sizeof(u32
))) {
587 LBA_CFG_SETUP(d
, tok
);
588 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
591 WRITE_REG8((u8
) data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
&3));
594 WRITE_REG16((u8
) data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+(reg
&2));
597 WRITE_REG32(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
602 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
603 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
608 * LBA 4.0 config write code implements non-postable semantics
609 * by doing a read of CONFIG ADDR after the write.
612 #define LBA_CFG_WR(size, mask) \
613 static int lba_cfg_write##size (struct pci_dev *dev, int pos, u##size data) \
615 struct lba_device *d = LBA_DEV(dev->bus->sysdata); \
616 u32 local_bus = (dev->bus->parent == NULL) ? 0 : dev->bus->secondary; \
617 u32 tok = LBA_CFG_TOK(local_bus,dev->devfn); \
619 ASSERT((tok & 0xff) == 0); \
620 ASSERT(pos < 0x100); \
622 if ((!LBA_TR4PLUS(d)) && (!LBA_SKIP_PROBE(d))) { \
623 /* Original Workaround */ \
624 lba_wr_cfg(d, tok, pos, (u32) data, sizeof(u##size)); \
625 DBG_CFG(KERN_DEBUG "%s(%s+%2x) = 0x%x (a)\n", __FUNCTION__, dev->slot_name, pos, data); \
629 if (LBA_SKIP_PROBE(d) && (!lba_device_present(dev->bus->secondary, dev->devfn, d))) { \
630 DBG_CFG(KERN_DEBUG "%s(%s+%2x) = 0x%x (b)\n", __FUNCTION__, dev->slot_name, pos, data); \
631 return 1; /* New Workaround */ \
634 DBG_CFG(KERN_DEBUG "%s(%s+%2x) = 0x%x (c)\n", __FUNCTION__, dev->slot_name, pos, data); \
635 /* Basic Algorithm */ \
636 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); \
637 WRITE_REG##size(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & mask)); \
638 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); \
647 static struct pci_ops lba_cfg_ops
= {
648 lba_cfg_read8
, lba_cfg_read16
, lba_cfg_read32
,
649 lba_cfg_write8
, lba_cfg_write16
, lba_cfg_write32
658 DBG(KERN_DEBUG MODULE_NAME
": lba_bios_init\n");
665 ** Determine if a device is already configured.
666 ** If so, reserve it resources.
668 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
669 ** PAT has to enable the devices it's using.
671 ** Note: resources are fixed up before we try to claim them.
674 lba_claim_dev_resources(struct pci_dev
*dev
)
679 (void) lba_cfg_read16(dev
, PCI_COMMAND
, &cmd
);
681 srch_flags
= (cmd
& PCI_COMMAND_IO
) ? IORESOURCE_IO
: 0;
682 if (cmd
& PCI_COMMAND_MEMORY
)
683 srch_flags
|= IORESOURCE_MEM
;
688 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
689 if (dev
->resource
[i
].flags
& srch_flags
) {
690 pci_claim_resource(dev
, i
);
691 DBG(" claimed %s %d [%lx,%lx]/%x\n",
693 dev
->resource
[i
].start
,
694 dev
->resource
[i
].end
,
695 (int) dev
->resource
[i
].flags
704 ** The algorithm is generic code.
705 ** But it needs to access local data structures to get the IRQ base.
706 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
709 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
710 ** Resources aren't allocated until recursive buswalk below HBA is completed.
713 lba_fixup_bus(struct pci_bus
*bus
)
715 struct list_head
*ln
;
717 u16 fbb_enable
= PCI_STATUS_FAST_BACK
;
719 struct lba_device
*ldev
= LBA_DEV(bus
->sysdata
);
723 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
724 bus
, bus
->secondary
, bus
->sysdata
);
727 ** Properly Setup MMIO resources for this bus.
728 ** pci_alloc_primary_bus() mangles this.
730 if (NULL
== bus
->self
) {
733 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
734 ldev
->hba
.io_space
.name
,
735 ldev
->hba
.io_space
.start
,
736 ldev
->hba
.io_space
.end
,
737 (int) ldev
->hba
.io_space
.flags
);
738 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
739 ldev
->hba
.mem_space
.name
,
740 ldev
->hba
.mem_space
.start
,
741 ldev
->hba
.mem_space
.end
,
742 (int) ldev
->hba
.mem_space
.flags
);
744 err
= request_resource(&ioport_resource
, &(ldev
->hba
.io_space
));
747 lba_dump_res(&ioport_resource
, 2);
749 err
= request_resource(&iomem_resource
, &(ldev
->hba
.mem_space
));
752 lba_dump_res(&iomem_resource
, 2);
755 bus
->resource
[0] = &(ldev
->hba
.io_space
);
756 bus
->resource
[1] = &(ldev
->hba
.mem_space
);
759 list_for_each(ln
, &bus
->devices
) {
765 ** 0-5 are the "standard PCI regions"
766 ** (see comments near PCI_NUM_RESOURCES in include/linux/pci.h)
768 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
769 struct resource
*res
= &(dev
->resource
[i
]);
771 if (res
->flags
& IORESOURCE_MEM
) {
772 /* "Globalize" PCI address */
773 res
->start
|= ldev
->lmmio_base
;
774 res
->end
|= ldev
->lmmio_base
;
780 ** If one device does not support FBB transfers,
781 ** No one on the bus can be allowed to use them.
783 (void) lba_cfg_read16(dev
, PCI_STATUS
, &status
);
784 fbb_enable
&= status
;
788 /* Claim resources for PDC's devices */
789 lba_claim_dev_resources(dev
);
791 #endif /* __LP64__ */
794 ** P2PB's have no IRQs. ignore them.
796 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
)
799 /* Adjust INTERRUPT_LINE for this dev */
800 iosapic_fixup_irq(LBA_DEV(bus
->sysdata
)->iosapic_obj
, dev
);
804 /* FIXME/REVISIT - finish figuring out to set FBB on both
805 ** pbus_set_ranges() clobbers PCI_BRIDGE_CONTROL.
806 ** Can't fixup here anyway....garr...
812 (void) lba_cfg_read8(bus
->self
, PCI_BRIDGE_CONTROL
, &control
);
813 (void) lba_cfg_write8(bus
->self
, PCI_BRIDGE_CONTROL
, control
| PCI_STATUS_FAST_BACK
);
818 fbb_enable
= PCI_COMMAND_FAST_BACK
;
821 /* Lastly enable FBB/PERR/SERR on all devices too */
822 list_for_each(ln
, &bus
->devices
) {
823 (void) lba_cfg_read16(dev
, PCI_COMMAND
, &status
);
824 status
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| fbb_enable
;
825 (void) lba_cfg_write16(dev
, PCI_COMMAND
, status
);
831 struct pci_bios_ops lba_bios_ops
= {
833 lba_fixup_bus
/* void lba_fixup_bus(struct pci_bus *bus) */
839 /*******************************************************
841 ** LBA Sprockets "I/O Port" Space Accessor Functions
843 ** This set of accessor functions is intended for use with
844 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
846 ** Many PCI devices don't require use of I/O port space (eg Tulip,
847 ** NCR720) since they export the same registers to both MMIO and
848 ** I/O port space. In general I/O port space is slower than
849 ** MMIO since drivers are designed so PIO writes can be posted.
851 ********************************************************/
853 #define LBA_PORT_IN(size, mask) \
854 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
857 ASSERT(bus != NULL); \
858 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x) ->", __FUNCTION__, bus, addr); \
859 t = READ_REG##size(LBA_ASTRO_PORT_BASE + addr); \
860 DBG_PORT(" 0x%x\n", t); \
871 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
873 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
874 ** guarantee non-postable completion semantics - not avoid X4107.
875 ** The READ_U32 only guarantees the write data gets to elroy but
876 ** out to the PCI bus. We can't read stuff from I/O port space
877 ** since we don't know what has side-effects. Attempting to read
878 ** from configuration space would be suicidal given the number of
879 ** bugs in that elroy functionality.
882 ** DMA read results can improperly pass PIO writes (X4107). The
883 ** result of this bug is that if a processor modifies a location in
884 ** memory after having issued PIO writes, the PIO writes are not
885 ** guaranteed to be completed before a PCI device is allowed to see
886 ** the modified data in a DMA read.
888 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
892 ** The workaround for this bug is to always follow a PIO write with
893 ** a PIO read to the same bus before starting DMA on that PCI bus.
896 #define LBA_PORT_OUT(size, mask) \
897 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
899 ASSERT(bus != NULL); \
900 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
901 WRITE_REG##size(val, LBA_ASTRO_PORT_BASE + addr); \
902 if (LBA_DEV(d)->hw_rev < 3) \
903 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
911 static struct pci_port_ops lba_astro_port_ops
= {
912 lba_astro_in8
, lba_astro_in16
, lba_astro_in32
,
913 lba_astro_out8
, lba_astro_out16
, lba_astro_out32
919 #define PIOP_TO_GMMIO(lba, addr) \
920 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
922 /*******************************************************
924 ** LBA PAT "I/O Port" Space Accessor Functions
926 ** This set of accessor functions is intended for use with
927 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
929 ** This uses the PIOP space located in the first 64MB of GMMIO.
930 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
931 ** bits 1:0 stay the same. bits 15:2 become 25:12.
932 ** Then add the base and we can generate an I/O Port cycle.
933 ********************************************************/
935 #define LBA_PORT_IN(size, mask) \
936 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
939 ASSERT(bus != NULL); \
940 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
941 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
942 DBG_PORT(" 0x%x\n", t); \
952 #define LBA_PORT_OUT(size, mask) \
953 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
955 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
956 ASSERT(bus != NULL); \
957 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
958 WRITE_REG##size(val, where); \
959 /* flush the I/O down to the elroy at least */ \
960 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
968 static struct pci_port_ops lba_pat_port_ops
= {
969 lba_pat_in8
, lba_pat_in16
, lba_pat_in32
,
970 lba_pat_out8
, lba_pat_out16
, lba_pat_out32
976 ** make range information from PDC available to PCI subsystem.
977 ** We make the PDC call here in order to get the PCI bus range
978 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
979 ** We don't have a struct pci_bus assigned to us yet.
982 lba_pat_resources( struct hp_device
*d
, struct lba_device
*lba_dev
)
984 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell
; /* PA_VIEW */
985 #ifdef DONT_NEED_THIS_FOR_ASTRO
986 pdc_pat_cell_mod_maddr_block_t io_pdc_cell
; /* IO_VIEW */
989 long status
; /* PDC return status */
993 /* return cell module (IO view) */
994 status
= pdc_pat_cell_module(& pdc_result
, d
->pcell_loc
, d
->mod_index
,
995 PA_VIEW
, & pa_pdc_cell
);
996 pa_count
= pa_pdc_cell
.mod
[1];
998 #ifdef DONT_NEED_THIS_FOR_ASTRO
999 status
|= pdc_pat_cell_module(& pdc_result
, d
->pcell_loc
, d
->mod_index
,
1000 IO_VIEW
, & io_pdc_cell
);
1001 io_count
= io_pdc_cell
.mod
[1];
1004 /* We've already done this once for device discovery...*/
1005 if (status
!= PDC_RET_OK
) {
1006 panic("pdc_pat_cell_module() call failed for LBA!\n");
1009 if (PAT_GET_ENTITY(pa_pdc_cell
.mod_info
) != PAT_ENTITY_LBA
) {
1010 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1014 ** Inspect the resources PAT tells us about
1016 for (i
= 0; i
< pa_count
; i
++) {
1019 unsigned long start
;
1020 unsigned long end
; /* aka finish */
1024 p
= (void *) &(pa_pdc_cell
.mod
[2+i
*3]);
1026 /* Convert the PAT range data to PCI "struct resource" */
1027 switch(p
->type
& 0xff) {
1029 lba_dev
->hba
.bus_num
.start
= p
->start
;
1030 lba_dev
->hba
.bus_num
.end
= p
->end
;
1033 /* used to fix up pre-initialized MEM BARs */
1034 lba_dev
->lmmio_base
= p
->start
;
1036 r
= &(lba_dev
->hba
.mem_space
);
1037 r
->name
= "LBA LMMIO";
1038 r
->start
= p
->start
;
1040 r
->flags
= IORESOURCE_MEM
;
1041 r
->parent
= r
->sibling
= r
->child
= NULL
;
1044 printk(KERN_WARNING MODULE_NAME
1045 " range[%d] : ignoring GMMIO (0x%lx)\n",
1047 lba_dev
->gmmio_base
= p
->start
;
1050 printk(KERN_WARNING MODULE_NAME
1051 " range[%d] : ignoring NPIOP (0x%lx)\n",
1056 ** Postable I/O port space is per PCI host adapter.
1059 /* save base of 64MB PIOP region */
1060 lba_dev
->iop_base
= p
->start
;
1062 r
= &(lba_dev
->hba
.io_space
);
1063 r
->name
= "LBA I/O Port";
1064 r
->start
= lba_dev
->hba
.hba_num
<< 16;
1065 r
->end
= r
->start
+ 0xffffUL
;
1066 r
->flags
= IORESOURCE_IO
;
1067 r
->parent
= r
->sibling
= r
->child
= NULL
;
1070 printk(KERN_WARNING MODULE_NAME
1071 " range[%d] : unknown pat range type (0x%lx)\n",
1077 #endif /* __LP64__ */
1081 lba_legacy_resources( struct hp_device
*d
, struct lba_device
*lba_dev
)
1087 ** Used to sign extend instead BAR values are only 32-bit.
1088 ** 64-bit BARs have the upper 32-bit's zero'd by firmware.
1089 ** "Sprockets" PDC initializes for 32-bit OS.
1091 lba_dev
->lmmio_base
= 0xffffffff00000000UL
;
1095 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1096 ** represents bus->secondary and the second byte represents
1097 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1098 ** PCI bus walk *should* end up with the same result.
1099 ** FIXME: But we don't have sanity checks in PCI or LBA.
1101 lba_num
= READ_REG32(d
->hpa
+ LBA_FW_SCRATCH
);
1102 r
= &(lba_dev
->hba
.bus_num
);
1103 r
->name
= "LBA PCI Busses";
1104 r
->start
= lba_num
& 0xff;
1105 r
->end
= (lba_num
>>8) & 0xff;
1107 /* Set up local PCI Bus resources - we don't really need
1108 ** them for Legacy boxes but it's nice to see in /proc.
1110 r
= &(lba_dev
->hba
.mem_space
);
1111 r
->name
= "LBA PCI LMMIO";
1112 r
->flags
= IORESOURCE_MEM
;
1113 r
->start
= READ_REG32(d
->hpa
+ LBA_LMMIO_BASE
);
1114 r
->end
= r
->start
+ ~ (READ_REG32(d
->hpa
+ LBA_LMMIO_MASK
));
1116 r
= &(lba_dev
->hba
.io_space
);
1117 r
->name
= "LBA PCI I/O Ports";
1118 r
->flags
= IORESOURCE_IO
;
1119 r
->start
= READ_REG32(d
->hpa
+ LBA_IOS_BASE
);
1120 r
->end
= r
->start
+ (READ_REG32(d
->hpa
+ LBA_IOS_MASK
) ^ 0xffff);
1122 lba_num
= lba_dev
->hba
.hba_num
<< 16;
1123 r
->start
|= lba_num
;
1128 /**************************************************************************
1130 ** LBA initialization code (HW and SW)
1132 ** o identify LBA chip itself
1133 ** o initialize LBA chip modes (HardFail)
1134 ** o FIXME: initialize DMA hints for reasonable defaults
1135 ** o enable configuration functions
1136 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1138 **************************************************************************/
1141 lba_hw_init(struct lba_device
*d
)
1145 /* Set HF mode as the default (vs. -1 mode). */
1146 stat
= READ_REG32(d
->hba
.base_addr
+ LBA_STAT_CTL
);
1147 WRITE_REG32(stat
| HF_ENABLE
, d
->hba
.base_addr
+ LBA_STAT_CTL
);
1150 ** FIXME: Hint registers are programmed with default hint
1151 ** values by firmware. Hints should be sane even if we
1152 ** can't reprogram them the way drivers want.
1159 lba_common_init(struct lba_device
*lba_dev
)
1161 pci_bios
= &lba_bios_ops
;
1162 pcibios_register_hba((struct pci_hba_data
*)lba_dev
);
1163 lba_dev
->lba_lock
= SPIN_LOCK_UNLOCKED
;
1166 ** Set flags which depend on hw_rev
1168 if (!LBA_TR4PLUS(lba_dev
)) {
1169 lba_dev
->flags
|= LBA_FLAG_NO_DMA_DURING_CFG
;
1176 ** Determine if lba should claim this chip (return 0) or not (return 1).
1177 ** If so, initialize the chip and tell other partners in crime they
1181 lba_driver_callback(struct hp_device
*d
, struct pa_iodc_driver
*dri
)
1183 struct lba_device
*lba_dev
;
1184 struct pci_bus
*lba_bus
;
1188 /* from drivers/pci/setup-bus.c */
1189 extern void __init
pbus_set_ranges(struct pci_bus
*, struct pbus_set_ranges_data
*);
1191 /* Read HW Rev First */
1192 func_class
= READ_REG32(d
->hpa
+ LBA_FCLASS
);
1195 switch (func_class
) {
1196 case 0: dri
->version
= "TR1.0"; break;
1197 case 1: dri
->version
= "TR2.0"; break;
1198 case 2: dri
->version
= "TR2.1"; break;
1199 case 3: dri
->version
= "TR2.2"; break;
1200 case 4: dri
->version
= "TR3.0"; break;
1201 case 5: dri
->version
= "TR4.0"; break;
1202 default: dri
->version
= "TR4+";
1205 printk("%s version %s (0x%x) found at 0x%p\n", dri
->name
, dri
->version
, func_class
& 0xf, d
->hpa
);
1207 /* Just in case we find some prototypes... */
1208 if (func_class
< 2) {
1209 printk(KERN_WARNING
"Can't support LBA older than TR2.1 "
1210 "- continuing under adversity.\n");
1214 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1216 tmp_obj
= iosapic_register(d
->hpa
+LBA_IOSAPIC_BASE
);
1217 if (NULL
== tmp_obj
) {
1218 /* iosapic may have failed. But more likely the
1219 ** slot isn't occupied and thus has no IRT entries.
1220 ** iosapic_register looks for this iosapic in the IRT
1221 ** before bothering to allocating data structures
1224 DBG(KERN_WARNING MODULE_NAME
": iosapic_register says not used\n");
1228 lba_dev
= kmalloc(sizeof(struct lba_device
), GFP_KERNEL
);
1229 if (NULL
== lba_dev
)
1231 printk("lba_init_chip - couldn't alloc lba_device\n");
1235 memset(lba_dev
, 0, sizeof(struct lba_device
));
1238 /* ---------- First : initialize data we already have --------- */
1241 ** Need hw_rev to adjust configuration space behavior.
1242 ** LBA_TR4PLUS macro uses hw_rev field.
1244 lba_dev
->hw_rev
= func_class
;
1246 lba_dev
->hba
.base_addr
= d
->hpa
; /* faster access */
1247 lba_dev
->iosapic_obj
= tmp_obj
; /* save interrupt handle */
1249 /* ------------ Second : initialize common stuff ---------- */
1250 lba_common_init(lba_dev
);
1251 lba_hw_init(lba_dev
);
1253 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1257 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1258 pci_port
= &lba_pat_port_ops
;
1260 /* Go ask PDC PAT what resources this LBA has */
1261 lba_pat_resources(d
, lba_dev
);
1265 /* Sprockets PDC uses NPIOP region */
1266 pci_port
= &lba_astro_port_ops
;
1268 /* Poke the chip a bit for /proc output */
1269 lba_legacy_resources(d
, lba_dev
);
1275 ** Tell PCI support another PCI bus was found.
1276 ** Walks PCI bus for us too.
1278 lba_bus
= lba_dev
->hba
.hba_bus
=
1279 pci_scan_bus( lba_dev
->hba
.bus_num
.start
, &lba_cfg_ops
, (void *) lba_dev
);
1284 /* determine window sizes needed by PCI-PCI bridges */
1285 DBG_PAT("LBA pcibios_size_bridge()\n");
1286 pcibios_size_bridge(lba_bus
, NULL
);
1288 /* assign resources to un-initialized devices */
1289 DBG_PAT("LBA pcibios_assign_unassigned_resources()\n");
1290 pcibios_assign_unassigned_resources(lba_bus
);
1292 #ifdef DEBUG_LBA_PAT
1293 DBG_PAT("\nLBA PIOP resource tree\n");
1294 lba_dump_res(&lba_dev
->hba
.io_space
, 2);
1295 DBG_PAT("\nLBA LMMIO resource tree\n");
1296 lba_dump_res(&lba_dev
->hba
.mem_space
, 2);
1299 /* program *all* PCI-PCI bridge range registers */
1300 DBG_PAT("LBA pbus_set_ranges()\n");
1301 pbus_set_ranges(lba_bus
, NULL
);
1303 #endif /* __LP64__ */
1306 ** Once PCI register ops has walked the bus, access to config
1307 ** space is restricted. Avoids master aborts on config cycles.
1308 ** Early LBA revs go fatal on *any* master abort.
1310 if (!LBA_TR4PLUS(lba_dev
)) {
1311 lba_dev
->flags
|= LBA_FLAG_SKIP_PROBE
;
1314 /* Whew! Finally done! Tell services we got this one covered. */
1320 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1321 ** Only called from sba_iommu.c initialization sequence.
1323 void lba_init_iregs(void *sba_hpa
, u32 ibase
, u32 imask
)
1325 extern struct pci_hba_data
*hba_list
; /* arch/parisc/kernel/pci.c */
1326 struct pci_hba_data
*lba
;
1328 imask
<<= 2; /* adjust for hints - 2 more bits */
1330 ASSERT((ibase
& 0x003fffff) == 0);
1331 ASSERT((imask
& 0x003fffff) == 0);
1333 /* FIXME: sba_hpa is intended to search some table to
1334 ** determine which LBA's belong to the caller's SBA.
1335 ** IS_ASTRO: just assume only one SBA for now.
1337 ASSERT(NULL
!= hba_list
);
1338 DBG(KERN_DEBUG
"%s() ibase 0x%x imask 0x%x\n", __FUNCTION__
, ibase
, imask
);
1340 for (lba
= hba_list
; NULL
!= lba
; lba
= lba
->next
) {
1341 DBG(KERN_DEBUG
"%s() base_addr %p\n", __FUNCTION__
, lba
->base_addr
);
1342 WRITE_REG32( imask
, lba
->base_addr
+ LBA_IMASK
);
1343 WRITE_REG32( ibase
, lba
->base_addr
+ LBA_IBASE
);
1345 DBG(KERN_DEBUG
"%s() done\n", __FUNCTION__
);