2 ** PCI Lower Bus Adapter (LBA) manager
4 ** (c) Copyright 1999,2000 Grant Grundler
5 ** (c) Copyright 1999,2000 Hewlett-Packard Company
7 ** This program is free software; you can redistribute it and/or modify
8 ** it under the terms of the GNU General Public License as published by
9 ** the Free Software Foundation; either version 2 of the License, or
10 ** (at your option) any later version.
13 ** This module primarily provides access to PCI bus (config/IOport
14 ** spaces) on platforms with an SBA/LBA chipset. A/B/C/J/L/N-class
15 ** with 4 digit model numbers - eg C3000 (and A400...sigh).
17 ** LBA driver isn't as simple as the Dino driver because:
18 ** (a) this chip has substantial bug fixes between revisions
19 ** (Only one Dino bug has a software workaround :^( )
20 ** (b) has more options which we don't (yet) support (DMA hints, OLARD)
21 ** (c) IRQ support lives in the I/O SAPIC driver (not with PCI driver)
22 ** (d) play nicely with both PAT and "Legacy" PA-RISC firmware (PDC).
23 ** (dino only deals with "Legacy" PDC)
25 ** LBA driver passes the I/O SAPIC HPA to the I/O SAPIC driver.
26 ** (I/O SAPIC is integratd in the LBA chip).
28 ** FIXME: Add support to SBA and LBA drivers for DMA hint sets
29 ** FIXME: Add support for PCI card hot-plug (OLARD).
32 #include <linux/delay.h>
33 #include <linux/types.h>
34 #include <linux/kernel.h>
35 #include <linux/spinlock.h>
36 #include <linux/init.h> /* for __init and __devinit */
37 #include <linux/pci.h>
38 #include <linux/ioport.h>
39 #include <linux/malloc.h>
40 #include <linux/smp_lock.h>
42 #include <asm/byteorder.h>
43 #include <asm/irq.h> /* for struct irq_region support */
45 #include <asm/pdcpat.h>
47 #include <asm/segment.h>
48 #include <asm/system.h>
50 #include <asm/hardware.h> /* for register_driver() stuff */
51 #include <asm/iosapic.h> /* for iosapic_register() */
52 #include <asm/gsc.h> /* gsc_read/write stuff */
57 #define FALSE (1 == 0)
60 #undef DEBUG_LBA /* general stuff */
61 #undef DEBUG_LBA_PORT /* debug I/O Port access */
62 #undef DEBUG_LBA_CFG /* debug Config Space Access (ie PCI Bus walk) */
63 #undef DEBUG_LBA_PAT /* debug PCI Resource Mgt code - PDC PAT only */
66 #define DBG(x...) printk(x)
72 #define DBG_PORT(x...) printk(x)
74 #define DBG_PORT(x...)
78 #define DBG_CFG(x...) printk(x)
84 #define DBG_PAT(x...) printk(x)
90 ** Config accessor functions only pass in the 8-bit bus number and not
91 ** the 8-bit "PCI Segment" number. Each LBA will be assigned a PCI bus
92 ** number based on what firmware wrote into the scratch register.
94 ** The "secondary" bus number is set to this before calling
95 ** pci_register_ops(). If any PPB's are present, the scan will
96 ** discover them and update the "secondary" and "subordinate"
97 ** fields in the pci_bus structure.
99 ** Changes in the configuration *may* result in a different
100 ** bus number for each LBA depending on what firmware does.
103 #define MODULE_NAME "lba"
105 static int lba_driver_callback(struct hp_device
*, struct pa_iodc_driver
*);
108 static struct pa_iodc_driver lba_drivers_for
[]= {
110 {HPHW_BRIDGE
, 0x782, 0x0, 0xa, 0,0,
111 DRIVER_CHECK_HVERSION
+
112 DRIVER_CHECK_SVERSION
+ DRIVER_CHECK_HWTYPE
,
113 MODULE_NAME
, "tbd", (void *) lba_driver_callback
},
117 (char *) NULL
, (char *) NULL
, (void *) NULL
}
121 #define LBA_FUNC_ID 0x0000 /* function id */
122 #define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
123 #define LBA_CAPABLE 0x0030 /* capabilities register */
125 #define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
126 #define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
128 #define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
129 #define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
130 #define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
132 #define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
133 #define LBA_ARB_PRI 0x0088 /* firmware sets this. */
134 #define LBA_ARB_MODE 0x0090 /* firmware sets this. */
135 #define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
137 #define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
139 #define LBA_STAT_CTL 0x0108 /* Status & Control */
140 #define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
142 #define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
143 #define LBA_LMMIO_MASK 0x0208
145 #define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
146 #define LBA_GMMIO_MASK 0x0218
148 #define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
149 #define LBA_WLMMIO_MASK 0x0228
151 #define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
152 #define LBA_WGMMIO_MASK 0x0238
154 #define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
155 #define LBA_IOS_MASK 0x0248
157 #define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
158 #define LBA_ELMMIO_MASK 0x0258
160 #define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
161 #define LBA_EIOS_MASK 0x0268
163 #define LBA_DMA_CTL 0x0278 /* firmware sets this */
165 /* RESET: ignore DMA stuff until we can measure performance */
166 #define LBA_IBASE 0x0300 /* DMA support */
167 #define LBA_IMASK 0x0308
168 #define LBA_HINT_CFG 0x0310
169 #define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
171 /* ERROR regs are needed for config cycle kluges */
172 #define LBA_ERROR_CONFIG 0x0680
173 #define LBA_ERROR_STATUS 0x0688
175 #define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
177 /* non-postable I/O port space, densely packed */
179 #define LBA_ASTRO_PORT_BASE (0xfffffffffee00000UL)
181 #define LBA_ASTRO_PORT_BASE (0xfee00000UL)
186 ** lba_device: Per instance Elroy data structure
189 struct pci_hba_data hba
;
195 unsigned long lmmio_base
; /* PA_VIEW - fixup MEM addresses */
196 unsigned long gmmio_base
; /* PA_VIEW - Not used (yet) */
197 unsigned long iop_base
; /* PA_VIEW - for IO port accessor funcs */
200 int flags
; /* state/functionality enabled */
201 int hw_rev
; /* HW revision of chip */
210 #define LBA_FLAG_NO_DMA_DURING_CFG 0x01
211 #define LBA_FLAG_SKIP_PROBE 0x10
213 /* Tape Release 4 == hw_rev 5 */
214 #define LBA_TR4PLUS(d) ((d)->hw_rev > 0x4)
215 #define LBA_DMA_DURING_CFG_DISABLED(d) ((d)->flags & LBA_FLAG_NO_DMA_DURING_CFG)
216 #define LBA_SKIP_PROBE(d) ((d)->flags & LBA_FLAG_SKIP_PROBE)
219 /* Looks nice and keeps the compiler happy */
220 #define LBA_DEV(d) ((struct lba_device *) (d))
224 ** Only allow 8 subsidiary busses per LBA
225 ** Problem is the PCI bus numbering is globally shared.
227 #define LBA_MAX_NUM_BUSES 8
229 /************************************
230 * LBA register read and write support
232 * BE WARNED: register writes are posted.
233 * (ie follow writes which must reach HW with a read)
235 #define READ_U8(addr) gsc_readb(addr)
236 #define READ_U16(addr) gsc_readw((u16 *) (addr))
237 #define READ_U32(addr) gsc_readl((u32 *) (addr))
238 #define WRITE_U8(value, addr) gsc_writeb(value, addr)
239 #define WRITE_U16(value, addr) gsc_writew(value, (u16 *) (addr))
240 #define WRITE_U32(value, addr) gsc_writel(value, (u32 *) (addr))
242 #define READ_REG8(addr) gsc_readb(addr)
243 #define READ_REG16(addr) le16_to_cpu(gsc_readw((u16 *) (addr)))
244 #define READ_REG32(addr) le32_to_cpu(gsc_readl((u32 *) (addr)))
245 #define WRITE_REG8(value, addr) gsc_writeb(value, addr)
246 #define WRITE_REG16(value, addr) gsc_writew(cpu_to_le16(value), (u16 *) (addr))
247 #define WRITE_REG32(value, addr) gsc_writel(cpu_to_le32(value), (u32 *) (addr))
250 #define LBA_CFG_TOK(bus,dfn) ((u32) ((bus)<<16 | (dfn)<<8))
251 #define LBA_CFG_BUS(tok) ((u8) ((tok)>>16))
252 #define LBA_CFG_DEV(tok) ((u8) ((tok)>>11) & 0x1f)
253 #define LBA_CFG_FUNC(tok) ((u8) ((tok)>>8 ) & 0x7)
257 /* Extract LBA (Rope) number from HPA */
258 #define LBA_NUM(x) ((((uintptr_t) x) >> 13) & 0xf)
259 #endif /* DEBUG_LBA */
263 static unsigned long pdc_result
[32] __attribute__ ((aligned (8))) = {0,0,0,0};
267 ** One time initialization to let the world know the LBA was found.
268 ** This is the only routine which is NOT static.
269 ** Must be called exactly once before pci_init().
271 void __init
lba_init(void)
273 register_driver(lba_drivers_for
);
278 lba_dump_res(struct resource
*r
, int d
)
285 printk("(%p)", r
->parent
);
286 for (i
= d
; i
; --i
) printk(" ");
287 printk("%p [%lx,%lx]/%x\n", r
, r
->start
, r
->end
, (int) r
->flags
);
288 lba_dump_res(r
->child
, d
+2);
289 lba_dump_res(r
->sibling
, d
);
294 ** LBA rev 2.0, 2.1, 2.2, and 3.0 bus walks require a complex
295 ** workaround for cfg cycles:
296 ** -- preserve LBA state
297 ** -- LBA_FLAG_NO_DMA_DURING_CFG workaround
298 ** -- turn on smart mode
299 ** -- probe with config writes before doing config reads
300 ** -- check ERROR_STATUS
301 ** -- clear ERROR_STATUS
302 ** -- restore LBA state
304 ** The workaround is only used for device discovery.
308 lba_device_present( u8 bus
, u8 dfn
, struct lba_device
*d
)
310 u8 first_bus
= d
->hba
.hba_bus
->secondary
;
311 u8 last_sub_bus
= d
->hba
.hba_bus
->subordinate
;
313 /* FIXME - see below in this function */
314 u8 dev
= PCI_SLOT(dfn
);
315 u8 func
= PCI_FUNC(dfn
);
318 ASSERT(bus
>= first_bus
);
319 ASSERT(bus
<= last_sub_bus
);
320 ASSERT((bus
- first_bus
) < LBA_MAX_NUM_BUSES
);
322 if ((bus
< first_bus
) ||
323 (bus
> last_sub_bus
) ||
324 ((bus
- first_bus
) >= LBA_MAX_NUM_BUSES
))
326 /* devices that fall into any of these cases won't get claimed */
332 ** FIXME: Need to implement code to fill the devices bitmap based
333 ** on contents of the local pci_bus tree "data base".
334 ** pci_register_ops() walks the bus for us and builds the tree.
335 ** For now, always do the config cycle.
339 return (((d
->devices
[bus
][dev
]) >> func
) & 0x1);
347 #define LBA_CFG_SETUP(d, tok) { \
348 /* Save contents of error config register. */ \
349 error_config = READ_REG32(d->hba.base_addr + LBA_ERROR_CONFIG); \
351 /* Save contents of status control register. */ \
352 status_control = READ_REG32(d->hba.base_addr + LBA_STAT_CTL); \
354 /* For LBA rev 2.0, 2.1, 2.2, and 3.0, we must disable DMA \
355 ** arbitration for full bus walks. \
357 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
358 /* Save contents of arb mask register. */ \
359 arb_mask = READ_REG32(d->hba.base_addr + LBA_ARB_MASK); \
362 * Turn off all device arbitration bits (i.e. everything \
363 * except arbitration enable bit). \
365 WRITE_REG32(0x1, d->hba.base_addr + LBA_ARB_MASK); \
369 * Set the smart mode bit so that master aborts don't cause \
370 * LBA to go into PCI fatal mode (required). \
372 WRITE_REG32(error_config | 0x20, d->hba.base_addr + LBA_ERROR_CONFIG); \
376 #define LBA_CFG_PROBE(d, tok) { \
378 * Setup Vendor ID write and read back the address register \
379 * to make sure that LBA is the bus master. \
381 WRITE_REG32(tok | PCI_VENDOR_ID, (d)->hba.base_addr + LBA_PCI_CFG_ADDR);\
383 * Read address register to ensure that LBA is the bus master, \
384 * which implies that DMA traffic has stopped when DMA arb is off. \
386 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
388 * Generate a cfg write cycle (will have no affect on \
389 * Vendor ID register since read-only). \
391 WRITE_REG32(~0, (d)->hba.base_addr + LBA_PCI_CFG_DATA); \
393 * Make sure write has completed before proceeding further, \
394 * i.e. before setting clear enable. \
396 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
402 * -- Can't tell if config cycle got the error.
404 * OV bit is broken until rev 4.0, so can't use OV bit and
405 * LBA_ERROR_LOG_ADDR to tell if error belongs to config cycle.
407 * As of rev 4.0, no longer need the error check.
409 * -- Even if we could tell, we still want to return -1
410 * for **ANY** error (not just master abort).
412 * -- Only clear non-fatal errors (we don't want to bring
413 * LBA out of pci-fatal mode).
415 * Actually, there is still a race in which
416 * we could be clearing a fatal error. We will
417 * live with this during our real mode bus walk
418 * until rev 4.0 (no driver activity during
419 * real mode bus walk). The real mode bus walk
420 * has race conditions concerning the use of
421 * smart mode as well.
424 #define LBA_MASTER_ABORT_ERROR 0xc
425 #define LBA_FATAL_ERROR 0x10
427 #define LBA_CFG_MASTER_ABORT_CHECK(d, base, tok, error) { \
428 u32 error_status = 0; \
430 * Set clear enable (CE) bit. Unset by HW when new \
431 * errors are logged -- LBA HW ERS section 14.3.3). \
433 WRITE_REG32(status_control | 0x20, base + LBA_STAT_CTL); \
434 error_status = READ_REG32(base + LBA_ERROR_STATUS); \
435 if ((error_status & 0x1f) != 0) { \
437 * Fail the config read request. \
440 if ((error_status & LBA_FATAL_ERROR) == 0) { \
442 * Clear error status (if fatal bit not set) by setting \
443 * clear error log bit (CL). \
445 WRITE_REG32(status_control | 0x10, base + LBA_STAT_CTL); \
450 #define LBA_CFG_TR4_ADDR_SETUP(d, addr) \
451 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR)
453 #define LBA_CFG_ADDR_SETUP(d, addr) { \
454 WRITE_REG32(((addr) & ~3), (d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
457 * -- Potentially could skip this once DMA bug fixed. \
459 * Read address register to ensure that LBA is the bus master, \
460 * which implies that DMA traffic has stopped when DMA arb is off. \
462 lba_t32 = READ_REG32((d)->hba.base_addr + LBA_PCI_CFG_ADDR); \
466 #define LBA_CFG_RESTORE(d, base) { \
468 * Restore status control register (turn off clear enable). \
470 WRITE_REG32(status_control, base + LBA_STAT_CTL); \
472 * Restore error config register (turn off smart mode). \
474 WRITE_REG32(error_config, base + LBA_ERROR_CONFIG); \
475 if (LBA_DMA_DURING_CFG_DISABLED(d)) { \
477 * Restore arb mask register (reenables DMA arbitration). \
479 WRITE_REG32(arb_mask, base + LBA_ARB_MASK); \
486 lba_rd_cfg( struct lba_device
*d
, u32 tok
, u8 reg
, u32 size
)
490 u32 arb_mask
= 0; /* used by LBA_CFG_SETUP/RESTORE */
491 u32 error_config
= 0; /* used by LBA_CFG_SETUP/RESTORE */
492 u32 status_control
= 0; /* used by LBA_CFG_SETUP/RESTORE */
494 ASSERT((size
== sizeof(u8
)) ||
495 (size
== sizeof(u16
)) ||
496 (size
== sizeof(u32
)));
498 if ((size
!= sizeof(u8
)) &&
499 (size
!= sizeof(u16
)) &&
500 (size
!= sizeof(u32
))) {
504 LBA_CFG_SETUP(d
, tok
);
505 LBA_CFG_PROBE(d
, tok
);
506 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
508 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
511 data
= (u32
) READ_REG8(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
& 3));
514 data
= (u32
) READ_REG16(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
& 2));
517 data
= READ_REG32(d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
520 break; /* leave data as -1 */
523 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
529 #define LBA_CFG_RD(size, mask) \
530 static int lba_cfg_read##size (struct pci_dev *dev, int pos, u##size *data) \
532 struct lba_device *d = LBA_DEV(dev->bus->sysdata); \
533 u32 local_bus = (dev->bus->parent == NULL) ? 0 : dev->bus->secondary; \
534 u32 tok = LBA_CFG_TOK(local_bus,dev->devfn); \
536 if ((!LBA_TR4PLUS(d)) && (!LBA_SKIP_PROBE(d))) { \
537 /* original - Generate config cycle on broken elroy \
538 with risk we will miss PCI bus errors. */ \
539 *data = (u##size) lba_rd_cfg(d, tok, pos, sizeof(u##size)); \
540 DBG_CFG(KERN_DEBUG "%s(%s+%2x) -> 0x%x (a)\n", __FUNCTION__, dev->slot_name, pos, *data); \
541 return(*data == (u##size) -1); \
544 if (LBA_SKIP_PROBE(d) && (!lba_device_present(dev->bus->secondary, dev->devfn, d))) \
546 DBG_CFG(KERN_DEBUG "%s(%s+%2x) -> -1 (b)\n", __FUNCTION__, dev->slot_name, pos, *data); \
547 /* either don't want to look or know device isn't present. */ \
548 *data = (u##size) -1; \
553 ** Should only get here on fully working LBA rev. \
554 ** This is how simple the code should have been. \
556 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); \
557 *data = READ_REG##size(d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & mask));\
558 DBG_CFG(KERN_DEBUG "%s(%s+%2x) -> 0x%x (c)\n", __FUNCTION__, dev->slot_name, pos, *data);\
559 return(*data == (u##size) -1); \
569 lba_wr_cfg( struct lba_device
*d
, u32 tok
, u8 reg
, u32 data
, u32 size
)
573 u32 error_config
= 0;
574 u32 status_control
= 0;
576 ASSERT((size
== sizeof(u8
)) ||
577 (size
== sizeof(u16
)) ||
578 (size
== sizeof(u32
)));
580 if ((size
!= sizeof(u8
)) &&
581 (size
!= sizeof(u16
)) &&
582 (size
!= sizeof(u32
))) {
586 LBA_CFG_SETUP(d
, tok
);
587 LBA_CFG_ADDR_SETUP(d
, tok
| reg
);
590 WRITE_REG8((u8
) data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+ (reg
&3));
593 WRITE_REG16((u8
) data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
+(reg
&2));
596 WRITE_REG32(data
, d
->hba
.base_addr
+ LBA_PCI_CFG_DATA
);
601 LBA_CFG_MASTER_ABORT_CHECK(d
, d
->hba
.base_addr
, tok
, error
);
602 LBA_CFG_RESTORE(d
, d
->hba
.base_addr
);
607 * LBA 4.0 config write code implements non-postable semantics
608 * by doing a read of CONFIG ADDR after the write.
611 #define LBA_CFG_WR(size, mask) \
612 static int lba_cfg_write##size (struct pci_dev *dev, int pos, u##size data) \
614 struct lba_device *d = LBA_DEV(dev->bus->sysdata); \
615 u32 local_bus = (dev->bus->parent == NULL) ? 0 : dev->bus->secondary; \
616 u32 tok = LBA_CFG_TOK(local_bus,dev->devfn); \
618 ASSERT((tok & 0xff) == 0); \
619 ASSERT(pos < 0x100); \
621 if ((!LBA_TR4PLUS(d)) && (!LBA_SKIP_PROBE(d))) { \
622 /* Original Workaround */ \
623 lba_wr_cfg(d, tok, pos, (u32) data, sizeof(u##size)); \
624 DBG_CFG(KERN_DEBUG "%s(%s+%2x) = 0x%x (a)\n", __FUNCTION__, dev->slot_name, pos, data); \
628 if (LBA_SKIP_PROBE(d) && (!lba_device_present(dev->bus->secondary, dev->devfn, d))) { \
629 DBG_CFG(KERN_DEBUG "%s(%s+%2x) = 0x%x (b)\n", __FUNCTION__, dev->slot_name, pos, data); \
630 return 1; /* New Workaround */ \
633 DBG_CFG(KERN_DEBUG "%s(%s+%2x) = 0x%x (c)\n", __FUNCTION__, dev->slot_name, pos, data); \
634 /* Basic Algorithm */ \
635 LBA_CFG_TR4_ADDR_SETUP(d, tok | pos); \
636 WRITE_REG##size(data, d->hba.base_addr + LBA_PCI_CFG_DATA + (pos & mask)); \
637 lba_t32 = READ_REG32(d->hba.base_addr + LBA_PCI_CFG_ADDR); \
646 static struct pci_ops lba_cfg_ops
= {
647 lba_cfg_read8
, lba_cfg_read16
, lba_cfg_read32
,
648 lba_cfg_write8
, lba_cfg_write16
, lba_cfg_write32
657 DBG(KERN_DEBUG MODULE_NAME
": lba_bios_init\n");
664 ** Determine if a device is already configured.
665 ** If so, reserve it resources.
667 ** Read PCI cfg command register and see if I/O or MMIO is enabled.
668 ** PAT has to enable the devices it's using.
670 ** Note: resources are fixed up before we try to claim them.
673 lba_claim_dev_resources(struct pci_dev
*dev
)
678 (void) lba_cfg_read16(dev
, PCI_COMMAND
, &cmd
);
680 srch_flags
= (cmd
& PCI_COMMAND_IO
) ? IORESOURCE_IO
: 0;
681 if (cmd
& PCI_COMMAND_MEMORY
)
682 srch_flags
|= IORESOURCE_MEM
;
687 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
688 if (dev
->resource
[i
].flags
& srch_flags
) {
689 pci_claim_resource(dev
, i
);
690 DBG(" claimed %s %d [%lx,%lx]/%x\n",
692 dev
->resource
[i
].start
,
693 dev
->resource
[i
].end
,
694 (int) dev
->resource
[i
].flags
703 ** The algorithm is generic code.
704 ** But it needs to access local data structures to get the IRQ base.
705 ** Could make this a "pci_fixup_irq(bus, region)" but not sure
708 ** Called by do_pci_scan_bus() immediately after each PCI bus is walked.
709 ** Resources aren't allocated until recursive buswalk below HBA is completed.
712 lba_fixup_bus(struct pci_bus
*bus
)
714 struct list_head
*ln
;
716 u16 fbb_enable
= PCI_STATUS_FAST_BACK
;
718 struct lba_device
*ldev
= LBA_DEV(bus
->sysdata
);
722 DBG("lba_fixup_bus(0x%p) bus %d sysdata 0x%p\n",
723 bus
, bus
->secondary
, bus
->sysdata
);
726 ** Properly Setup MMIO resources for this bus.
727 ** pci_alloc_primary_bus() mangles this.
729 if (NULL
== bus
->self
) {
732 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
733 ldev
->hba
.io_space
.name
,
734 ldev
->hba
.io_space
.start
,
735 ldev
->hba
.io_space
.end
,
736 (int) ldev
->hba
.io_space
.flags
);
737 DBG("lba_fixup_bus() %s [%lx/%lx]/%x\n",
738 ldev
->hba
.mem_space
.name
,
739 ldev
->hba
.mem_space
.start
,
740 ldev
->hba
.mem_space
.end
,
741 (int) ldev
->hba
.mem_space
.flags
);
743 err
= request_resource(&ioport_resource
, &(ldev
->hba
.io_space
));
746 lba_dump_res(&ioport_resource
, 2);
748 err
= request_resource(&iomem_resource
, &(ldev
->hba
.mem_space
));
751 lba_dump_res(&iomem_resource
, 2);
754 bus
->resource
[0] = &(ldev
->hba
.io_space
);
755 bus
->resource
[1] = &(ldev
->hba
.mem_space
);
758 list_for_each(ln
, &bus
->devices
) {
764 ** 0-5 are the "standard PCI regions"
765 ** (see comments near PCI_NUM_RESOURCES in include/linux/pci.h)
767 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
768 struct resource
*res
= &(dev
->resource
[i
]);
770 if (res
->flags
& IORESOURCE_MEM
) {
771 /* "Globalize" PCI address */
772 res
->start
|= ldev
->lmmio_base
;
773 res
->end
|= ldev
->lmmio_base
;
779 ** If one device does not support FBB transfers,
780 ** No one on the bus can be allowed to use them.
782 (void) lba_cfg_read16(dev
, PCI_STATUS
, &status
);
783 fbb_enable
&= status
;
787 /* Claim resources for PDC's devices */
788 lba_claim_dev_resources(dev
);
790 #endif /* __LP64__ */
793 ** P2PB's have no IRQs. ignore them.
795 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
)
798 /* Adjust INTERRUPT_LINE for this dev */
799 iosapic_fixup_irq(LBA_DEV(bus
->sysdata
)->iosapic_obj
, dev
);
803 /* FIXME/REVISIT - finish figuring out to set FBB on both
804 ** pbus_set_ranges() clobbers PCI_BRIDGE_CONTROL.
805 ** Can't fixup here anyway....garr...
811 (void) lba_cfg_read8(bus
->self
, PCI_BRIDGE_CONTROL
, &control
);
812 (void) lba_cfg_write8(bus
->self
, PCI_BRIDGE_CONTROL
, control
| PCI_STATUS_FAST_BACK
);
817 fbb_enable
= PCI_COMMAND_FAST_BACK
;
820 /* Lastly enable FBB/PERR/SERR on all devices too */
821 list_for_each(ln
, &bus
->devices
) {
822 (void) lba_cfg_read16(dev
, PCI_COMMAND
, &status
);
823 status
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
| fbb_enable
;
824 (void) lba_cfg_write16(dev
, PCI_COMMAND
, status
);
830 struct pci_bios_ops lba_bios_ops
= {
832 lba_fixup_bus
/* void lba_fixup_bus(struct pci_bus *bus) */
838 /*******************************************************
840 ** LBA Sprockets "I/O Port" Space Accessor Functions
842 ** This set of accessor functions is intended for use with
843 ** "legacy firmware" (ie Sprockets on Allegro/Forte boxes).
845 ** Many PCI devices don't require use of I/O port space (eg Tulip,
846 ** NCR720) since they export the same registers to both MMIO and
847 ** I/O port space. In general I/O port space is slower than
848 ** MMIO since drivers are designed so PIO writes can be posted.
850 ********************************************************/
852 #define LBA_PORT_IN(size, mask) \
853 static u##size lba_astro_in##size (struct pci_hba_data *d, u16 addr) \
856 ASSERT(bus != NULL); \
857 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x) ->", __FUNCTION__, bus, addr); \
858 t = READ_REG##size(LBA_ASTRO_PORT_BASE + addr); \
859 DBG_PORT(" 0x%x\n", t); \
870 ** BUG X4107: Ordering broken - DMA RD return can bypass PIO WR
872 ** Fixed in Elroy 2.2. The READ_U32(..., LBA_FUNC_ID) below is
873 ** guarantee non-postable completion semantics - not avoid X4107.
874 ** The READ_U32 only guarantees the write data gets to elroy but
875 ** out to the PCI bus. We can't read stuff from I/O port space
876 ** since we don't know what has side-effects. Attempting to read
877 ** from configuration space would be suicidal given the number of
878 ** bugs in that elroy functionality.
881 ** DMA read results can improperly pass PIO writes (X4107). The
882 ** result of this bug is that if a processor modifies a location in
883 ** memory after having issued PIO writes, the PIO writes are not
884 ** guaranteed to be completed before a PCI device is allowed to see
885 ** the modified data in a DMA read.
887 ** Note that IKE bug X3719 in TR1 IKEs will result in the same
891 ** The workaround for this bug is to always follow a PIO write with
892 ** a PIO read to the same bus before starting DMA on that PCI bus.
895 #define LBA_PORT_OUT(size, mask) \
896 static void lba_astro_out##size (struct pci_hba_data *d, u16 addr, u##size val) \
898 ASSERT(bus != NULL); \
899 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, d, addr, val); \
900 WRITE_REG##size(val, LBA_ASTRO_PORT_BASE + addr); \
901 if (LBA_DEV(d)->hw_rev < 3) \
902 lba_t32 = READ_U32(d->base_addr + LBA_FUNC_ID); \
910 static struct pci_port_ops lba_astro_port_ops
= {
911 lba_astro_in8
, lba_astro_in16
, lba_astro_in32
,
912 lba_astro_out8
, lba_astro_out16
, lba_astro_out32
918 #define PIOP_TO_GMMIO(lba, addr) \
919 ((lba)->iop_base + (((addr)&0xFFFC)<<10) + ((addr)&3))
921 /*******************************************************
923 ** LBA PAT "I/O Port" Space Accessor Functions
925 ** This set of accessor functions is intended for use with
926 ** "PAT PDC" firmware (ie Prelude/Rhapsody/Piranha boxes).
928 ** This uses the PIOP space located in the first 64MB of GMMIO.
929 ** Each rope gets a full 64*KB* (ie 4 bytes per page) this way.
930 ** bits 1:0 stay the same. bits 15:2 become 25:12.
931 ** Then add the base and we can generate an I/O Port cycle.
932 ********************************************************/
934 #define LBA_PORT_IN(size, mask) \
935 static u##size lba_pat_in##size (struct pci_hba_data *l, u16 addr) \
938 ASSERT(bus != NULL); \
939 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x) ->", __FUNCTION__, l, addr); \
940 t = READ_REG##size(PIOP_TO_GMMIO(LBA_DEV(l), addr)); \
941 DBG_PORT(" 0x%x\n", t); \
951 #define LBA_PORT_OUT(size, mask) \
952 static void lba_pat_out##size (struct pci_hba_data *l, u16 addr, u##size val) \
954 void *where = (void *) PIOP_TO_GMMIO(LBA_DEV(l), addr); \
955 ASSERT(bus != NULL); \
956 DBG_PORT(KERN_DEBUG "%s(0x%p, 0x%x, 0x%x)\n", __FUNCTION__, l, addr, val); \
957 WRITE_REG##size(val, where); \
958 /* flush the I/O down to the elroy at least */ \
959 lba_t32 = READ_U32(l->base_addr + LBA_FUNC_ID); \
967 static struct pci_port_ops lba_pat_port_ops
= {
968 lba_pat_in8
, lba_pat_in16
, lba_pat_in32
,
969 lba_pat_out8
, lba_pat_out16
, lba_pat_out32
975 ** make range information from PDC available to PCI subsystem.
976 ** We make the PDC call here in order to get the PCI bus range
977 ** numbers. The rest will get forwarded in pcibios_fixup_bus().
978 ** We don't have a struct pci_bus assigned to us yet.
981 lba_pat_resources( struct hp_device
*d
, struct lba_device
*lba_dev
)
983 pdc_pat_cell_mod_maddr_block_t pa_pdc_cell
; /* PA_VIEW */
984 #ifdef DONT_NEED_THIS_FOR_ASTRO
985 pdc_pat_cell_mod_maddr_block_t io_pdc_cell
; /* IO_VIEW */
988 long status
; /* PDC return status */
992 /* return cell module (IO view) */
993 status
= pdc_pat_cell_module(& pdc_result
, d
->pcell_loc
, d
->mod_index
,
994 PA_VIEW
, & pa_pdc_cell
);
995 pa_count
= pa_pdc_cell
.mod
[1];
997 #ifdef DONT_NEED_THIS_FOR_ASTRO
998 status
|= pdc_pat_cell_module(& pdc_result
, d
->pcell_loc
, d
->mod_index
,
999 IO_VIEW
, & io_pdc_cell
);
1000 io_count
= io_pdc_cell
.mod
[1];
1003 /* We've already done this once for device discovery...*/
1004 if (status
!= PDC_RET_OK
) {
1005 panic("pdc_pat_cell_module() call failed for LBA!\n");
1008 if (PAT_GET_ENTITY(pa_pdc_cell
.mod_info
) != PAT_ENTITY_LBA
) {
1009 panic("pdc_pat_cell_module() entity returned != PAT_ENTITY_LBA!\n");
1013 ** Inspect the resources PAT tells us about
1015 for (i
= 0; i
< pa_count
; i
++) {
1018 unsigned long start
;
1019 unsigned long end
; /* aka finish */
1023 p
= (void *) &(pa_pdc_cell
.mod
[2+i
*3]);
1025 /* Convert the PAT range data to PCI "struct resource" */
1026 switch(p
->type
& 0xff) {
1028 lba_dev
->hba
.bus_num
.start
= p
->start
;
1029 lba_dev
->hba
.bus_num
.end
= p
->end
;
1032 /* used to fix up pre-initialized MEM BARs */
1033 lba_dev
->lmmio_base
= p
->start
;
1035 r
= &(lba_dev
->hba
.mem_space
);
1036 r
->name
= "LBA LMMIO";
1037 r
->start
= p
->start
;
1039 r
->flags
= IORESOURCE_MEM
;
1040 r
->parent
= r
->sibling
= r
->child
= NULL
;
1043 printk(KERN_WARNING MODULE_NAME
1044 " range[%d] : ignoring GMMIO (0x%lx)\n",
1046 lba_dev
->gmmio_base
= p
->start
;
1049 printk(KERN_WARNING MODULE_NAME
1050 " range[%d] : ignoring NPIOP (0x%lx)\n",
1055 ** Postable I/O port space is per PCI host adapter.
1058 /* save base of 64MB PIOP region */
1059 lba_dev
->iop_base
= p
->start
;
1061 r
= &(lba_dev
->hba
.io_space
);
1062 r
->name
= "LBA I/O Port";
1063 r
->start
= lba_dev
->hba
.hba_num
<< 16;
1064 r
->end
= r
->start
+ 0xffffUL
;
1065 r
->flags
= IORESOURCE_IO
;
1066 r
->parent
= r
->sibling
= r
->child
= NULL
;
1069 printk(KERN_WARNING MODULE_NAME
1070 " range[%d] : unknown pat range type (0x%lx)\n",
1076 #endif /* __LP64__ */
1080 lba_legacy_resources( struct hp_device
*d
, struct lba_device
*lba_dev
)
1086 ** Used to sign extend instead BAR values are only 32-bit.
1087 ** 64-bit BARs have the upper 32-bit's zero'd by firmware.
1088 ** "Sprockets" PDC initializes for 32-bit OS.
1090 lba_dev
->lmmio_base
= 0xffffffff00000000UL
;
1094 ** With "legacy" firmware, the lowest byte of FW_SCRATCH
1095 ** represents bus->secondary and the second byte represents
1096 ** bus->subsidiary (i.e. highest PPB programmed by firmware).
1097 ** PCI bus walk *should* end up with the same result.
1098 ** FIXME: But we don't have sanity checks in PCI or LBA.
1100 lba_num
= READ_REG32(d
->hpa
+ LBA_FW_SCRATCH
);
1101 r
= &(lba_dev
->hba
.bus_num
);
1102 r
->name
= "LBA PCI Busses";
1103 r
->start
= lba_num
& 0xff;
1104 r
->end
= (lba_num
>>8) & 0xff;
1106 /* Set up local PCI Bus resources - we don't really need
1107 ** them for Legacy boxes but it's nice to see in /proc.
1109 r
= &(lba_dev
->hba
.mem_space
);
1110 r
->name
= "LBA PCI LMMIO";
1111 r
->flags
= IORESOURCE_MEM
;
1112 r
->start
= READ_REG32(d
->hpa
+ LBA_LMMIO_BASE
);
1113 r
->end
= r
->start
+ ~ (READ_REG32(d
->hpa
+ LBA_LMMIO_MASK
));
1115 r
= &(lba_dev
->hba
.io_space
);
1116 r
->name
= "LBA PCI I/O Ports";
1117 r
->flags
= IORESOURCE_IO
;
1118 r
->start
= READ_REG32(d
->hpa
+ LBA_IOS_BASE
);
1119 r
->end
= r
->start
+ (READ_REG32(d
->hpa
+ LBA_IOS_MASK
) ^ 0xffff);
1121 lba_num
= lba_dev
->hba
.hba_num
<< 16;
1122 r
->start
|= lba_num
;
1127 /**************************************************************************
1129 ** LBA initialization code (HW and SW)
1131 ** o identify LBA chip itself
1132 ** o initialize LBA chip modes (HardFail)
1133 ** o FIXME: initialize DMA hints for reasonable defaults
1134 ** o enable configuration functions
1135 ** o call pci_register_ops() to discover devs (fixup/fixup_bus get invoked)
1137 **************************************************************************/
1140 lba_hw_init(struct lba_device
*d
)
1144 /* Set HF mode as the default (vs. -1 mode). */
1145 stat
= READ_REG32(d
->hba
.base_addr
+ LBA_STAT_CTL
);
1146 WRITE_REG32(stat
| HF_ENABLE
, d
->hba
.base_addr
+ LBA_STAT_CTL
);
1149 ** FIXME: Hint registers are programmed with default hint
1150 ** values by firmware. Hints should be sane even if we
1151 ** can't reprogram them the way drivers want.
1158 lba_common_init(struct lba_device
*lba_dev
)
1160 pci_bios
= &lba_bios_ops
;
1161 pcibios_register_hba((struct pci_hba_data
*)lba_dev
);
1162 lba_dev
->lba_lock
= SPIN_LOCK_UNLOCKED
;
1165 ** Set flags which depend on hw_rev
1167 if (!LBA_TR4PLUS(lba_dev
)) {
1168 lba_dev
->flags
|= LBA_FLAG_NO_DMA_DURING_CFG
;
1175 ** Determine if lba should claim this chip (return 0) or not (return 1).
1176 ** If so, initialize the chip and tell other partners in crime they
1180 lba_driver_callback(struct hp_device
*d
, struct pa_iodc_driver
*dri
)
1182 struct lba_device
*lba_dev
;
1183 struct pci_bus
*lba_bus
;
1187 /* from drivers/pci/setup-bus.c */
1188 extern void __init
pbus_set_ranges(struct pci_bus
*, struct pbus_set_ranges_data
*);
1190 /* Read HW Rev First */
1191 func_class
= READ_REG32(d
->hpa
+ LBA_FCLASS
);
1194 switch (func_class
) {
1195 case 0: dri
->version
= "TR1.0"; break;
1196 case 1: dri
->version
= "TR2.0"; break;
1197 case 2: dri
->version
= "TR2.1"; break;
1198 case 3: dri
->version
= "TR2.2"; break;
1199 case 4: dri
->version
= "TR3.0"; break;
1200 case 5: dri
->version
= "TR4.0"; break;
1201 default: dri
->version
= "TR4+";
1204 printk("%s version %s (0x%x) found at 0x%p\n", dri
->name
, dri
->version
, func_class
& 0xf, d
->hpa
);
1206 /* Just in case we find some prototypes... */
1207 if (func_class
< 2) {
1208 printk(KERN_WARNING
"Can't support LBA older than TR2.1 "
1209 "- continuing under adversity.\n");
1213 ** Tell I/O SAPIC driver we have a IRQ handler/region.
1215 tmp_obj
= iosapic_register(d
->hpa
+LBA_IOSAPIC_BASE
);
1216 if (NULL
== tmp_obj
) {
1217 /* iosapic may have failed. But more likely the
1218 ** slot isn't occupied and thus has no IRT entries.
1219 ** iosapic_register looks for this iosapic in the IRT
1220 ** before bothering to allocating data structures
1223 DBG(KERN_WARNING MODULE_NAME
": iosapic_register says not used\n");
1227 lba_dev
= kmalloc(sizeof(struct lba_device
), GFP_KERNEL
);
1228 if (NULL
== lba_dev
)
1230 printk("lba_init_chip - couldn't alloc lba_device\n");
1234 memset(lba_dev
, 0, sizeof(struct lba_device
));
1237 /* ---------- First : initialize data we already have --------- */
1240 ** Need hw_rev to adjust configuration space behavior.
1241 ** LBA_TR4PLUS macro uses hw_rev field.
1243 lba_dev
->hw_rev
= func_class
;
1245 lba_dev
->hba
.base_addr
= d
->hpa
; /* faster access */
1246 lba_dev
->iosapic_obj
= tmp_obj
; /* save interrupt handle */
1248 /* ------------ Second : initialize common stuff ---------- */
1249 lba_common_init(lba_dev
);
1250 lba_hw_init(lba_dev
);
1252 /* ---------- Third : setup I/O Port and MMIO resources --------- */
1256 /* PDC PAT firmware uses PIOP region of GMMIO space. */
1257 pci_port
= &lba_pat_port_ops
;
1259 /* Go ask PDC PAT what resources this LBA has */
1260 lba_pat_resources(d
, lba_dev
);
1264 /* Sprockets PDC uses NPIOP region */
1265 pci_port
= &lba_astro_port_ops
;
1267 /* Poke the chip a bit for /proc output */
1268 lba_legacy_resources(d
, lba_dev
);
1274 ** Tell PCI support another PCI bus was found.
1275 ** Walks PCI bus for us too.
1277 lba_bus
= lba_dev
->hba
.hba_bus
=
1278 pci_scan_bus( lba_dev
->hba
.bus_num
.start
, &lba_cfg_ops
, (void *) lba_dev
);
1283 /* determine window sizes needed by PCI-PCI bridges */
1284 DBG_PAT("LBA pcibios_size_bridge()\n");
1285 pcibios_size_bridge(lba_bus
, NULL
);
1287 /* assign resources to un-initialized devices */
1288 DBG_PAT("LBA pcibios_assign_unassigned_resources()\n");
1289 pcibios_assign_unassigned_resources(lba_bus
);
1291 #ifdef DEBUG_LBA_PAT
1292 DBG_PAT("\nLBA PIOP resource tree\n");
1293 lba_dump_res(&lba_dev
->hba
.io_space
, 2);
1294 DBG_PAT("\nLBA LMMIO resource tree\n");
1295 lba_dump_res(&lba_dev
->hba
.mem_space
, 2);
1298 /* program *all* PCI-PCI bridge range registers */
1299 DBG_PAT("LBA pbus_set_ranges()\n");
1300 pbus_set_ranges(lba_bus
, NULL
);
1302 #endif /* __LP64__ */
1305 ** Once PCI register ops has walked the bus, access to config
1306 ** space is restricted. Avoids master aborts on config cycles.
1307 ** Early LBA revs go fatal on *any* master abort.
1309 if (!LBA_TR4PLUS(lba_dev
)) {
1310 lba_dev
->flags
|= LBA_FLAG_SKIP_PROBE
;
1313 /* Whew! Finally done! Tell services we got this one covered. */
1319 ** Initialize the IBASE/IMASK registers for LBA (Elroy).
1320 ** Only called from sba_iommu.c initialization sequence.
1322 void lba_init_iregs(void *sba_hpa
, u32 ibase
, u32 imask
)
1324 extern struct pci_hba_data
*hba_list
; /* arch/parisc/kernel/pci.c */
1325 struct pci_hba_data
*lba
;
1327 imask
<<= 2; /* adjust for hints - 2 more bits */
1329 ASSERT((ibase
& 0x003fffff) == 0);
1330 ASSERT((imask
& 0x003fffff) == 0);
1332 /* FIXME: sba_hpa is intended to search some table to
1333 ** determine which LBA's belong to the caller's SBA.
1334 ** IS_ASTRO: just assume only one SBA for now.
1336 ASSERT(NULL
!= hba_list
);
1337 DBG(KERN_DEBUG
"%s() ibase 0x%x imask 0x%x\n", __FUNCTION__
, ibase
, imask
);
1339 for (lba
= hba_list
; NULL
!= lba
; lba
= lba
->next
) {
1340 DBG(KERN_DEBUG
"%s() base_addr %p\n", __FUNCTION__
, lba
->base_addr
);
1341 WRITE_REG32( imask
, lba
->base_addr
+ LBA_IMASK
);
1342 WRITE_REG32( ibase
, lba
->base_addr
+ LBA_IBASE
);
1344 DBG(KERN_DEBUG
"%s() done\n", __FUNCTION__
);