include/asm-sparc64/mmu_context.h

   1 /* $Id: mmu_context.h,v 1.39 1999/08/02 08:39:57 davem Exp $ */
   2 #ifndef __SPARC64_MMU_CONTEXT_H
   3 #define __SPARC64_MMU_CONTEXT_H
   4
   5 /* Derived heavily from Linus's Alpha/AXP ASN code... */
   6
   7 #include <linux/spinlock.h>
   8 #include <asm/system.h>
   9 #include <asm/spitfire.h>
  10
  11 #ifndef __ASSEMBLY__
  12
  13 extern spinlock_t ctx_alloc_lock;
  14 extern unsigned long tlb_context_cache;
  15 extern unsigned long mmu_context_bmap[];
  16
  17 #define CTX_VERSION_SHIFT       (PAGE_SHIFT - 3)
  18 #define CTX_VERSION_MASK        ((~0UL) << CTX_VERSION_SHIFT)
  19 #define CTX_FIRST_VERSION       ((1UL << CTX_VERSION_SHIFT) + 1UL)
  20 #define CTX_VALID(__ctx)        \
  21          (!(((__ctx) ^ tlb_context_cache) & CTX_VERSION_MASK))
  22 #define CTX_HWBITS(__ctx)       ((__ctx) & ~CTX_VERSION_MASK)
  23
  24 extern void get_new_mmu_context(struct mm_struct *mm);
  25
  26 /* Initialize a new mmu context.  This is invoked when a new
  27  * address space instance (unique or shared) is instantiated.
  28  * A fresh mm_struct is cleared out to zeros, so this need not
  29  * do anything on Sparc64 since the only thing we care about
  30  * is that mm->context is an invalid context (ie. zero).
  31  */
  32 #define init_new_context(__tsk, __mm)   do { } while(0)
  33
  34 /* Destroy a dead context.  This occurs when mmput drops the
  35  * mm_users count to zero, the mmaps have been released, and
  36  * all the page tables have been flushed.  Our job is to destroy
  37  * any remaining processor-specific state, and in the sparc64
  38  * case this just means freeing up the mmu context ID held by
  39  * this task if valid.
  40  */
  41 #define destroy_context(__mm)                                   \
  42 do {    spin_lock(&ctx_alloc_lock);                             \
  43         if (CTX_VALID((__mm)->context)) {                       \
  44                 unsigned long nr = CTX_HWBITS((__mm)->context); \
  45                 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \
  46         }                                                       \
  47         spin_unlock(&ctx_alloc_lock);                           \
  48 } while(0)
  49
  50 /* Reload the two core values used by TLB miss handler
  51  * processing on sparc64.  They are:
  52  * 1) The physical address of mm->pgd, when full page
  53  *    table walks are necessary, this is where the
  54  *    search begins.
  55  * 2) A "PGD cache".  For 32-bit tasks only pgd[0] is
  56  *    ever used since that maps the entire low 4GB
  57  *    completely.  To speed up TLB miss processing we
  58  *    make this value available to the handlers.  This
  59  *    decreases the amount of memory traffic incurred.
  60  */
  61 #define reload_tlbmiss_state(__tsk, __mm) \
  62 do { \
  63         register unsigned long paddr asm("o5"); \
  64         register unsigned long pgd_cache asm("o4"); \
  65         paddr = __pa((__mm)->pgd); \
  66         pgd_cache = 0UL; \
  67         if ((__tsk)->thread.flags & SPARC_FLAG_32BIT) \
  68                 pgd_cache = pgd_val((__mm)->pgd[0]) << 11UL; \
  69         __asm__ __volatile__("wrpr      %%g0, 0x494, %%pstate\n\t" \
  70                              "mov       %3, %%g4\n\t" \
  71                              "mov       %0, %%g7\n\t" \
  72                              "stxa      %1, [%%g4] %2\n\t" \
  73                              "wrpr      %%g0, 0x096, %%pstate" \
  74                              : /* no outputs */ \
  75                              : "r" (paddr), "r" (pgd_cache),\
  76                                "i" (ASI_DMMU), "i" (TSB_REG)); \
  77 } while(0)
  78
  79 /* Set MMU context in the actual hardware. */
  80 #define load_secondary_context(__mm) \
  81         __asm__ __volatile__("stxa      %0, [%1] %2\n\t" \
  82                              "flush     %%g6" \
  83                              : /* No outputs */ \
  84                              : "r" (CTX_HWBITS((__mm)->context)), \
  85                                "r" (0x10), "i" (0x58))
  86
  87 /* Clean out potential stale TLB entries due to previous
  88  * users of this TLB context.  We flush TLB contexts
  89  * lazily on sparc64.
  90  */
  91 #define clean_secondary_context() \
  92         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t" \
  93                              "stxa      %%g0, [%0] %2\n\t" \
  94                              "flush     %%g6" \
  95                              : /* No outputs */ \
  96                              : "r" (0x50), "i" (0x5f), "i" (0x57))
  97
  98 /* Switch the current MM context. */
  99 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu)
 100 {
 101         long dirty;
 102
 103         spin_lock(&mm->page_table_lock);
 104         if (CTX_VALID(mm->context))
 105                 dirty = 0;
 106         else
 107                 dirty = 1;
 108         if (dirty || (old_mm != mm)) {
 109                 unsigned long vm_mask;
 110
 111                 if (dirty)
 112                         get_new_mmu_context(mm);
 113
 114                 vm_mask = (1UL << cpu);
 115                 if (!(mm->cpu_vm_mask & vm_mask)) {
 116                         mm->cpu_vm_mask |= vm_mask;
 117                         dirty = 1;
 118                 }
 119
 120                 load_secondary_context(mm);
 121                 if (dirty != 0)
 122                         clean_secondary_context();
 123                 reload_tlbmiss_state(tsk, mm);
 124         }
 125         spin_unlock(&mm->page_table_lock);
 126 }
 127
 128 /* Activate a new MM instance for the current task. */
 129 static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
 130 {
 131         unsigned long vm_mask;
 132
 133         spin_lock(&mm->page_table_lock);
 134         if (!CTX_VALID(mm->context))
 135                 get_new_mmu_context(mm);
 136         vm_mask = (1UL << smp_processor_id());
 137         if (!(mm->cpu_vm_mask & vm_mask))
 138                 mm->cpu_vm_mask |= vm_mask;
 139         spin_unlock(&mm->page_table_lock);
 140
 141         load_secondary_context(mm);
 142         clean_secondary_context();
 143         reload_tlbmiss_state(current, mm);
 144 }
 145
 146 #endif /* !(__ASSEMBLY__) */
 147
 148 #endif /* !(__SPARC64_MMU_CONTEXT_H) */