include/asm-sparc64/mmu_context.h

   1 /* $Id: mmu_context.h,v 1.45 2000/08/12 13:25:52 davem Exp $ */
   2 #ifndef __SPARC64_MMU_CONTEXT_H
   3 #define __SPARC64_MMU_CONTEXT_H
   4
   5 /* Derived heavily from Linus's Alpha/AXP ASN code... */
   6
   7 #ifndef __ASSEMBLY__
   8
   9 #include <linux/spinlock.h>
  10 #include <asm/system.h>
  11 #include <asm/spitfire.h>
  12
  13 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
  14 {
  15 }
  16
  17 extern spinlock_t ctx_alloc_lock;
  18 extern unsigned long tlb_context_cache;
  19 extern unsigned long mmu_context_bmap[];
  20
  21 #define CTX_VERSION_SHIFT       (PAGE_SHIFT - 3)
  22 #define CTX_VERSION_MASK        ((~0UL) << CTX_VERSION_SHIFT)
  23 #define CTX_FIRST_VERSION       ((1UL << CTX_VERSION_SHIFT) + 1UL)
  24 #define CTX_VALID(__ctx)        \
  25          (!(((__ctx) ^ tlb_context_cache) & CTX_VERSION_MASK))
  26 #define CTX_HWBITS(__ctx)       ((__ctx) & ~CTX_VERSION_MASK)
  27
  28 extern void get_new_mmu_context(struct mm_struct *mm);
  29
  30 /* Initialize a new mmu context.  This is invoked when a new
  31  * address space instance (unique or shared) is instantiated.
  32  * This just needs to set mm->context to an invalid context.
  33  */
  34 #define init_new_context(__tsk, __mm)   (((__mm)->context = 0UL), 0)
  35
  36 /* Destroy a dead context.  This occurs when mmput drops the
  37  * mm_users count to zero, the mmaps have been released, and
  38  * all the page tables have been flushed.  Our job is to destroy
  39  * any remaining processor-specific state, and in the sparc64
  40  * case this just means freeing up the mmu context ID held by
  41  * this task if valid.
  42  */
  43 #define destroy_context(__mm)                                   \
  44 do {    spin_lock(&ctx_alloc_lock);                             \
  45         if (CTX_VALID((__mm)->context)) {                       \
  46                 unsigned long nr = CTX_HWBITS((__mm)->context); \
  47                 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); \
  48         }                                                       \
  49         spin_unlock(&ctx_alloc_lock);                           \
  50 } while(0)
  51
  52 /* Reload the two core values used by TLB miss handler
  53  * processing on sparc64.  They are:
  54  * 1) The physical address of mm->pgd, when full page
  55  *    table walks are necessary, this is where the
  56  *    search begins.
  57  * 2) A "PGD cache".  For 32-bit tasks only pgd[0] is
  58  *    ever used since that maps the entire low 4GB
  59  *    completely.  To speed up TLB miss processing we
  60  *    make this value available to the handlers.  This
  61  *    decreases the amount of memory traffic incurred.
  62  */
  63 #define reload_tlbmiss_state(__tsk, __mm) \
  64 do { \
  65         register unsigned long paddr asm("o5"); \
  66         register unsigned long pgd_cache asm("o4"); \
  67         paddr = __pa((__mm)->pgd); \
  68         pgd_cache = 0UL; \
  69         if ((__tsk)->thread.flags & SPARC_FLAG_32BIT) \
  70                 pgd_cache = pgd_val((__mm)->pgd[0]) << 11UL; \
  71         __asm__ __volatile__("wrpr      %%g0, 0x494, %%pstate\n\t" \
  72                              "mov       %3, %%g4\n\t" \
  73                              "mov       %0, %%g7\n\t" \
  74                              "stxa      %1, [%%g4] %2\n\t" \
  75                              "wrpr      %%g0, 0x096, %%pstate" \
  76                              : /* no outputs */ \
  77                              : "r" (paddr), "r" (pgd_cache),\
  78                                "i" (ASI_DMMU), "i" (TSB_REG)); \
  79 } while(0)
  80
  81 /* Set MMU context in the actual hardware. */
  82 #define load_secondary_context(__mm) \
  83         __asm__ __volatile__("stxa      %0, [%1] %2\n\t" \
  84                              "flush     %%g6" \
  85                              : /* No outputs */ \
  86                              : "r" (CTX_HWBITS((__mm)->context)), \
  87                                "r" (0x10), "i" (0x58))
  88
  89 /* Clean out potential stale TLB entries due to previous
  90  * users of this TLB context.  We flush TLB contexts
  91  * lazily on sparc64.
  92  */
  93 #define clean_secondary_context() \
  94         __asm__ __volatile__("stxa      %%g0, [%0] %1\n\t" \
  95                              "stxa      %%g0, [%0] %2\n\t" \
  96                              "flush     %%g6" \
  97                              : /* No outputs */ \
  98                              : "r" (0x50), "i" (0x5f), "i" (0x57))
  99
 100 /* Switch the current MM context. */
 101 static inline void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, struct task_struct *tsk, int cpu)
 102 {
 103         unsigned long ctx_valid;
 104
 105         spin_lock(&mm->page_table_lock);
 106         if (CTX_VALID(mm->context))
 107                 ctx_valid = 1;
 108         else
 109                 ctx_valid = 0;
 110
 111         if (!ctx_valid || (old_mm != mm)) {
 112                 if (!ctx_valid)
 113                         get_new_mmu_context(mm);
 114
 115                 load_secondary_context(mm);
 116                 reload_tlbmiss_state(tsk, mm);
 117         }
 118
 119         {
 120                 unsigned long vm_mask = (1UL << cpu);
 121
 122                 /* Even if (mm == old_mm) we _must_ check
 123                  * the cpu_vm_mask.  If we do not we could
 124                  * corrupt the TLB state because of how
 125                  * smp_flush_tlb_{page,range,mm} on sparc64
 126                  * and lazy tlb switches work. -DaveM
 127                  */
 128                 if (!ctx_valid || !(mm->cpu_vm_mask & vm_mask)) {
 129                         mm->cpu_vm_mask |= vm_mask;
 130                         clean_secondary_context();
 131                 }
 132         }
 133         spin_unlock(&mm->page_table_lock);
 134 }
 135
 136 /* Activate a new MM instance for the current task. */
 137 static inline void activate_mm(struct mm_struct *active_mm, struct mm_struct *mm)
 138 {
 139         unsigned long vm_mask;
 140
 141         spin_lock(&mm->page_table_lock);
 142         if (!CTX_VALID(mm->context))
 143                 get_new_mmu_context(mm);
 144         vm_mask = (1UL << smp_processor_id());
 145         if (!(mm->cpu_vm_mask & vm_mask))
 146                 mm->cpu_vm_mask |= vm_mask;
 147         spin_unlock(&mm->page_table_lock);
 148
 149         load_secondary_context(mm);
 150         clean_secondary_context();
 151         reload_tlbmiss_state(current, mm);
 152 }
 153
 154 #endif /* !(__ASSEMBLY__) */
 155
 156 #endif /* !(__SPARC64_MMU_CONTEXT_H) */