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Import 2.1.118
[davej-history.git] / drivers / sbus / char / bpp.c
blob846f7cd7bb7800aa6e0a8b17c8b2f54527f6c5c5
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/version.h>
16 #include <linux/fs.h>
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/timer.h>
20 #include <linux/ioport.h>
21 #include <linux/major.h>
22
23 #include <asm/uaccess.h>
24
25 #if defined(__i386__)
26 # include <asm/io.h>
27 # include <asm/system.h>
28 # include <asm/segment.h>
29 #endif
30
31 #if defined(__sparc__)
32 # include <linux/init.h>
33 # include <linux/delay.h> /* udelay() */
34
35 # include <asm/oplib.h> /* OpenProm Library */
36 # include <asm/sbus.h> /* struct linux_sbus *SBus_chain */
37 # include <asm/io.h> /* sparc_alloc_io() */
38 #endif
39
40 #include <asm/bpp.h>
41
42 #define BPP_PROBE_CODE 0x55
43 #define BPP_DELAY 100
44
45 static const unsigned BPP_MAJOR = LP_MAJOR;
46 static const char* dev_name = "bpp";
47
48 /* When switching from compatibility to a mode where I can read, try
49 the following mode first. */
50
51 /* const unsigned char DEFAULT_ECP = 0x10; */
52 static const unsigned char DEFAULT_ECP = 0x30;
53 static const unsigned char DEFAULT_NIBBLE = 0x00;
54
55 /*
56 * These are 1284 time constraints, in units of jiffies.
57 */
58
59 static const unsigned long TIME_PSetup = 1;
60 static const unsigned long TIME_PResponse = 6;
61 static const unsigned long TIME_IDLE_LIMIT = 2000;
62
63 /*
64 * One instance per supported subdevice...
65 */
66 # define BPP_NO 3
67
68 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
69
70 struct inst {
71 unsigned present : 1; /* True if the hardware exists */
72 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
73 unsigned opened : 1; /* True if the device is opened already */
74 unsigned run_flag : 1; /* True if waiting for a repeate byte */
75
76 unsigned char direction; /* 0 --> out, 0x20 --> IN */
77 unsigned char pp_state; /* State of host controlled pins. */
78 enum IEEE_Mode mode;
79
80 unsigned char run_length;
81 unsigned char repeat_byte;
82
83 /* These members manage timeouts for programmed delays */
84 struct wait_queue *wait_queue;
85 struct timer_list timer_list;
86 };
87
88 static struct inst instances[BPP_NO];
89
90 #if defined(__i386__)
91
92 const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
93
94 /*
95 * These are for data access.
96 * Control lines accesses are hidden in set_bits() and get_bits().
97 * The exeption is the probe procedure, which is system-dependent.
98 */
99 #define bpp_outb_p(data, base) outb_p((data), (base))
100 #define bpp_inb(base) inb(base)
101 #define bpp_inb_p(base) inb_p(base)
102
103 /*
104 * This method takes the pin values mask and sets the hardware pins to
105 * the requested value: 1 == high voltage, 0 == low voltage. This
106 * burries the annoying PC bit inversion and preserves the direction
107 * flag.
108 */
109 static void set_pins(unsigned short pins, unsigned minor)
110 {
111 unsigned char bits = instances[minor].direction; /* == 0x20 */
112
113 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
114 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
115 if ( pins & BPP_PP_nInit) bits |= 4;
116 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
117
118 instances[minor].pp_state = bits;
119
120 outb_p(bits, base_addrs[minor]+2);
121 }
122
123 static unsigned short get_pins(unsigned minor)
124 {
125 unsigned short bits = 0;
126
127 unsigned value = instances[minor].pp_state;
128 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
129 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
130 if (value & 0x04) bits |= BPP_PP_nInit;
131 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
132
133 value = inb_p(base_addrs[minor]+1);
134 if (value & 0x08) bits |= BPP_GP_nFault;
135 if (value & 0x10) bits |= BPP_GP_Select;
136 if (value & 0x20) bits |= BPP_GP_PError;
137 if (value & 0x40) bits |= BPP_GP_nAck;
138 if (! (value & 0x80)) bits |= BPP_GP_Busy;
139
140 return bits;
141 }
142
143 #endif /* __i386__ */
144
145 #if defined(__sparc__)
146
147 /*
148 * Register block
149 */
150 struct bpp_regs {
151 /* DMA registers */
152 __u32 p_csr; /* DMA Control/Status Register */
153 __u32 p_addr; /* Address Register */
154 __u32 p_bcnt; /* Byte Count Register */
155 __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
156 /* Parallel Port registers */
157 __u16 p_hcr; /* Hardware Configuration Register */
158 __u16 p_ocr; /* Operation Configuration Register */
159 __u8 p_dr; /* Parallel Data Register */
160 __u8 p_tcr; /* Transfer Control Register */
161 __u8 p_or; /* Output Register */
162 __u8 p_ir; /* Input Register */
163 __u16 p_icr; /* Interrupt Control Register */
164 };
165
166 /* P_CSR. Bits of type RW1 are cleared with writting '1'. */
167 #define P_DEV_ID_MASK 0xf0000000 /* R */
168 #define P_DEV_ID_ZEBRA 0x40000000
169 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
170 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
171 #define P_A_LOADED 0x04000000 /* R */
172 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
173 #define P_EN_NEXT 0x01000000 /* RW */
174 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
175 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
176 of P-FIFO on loading of P_ADDR*/
177 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
178 #define P_BURST_8 0x00000000
179 #define P_BURST_4 0x00040000
180 #define P_BURST_1 0x00080000 /* "No burst" write */
181 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
182 P_EN_NEXT=1 */
183 #define P_EN_CNT 0x00002000 /* RW */
184 #define P_EN_DMA 0x00000200 /* RW */
185 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
186 #define P_RESET 0x00000080 /* RW */
187 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
188 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
189 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
190 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
191 #define P_ERR_PEND 0x00000002 /* R */
192 #define P_INT_PEND 0x00000001 /* R */
193
194 /* P_HCR. Time is in increments of SBus clock. */
195 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
196 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
197 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
198
199 /* P_OCR. */
200 #define P_OCR_MEM_CLR 0x8000
201 #define P_OCR_DATA_SRC 0x4000 /* ) */
202 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
203 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
204 #define P_OCR_ACK_DSEL 0x0800 /* ) */
205 #define P_OCR_EN_DIAG 0x0400
206 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
207 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
208 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
209 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
210 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
211 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
212
213 /* P_TCR */
214 #define P_TCR_DIR 0x08
215 #define P_TCR_BUSY 0x04
216 #define P_TCR_ACK 0x02
217 #define P_TCR_DS 0x01 /* Strobe */
218
219 /* P_OR */
220 #define P_OR_V3 0x20 /* ) */
221 #define P_OR_V2 0x10 /* ) on Zebra only */
222 #define P_OR_V1 0x08 /* ) */
223 #define P_OR_INIT 0x04
224 #define P_OR_AFXN 0x02 /* Auto Feed */
225 #define P_OR_SLCT_IN 0x01
226
227 /* P_IR */
228 #define P_IR_PE 0x04
229 #define P_IR_SLCT 0x02
230 #define P_IR_ERR 0x01
231
232 /* P_ICR */
233 #define P_DS_IRQ 0x8000 /* RW1 */
234 #define P_ACK_IRQ 0x4000 /* RW1 */
235 #define P_BUSY_IRQ 0x2000 /* RW1 */
236 #define P_PE_IRQ 0x1000 /* RW1 */
237 #define P_SLCT_IRQ 0x0800 /* RW1 */
238 #define P_ERR_IRQ 0x0400 /* RW1 */
239 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
240 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
241 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
242 #define P_BUSY_IRQ_EN 0x0040 /* RW */
243 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
244 #define P_PE_IRQ_EN 0x0010 /* RW */
245 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
246 #define P_SLCT_IRQ_EN 0x0004 /* RW */
247 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
248 #define P_ERR_IRQ_EN 0x0001 /* RW */
249
250 volatile struct bpp_regs *base_addrs[BPP_NO];
251
252 static inline void bpp_outb_p(__u8 data, volatile struct bpp_regs *base){
253 base->p_dr = data;
254 }
255
256 #define bpp_inb_p(base) bpp_inb(base)
257
258 static inline __u8 bpp_inb(volatile struct bpp_regs *base){
259 return base->p_dr;
260 }
261
262
263 static void set_pins(unsigned short pins, unsigned minor)
264 {
265 volatile struct bpp_regs *base = base_addrs[minor];
266 unsigned char bits_tcr = 0, bits_or = 0;
267
268 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
269 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
270
271 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
272 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
273 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
274
275 base->p_or = bits_or;
276 base->p_tcr = bits_tcr;
277 }
278
279 /*
280 * i386 people read output pins from a software image.
281 * We may get them back from hardware.
282 * Again, inversion of pins must he buried here.
283 */
284 static unsigned short get_pins(unsigned minor)
285 {
286 volatile struct bpp_regs *base = base_addrs[minor];
287 unsigned short bits = 0;
288 unsigned value_tcr = base->p_tcr;
289 unsigned value_ir = base->p_ir;
290 unsigned value_or = base->p_or;
291
292 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
293 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
294 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
295 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
296
297 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
298 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
299 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
300 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
301 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
302
303 return bits;
304 }
305
306 #if 0
307 /* P3 */
308 static inline void bpp_snap(const char *msg, unsigned minor)
309 {
310 volatile struct bpp_regs *r = base_addrs[minor];
311 printk("bpp.%s: c=%02x o=%02x i=%02x\n", msg, r->p_tcr, r->p_or, r->p_ir);
312 }
313 #endif
314
315 #endif /* __sparc__ */
316
317 /*
318 * This is TRUE if the module_init successfully loaded the module.
319 */
320 #if 0
321 static int loaded_flag = 0;
322 #endif
323
324 static void bpp_wake_up(unsigned long val)
325 { wake_up(&instances[val].wait_queue); }
326
327 static void snooze(unsigned long snooze_time, unsigned minor)
328 {
329 instances[minor].timer_list.expires = jiffies + snooze_time + 1;
330 instances[minor].timer_list.data = minor;
331 add_timer(&instances[minor].timer_list);
332 sleep_on (&instances[minor].wait_queue);
333 }
334
335 static int wait_for(unsigned short set, unsigned short clr,
336 unsigned long delay, unsigned minor)
337 {
338 unsigned short pins = get_pins(minor);
339
340 unsigned long extime = 0;
341
342 /*
343 * Try a real fast scan for the first jiffy, in case the device
344 * responds real good. The first while loop guesses an expire
345 * time accounting for possible wraparound of jiffies.
346 */
347 while (extime <= jiffies) extime = jiffies + 1;
348 while ( (jiffies < extime)
349 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
350 pins = get_pins(minor);
351 }
352
353 delay -= 1;
354
355 /*
356 * If my delay expired or the pins are still not where I want
357 * them, then resort to using the timer and greatly reduce my
358 * sample rate. If the peripheral is going to be slow, this will
359 * give the CPU up to some more worthy process.
360 */
361 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
362
363 snooze(1, minor);
364 pins = get_pins(minor);
365 delay -= 1;
366 }
367
368 if (delay == 0) return -1;
369 else return pins;
370 }
371
372 /*
373 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
374 * errno means something broke, and I do not yet know how to fix it.
375 */
376 static int negotiate(unsigned char mode, unsigned minor)
377 {
378 int rc;
379 unsigned short pins = get_pins(minor);
380 if (pins & BPP_PP_nSelectIn) return -EIO;
381
382
383 /* Event 0: Write the mode to the data lines */
384 bpp_outb_p(mode, base_addrs[minor]);
385
386 snooze(TIME_PSetup, minor);
387
388 /* Event 1: Strobe the mode code into the peripheral */
389 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
390
391 /* Wait for Event 2: Peripheral responds as a 1284 device. */
392 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
393 BPP_GP_nAck,
394 TIME_PResponse,
395 minor);
396
397 if (rc == -1) return -ETIMEDOUT;
398
399 /* Event 3: latch extensibility request */
400 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
401
402 /* ... quick nap while peripheral ponders the byte i'm sending...*/
403 snooze(1, minor);
404
405 /* Event 4: restore strobe, to ACK peripheral's response. */
406 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
407
408 /* Wait for Event 6: Peripheral latches response bits */
409 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
410 if (rc == -1) return -EIO;
411
412 /* A 1284 device cannot refuse nibble mode */
413 if (mode == DEFAULT_NIBBLE) return 0;
414
415 if (pins & BPP_GP_Select) return 0;
416
417 return -EPROTONOSUPPORT;
418 }
419
420 static int terminate(unsigned minor)
421 {
422 int rc;
423
424 /* Event 22: Request termination of 1284 mode */
425 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
426
427 /* Wait for Events 23 and 24: ACK termination request. */
428 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
429 BPP_GP_nAck,
430 TIME_PSetup+TIME_PResponse,
431 minor);
432
433 instances[minor].direction = 0;
434 instances[minor].mode = COMPATIBILITY;
435
436 if (rc == -1) {
437 return -EIO;
438 }
439
440 /* Event 25: Handshake by lowering nAutoFd */
441 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
442
443 /* Event 26: Peripheral wiggles lines... */
444
445 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
446 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
447 if (rc == -1) {
448 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
449 return -EIO;
450 }
451
452 /* Event 28: Finish phase by raising nAutoFd */
453 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
454
455 return 0;
456 }
457
458
459 /*
460 * Allow only one process to open the device at a time.
461 */
462 static int bpp_open(struct inode *inode, struct file *f)
463 {
464 unsigned minor = MINOR(inode->i_rdev);
465 if (minor >= BPP_NO) return -ENODEV;
466 if (! instances[minor].present) return -ENODEV;
467 if (instances[minor].opened) return -EBUSY;
468
469 instances[minor].opened = 1;
470
471 return 0;
472 }
473
474 /*
475 * When the process closes the device, this method is called to clean
476 * up and reset the hardware. Always leave the device in compatibility
477 * mode as this is a reasonable place to clean up from messes made by
478 * ioctls, or other mayhem.
479 */
480 static void bpp_release(struct inode *inode, struct file *f)
481 {
482 unsigned minor = MINOR(inode->i_rdev);
483 instances[minor].opened = 0;
484
485 if (instances[minor].mode != COMPATIBILITY)
486 terminate(minor);
487 }
488
489 static long read_nibble(unsigned minor, char *c, unsigned long cnt)
490 {
491 unsigned long remaining = cnt;
492 long rc;
493
494 while (remaining > 0) {
495 unsigned char byte = 0;
496 int pins;
497
498 /* Event 7: request nibble */
499 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
500
501 /* Wait for event 9: Peripher strobes first nibble */
502 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
503 if (pins == -1) return -ETIMEDOUT;
504
505 /* Event 10: I handshake nibble */
506 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
507 if (pins & BPP_GP_nFault) byte |= 0x01;
508 if (pins & BPP_GP_Select) byte |= 0x02;
509 if (pins & BPP_GP_PError) byte |= 0x04;
510 if (pins & BPP_GP_Busy) byte |= 0x08;
511
512 /* Wait for event 11: Peripheral handshakes nibble */
513 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
514
515 /* Event 7: request nibble */
516 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
517
518 /* Wait for event 9: Peripher strobes first nibble */
519 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
520 if (rc == -1) return -ETIMEDOUT;
521
522 /* Event 10: I handshake nibble */
523 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
524 if (pins & BPP_GP_nFault) byte |= 0x10;
525 if (pins & BPP_GP_Select) byte |= 0x20;
526 if (pins & BPP_GP_PError) byte |= 0x40;
527 if (pins & BPP_GP_Busy) byte |= 0x80;
528
529 put_user_ret(byte, c, -EFAULT);
530 c += 1;
531 remaining -= 1;
532
533 /* Wait for event 11: Peripheral handshakes nibble */
534 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
535 if (rc == -1) return -EIO;
536 }
537
538 return cnt - remaining;
539 }
540
541 static long read_ecp(unsigned minor, char *c, unsigned long cnt)
542 {
543 unsigned long remaining;
544 long rc;
545
546 /* Turn ECP mode from forward to reverse if needed. */
547 if (! instances[minor].direction) {
548 unsigned short pins = get_pins(minor);
549
550 /* Event 38: Turn the bus around */
551 instances[minor].direction = 0x20;
552 pins &= ~BPP_PP_nAutoFd;
553 set_pins(pins, minor);
554
555 /* Event 39: Set pins for reverse mode. */
556 snooze(TIME_PSetup, minor);
557 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
558
559 /* Wait for event 40: Peripheral ready to be strobed */
560 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
561 if (rc == -1) return -ETIMEDOUT;
562 }
563
564 remaining = cnt;
565
566 while (remaining > 0) {
567
568 /* If there is a run length for a repeated byte, repeat */
569 /* that byte a few times. */
570 if (instances[minor].run_length && !instances[minor].run_flag) {
571
572 char buffer[128];
573 unsigned idx;
574 unsigned repeat = remaining < instances[minor].run_length
575 ? remaining
576 : instances[minor].run_length;
577
578 for (idx = 0 ; idx < repeat ; idx += 1)
579 buffer[idx] = instances[minor].repeat_byte;
580
581 copy_to_user_ret(c, buffer, repeat, -EFAULT);
582 remaining -= repeat;
583 c += repeat;
584 instances[minor].run_length -= repeat;
585 }
586
587 if (remaining == 0) break;
588
589
590 /* Wait for Event 43: Data active on the bus. */
591 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
592 if (rc == -1) break;
593
594 if (rc & BPP_GP_Busy) {
595 /* OK, this is data. read it in. */
596 unsigned char byte = bpp_inb(base_addrs[minor]);
597 put_user_ret(byte, c, -EFAULT);
598 c += 1;
599 remaining -= 1;
600
601 if (instances[minor].run_flag) {
602 instances[minor].repeat_byte = byte;
603 instances[minor].run_flag = 0;
604 }
605
606 } else {
607 unsigned char byte = bpp_inb(base_addrs[minor]);
608 if (byte & 0x80) {
609 printk("bpp%d: "
610 "Ignoring ECP channel %u from device.\n",
611 minor, byte & 0x7f);
612 } else {
613 instances[minor].run_length = byte;
614 instances[minor].run_flag = 1;
615 }
616 }
617
618 /* Event 44: I got it. */
619 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
620
621 /* Wait for event 45: peripheral handshake */
622 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
623 if (rc == -1) return -ETIMEDOUT;
624
625 /* Event 46: Finish handshake */
626 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
627
628 }
629
630
631 return cnt - remaining;
632 }
633
634 static long bpp_read(struct inode *inode, struct file *f,
635 char *c, unsigned long cnt)
636 {
637 long rc;
638 const unsigned minor = MINOR(inode->i_rdev);
639 if (minor >= BPP_NO) return -ENODEV;
640 if (!instances[minor].present) return -ENODEV;
641
642 switch (instances[minor].mode) {
643
644 default:
645 if (instances[minor].mode != COMPATIBILITY)
646 terminate(minor);
647
648 if (instances[minor].enhanced) {
649 /* For now, do all reads with ECP-RLE mode */
650 unsigned short pins;
651
652 rc = negotiate(DEFAULT_ECP, minor);
653 if (rc < 0) break;
654
655 instances[minor].mode = ECP_RLE;
656
657 /* Event 30: set nAutoFd low to setup for ECP mode */
658 pins = get_pins(minor);
659 pins &= ~BPP_PP_nAutoFd;
660 set_pins(pins, minor);
661
662 /* Wait for Event 31: peripheral ready */
663 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
664 if (rc == -1) return -ETIMEDOUT;
665
666 rc = read_ecp(minor, c, cnt);
667
668 } else {
669 rc = negotiate(DEFAULT_NIBBLE, minor);
670 if (rc < 0) break;
671
672 instances[minor].mode = NIBBLE;
673
674 rc = read_nibble(minor, c, cnt);
675 }
676 break;
677
678 case NIBBLE:
679 rc = read_nibble(minor, c, cnt);
680 break;
681
682 case ECP:
683 case ECP_RLE:
684 rc = read_ecp(minor, c, cnt);
685 break;
686
687 }
688
689
690 return rc;
691 }
692
693 /*
694 * Compatibility mode handshaking is a matter of writing data,
695 * strobing it, and waiting for the printer to stop being busy.
696 */
697 static long write_compat(unsigned minor, const char *c, unsigned long cnt)
698 {
699 long rc;
700 unsigned short pins = get_pins(minor);
701
702 unsigned long remaining = cnt;
703
704 while (remaining > 0) {
705 unsigned char byte;
706 c += 1;
707 get_user_ret(byte, c, -EFAULT);
708
709 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
710 if (rc == -1) return -ETIMEDOUT;
711
712 bpp_outb_p(byte, base_addrs[minor]);
713 remaining -= 1;
714 /* snooze(1, minor); */
715
716 pins &= ~BPP_PP_nStrobe;
717 set_pins(pins, minor);
718
719 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
720
721 pins |= BPP_PP_nStrobe;
722 set_pins(pins, minor);
723 }
724
725 return cnt - remaining;
726 }
727
728 /*
729 * Write data using ECP mode. Watch out that the port may be set up
730 * for reading. If so, turn the port around.
731 */
732 static long write_ecp(unsigned minor, const char *c, unsigned long cnt)
733 {
734 unsigned short pins = get_pins(minor);
735 unsigned long remaining = cnt;
736
737 if (instances[minor].direction) {
738 int rc;
739
740 /* Event 47 Request bus be turned around */
741 pins |= BPP_PP_nInit;
742 set_pins(pins, minor);
743
744 /* Wait for Event 49: Peripheral relinquished bus */
745 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
746
747 pins |= BPP_PP_nAutoFd;
748 instances[minor].direction = 0;
749 set_pins(pins, minor);
750 }
751
752 while (remaining > 0) {
753 unsigned char byte;
754 int rc;
755
756 get_user_ret(byte, c, -EFAULT);
757
758 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
759 if (rc == -1) return -ETIMEDOUT;
760
761 c += 1;
762
763 bpp_outb_p(byte, base_addrs[minor]);
764
765 pins &= ~BPP_PP_nStrobe;
766 set_pins(pins, minor);
767
768 pins |= BPP_PP_nStrobe;
769 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
770 if (rc == -1) return -EIO;
771
772 set_pins(pins, minor);
773 }
774
775 return cnt - remaining;
776 }
777
778 /*
779 * Write to the peripheral. Be sensitive of the current mode. If I'm
780 * in a mode that can be turned around (ECP) then just do
781 * that. Otherwise, terminate and do my writing in compat mode. This
782 * is the safest course as any device can handle it.
783 */
784 static long bpp_write(struct inode *inode, struct file *f,
785 const char *c, unsigned long cnt)
786 {
787 long errno = 0;
788 unsigned minor = MINOR(inode->i_rdev);
789 if (minor >= BPP_NO) return -ENODEV;
790 if (!instances[minor].present) return -ENODEV;
791
792 switch (instances[minor].mode) {
793
794 case ECP:
795 case ECP_RLE:
796 errno = write_ecp(minor, c, cnt);
797 break;
798 case COMPATIBILITY:
799 errno = write_compat(minor, c, cnt);
800 break;
801 default:
802 terminate(minor);
803 errno = write_compat(minor, c, cnt);
804 }
805
806 return errno;
807 }
808
809 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
810 unsigned long arg)
811 {
812 int errno = 0;
813
814 unsigned minor = MINOR(inode->i_rdev);
815 if (minor >= BPP_NO) return -ENODEV;
816 if (!instances[minor].present) return -ENODEV;
817
818
819 switch (cmd) {
820
821 case BPP_PUT_PINS:
822 set_pins(arg, minor);
823 break;
824
825 case BPP_GET_PINS:
826 errno = get_pins(minor);
827 break;
828
829 case BPP_PUT_DATA:
830 bpp_outb_p(arg, base_addrs[minor]);
831 break;
832
833 case BPP_GET_DATA:
834 errno = bpp_inb_p(base_addrs[minor]);
835 break;
836
837 case BPP_SET_INPUT:
838 if (arg)
839 if (instances[minor].enhanced) {
840 unsigned short bits = get_pins(minor);
841 instances[minor].direction = 0x20;
842 set_pins(bits, minor);
843 } else {
844 errno = -ENOTTY;
845 }
846 else {
847 unsigned short bits = get_pins(minor);
848 instances[minor].direction = 0x00;
849 set_pins(bits, minor);
850 }
851 break;
852
853 default:
854 errno = -EINVAL;
855 }
856
857 return errno;
858 }
859
860 static struct file_operations bpp_fops = {
861 NULL, /* bpp_lseek */
862 bpp_read,
863 bpp_write,
864 NULL, /* bpp_readdir */
865 NULL, /* bpp_select */
866 bpp_ioctl,
867 NULL, /* bpp_mmap */
868 bpp_open,
869 NULL, /* flush */
870 bpp_release,
871 };
872
873 #if defined(__i386__)
874
875 #define collectLptPorts() {}
876
877 static void probeLptPort(unsigned idx)
878 {
879 unsigned int testvalue;
880 const unsigned short lpAddr = base_addrs[idx];
881
882 instances[idx].present = 0;
883 instances[idx].enhanced = 0;
884 instances[idx].direction = 0;
885 instances[idx].mode = COMPATIBILITY;
886 instances[idx].wait_queue = 0;
887 instances[idx].run_length = 0;
888 instances[idx].run_flag = 0;
889 init_timer(&instances[idx].timer_list);
890 instances[idx].timer_list.function = bpp_wake_up;
891 if (check_region(lpAddr,3)) return;
892
893 /*
894 * First, make sure the instance exists. Do this by writing to
895 * the data latch and reading the value back. If the port *is*
896 * present, test to see if it supports extended-mode
897 * operation. This will be required for IEEE1284 reverse
898 * transfers.
899 */
900
901 outb_p(BPP_PROBE_CODE, lpAddr);
902 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
903 ;
904 testvalue = inb_p(lpAddr);
905 if (testvalue == BPP_PROBE_CODE) {
906 unsigned save;
907 instances[idx].present = 1;
908
909 request_region(lpAddr,3, dev_name);
910 save = inb_p(lpAddr+2);
911 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
912 ;
913 outb_p(save|0x20, lpAddr+2);
914 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
915 ;
916 outb_p(~BPP_PROBE_CODE, lpAddr);
917 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
918 ;
919 testvalue = inb_p(lpAddr);
920 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
921 instances[idx].enhanced = 0;
922 else
923 instances[idx].enhanced = 1;
924 outb_p(save, lpAddr+2);
925 }
926
927 /*
928 * Leave the port in compat idle mode.
929 */
930 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
931
932 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
933 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
934 }
935
936 static inline void freeLptPort(int idx)
937 {
938 release_region(base_addrs[idx], 3);
939 }
940
941 #endif
942
943 #if defined(__sparc__)
944
945 static volatile struct bpp_regs *map_bpp(struct linux_sbus_device *dev, int idx)
946 {
947 volatile struct bpp_regs *regs;
948
949 /* Apply ranges to here, do not pollute Sbus devices list. */
950 struct linux_prom_registers areg;
951
952 /*
953 * PROM reports different numbers on Zebra and on DMA2.
954 * We need to figure out when to apply parent ranges.
955 * printk will show this on different machines.
956 */
957
958 areg = dev->reg_addrs[0];
959 printk("bpp%d.map_bpp: 0x%x.%p[0x%x] i=%d\n", idx,
960 areg.which_io, areg.phys_addr, areg.reg_size,
961 dev->irqs[0]);
962 /* IPC Zebra 1.fa200000[1c] i=2 */
963 /** prom_apply_sbus_ranges (&areg, 1); **/
964
965 regs = sparc_alloc_io (areg.phys_addr, 0,
966 sizeof(struct bpp_regs), "bpp",
967 areg.which_io, 0x0);
968
969 return regs;
970 }
971
972 static int collectLptPorts(void)
973 {
974 struct linux_sbus *bus;
975 struct linux_sbus_device *dev;
976 int count;
977
978 count = 0;
979 for_all_sbusdev(dev, bus) {
980 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
981 if (count >= BPP_NO) {
982 printk(KERN_NOTICE
983 "bpp: More than %d bpp ports,"
984 " rest is ignored\n", BPP_NO);
985 return count;
986 }
987 base_addrs[count] = map_bpp(dev, count);
988 count++;
989 }
990 }
991 return count;
992 }
993
994 static void probeLptPort(unsigned idx)
995 {
996 volatile struct bpp_regs *rp = base_addrs[idx];
997 __u32 csr;
998 char *brand;
999
1000 instances[idx].present = 0;
1001 instances[idx].enhanced = 0;
1002 instances[idx].direction = 0;
1003 instances[idx].mode = COMPATIBILITY;
1004 instances[idx].wait_queue = 0;
1005 instances[idx].run_length = 0;
1006 instances[idx].run_flag = 0;
1007 init_timer(&instances[idx].timer_list);
1008 instances[idx].timer_list.function = bpp_wake_up;
1009
1010 if (rp == 0) return;
1011
1012 instances[idx].present = 1;
1013 instances[idx].enhanced = 1; /* Sure */
1014
1015 if (((csr = rp->p_csr) & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
1016 udelay(20);
1017 csr = rp->p_csr;
1018 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
1019 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
1020 }
1021 }
1022 printk("bpp%d: reset with 0x%08x ..", idx, csr);
1023 rp->p_csr = (csr | P_RESET) & ~P_INT_EN;
1024 udelay(500);
1025 rp->p_csr &= ~P_RESET;
1026 printk(" done with csr=0x%08x ocr=0x%04x\n", rp->p_csr, rp->p_ocr);
1027
1028 switch (rp->p_csr & P_DEV_ID_MASK) {
1029 case P_DEV_ID_ZEBRA:
1030 brand = "Zebra";
1031 break;
1032 case P_DEV_ID_L64854:
1033 brand = "DMA2";
1034 break;
1035 default:
1036 brand = "Unknown";
1037 }
1038 printk("bpp%d: %s at 0x%p\n", idx, brand, rp);
1039
1040 /*
1041 * Leave the port in compat idle mode.
1042 */
1043 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1044
1045 return;
1046 }
1047
1048 static inline void freeLptPort(int idx)
1049 {
1050 sparc_free_io ((void *)base_addrs[idx], sizeof(struct bpp_regs));
1051 }
1052
1053 #endif
1054
1055 #ifdef MODULE
1056 int init_module(void)
1057 #else
1058 __initfunc(int bpp_init(void))
1059 #endif
1060 {
1061 int rc;
1062 unsigned idx;
1063
1064 rc = collectLptPorts();
1065 if (rc == 0)
1066 return -ENODEV;
1067
1068 rc = register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1069 if (rc < 0)
1070 return rc;
1071
1072 for (idx = 0; idx < BPP_NO; idx += 1) {
1073 instances[idx].opened = 0;
1074 probeLptPort(idx);
1075 }
1076
1077 return 0;
1078 }
1079
1080 #ifdef MODULE
1081 void cleanup_module(void)
1082 {
1083 unsigned idx;
1084
1085 unregister_chrdev(BPP_MAJOR, dev_name);
1086
1087 for (idx = 0 ; idx < BPP_NO ; idx += 1) {
1088 if (instances[idx].present)
1089 freeLptPort(idx);
1090 }
1091 }
1092 #endif
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