?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Import 2.1.116pre2
[davej-history.git] / drivers / net / de4x5.c
blobdeb25d9491d01fad3e035922d56a1dc0666cf8a8
1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
109 hh = device number
110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
125 7) enjoy!
126
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
207 autosense to set the media/speed; with the following
208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 TO DO:
229 ------
230
231 o check what revision numbers the 21142 and 21143 have
232 o
233
234 Revision History
235 ----------------
236
237 Version Date Description
238
239 0.1 17-Nov-94 Initial writing. ALPHA code release.
240 0.2 13-Jan-95 Added PCI support for DE435's.
241 0.21 19-Jan-95 Added auto media detection.
242 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
243 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
244 Add request/release_region code.
245 Add loadable modules support for PCI.
246 Clean up loadable modules support.
247 0.23 28-Feb-95 Added DC21041 and DC21140 support.
248 Fix missed frame counter value and initialisation.
249 Fixed EISA probe.
250 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
251 Change TX_BUFFS_AVAIL macro.
252 Change media autodetection to allow manual setting.
253 Completed DE500 (DC21140) support.
254 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
255 0.242 10-May-95 Minor changes.
256 0.30 12-Jun-95 Timer fix for DC21140.
257 Portability changes.
258 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
259 Add DE500 semi automatic autosense.
260 Add Link Fail interrupt TP failure detection.
261 Add timer based link change detection.
262 Plugged a memory leak in de4x5_queue_pkt().
263 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
264 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
265 suggestion by <heiko@colossus.escape.de>.
266 0.33 8-Aug-95 Add shared interrupt support (not released yet).
267 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
268 Fix de4x5_interrupt().
269 Fix dc21140_autoconf() mess.
270 No shared interrupt support.
271 0.332 11-Sep-95 Added MII management interface routines.
272 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
273 Add kernel timer code (h/w is too flaky).
274 Add MII based PHY autosense.
275 Add new multicasting code.
276 Add new autosense algorithms for media/mode
277 selection using kernel scheduling/timing.
278 Re-formatted.
279 Made changes suggested by <jeff@router.patch.net>:
280 Change driver to detect all DECchip based cards
281 with DEC_ONLY restriction a special case.
282 Changed driver to autoprobe as a module. No irq
283 checking is done now - assume BIOS is good!
284 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
285 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
286 only <niles@axp745gsfc.nasa.gov>
287 Fix for multiple PCI cards reported by <jos@xos.nl>
288 Duh, put the SA_SHIRQ flag into request_interrupt().
289 Fix SMC ethernet address in enet_det[].
290 Print chip name instead of "UNKNOWN" during boot.
291 0.42 26-Apr-96 Fix MII write TA bit error.
292 Fix bug in dc21040 and dc21041 autosense code.
293 Remove buffer copies on receive for Intels.
294 Change sk_buff handling during media disconnects to
295 eliminate DUP packets.
296 Add dynamic TX thresholding.
297 Change all chips to use perfect multicast filtering.
298 Fix alloc_device() bug <jari@markkus2.fimr.fi>
299 0.43 21-Jun-96 Fix unconnected media TX retry bug.
300 Add Accton to the list of broken cards.
301 Fix TX under-run bug for non DC21140 chips.
302 Fix boot command probe bug in alloc_device() as
303 reported by <koen.gadeyne@barco.com> and
304 <orava@nether.tky.hut.fi>.
305 Add cache locks to prevent a race condition as
306 reported by <csd@microplex.com> and
307 <baba@beckman.uiuc.edu>.
308 Upgraded alloc_device() code.
309 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
310 with <csd@microplex.com>
311 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
312 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
313 and <michael@compurex.com>.
314 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
315 with a loopback packet.
316 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
317 by <bhat@mundook.cs.mu.OZ.AU>
318 0.45 8-Dec-96 Include endian functions for PPC use, from work
319 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
320 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
321 suggestion from <mjacob@feral.com>.
322 0.5 30-Jan-97 Added SROM decoding functions.
323 Updated debug flags.
324 Fix sleep/wakeup calls for PCI cards, bug reported
325 by <cross@gweep.lkg.dec.com>.
326 Added multi-MAC, one SROM feature from discussion
327 with <mjacob@feral.com>.
328 Added full module autoprobe capability.
329 Added attempt to use an SMC9332 with broken SROM.
330 Added fix for ZYNX multi-mac cards that didn't
331 get their IRQs wired correctly.
332 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
333 <paubert@iram.es>
334 Fix init_connection() to remove extra device reset.
335 Fix MAC/PHY reset ordering in dc21140m_autoconf().
336 Fix initialisation problem with lp->timeout in
337 typeX_infoblock() from <paubert@iram.es>.
338 Fix MII PHY reset problem from work done by
339 <paubert@iram.es>.
340 0.52 26-Apr-97 Some changes may not credit the right people -
341 a disk crash meant I lost some mail.
342 Change RX interrupt routine to drop rather than
343 defer packets to avoid hang reported by
344 <g.thomas@opengroup.org>.
345 Fix srom_exec() to return for COMPACT and type 1
346 infoblocks.
347 Added DC21142 and DC21143 functions.
348 Added byte counters from <phil@tazenda.demon.co.uk>
349 Added SA_INTERRUPT temporary fix from
350 <mjacob@feral.com>.
351 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
352 module load: bug reported by
353 <Piete.Brooks@cl.cam.ac.uk>
354 Fix multi-MAC, one SROM, to work with 2114x chips:
355 bug reported by <cmetz@inner.net>.
356 Make above search independent of BIOS device scan
357 direction.
358 Completed DC2114[23] autosense functions.
359 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
360 <robin@intercore.com
361 Fix type1_infoblock() bug introduced in 0.53, from
362 problem reports by
363 <parmee@postecss.ncrfran.france.ncr.com> and
364 <jo@ice.dillingen.baynet.de>.
365 Added argument list to set up each board from either
366 a module's command line or a compiled in #define.
367 Added generic MII PHY functionality to deal with
368 newer PHY chips.
369 Fix the mess in 2.1.67.
370 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
371 <redhat@cococo.net>.
372 Fix bug in pci_probe() for 64 bit systems reported
373 by <belliott@accessone.com>.
374 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
375 0.534 24-Jan-98 Fix last (?) endian bug from
376 <Geert.Uytterhoeven@cs.kuleuven.ac.be>
377 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
378 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
379 **Incompatible with 2.0.x from here.**
380 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
381 from <lma@varesearch.com>
382 Add TP, AUI and BNC cases to 21140m_autoconf() for
383 case where a 21140 under SROM control uses, e.g. AUI
384 from problem report by <delchini@lpnp09.in2p3.fr>
385 Add MII parallel detection to 2114x_autoconf() for
386 case where no autonegotiation partner exists from
387 problem report by <mlapsley@ndirect.co.uk>.
388 Add ability to force connection type directly even
389 when using SROM control from problem report by
390 <earl@exis.net>.
391 Updated the PCI interface to conform with the latest
392 version. I hope nothing is broken...
393 Add TX done interrupt modification from suggestion
394 by <Austin.Donnelly@cl.cam.ac.uk>.
395 Fix is_anc_capable() bug reported by
396 <Austin.Donnelly@cl.cam.ac.uk>.
397 Fix type[13]_infoblock() bug: during MII search, PHY
398 lp->rst not run because lp->ibn not initialised -
399 from report & fix by <paubert@iram.es>.
400 Fix probe bug with EISA & PCI cards present from
401 report by <eirik@netcom.com>.
402
403 =========================================================================
404 */
405
406 static const char *version = "de4x5.c:V0.540 1998/7/5 davies@maniac.ultranet.com\n";
407
408 #include <linux/config.h>
409 #include <linux/module.h>
410
411 #include <linux/kernel.h>
412 #include <linux/sched.h>
413 #include <linux/string.h>
414 #include <linux/interrupt.h>
415 #include <linux/ptrace.h>
416 #include <linux/errno.h>
417 #include <linux/ioport.h>
418 #include <linux/malloc.h>
419 #include <linux/pci.h>
420 #include <linux/delay.h>
421 #include <linux/init.h>
422 #include <linux/version.h>
423
424 #include <asm/bitops.h>
425 #include <asm/io.h>
426 #include <asm/dma.h>
427 #include <asm/byteorder.h>
428 #include <asm/unaligned.h>
429 #include <asm/uaccess.h>
430
431 #include <linux/netdevice.h>
432 #include <linux/etherdevice.h>
433 #include <linux/skbuff.h>
434
435 #include <linux/time.h>
436 #include <linux/types.h>
437 #include <linux/unistd.h>
438 #include <linux/ctype.h>
439
440 #include "de4x5.h"
441
442 #define c_char const char
443 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
444
445 /*
446 ** MII Information
447 */
448 struct phy_table {
449 int reset; /* Hard reset required? */
450 int id; /* IEEE OUI */
451 int ta; /* One cycle TA time - 802.3u is confusing here */
452 struct { /* Non autonegotiation (parallel) speed det. */
453 int reg;
454 int mask;
455 int value;
456 } spd;
457 };
458
459 struct mii_phy {
460 int reset; /* Hard reset required? */
461 int id; /* IEEE OUI */
462 int ta; /* One cycle TA time */
463 struct { /* Non autonegotiation (parallel) speed det. */
464 int reg;
465 int mask;
466 int value;
467 } spd;
468 int addr; /* MII address for the PHY */
469 u_char *gep; /* Start of GEP sequence block in SROM */
470 u_char *rst; /* Start of reset sequence in SROM */
471 u_int mc; /* Media Capabilities */
472 u_int ana; /* NWay Advertisement */
473 u_int fdx; /* Full DupleX capabilites for each media */
474 u_int ttm; /* Transmit Threshold Mode for each media */
475 u_int mci; /* 21142 MII Connector Interrupt info */
476 };
477
478 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
479
480 struct sia_phy {
481 u_char mc; /* Media Code */
482 u_char ext; /* csr13-15 valid when set */
483 int csr13; /* SIA Connectivity Register */
484 int csr14; /* SIA TX/RX Register */
485 int csr15; /* SIA General Register */
486 int gepc; /* SIA GEP Control Information */
487 int gep; /* SIA GEP Data */
488 };
489
490 /*
491 ** Define the know universe of PHY devices that can be
492 ** recognised by this driver.
493 */
494 static struct phy_table phy_info[] = {
495 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
496 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
497 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
498 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
499 {0, 0x7810 , 1, {0x05, 0x0380, 0x0380}} /* Level One? */
500 };
501
502 /*
503 ** These GENERIC values assumes that the PHY devices follow 802.3u and
504 ** allow parallel detection to set the link partner ability register.
505 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
506 */
507 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
508 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
509 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
510
511 /*
512 ** Define special SROM detection cases
513 */
514 static c_char enet_det[][ETH_ALEN] = {
515 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
516 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
517 };
518
519 #define SMC 1
520 #define ACCTON 2
521
522 /*
523 ** SROM Repair definitions. If a broken SROM is detected a card may
524 ** use this information to help figure out what to do. This is a
525 ** "stab in the dark" and so far for SMC9332's only.
526 */
527 static c_char srom_repair_info[][100] = {
528 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
529 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
530 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
531 0x00,0x18,}
532 };
533
534
535 #ifdef DE4X5_DEBUG
536 static int de4x5_debug = DE4X5_DEBUG;
537 #else
538 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
539 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
540 #endif
541
542 /*
543 ** Allow per adapter set up. For modules this is simply a command line
544 ** parameter, e.g.:
545 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
546 **
547 ** For a compiled in driver, place e.g.
548 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
549 ** here
550 */
551 #ifdef DE4X5_PARM
552 static char *args = DE4X5_PARM;
553 #else
554 static char *args = NULL;
555 #endif
556
557 struct parameters {
558 int fdx;
559 int autosense;
560 };
561
562 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
563
564 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
565
566 /*
567 ** Ethernet PROM defines
568 */
569 #define PROBE_LENGTH 32
570 #define ETH_PROM_SIG 0xAA5500FFUL
571
572 /*
573 ** Ethernet Info
574 */
575 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
576 #define IEEE802_3_SZ 1518 /* Packet + CRC */
577 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
578 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
579 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
580 #define PKT_HDR_LEN 14 /* Addresses and data length info */
581 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
582 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
583
584
585 #define CRC_POLYNOMIAL_BE 0x04c11db7UL /* Ethernet CRC, big endian */
586 #define CRC_POLYNOMIAL_LE 0xedb88320UL /* Ethernet CRC, little endian */
587
588 /*
589 ** EISA bus defines
590 */
591 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
592 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
593
594 #define MAX_EISA_SLOTS 16
595 #define EISA_SLOT_INC 0x1000
596 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
597
598 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
599 #define DE4X5_NAME_LENGTH 8
600
601 /*
602 ** Ethernet PROM defines for DC21040
603 */
604 #define PROBE_LENGTH 32
605 #define ETH_PROM_SIG 0xAA5500FFUL
606
607 /*
608 ** PCI Bus defines
609 */
610 #define PCI_MAX_BUS_NUM 8
611 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
612 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
613 #define NO_MORE_PCI -2 /* PCI bus search all done */
614
615 /*
616 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
617 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
618 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
619 ** and hence the RX descriptor ring's first entry.
620 */
621 #define ALIGN4 ((u_long)4 - 1) /* 1 longword align */
622 #define ALIGN8 ((u_long)8 - 1) /* 2 longword align */
623 #define ALIGN16 ((u_long)16 - 1) /* 4 longword align */
624 #define ALIGN32 ((u_long)32 - 1) /* 8 longword align */
625 #define ALIGN64 ((u_long)64 - 1) /* 16 longword align */
626 #define ALIGN128 ((u_long)128 - 1) /* 32 longword align */
627
628 #define ALIGN ALIGN32 /* Keep the DC21040 happy... */
629 #define CACHE_ALIGN CAL_16LONG
630 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
631 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
632 #define DESC_ALIGN
633
634 #ifndef DEC_ONLY /* See README.de4x5 for using this */
635 static int dec_only = 0;
636 #else
637 static int dec_only = 1;
638 #endif
639
640 /*
641 ** DE4X5 IRQ ENABLE/DISABLE
642 */
643 #define ENABLE_IRQs { \
644 imr |= lp->irq_en;\
645 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
646 }
647
648 #define DISABLE_IRQs {\
649 imr = inl(DE4X5_IMR);\
650 imr &= ~lp->irq_en;\
651 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
652 }
653
654 #define UNMASK_IRQs {\
655 imr |= lp->irq_mask;\
656 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
657 }
658
659 #define MASK_IRQs {\
660 imr = inl(DE4X5_IMR);\
661 imr &= ~lp->irq_mask;\
662 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
663 }
664
665 /*
666 ** DE4X5 START/STOP
667 */
668 #define START_DE4X5 {\
669 omr = inl(DE4X5_OMR);\
670 omr |= OMR_ST | OMR_SR;\
671 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
672 }
673
674 #define STOP_DE4X5 {\
675 omr = inl(DE4X5_OMR);\
676 omr &= ~(OMR_ST|OMR_SR);\
677 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
678 }
679
680 /*
681 ** DE4X5 SIA RESET
682 */
683 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
684
685 /*
686 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
687 */
688 #define DE4X5_AUTOSENSE_MS 250
689
690 /*
691 ** SROM Structure
692 */
693 struct de4x5_srom {
694 char sub_vendor_id[2];
695 char sub_system_id[2];
696 char reserved[12];
697 char id_block_crc;
698 char reserved2;
699 char version;
700 char num_controllers;
701 char ieee_addr[6];
702 char info[100];
703 short chksum;
704 };
705 #define SUB_VENDOR_ID 0x500a
706
707 /*
708 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
709 ** and have sizes of both a power of 2 and a multiple of 4.
710 ** A size of 256 bytes for each buffer could be chosen because over 90% of
711 ** all packets in our network are <256 bytes long and 64 longword alignment
712 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
713 ** descriptors are needed for machines with an ALPHA CPU.
714 */
715 #define NUM_RX_DESC 8 /* Number of RX descriptors */
716 #define NUM_TX_DESC 32 /* Number of TX descriptors */
717 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
718 /* Multiple of 4 for DC21040 */
719 /* Allows 512 byte alignment */
720 struct de4x5_desc {
721 volatile s32 status;
722 u32 des1;
723 u32 buf;
724 u32 next;
725 DESC_ALIGN
726 };
727
728 /*
729 ** The DE4X5 private structure
730 */
731 #define DE4X5_PKT_STAT_SZ 16
732 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
733 increase DE4X5_PKT_STAT_SZ */
734
735 struct de4x5_private {
736 char adapter_name[80]; /* Adapter name */
737 struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
738 struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
739 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
740 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
741 int rx_new, rx_old; /* RX descriptor ring pointers */
742 int tx_new, tx_old; /* TX descriptor ring pointers */
743 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
744 char frame[64]; /* Min sized packet for loopback*/
745 struct net_device_stats stats; /* Public stats */
746 struct {
747 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
748 u_int unicast;
749 u_int multicast;
750 u_int broadcast;
751 u_int excessive_collisions;
752 u_int tx_underruns;
753 u_int excessive_underruns;
754 u_int rx_runt_frames;
755 u_int rx_collision;
756 u_int rx_dribble;
757 u_int rx_overflow;
758 } pktStats;
759 char rxRingSize;
760 char txRingSize;
761 int bus; /* EISA or PCI */
762 int bus_num; /* PCI Bus number */
763 int device; /* Device number on PCI bus */
764 int state; /* Adapter OPENED or CLOSED */
765 int chipset; /* DC21040, DC21041 or DC21140 */
766 s32 irq_mask; /* Interrupt Mask (Enable) bits */
767 s32 irq_en; /* Summary interrupt bits */
768 int media; /* Media (eg TP), mode (eg 100B)*/
769 int c_media; /* Remember the last media conn */
770 int fdx; /* media full duplex flag */
771 int linkOK; /* Link is OK */
772 int autosense; /* Allow/disallow autosensing */
773 int tx_enable; /* Enable descriptor polling */
774 int setup_f; /* Setup frame filtering type */
775 int local_state; /* State within a 'media' state */
776 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
777 struct sia_phy sia; /* SIA PHY Information */
778 int active; /* Index to active PHY device */
779 int mii_cnt; /* Number of attached PHY's */
780 int timeout; /* Scheduling counter */
781 struct timer_list timer; /* Timer info for kernel */
782 int tmp; /* Temporary global per card */
783 struct {
784 void *priv; /* Original kmalloc'd mem addr */
785 void *buf; /* Original kmalloc'd mem addr */
786 u_long lock; /* Lock the cache accesses */
787 s32 csr0; /* Saved Bus Mode Register */
788 s32 csr6; /* Saved Operating Mode Reg. */
789 s32 csr7; /* Saved IRQ Mask Register */
790 s32 gep; /* Saved General Purpose Reg. */
791 s32 gepc; /* Control info for GEP */
792 s32 csr13; /* Saved SIA Connectivity Reg. */
793 s32 csr14; /* Saved SIA TX/RX Register */
794 s32 csr15; /* Saved SIA General Register */
795 int save_cnt; /* Flag if state already saved */
796 struct sk_buff *skb; /* Save the (re-ordered) skb's */
797 } cache;
798 struct de4x5_srom srom; /* A copy of the SROM */
799 struct device *next_module; /* Link to the next module */
800 int rx_ovf; /* Check for 'RX overflow' tag */
801 int useSROM; /* For non-DEC card use SROM */
802 int useMII; /* Infoblock using the MII */
803 int asBitValid; /* Autosense bits in GEP? */
804 int asPolarity; /* 0 => asserted high */
805 int asBit; /* Autosense bit number in GEP */
806 int defMedium; /* SROM default medium */
807 int tcount; /* Last infoblock number */
808 int infoblock_init; /* Initialised this infoblock? */
809 int infoleaf_offset; /* SROM infoleaf for controller */
810 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
811 int infoblock_media; /* infoblock media */
812 int (*infoleaf_fn)(struct device *); /* Pointer to infoleaf function */
813 u_char *rst; /* Pointer to Type 5 reset info */
814 u_char ibn; /* Infoblock number */
815 struct parameters params; /* Command line/ #defined params */
816 };
817
818 /*
819 ** Kludge to get around the fact that the CSR addresses have different
820 ** offsets in the PCI and EISA boards. Also note that the ethernet address
821 ** PROM is accessed differently.
822 */
823 static struct bus_type {
824 int bus;
825 int bus_num;
826 int device;
827 int chipset;
828 struct de4x5_srom srom;
829 int autosense;
830 int useSROM;
831 } bus;
832
833 /*
834 ** To get around certain poxy cards that don't provide an SROM
835 ** for the second and more DECchip, I have to key off the first
836 ** chip's address. I'll assume there's not a bad SROM iff:
837 **
838 ** o the chipset is the same
839 ** o the bus number is the same and > 0
840 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
841 **
842 ** Also have to save the irq for those cards whose hardware designers
843 ** can't follow the PCI to PCI Bridge Architecture spec.
844 */
845 static struct {
846 int chipset;
847 int bus;
848 int irq;
849 u_char addr[ETH_ALEN];
850 } last = {0,};
851
852 /*
853 ** The transmit ring full condition is described by the tx_old and tx_new
854 ** pointers by:
855 ** tx_old = tx_new Empty ring
856 ** tx_old = tx_new+1 Full ring
857 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
858 */
859 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
860 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
861 lp->tx_old -lp->tx_new-1)
862
863 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
864
865 /*
866 ** Public Functions
867 */
868 static int de4x5_open(struct device *dev);
869 static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
870 static void de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
871 static int de4x5_close(struct device *dev);
872 static struct net_device_stats *de4x5_get_stats(struct device *dev);
873 static void de4x5_local_stats(struct device *dev, char *buf, int pkt_len);
874 static void set_multicast_list(struct device *dev);
875 static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
876
877 /*
878 ** Private functions
879 */
880 static int de4x5_hw_init(struct device *dev, u_long iobase);
881 static int de4x5_init(struct device *dev);
882 static int de4x5_sw_reset(struct device *dev);
883 static int de4x5_rx(struct device *dev);
884 static int de4x5_tx(struct device *dev);
885 static int de4x5_ast(struct device *dev);
886 static int de4x5_txur(struct device *dev);
887 static int de4x5_rx_ovfc(struct device *dev);
888
889 static int autoconf_media(struct device *dev);
890 static void create_packet(struct device *dev, char *frame, int len);
891 static void de4x5_us_delay(u32 usec);
892 static void de4x5_ms_delay(u32 msec);
893 static void load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb);
894 static int dc21040_autoconf(struct device *dev);
895 static int dc21041_autoconf(struct device *dev);
896 static int dc21140m_autoconf(struct device *dev);
897 static int dc2114x_autoconf(struct device *dev);
898 static int srom_autoconf(struct device *dev);
899 static int de4x5_suspect_state(struct device *dev, int timeout, int prev_state, int (*fn)(struct device *, int), int (*asfn)(struct device *));
900 static int dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct device *, int));
901 static int test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
902 static int test_for_100Mb(struct device *dev, int msec);
903 static int wait_for_link(struct device *dev);
904 static int test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec);
905 static int is_spd_100(struct device *dev);
906 static int is_100_up(struct device *dev);
907 static int is_10_up(struct device *dev);
908 static int is_anc_capable(struct device *dev);
909 static int ping_media(struct device *dev, int msec);
910 static struct sk_buff *de4x5_alloc_rx_buff(struct device *dev, int index, int len);
911 static void de4x5_free_rx_buffs(struct device *dev);
912 static void de4x5_free_tx_buffs(struct device *dev);
913 static void de4x5_save_skbs(struct device *dev);
914 static void de4x5_rst_desc_ring(struct device *dev);
915 static void de4x5_cache_state(struct device *dev, int flag);
916 static void de4x5_put_cache(struct device *dev, struct sk_buff *skb);
917 static void de4x5_putb_cache(struct device *dev, struct sk_buff *skb);
918 static struct sk_buff *de4x5_get_cache(struct device *dev);
919 static void de4x5_setup_intr(struct device *dev);
920 static void de4x5_init_connection(struct device *dev);
921 static int de4x5_reset_phy(struct device *dev);
922 static void reset_init_sia(struct device *dev, s32 sicr, s32 strr, s32 sigr);
923 static int test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec);
924 static int test_tp(struct device *dev, s32 msec);
925 static int EISA_signature(char *name, s32 eisa_id);
926 static int PCI_signature(char *name, struct bus_type *lp);
927 static void DevicePresent(u_long iobase);
928 static void enet_addr_rst(u_long aprom_addr);
929 static int de4x5_bad_srom(struct bus_type *lp);
930 static short srom_rd(u_long address, u_char offset);
931 static void srom_latch(u_int command, u_long address);
932 static void srom_command(u_int command, u_long address);
933 static void srom_address(u_int command, u_long address, u_char offset);
934 static short srom_data(u_int command, u_long address);
935 /*static void srom_busy(u_int command, u_long address);*/
936 static void sendto_srom(u_int command, u_long addr);
937 static int getfrom_srom(u_long addr);
938 static int srom_map_media(struct device *dev);
939 static int srom_infoleaf_info(struct device *dev);
940 static void srom_init(struct device *dev);
941 static void srom_exec(struct device *dev, u_char *p);
942 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
943 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
944 static int mii_rdata(u_long ioaddr);
945 static void mii_wdata(int data, int len, u_long ioaddr);
946 static void mii_ta(u_long rw, u_long ioaddr);
947 static int mii_swap(int data, int len);
948 static void mii_address(u_char addr, u_long ioaddr);
949 static void sendto_mii(u32 command, int data, u_long ioaddr);
950 static int getfrom_mii(u32 command, u_long ioaddr);
951 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
952 static int mii_get_phy(struct device *dev);
953 static void SetMulticastFilter(struct device *dev);
954 static int get_hw_addr(struct device *dev);
955 static void srom_repair(struct device *dev, int card);
956 static int test_bad_enet(struct device *dev, int status);
957 #if !defined(__sparc_v9__) && !defined(__powerpc__)
958 static void eisa_probe(struct device *dev, u_long iobase);
959 #endif
960 static void pci_probe(struct device *dev, u_long iobase);
961 static void srom_search(struct pci_dev *pdev);
962 static char *build_setup_frame(struct device *dev, int mode);
963 static void disable_ast(struct device *dev);
964 static void enable_ast(struct device *dev, u32 time_out);
965 static long de4x5_switch_mac_port(struct device *dev);
966 static int gep_rd(struct device *dev);
967 static void gep_wr(s32 data, struct device *dev);
968 static void timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec);
969 static void yawn(struct device *dev, int state);
970 static void link_modules(struct device *dev, struct device *tmp);
971 static void de4x5_parse_params(struct device *dev);
972 static void de4x5_dbg_open(struct device *dev);
973 static void de4x5_dbg_mii(struct device *dev, int k);
974 static void de4x5_dbg_media(struct device *dev);
975 static void de4x5_dbg_srom(struct de4x5_srom *p);
976 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
977 static int de4x5_strncmp(char *a, char *b, int n);
978 static int dc21041_infoleaf(struct device *dev);
979 static int dc21140_infoleaf(struct device *dev);
980 static int dc21142_infoleaf(struct device *dev);
981 static int dc21143_infoleaf(struct device *dev);
982 static int type0_infoblock(struct device *dev, u_char count, u_char *p);
983 static int type1_infoblock(struct device *dev, u_char count, u_char *p);
984 static int type2_infoblock(struct device *dev, u_char count, u_char *p);
985 static int type3_infoblock(struct device *dev, u_char count, u_char *p);
986 static int type4_infoblock(struct device *dev, u_char count, u_char *p);
987 static int type5_infoblock(struct device *dev, u_char count, u_char *p);
988 static int compact_infoblock(struct device *dev, u_char count, u_char *p);
989
990 #ifdef MODULE
991 int init_module(void);
992 void cleanup_module(void);
993 static struct device *unlink_modules(struct device *p);
994 static struct device *insert_device(struct device *dev, u_long iobase,
995 int (*init)(struct device *));
996 static int count_adapters(void);
997 static int loading_module = 1;
998 MODULE_PARM(de4x5_debug, "i");
999 MODULE_PARM(dec_only, "i");
1000 MODULE_PARM(args, "s");
1001 # else
1002 static int loading_module = 0;
1003 #endif /* MODULE */
1004
1005 static char name[DE4X5_NAME_LENGTH + 1];
1006 #if !defined(__sparc_v9__) && !defined(__powerpc__)
1007 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1008 static int lastEISA = 0;
1009 #else
1010 static int lastEISA = MAX_EISA_SLOTS; /* Only PCI probes */
1011 #endif
1012 static int num_de4x5s = 0;
1013 static int cfrv = 0, useSROM = 0;
1014 static int lastPCI = -1;
1015 static struct device *lastModule = NULL;
1016
1017 /*
1018 ** List the SROM infoleaf functions and chipsets
1019 */
1020 struct InfoLeaf {
1021 int chipset;
1022 int (*fn)(struct device *);
1023 };
1024 static struct InfoLeaf infoleaf_array[] = {
1025 {DC21041, dc21041_infoleaf},
1026 {DC21140, dc21140_infoleaf},
1027 {DC21142, dc21142_infoleaf},
1028 {DC21143, dc21143_infoleaf}
1029 };
1030 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1031
1032 /*
1033 ** List the SROM info block functions
1034 */
1035 static int (*dc_infoblock[])(struct device *dev, u_char, u_char *) = {
1036 type0_infoblock,
1037 type1_infoblock,
1038 type2_infoblock,
1039 type3_infoblock,
1040 type4_infoblock,
1041 type5_infoblock,
1042 compact_infoblock
1043 };
1044
1045 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1046
1047 /*
1048 ** Miscellaneous defines...
1049 */
1050 #define RESET_DE4X5 {\
1051 int i;\
1052 i=inl(DE4X5_BMR);\
1053 de4x5_ms_delay(1);\
1054 outl(i | BMR_SWR, DE4X5_BMR);\
1055 de4x5_ms_delay(1);\
1056 outl(i, DE4X5_BMR);\
1057 de4x5_ms_delay(1);\
1058 for (i=0;i<5;i++) {inl(DE4X5_BMR); de4x5_ms_delay(1);}\
1059 de4x5_ms_delay(1);\
1060 }
1061
1062 #define PHY_HARD_RESET {\
1063 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1064 mdelay(1); /* Assert for 1ms */\
1065 outl(0x00, DE4X5_GEP);\
1066 mdelay(2); /* Wait for 2ms */\
1067 }
1068
1069 \f
1070 /*
1071 ** Autoprobing in modules is allowed here. See the top of the file for
1072 ** more info.
1073 */
1074 __initfunc(int
1075 de4x5_probe(struct device *dev))
1076 {
1077 u_long iobase = dev->base_addr;
1078
1079 #if !defined(__sparc_v9__) && !defined(__powerpc__)
1080 eisa_probe(dev, iobase);
1081 #endif
1082 if (lastEISA == MAX_EISA_SLOTS) {
1083 pci_probe(dev, iobase);
1084 }
1085
1086 return (dev->priv ? 0 : -ENODEV);
1087 }
1088
1089 __initfunc(static int
1090 de4x5_hw_init(struct device *dev, u_long iobase))
1091 {
1092 struct bus_type *lp = &bus;
1093 int i, status=0;
1094 char *tmp;
1095
1096 /* Ensure we're not sleeping */
1097 if (lp->bus == EISA) {
1098 outb(WAKEUP, PCI_CFPM);
1099 } else {
1100 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
1101 PCI_CFDA_PSM, WAKEUP);
1102 }
1103 de4x5_ms_delay(10);
1104
1105 RESET_DE4X5;
1106
1107 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1108 return -ENXIO; /* Hardware could not reset */
1109 }
1110
1111 /*
1112 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1113 */
1114 useSROM = FALSE;
1115 if (lp->bus == PCI) {
1116 PCI_signature(name, lp);
1117 } else {
1118 EISA_signature(name, EISA_ID0);
1119 }
1120
1121 if (*name == '\0') { /* Not found a board signature */
1122 return -ENXIO;
1123 }
1124
1125 dev->base_addr = iobase;
1126 if (lp->bus == EISA) {
1127 printk("%s: %s at 0x%04lx (EISA slot %ld)",
1128 dev->name, name, iobase, ((iobase>>12)&0x0f));
1129 } else { /* PCI port address */
1130 printk("%s: %s at 0x%04lx (PCI bus %d, device %d)", dev->name, name,
1131 iobase, lp->bus_num, lp->device);
1132 }
1133
1134 printk(", h/w address ");
1135 status = get_hw_addr(dev);
1136 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1137 printk("%2.2x:", dev->dev_addr[i]);
1138 }
1139 printk("%2.2x,\n", dev->dev_addr[i]);
1140
1141 if (status != 0) {
1142 printk(" which has an Ethernet PROM CRC error.\n");
1143 return -ENXIO;
1144 } else {
1145 struct de4x5_private *lp;
1146
1147 /*
1148 ** Reserve a section of kernel memory for the adapter
1149 ** private area and the TX/RX descriptor rings.
1150 */
1151 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
1152 GFP_KERNEL);
1153 if (dev->priv == NULL) {
1154 return -ENOMEM;
1155 }
1156
1157 /*
1158 ** Align to a longword boundary
1159 */
1160 tmp = dev->priv;
1161 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
1162 lp = (struct de4x5_private *)dev->priv;
1163 memset(dev->priv, 0, sizeof(struct de4x5_private));
1164 lp->bus = bus.bus;
1165 lp->bus_num = bus.bus_num;
1166 lp->device = bus.device;
1167 lp->chipset = bus.chipset;
1168 lp->cache.priv = tmp;
1169 lp->cache.gepc = GEP_INIT;
1170 lp->asBit = GEP_SLNK;
1171 lp->asPolarity = GEP_SLNK;
1172 lp->asBitValid = TRUE;
1173 lp->timeout = -1;
1174 lp->useSROM = useSROM;
1175 memcpy((char *)&lp->srom,(char *)&bus.srom,sizeof(struct de4x5_srom));
1176 de4x5_parse_params(dev);
1177
1178 /*
1179 ** Choose correct autosensing in case someone messed up
1180 */
1181 lp->autosense = lp->params.autosense;
1182 if (lp->chipset != DC21140) {
1183 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1184 lp->params.autosense = TP;
1185 }
1186 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1187 lp->params.autosense = BNC;
1188 }
1189 }
1190 lp->fdx = lp->params.fdx;
1191 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
1192
1193 /*
1194 ** Set up the RX descriptor ring (Intels)
1195 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1196 */
1197 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1198 for (i=0; i<NUM_RX_DESC; i++) {
1199 lp->rx_ring[i].status = 0;
1200 lp->rx_ring[i].des1 = RX_BUFF_SZ;
1201 lp->rx_ring[i].buf = 0;
1202 lp->rx_ring[i].next = 0;
1203 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1204 }
1205
1206 #else
1207 if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
1208 GFP_KERNEL)) == NULL) {
1209 kfree(lp->cache.priv);
1210 return -ENOMEM;
1211 }
1212
1213 lp->cache.buf = tmp;
1214 tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
1215 for (i=0; i<NUM_RX_DESC; i++) {
1216 lp->rx_ring[i].status = 0;
1217 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1218 lp->rx_ring[i].buf = cpu_to_le32(virt_to_bus(tmp+i*RX_BUFF_SZ));
1219 lp->rx_ring[i].next = 0;
1220 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1221 }
1222 #endif
1223
1224 barrier();
1225
1226 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
1227 DE4X5_EISA_TOTAL_SIZE),
1228 lp->adapter_name);
1229
1230 lp->rxRingSize = NUM_RX_DESC;
1231 lp->txRingSize = NUM_TX_DESC;
1232
1233 /* Write the end of list marker to the descriptor lists */
1234 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1235 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1236
1237 /* Tell the adapter where the TX/RX rings are located. */
1238 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1239 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1240
1241 /* Initialise the IRQ mask and Enable/Disable */
1242 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1243 lp->irq_en = IMR_NIM | IMR_AIM;
1244
1245 /* Create a loopback packet frame for later media probing */
1246 create_packet(dev, lp->frame, sizeof(lp->frame));
1247
1248 /* Check if the RX overflow bug needs testing for */
1249 i = cfrv & 0x000000fe;
1250 if ((lp->chipset == DC21140) && (i == 0x20)) {
1251 lp->rx_ovf = 1;
1252 }
1253
1254 /* Initialise the SROM pointers if possible */
1255 if (lp->useSROM) {
1256 lp->state = INITIALISED;
1257 if (srom_infoleaf_info(dev)) {
1258 return -ENXIO;
1259 }
1260 srom_init(dev);
1261 }
1262
1263 lp->state = CLOSED;
1264
1265 /*
1266 ** Check for an MII interface
1267 */
1268 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1269 mii_get_phy(dev);
1270 }
1271
1272 #ifndef __sparc_v9__
1273 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1274 #else
1275 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1276 #endif
1277 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1278 }
1279
1280 if (de4x5_debug & DEBUG_VERSION) {
1281 printk(version);
1282 }
1283
1284 /* The DE4X5-specific entries in the device structure. */
1285 dev->open = &de4x5_open;
1286 dev->hard_start_xmit = &de4x5_queue_pkt;
1287 dev->stop = &de4x5_close;
1288 dev->get_stats = &de4x5_get_stats;
1289 dev->set_multicast_list = &set_multicast_list;
1290 dev->do_ioctl = &de4x5_ioctl;
1291
1292 dev->mem_start = 0;
1293
1294 /* Fill in the generic fields of the device structure. */
1295 ether_setup(dev);
1296
1297 /* Let the adapter sleep to save power */
1298 yawn(dev, SLEEP);
1299
1300 return status;
1301 }
1302
1303 \f
1304 static int
1305 de4x5_open(struct device *dev)
1306 {
1307 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1308 u_long iobase = dev->base_addr;
1309 int i, status = 0;
1310 s32 omr;
1311
1312 /* Allocate the RX buffers */
1313 for (i=0; i<lp->rxRingSize; i++) {
1314 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1315 de4x5_free_rx_buffs(dev);
1316 return -EAGAIN;
1317 }
1318 }
1319
1320 /*
1321 ** Wake up the adapter
1322 */
1323 yawn(dev, WAKEUP);
1324
1325 /*
1326 ** Re-initialize the DE4X5...
1327 */
1328 status = de4x5_init(dev);
1329
1330 lp->state = OPEN;
1331 de4x5_dbg_open(dev);
1332
1333 if (request_irq(dev->irq, (void *)de4x5_interrupt, SA_SHIRQ,
1334 lp->adapter_name, dev)) {
1335 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1336 if (request_irq(dev->irq, de4x5_interrupt, SA_INTERRUPT | SA_SHIRQ,
1337 lp->adapter_name, dev)) {
1338 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1339 disable_ast(dev);
1340 de4x5_free_rx_buffs(dev);
1341 de4x5_free_tx_buffs(dev);
1342 yawn(dev, SLEEP);
1343 lp->state = CLOSED;
1344 return -EAGAIN;
1345 } else {
1346 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1347 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1348 }
1349 }
1350
1351 dev->tbusy = 0;
1352 dev->start = 1;
1353 dev->interrupt = UNMASK_INTERRUPTS;
1354 dev->trans_start = jiffies;
1355
1356 START_DE4X5;
1357
1358 de4x5_setup_intr(dev);
1359
1360 if (de4x5_debug & DEBUG_OPEN) {
1361 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1362 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1363 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1364 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1365 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1366 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1367 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1368 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1369 }
1370
1371 MOD_INC_USE_COUNT;
1372
1373 return status;
1374 }
1375
1376 /*
1377 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1378 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1379 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1380 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1381 ** to be data corruption problems if it is larger (UDP errors seen from a
1382 ** ttcp source).
1383 */
1384 static int
1385 de4x5_init(struct device *dev)
1386 {
1387 /* Lock out other processes whilst setting up the hardware */
1388 test_and_set_bit(0, (void *)&dev->tbusy);
1389
1390 de4x5_sw_reset(dev);
1391
1392 /* Autoconfigure the connected port */
1393 autoconf_media(dev);
1394
1395 return 0;
1396 }
1397
1398 static int
1399 de4x5_sw_reset(struct device *dev)
1400 {
1401 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1402 u_long iobase = dev->base_addr;
1403 int i, j, status = 0;
1404 s32 bmr, omr;
1405
1406 /* Select the MII or SRL port now and RESET the MAC */
1407 if (!lp->useSROM) {
1408 if (lp->phy[lp->active].id != 0) {
1409 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1410 } else {
1411 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1412 }
1413 de4x5_switch_mac_port(dev);
1414 }
1415
1416 /*
1417 ** Set the programmable burst length to 8 longwords for all the DC21140
1418 ** Fasternet chips and 4 longwords for all others: DMA errors result
1419 ** without these values. Cache align 16 long.
1420 */
1421 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | CACHE_ALIGN;
1422 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1423 outl(bmr, DE4X5_BMR);
1424
1425 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1426 if (lp->chipset == DC21140) {
1427 omr |= (OMR_SDP | OMR_SB);
1428 }
1429 lp->setup_f = PERFECT;
1430 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
1431 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
1432
1433 lp->rx_new = lp->rx_old = 0;
1434 lp->tx_new = lp->tx_old = 0;
1435
1436 for (i = 0; i < lp->rxRingSize; i++) {
1437 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1438 }
1439
1440 for (i = 0; i < lp->txRingSize; i++) {
1441 lp->tx_ring[i].status = cpu_to_le32(0);
1442 }
1443
1444 barrier();
1445
1446 /* Build the setup frame depending on filtering mode */
1447 SetMulticastFilter(dev);
1448
1449 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
1450 outl(omr|OMR_ST, DE4X5_OMR);
1451
1452 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1453 sti(); /* Ensure timer interrupts */
1454 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1455 mdelay(1);
1456 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1457 }
1458 outl(omr, DE4X5_OMR); /* Stop everything! */
1459
1460 if (j == 0) {
1461 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1462 inl(DE4X5_STS));
1463 status = -EIO;
1464 }
1465
1466 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1467 lp->tx_old = lp->tx_new;
1468
1469 return status;
1470 }
1471
1472 /*
1473 ** Writes a socket buffer address to the next available transmit descriptor.
1474 */
1475 static int
1476 de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
1477 {
1478 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1479 u_long iobase = dev->base_addr;
1480 int status = 0;
1481
1482 test_and_set_bit(0, (void*)&dev->tbusy); /* Stop send re-tries */
1483 if (lp->tx_enable == NO) { /* Cannot send for now */
1484 return -1;
1485 }
1486
1487 /*
1488 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1489 ** interrupts are lost by delayed descriptor status updates relative to
1490 ** the irq assertion, especially with a busy PCI bus.
1491 */
1492 cli();
1493 de4x5_tx(dev);
1494 sti();
1495
1496 /* Test if cache is already locked - requeue skb if so */
1497 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !dev->interrupt)
1498 return -1;
1499
1500 /* Transmit descriptor ring full or stale skb */
1501 if (dev->tbusy || lp->tx_skb[lp->tx_new]) {
1502 if (dev->interrupt) {
1503 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1504 } else {
1505 de4x5_put_cache(dev, skb);
1506 }
1507 if (de4x5_debug & DEBUG_TX) {
1508 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%ld\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), dev->tbusy, inl(DE4X5_IMR), inl(DE4X5_OMR), (lp->tx_skb[lp->tx_new] ? "YES" : "NO"));
1509 }
1510 } else if (skb->len > 0) {
1511 /* If we already have stuff queued locally, use that first */
1512 if (lp->cache.skb && !dev->interrupt) {
1513 de4x5_put_cache(dev, skb);
1514 skb = de4x5_get_cache(dev);
1515 }
1516
1517 while (skb && !dev->tbusy && !lp->tx_skb[lp->tx_new]) {
1518 cli();
1519 test_and_set_bit(0, (void*)&dev->tbusy);
1520 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1521 lp->stats.tx_bytes += skb->len;
1522 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1523
1524 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1525 dev->trans_start = jiffies;
1526
1527 if (TX_BUFFS_AVAIL) {
1528 dev->tbusy = 0; /* Another pkt may be queued */
1529 }
1530 skb = de4x5_get_cache(dev);
1531 sti();
1532 }
1533 if (skb) de4x5_putb_cache(dev, skb);
1534 }
1535
1536 lp->cache.lock = 0;
1537
1538 return status;
1539 }
1540
1541 /*
1542 ** The DE4X5 interrupt handler.
1543 **
1544 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1545 ** so that the asserted interrupt always has some real data to work with -
1546 ** if these I/O accesses are ever changed to memory accesses, ensure the
1547 ** STS write is read immediately to complete the transaction if the adapter
1548 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1549 ** is high and descriptor status bits cannot be set before the associated
1550 ** interrupt is asserted and this routine entered.
1551 */
1552 static void
1553 de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1554 {
1555 struct device *dev = (struct device *)dev_id;
1556 struct de4x5_private *lp;
1557 s32 imr, omr, sts, limit;
1558 u_long iobase;
1559
1560 if (dev == NULL) {
1561 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1562 return;
1563 }
1564 lp = (struct de4x5_private *)dev->priv;
1565 iobase = dev->base_addr;
1566
1567 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &dev->interrupt))
1568 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1569
1570 DISABLE_IRQs; /* Ensure non re-entrancy */
1571 synchronize_irq();
1572
1573 for (limit=0; limit<8; limit++) {
1574 sts = inl(DE4X5_STS); /* Read IRQ status */
1575 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1576
1577 if (!(sts & lp->irq_mask)) break;/* All done */
1578
1579 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1580 de4x5_rx(dev);
1581
1582 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1583 de4x5_tx(dev);
1584
1585 if (sts & STS_LNF) { /* TP Link has failed */
1586 lp->irq_mask &= ~IMR_LFM;
1587 }
1588
1589 if (sts & STS_UNF) { /* Transmit underrun */
1590 de4x5_txur(dev);
1591 }
1592
1593 if (sts & STS_SE) { /* Bus Error */
1594 STOP_DE4X5;
1595 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1596 dev->name, sts);
1597 return;
1598 }
1599 }
1600
1601 /* Load the TX ring with any locally stored packets */
1602 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1603 while (lp->cache.skb && !dev->tbusy && lp->tx_enable) {
1604 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1605 }
1606 lp->cache.lock = 0;
1607 }
1608
1609 dev->interrupt = UNMASK_INTERRUPTS;
1610 ENABLE_IRQs;
1611
1612 return;
1613 }
1614
1615 static int
1616 de4x5_rx(struct device *dev)
1617 {
1618 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1619 u_long iobase = dev->base_addr;
1620 int entry;
1621 s32 status;
1622
1623 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1624 entry=lp->rx_new) {
1625 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1626
1627 if (lp->rx_ovf) {
1628 if (inl(DE4X5_MFC) & MFC_FOCM) {
1629 de4x5_rx_ovfc(dev);
1630 break;
1631 }
1632 }
1633
1634 if (status & RD_FS) { /* Remember the start of frame */
1635 lp->rx_old = entry;
1636 }
1637
1638 if (status & RD_LS) { /* Valid frame status */
1639 if (lp->tx_enable) lp->linkOK++;
1640 if (status & RD_ES) { /* There was an error. */
1641 lp->stats.rx_errors++; /* Update the error stats. */
1642 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1643 if (status & RD_CE) lp->stats.rx_crc_errors++;
1644 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1645 if (status & RD_TL) lp->stats.rx_length_errors++;
1646 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1647 if (status & RD_CS) lp->pktStats.rx_collision++;
1648 if (status & RD_DB) lp->pktStats.rx_dribble++;
1649 if (status & RD_OF) lp->pktStats.rx_overflow++;
1650 } else { /* A valid frame received */
1651 struct sk_buff *skb;
1652 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1653 >> 16) - 4;
1654
1655 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1656 printk("%s: Insufficient memory; nuking packet.\n",
1657 dev->name);
1658 lp->stats.rx_dropped++;
1659 } else {
1660 de4x5_dbg_rx(skb, pkt_len);
1661
1662 /* Push up the protocol stack */
1663 skb->protocol=eth_type_trans(skb,dev);
1664 netif_rx(skb);
1665
1666 /* Update stats */
1667 lp->stats.rx_packets++;
1668 lp->stats.rx_bytes += pkt_len;
1669 de4x5_local_stats(dev, skb->data, pkt_len);
1670 }
1671 }
1672
1673 /* Change buffer ownership for this frame, back to the adapter */
1674 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1675 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1676 barrier();
1677 }
1678 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1679 barrier();
1680 }
1681
1682 /*
1683 ** Update entry information
1684 */
1685 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1686 }
1687
1688 return 0;
1689 }
1690
1691 /*
1692 ** Buffer sent - check for TX buffer errors.
1693 */
1694 static int
1695 de4x5_tx(struct device *dev)
1696 {
1697 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1698 u_long iobase = dev->base_addr;
1699 int entry;
1700 s32 status;
1701
1702 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1703 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1704 if (status < 0) { /* Buffer not sent yet */
1705 break;
1706 } else if (status != 0x7fffffff) { /* Not setup frame */
1707 if (status & TD_ES) { /* An error happened */
1708 lp->stats.tx_errors++;
1709 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1710 if (status & TD_LC) lp->stats.tx_window_errors++;
1711 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1712 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1713 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1714
1715 if (TX_PKT_PENDING) {
1716 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1717 }
1718 } else { /* Packet sent */
1719 lp->stats.tx_packets++;
1720 if (lp->tx_enable) lp->linkOK++;
1721 }
1722 /* Update the collision counter */
1723 lp->stats.collisions += ((status & TD_EC) ? 16 :
1724 ((status & TD_CC) >> 3));
1725
1726 /* Free the buffer. */
1727 if (lp->tx_skb[entry] != NULL) {
1728 dev_kfree_skb(lp->tx_skb[entry]);
1729 lp->tx_skb[entry] = NULL;
1730 }
1731 }
1732
1733 /* Update all the pointers */
1734 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1735 }
1736
1737 if (TX_BUFFS_AVAIL && dev->tbusy) { /* Any resources available? */
1738 dev->tbusy = 0; /* Clear TX busy flag */
1739 if (dev->interrupt) mark_bh(NET_BH);
1740 }
1741
1742 return 0;
1743 }
1744
1745 static int
1746 de4x5_ast(struct device *dev)
1747 {
1748 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1749 int next_tick = DE4X5_AUTOSENSE_MS;
1750
1751 disable_ast(dev);
1752
1753 if (lp->useSROM) {
1754 next_tick = srom_autoconf(dev);
1755 } else if (lp->chipset == DC21140) {
1756 next_tick = dc21140m_autoconf(dev);
1757 } else if (lp->chipset == DC21041) {
1758 next_tick = dc21041_autoconf(dev);
1759 } else if (lp->chipset == DC21040) {
1760 next_tick = dc21040_autoconf(dev);
1761 }
1762 lp->linkOK = 0;
1763 enable_ast(dev, next_tick);
1764
1765 return 0;
1766 }
1767
1768 static int
1769 de4x5_txur(struct device *dev)
1770 {
1771 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1772 u_long iobase = dev->base_addr;
1773 int omr;
1774
1775 omr = inl(DE4X5_OMR);
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1777 omr &= ~(OMR_ST|OMR_SR);
1778 outl(omr, DE4X5_OMR);
1779 while (inl(DE4X5_STS) & STS_TS);
1780 if ((omr & OMR_TR) < OMR_TR) {
1781 omr += 0x4000;
1782 } else {
1783 omr |= OMR_SF;
1784 }
1785 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1786 }
1787
1788 return 0;
1789 }
1790
1791 static int
1792 de4x5_rx_ovfc(struct device *dev)
1793 {
1794 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1795 u_long iobase = dev->base_addr;
1796 int omr;
1797
1798 omr = inl(DE4X5_OMR);
1799 outl(omr & ~OMR_SR, DE4X5_OMR);
1800 while (inl(DE4X5_STS) & STS_RS);
1801
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1805 }
1806
1807 outl(omr, DE4X5_OMR);
1808
1809 return 0;
1810 }
1811
1812 static int
1813 de4x5_close(struct device *dev)
1814 {
1815 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1816 u_long iobase = dev->base_addr;
1817 s32 imr, omr;
1818
1819 disable_ast(dev);
1820 dev->start = 0;
1821 dev->tbusy = 1;
1822
1823 if (de4x5_debug & DEBUG_CLOSE) {
1824 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1825 dev->name, inl(DE4X5_STS));
1826 }
1827
1828 /*
1829 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1830 */
1831 DISABLE_IRQs;
1832 STOP_DE4X5;
1833
1834 /* Free the associated irq */
1835 free_irq(dev->irq, dev);
1836 lp->state = CLOSED;
1837
1838 /* Free any socket buffers */
1839 de4x5_free_rx_buffs(dev);
1840 de4x5_free_tx_buffs(dev);
1841
1842 MOD_DEC_USE_COUNT;
1843
1844 /* Put the adapter to sleep to save power */
1845 yawn(dev, SLEEP);
1846
1847 return 0;
1848 }
1849
1850 static struct net_device_stats *
1851 de4x5_get_stats(struct device *dev)
1852 {
1853 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1854 u_long iobase = dev->base_addr;
1855
1856 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1857
1858 return &lp->stats;
1859 }
1860
1861 static void
1862 de4x5_local_stats(struct device *dev, char *buf, int pkt_len)
1863 {
1864 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1865 int i;
1866
1867 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1868 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1869 lp->pktStats.bins[i]++;
1870 i = DE4X5_PKT_STAT_SZ;
1871 }
1872 }
1873 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1874 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1875 lp->pktStats.broadcast++;
1876 } else {
1877 lp->pktStats.multicast++;
1878 }
1879 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1880 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1881 lp->pktStats.unicast++;
1882 }
1883
1884 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1885 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1886 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1887 }
1888
1889 return;
1890 }
1891
1892 /*
1893 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1894 ** If the flag is changed on a descriptor that is being read by the hardware,
1895 ** I assume PCI transaction ordering will mean you are either successful or
1896 ** just miss asserting the change to the hardware. Anyway you're messing with
1897 ** a descriptor you don't own, but this shouldn't kill the chip provided
1898 ** the descriptor register is read only to the hardware.
1899 */
1900 static void
1901 load_packet(struct device *dev, char *buf, u32 flags, struct sk_buff *skb)
1902 {
1903 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1904 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1905
1906 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(virt_to_bus(buf));
1907 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1908 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1909 lp->tx_skb[lp->tx_new] = skb;
1910 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1911 barrier();
1912
1913 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1914 barrier();
1915
1916 return;
1917 }
1918
1919 /*
1920 ** Set or clear the multicast filter for this adaptor.
1921 */
1922 static void
1923 set_multicast_list(struct device *dev)
1924 {
1925 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1926 u_long iobase = dev->base_addr;
1927
1928 /* First, double check that the adapter is open */
1929 if (lp->state == OPEN) {
1930 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1931 u32 omr;
1932 omr = inl(DE4X5_OMR);
1933 omr |= OMR_PR;
1934 outl(omr, DE4X5_OMR);
1935 } else {
1936 SetMulticastFilter(dev);
1937 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1938 SETUP_FRAME_LEN, NULL);
1939
1940 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1941 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1942 dev->trans_start = jiffies;
1943 }
1944 }
1945
1946 return;
1947 }
1948
1949 /*
1950 ** Calculate the hash code and update the logical address filter
1951 ** from a list of ethernet multicast addresses.
1952 ** Little endian crc one liner from Matt Thomas, DEC.
1953 */
1954 static void
1955 SetMulticastFilter(struct device *dev)
1956 {
1957 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1958 struct dev_mc_list *dmi=dev->mc_list;
1959 u_long iobase = dev->base_addr;
1960 int i, j, bit, byte;
1961 u16 hashcode;
1962 u32 omr, crc, poly = CRC_POLYNOMIAL_LE;
1963 char *pa;
1964 unsigned char *addrs;
1965
1966 omr = inl(DE4X5_OMR);
1967 omr &= ~(OMR_PR | OMR_PM);
1968 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1969
1970 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1971 omr |= OMR_PM; /* Pass all multicasts */
1972 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1973 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1974 addrs=dmi->dmi_addr;
1975 dmi=dmi->next;
1976 if ((*addrs & 0x01) == 1) { /* multicast address? */
1977 crc = 0xffffffff; /* init CRC for each address */
1978 for (byte=0;byte<ETH_ALEN;byte++) {/* for each address byte */
1979 /* process each address bit */
1980 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1981 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1982 }
1983 }
1984 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1985
1986 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1987 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1988
1989 byte <<= 1; /* calc offset into setup frame */
1990 if (byte & 0x02) {
1991 byte -= 1;
1992 }
1993 lp->setup_frame[byte] |= bit;
1994 }
1995 }
1996 } else { /* Perfect filtering */
1997 for (j=0; j<dev->mc_count; j++) {
1998 addrs=dmi->dmi_addr;
1999 dmi=dmi->next;
2000 for (i=0; i<ETH_ALEN; i++) {
2001 *(pa + (i&1)) = *addrs++;
2002 if (i & 0x01) pa += 4;
2003 }
2004 }
2005 }
2006 outl(omr, DE4X5_OMR);
2007
2008 return;
2009 }
2010
2011 #if !defined(__sparc_v9__) && !defined(__powerpc__)
2012 /*
2013 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually
2014 ** the motherboard. Upto 15 EISA devices are supported.
2015 */
2016 __initfunc(static void
2017 eisa_probe(struct device *dev, u_long ioaddr))
2018 {
2019 int i, maxSlots, status, device;
2020 u_char irq;
2021 u_short vendor;
2022 u32 cfid;
2023 u_long iobase;
2024 struct bus_type *lp = &bus;
2025 char name[DE4X5_STRLEN];
2026
2027 if (lastEISA == MAX_EISA_SLOTS) return;/* No more EISA devices to search */
2028
2029 lp->bus = EISA;
2030
2031 if (ioaddr == 0) { /* Autoprobing */
2032 iobase = EISA_SLOT_INC; /* Get the first slot address */
2033 i = 1;
2034 maxSlots = MAX_EISA_SLOTS;
2035 } else { /* Probe a specific location */
2036 iobase = ioaddr;
2037 i = (ioaddr >> 12);
2038 maxSlots = i + 1;
2039 }
2040
2041 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
2042 if (EISA_signature(name, EISA_ID)) {
2043 cfid = (u32) inl(PCI_CFID);
2044 cfrv = (u_short) inl(PCI_CFRV);
2045 device = (cfid >> 8) & 0x00ffff00;
2046 vendor = (u_short) cfid;
2047
2048 /* Read the EISA Configuration Registers */
2049 irq = inb(EISA_REG0);
2050 irq = de4x5_irq[(irq >> 1) & 0x03];
2051
2052 if (is_DC2114x) device |= (cfrv & CFRV_RN);
2053 lp->chipset = device;
2054
2055 /* Write the PCI Configuration Registers */
2056 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2057 outl(0x00006000, PCI_CFLT);
2058 outl(iobase, PCI_CBIO);
2059
2060 DevicePresent(EISA_APROM);
2061 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
2062 dev->irq = irq;
2063 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2064 num_de4x5s++;
2065 if (loading_module) link_modules(lastModule, dev);
2066 lastEISA = i;
2067 return;
2068 }
2069 } else if (ioaddr != 0) {
2070 printk("%s: region already allocated at 0x%04lx.\n", dev->name,iobase);
2071 }
2072 }
2073 }
2074
2075 if (ioaddr == 0) lastEISA = i;
2076
2077 return;
2078 }
2079 #endif /* !(__sparc_v9__) && !(__powerpc__) */
2080
2081 /*
2082 ** PCI bus I/O device probe
2083 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2084 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2085 ** enabled by the user first in the set up utility. Hence we just check for
2086 ** enabled features and silently ignore the card if they're not.
2087 **
2088 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2089 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2090 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2091 ** PC doesn't conform to the PCI standard)!
2092 **
2093 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2094 ** kernels use the V0.535[n] drivers.
2095 */
2096 #define PCI_LAST_DEV 32
2097
2098 __initfunc(static void
2099 pci_probe(struct device *dev, u_long ioaddr))
2100 {
2101 u_char pb, pbus, dev_num, dnum, timer;
2102 u_short vendor, index, status;
2103 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2104 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2105 struct bus_type *lp = &bus;
2106 struct pci_dev *pdev = NULL;
2107
2108 if (lastPCI == NO_MORE_PCI) return;
2109
2110 if (!pcibios_present()) {
2111 lastPCI = NO_MORE_PCI;
2112 return; /* No PCI bus in this machine! */
2113 }
2114
2115 lp->bus = PCI;
2116 lp->bus_num = 0;
2117
2118 if ((ioaddr < 0x1000) && loading_module) {
2119 pbus = (u_short)(ioaddr >> 8);
2120 dnum = (u_short)(ioaddr & 0xff);
2121 } else {
2122 pbus = 0;
2123 dnum = 0;
2124 }
2125
2126 for (index=lastPCI+1; (pdev=pci_find_class(class, pdev))!=NULL; index++) {
2127 dev_num = PCI_SLOT(pdev->devfn);
2128 pb = pdev->bus->number;
2129 if ((pbus || dnum) && ((pbus != pb) || (dnum != dev_num))) continue;
2130
2131 vendor = pdev->vendor;
2132 device = pdev->device << 8;
2133 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2134
2135 /* Search for an SROM on this bus */
2136 if (lp->bus_num != pb) {
2137 lp->bus_num = pb;
2138 srom_search(pdev);
2139 }
2140
2141 /* Get the chip configuration revision register */
2142 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2143
2144 /* Set the device number information */
2145 lp->device = dev_num;
2146 lp->bus_num = pb;
2147
2148 /* Set the chipset information */
2149 if (is_DC2114x) device |= (cfrv & CFRV_RN);
2150 lp->chipset = device;
2151
2152 /* Get the board I/O address (64 bits on sparc64) */
2153 iobase = pdev->base_address[0] & CBIO_MASK;
2154
2155 /* Fetch the IRQ to be used */
2156 irq = pdev->irq;
2157 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2158
2159 /* Check if I/O accesses and Bus Mastering are enabled */
2160 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2161 #ifdef __powerpc__
2162 if (!(status & PCI_COMMAND_IO)) {
2163 status |= PCI_COMMAND_IO;
2164 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2165 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2166 }
2167 #endif /* __powerpc__ */
2168 if (!(status & PCI_COMMAND_IO)) continue;
2169
2170 if (!(status & PCI_COMMAND_MASTER)) {
2171 status |= PCI_COMMAND_MASTER;
2172 pcibios_write_config_word(pb, pdev->devfn, PCI_COMMAND, status);
2173 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2174 }
2175 if (!(status & PCI_COMMAND_MASTER)) continue;
2176
2177 /* Check the latency timer for values >= 0x60 */
2178 pcibios_read_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, &timer);
2179 if (timer < 0x60) {
2180 pcibios_write_config_byte(pb, pdev->devfn, PCI_LATENCY_TIMER, 0x60);
2181 }
2182
2183 DevicePresent(DE4X5_APROM);
2184 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
2185 dev->irq = irq;
2186 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
2187 num_de4x5s++;
2188 if (loading_module) {
2189 link_modules(lastModule, dev);
2190 lastPCI = index;
2191 }
2192 return;
2193 }
2194 } else if (ioaddr != 0) {
2195 printk("%s: region already allocated at 0x%04lx.\n", dev->name,
2196 iobase);
2197 }
2198 }
2199
2200 lastPCI = NO_MORE_PCI;
2201
2202 return;
2203 }
2204
2205 /*
2206 ** This function searches the current bus (which is >0) for a DECchip with an
2207 ** SROM, so that in multiport cards that have one SROM shared between multiple
2208 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2209 ** For single port cards this is a time waster...
2210 */
2211 __initfunc(static void
2212 srom_search(struct pci_dev *pdev))
2213 {
2214 u_char pb;
2215 u_short vendor, status;
2216 u_int irq = 0, device, class = DE4X5_CLASS_CODE;
2217 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2218 int i, j;
2219 struct bus_type *lp = &bus;
2220
2221 while ((pdev = pci_find_class(class, pdev))!= NULL) {
2222 if (lp->bus_num != pdev->bus->number) return;
2223 pb = pdev->bus->number;
2224 vendor = pdev->vendor;
2225 device = pdev->device << 8;
2226 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2227
2228 /* Get the chip configuration revision register */
2229 pcibios_read_config_dword(pb, pdev->devfn, PCI_REVISION_ID, &cfrv);
2230
2231 /* Set the device number information */
2232 lp->device = PCI_SLOT(pdev->devfn);
2233 lp->bus_num = pb;
2234
2235 /* Set the chipset information */
2236 if (is_DC2114x) device |= (cfrv & CFRV_RN);
2237 lp->chipset = device;
2238
2239 /* Get the board I/O address (64 bits on sparc64) */
2240 iobase = pdev->base_address[0] & CBIO_MASK;
2241
2242 /* Fetch the IRQ to be used */
2243 irq = pdev->irq;
2244 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2245
2246 /* Check if I/O accesses are enabled */
2247 pcibios_read_config_word(pb, pdev->devfn, PCI_COMMAND, &status);
2248 if (!(status & PCI_COMMAND_IO)) continue;
2249
2250 /* Search for a valid SROM attached to this DECchip */
2251 DevicePresent(DE4X5_APROM);
2252 for (j=0, i=0; i<ETH_ALEN; i++) {
2253 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2254 }
2255 if ((j != 0) && (j != 0x5fa)) {
2256 last.chipset = device;
2257 last.bus = pb;
2258 last.irq = irq;
2259 for (i=0; i<ETH_ALEN; i++) {
2260 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2261 }
2262 return;
2263 }
2264 }
2265
2266 return;
2267 }
2268
2269 __initfunc(static void
2270 link_modules(struct device *dev, struct device *tmp))
2271 {
2272 struct device *p=dev;
2273
2274 if (p) {
2275 while (((struct de4x5_private *)(p->priv))->next_module) {
2276 p = ((struct de4x5_private *)(p->priv))->next_module;
2277 }
2278
2279 if (dev != tmp) {
2280 ((struct de4x5_private *)(p->priv))->next_module = tmp;
2281 } else {
2282 ((struct de4x5_private *)(p->priv))->next_module = NULL;
2283 }
2284 }
2285
2286 return;
2287 }
2288
2289 /*
2290 ** Auto configure the media here rather than setting the port at compile
2291 ** time. This routine is called by de4x5_init() and when a loss of media is
2292 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2293 ** [TP] or no recent receive activity) to check whether the user has been
2294 ** sneaky and changed the port on us.
2295 */
2296 static int
2297 autoconf_media(struct device *dev)
2298 {
2299 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2300 u_long iobase = dev->base_addr;
2301 int next_tick = DE4X5_AUTOSENSE_MS;
2302
2303 lp->linkOK = 0;
2304 lp->c_media = AUTO; /* Bogus last media */
2305 disable_ast(dev);
2306 inl(DE4X5_MFC); /* Zero the lost frames counter */
2307 lp->media = INIT;
2308 lp->tcount = 0;
2309
2310 if (lp->useSROM) {
2311 next_tick = srom_autoconf(dev);
2312 } else if (lp->chipset == DC21040) {
2313 next_tick = dc21040_autoconf(dev);
2314 } else if (lp->chipset == DC21041) {
2315 next_tick = dc21041_autoconf(dev);
2316 } else if (lp->chipset == DC21140) {
2317 next_tick = dc21140m_autoconf(dev);
2318 }
2319
2320 enable_ast(dev, next_tick);
2321
2322 return (lp->media);
2323 }
2324
2325 /*
2326 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2327 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2328 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2329 ** The only way to test for that is to place a loopback packet onto the
2330 ** network and watch for errors. Since we're messing with the interrupt mask
2331 ** register, disable the board interrupts and do not allow any more packets to
2332 ** be queued to the hardware. Re-enable everything only when the media is
2333 ** found.
2334 ** I may have to "age out" locally queued packets so that the higher layer
2335 ** timeouts don't effectively duplicate packets on the network.
2336 */
2337 static int
2338 dc21040_autoconf(struct device *dev)
2339 {
2340 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2341 u_long iobase = dev->base_addr;
2342 int next_tick = DE4X5_AUTOSENSE_MS;
2343 s32 imr;
2344
2345 switch (lp->media) {
2346 case INIT:
2347 DISABLE_IRQs;
2348 lp->tx_enable = NO;
2349 lp->timeout = -1;
2350 de4x5_save_skbs(dev);
2351 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2352 lp->media = TP;
2353 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2354 lp->media = BNC_AUI;
2355 } else if (lp->autosense == EXT_SIA) {
2356 lp->media = EXT_SIA;
2357 } else {
2358 lp->media = NC;
2359 }
2360 lp->local_state = 0;
2361 next_tick = dc21040_autoconf(dev);
2362 break;
2363
2364 case TP:
2365 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2366 TP_SUSPECT, test_tp);
2367 break;
2368
2369 case TP_SUSPECT:
2370 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2371 break;
2372
2373 case BNC:
2374 case AUI:
2375 case BNC_AUI:
2376 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2377 BNC_AUI_SUSPECT, ping_media);
2378 break;
2379
2380 case BNC_AUI_SUSPECT:
2381 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2382 break;
2383
2384 case EXT_SIA:
2385 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2386 NC, EXT_SIA_SUSPECT, ping_media);
2387 break;
2388
2389 case EXT_SIA_SUSPECT:
2390 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2391 break;
2392
2393 case NC:
2394 /* default to TP for all */
2395 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2396 if (lp->media != lp->c_media) {
2397 de4x5_dbg_media(dev);
2398 lp->c_media = lp->media;
2399 }
2400 lp->media = INIT;
2401 lp->tx_enable = NO;
2402 break;
2403 }
2404
2405 return next_tick;
2406 }
2407
2408 static int
2409 dc21040_state(struct device *dev, int csr13, int csr14, int csr15, int timeout,
2410 int next_state, int suspect_state,
2411 int (*fn)(struct device *, int))
2412 {
2413 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2414 int next_tick = DE4X5_AUTOSENSE_MS;
2415 int linkBad;
2416
2417 switch (lp->local_state) {
2418 case 0:
2419 reset_init_sia(dev, csr13, csr14, csr15);
2420 lp->local_state++;
2421 next_tick = 500;
2422 break;
2423
2424 case 1:
2425 if (!lp->tx_enable) {
2426 linkBad = fn(dev, timeout);
2427 if (linkBad < 0) {
2428 next_tick = linkBad & ~TIMER_CB;
2429 } else {
2430 if (linkBad && (lp->autosense == AUTO)) {
2431 lp->local_state = 0;
2432 lp->media = next_state;
2433 } else {
2434 de4x5_init_connection(dev);
2435 }
2436 }
2437 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2438 lp->media = suspect_state;
2439 next_tick = 3000;
2440 }
2441 break;
2442 }
2443
2444 return next_tick;
2445 }
2446
2447 static int
2448 de4x5_suspect_state(struct device *dev, int timeout, int prev_state,
2449 int (*fn)(struct device *, int),
2450 int (*asfn)(struct device *))
2451 {
2452 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2453 int next_tick = DE4X5_AUTOSENSE_MS;
2454 int linkBad;
2455
2456 switch (lp->local_state) {
2457 case 1:
2458 if (lp->linkOK) {
2459 lp->media = prev_state;
2460 } else {
2461 lp->local_state++;
2462 next_tick = asfn(dev);
2463 }
2464 break;
2465
2466 case 2:
2467 linkBad = fn(dev, timeout);
2468 if (linkBad < 0) {
2469 next_tick = linkBad & ~TIMER_CB;
2470 } else if (!linkBad) {
2471 lp->local_state--;
2472 lp->media = prev_state;
2473 } else {
2474 lp->media = INIT;
2475 lp->tcount++;
2476 }
2477 }
2478
2479 return next_tick;
2480 }
2481
2482 /*
2483 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2484 ** before BNC, because the BNC port will indicate activity if it's not
2485 ** terminated correctly. The only way to test for that is to place a loopback
2486 ** packet onto the network and watch for errors. Since we're messing with
2487 ** the interrupt mask register, disable the board interrupts and do not allow
2488 ** any more packets to be queued to the hardware. Re-enable everything only
2489 ** when the media is found.
2490 */
2491 static int
2492 dc21041_autoconf(struct device *dev)
2493 {
2494 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2495 u_long iobase = dev->base_addr;
2496 s32 sts, irqs, irq_mask, imr, omr;
2497 int next_tick = DE4X5_AUTOSENSE_MS;
2498
2499 switch (lp->media) {
2500 case INIT:
2501 DISABLE_IRQs;
2502 lp->tx_enable = NO;
2503 lp->timeout = -1;
2504 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2505 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2506 lp->media = TP; /* On chip auto negotiation is broken */
2507 } else if (lp->autosense == TP) {
2508 lp->media = TP;
2509 } else if (lp->autosense == BNC) {
2510 lp->media = BNC;
2511 } else if (lp->autosense == AUI) {
2512 lp->media = AUI;
2513 } else {
2514 lp->media = NC;
2515 }
2516 lp->local_state = 0;
2517 next_tick = dc21041_autoconf(dev);
2518 break;
2519
2520 case TP_NW:
2521 if (lp->timeout < 0) {
2522 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2523 outl(omr | OMR_FDX, DE4X5_OMR);
2524 }
2525 irqs = STS_LNF | STS_LNP;
2526 irq_mask = IMR_LFM | IMR_LPM;
2527 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2528 if (sts < 0) {
2529 next_tick = sts & ~TIMER_CB;
2530 } else {
2531 if (sts & STS_LNP) {
2532 lp->media = ANS;
2533 } else {
2534 lp->media = AUI;
2535 }
2536 next_tick = dc21041_autoconf(dev);
2537 }
2538 break;
2539
2540 case ANS:
2541 if (!lp->tx_enable) {
2542 irqs = STS_LNP;
2543 irq_mask = IMR_LPM;
2544 sts = test_ans(dev, irqs, irq_mask, 3000);
2545 if (sts < 0) {
2546 next_tick = sts & ~TIMER_CB;
2547 } else {
2548 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2549 lp->media = TP;
2550 next_tick = dc21041_autoconf(dev);
2551 } else {
2552 lp->local_state = 1;
2553 de4x5_init_connection(dev);
2554 }
2555 }
2556 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2557 lp->media = ANS_SUSPECT;
2558 next_tick = 3000;
2559 }
2560 break;
2561
2562 case ANS_SUSPECT:
2563 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2564 break;
2565
2566 case TP:
2567 if (!lp->tx_enable) {
2568 if (lp->timeout < 0) {
2569 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2570 outl(omr & ~OMR_FDX, DE4X5_OMR);
2571 }
2572 irqs = STS_LNF | STS_LNP;
2573 irq_mask = IMR_LFM | IMR_LPM;
2574 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2575 if (sts < 0) {
2576 next_tick = sts & ~TIMER_CB;
2577 } else {
2578 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2579 if (inl(DE4X5_SISR) & SISR_NRA) {
2580 lp->media = AUI; /* Non selected port activity */
2581 } else {
2582 lp->media = BNC;
2583 }
2584 next_tick = dc21041_autoconf(dev);
2585 } else {
2586 lp->local_state = 1;
2587 de4x5_init_connection(dev);
2588 }
2589 }
2590 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2591 lp->media = TP_SUSPECT;
2592 next_tick = 3000;
2593 }
2594 break;
2595
2596 case TP_SUSPECT:
2597 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2598 break;
2599
2600 case AUI:
2601 if (!lp->tx_enable) {
2602 if (lp->timeout < 0) {
2603 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2604 outl(omr & ~OMR_FDX, DE4X5_OMR);
2605 }
2606 irqs = 0;
2607 irq_mask = 0;
2608 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2609 if (sts < 0) {
2610 next_tick = sts & ~TIMER_CB;
2611 } else {
2612 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2613 lp->media = BNC;
2614 next_tick = dc21041_autoconf(dev);
2615 } else {
2616 lp->local_state = 1;
2617 de4x5_init_connection(dev);
2618 }
2619 }
2620 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2621 lp->media = AUI_SUSPECT;
2622 next_tick = 3000;
2623 }
2624 break;
2625
2626 case AUI_SUSPECT:
2627 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2628 break;
2629
2630 case BNC:
2631 switch (lp->local_state) {
2632 case 0:
2633 if (lp->timeout < 0) {
2634 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2635 outl(omr & ~OMR_FDX, DE4X5_OMR);
2636 }
2637 irqs = 0;
2638 irq_mask = 0;
2639 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2640 if (sts < 0) {
2641 next_tick = sts & ~TIMER_CB;
2642 } else {
2643 lp->local_state++; /* Ensure media connected */
2644 next_tick = dc21041_autoconf(dev);
2645 }
2646 break;
2647
2648 case 1:
2649 if (!lp->tx_enable) {
2650 if ((sts = ping_media(dev, 3000)) < 0) {
2651 next_tick = sts & ~TIMER_CB;
2652 } else {
2653 if (sts) {
2654 lp->local_state = 0;
2655 lp->media = NC;
2656 } else {
2657 de4x5_init_connection(dev);
2658 }
2659 }
2660 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2661 lp->media = BNC_SUSPECT;
2662 next_tick = 3000;
2663 }
2664 break;
2665 }
2666 break;
2667
2668 case BNC_SUSPECT:
2669 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2670 break;
2671
2672 case NC:
2673 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2674 outl(omr | OMR_FDX, DE4X5_OMR);
2675 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2676 if (lp->media != lp->c_media) {
2677 de4x5_dbg_media(dev);
2678 lp->c_media = lp->media;
2679 }
2680 lp->media = INIT;
2681 lp->tx_enable = NO;
2682 break;
2683 }
2684
2685 return next_tick;
2686 }
2687
2688 /*
2689 ** Some autonegotiation chips are broken in that they do not return the
2690 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2691 ** register, except at the first power up negotiation.
2692 */
2693 static int
2694 dc21140m_autoconf(struct device *dev)
2695 {
2696 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2697 int ana, anlpa, cap, cr, slnk, sr;
2698 int next_tick = DE4X5_AUTOSENSE_MS;
2699 u_long imr, omr, iobase = dev->base_addr;
2700
2701 switch(lp->media) {
2702 case INIT:
2703 if (lp->timeout < 0) {
2704 DISABLE_IRQs;
2705 lp->tx_enable = FALSE;
2706 lp->linkOK = 0;
2707 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2708 }
2709 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2710 next_tick &= ~TIMER_CB;
2711 } else {
2712 if (lp->useSROM) {
2713 if (srom_map_media(dev) < 0) {
2714 lp->tcount++;
2715 return next_tick;
2716 }
2717 srom_exec(dev, lp->phy[lp->active].gep);
2718 if (lp->infoblock_media == ANS) {
2719 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2720 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2721 }
2722 } else {
2723 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2724 SET_10Mb;
2725 if (lp->autosense == _100Mb) {
2726 lp->media = _100Mb;
2727 } else if (lp->autosense == _10Mb) {
2728 lp->media = _10Mb;
2729 } else if ((lp->autosense == AUTO) &&
2730 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2731 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2732 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2733 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2734 lp->media = ANS;
2735 } else if (lp->autosense == AUTO) {
2736 lp->media = SPD_DET;
2737 } else if (is_spd_100(dev) && is_100_up(dev)) {
2738 lp->media = _100Mb;
2739 } else {
2740 lp->media = NC;
2741 }
2742 }
2743 lp->local_state = 0;
2744 next_tick = dc21140m_autoconf(dev);
2745 }
2746 break;
2747
2748 case ANS:
2749 switch (lp->local_state) {
2750 case 0:
2751 if (lp->timeout < 0) {
2752 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2753 }
2754 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2755 if (cr < 0) {
2756 next_tick = cr & ~TIMER_CB;
2757 } else {
2758 if (cr) {
2759 lp->local_state = 0;
2760 lp->media = SPD_DET;
2761 } else {
2762 lp->local_state++;
2763 }
2764 next_tick = dc21140m_autoconf(dev);
2765 }
2766 break;
2767
2768 case 1:
2769 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2770 next_tick = sr & ~TIMER_CB;
2771 } else {
2772 lp->media = SPD_DET;
2773 lp->local_state = 0;
2774 if (sr) { /* Success! */
2775 lp->tmp = MII_SR_ASSC;
2776 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2777 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2778 if (!(anlpa & MII_ANLPA_RF) &&
2779 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2780 if (cap & MII_ANA_100M) {
2781 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2782 lp->media = _100Mb;
2783 } else if (cap & MII_ANA_10M) {
2784 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2785
2786 lp->media = _10Mb;
2787 }
2788 }
2789 } /* Auto Negotiation failed to finish */
2790 next_tick = dc21140m_autoconf(dev);
2791 } /* Auto Negotiation failed to start */
2792 break;
2793 }
2794 break;
2795
2796 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2797 if (lp->timeout < 0) {
2798 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2799 (~gep_rd(dev) & GEP_LNP));
2800 SET_100Mb_PDET;
2801 }
2802 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2803 next_tick = slnk & ~TIMER_CB;
2804 } else {
2805 if (is_spd_100(dev) && is_100_up(dev)) {
2806 lp->media = _100Mb;
2807 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2808 lp->media = _10Mb;
2809 } else {
2810 lp->media = NC;
2811 }
2812 next_tick = dc21140m_autoconf(dev);
2813 }
2814 break;
2815
2816 case _100Mb: /* Set 100Mb/s */
2817 next_tick = 3000;
2818 if (!lp->tx_enable) {
2819 SET_100Mb;
2820 de4x5_init_connection(dev);
2821 } else {
2822 if (!lp->linkOK && (lp->autosense == AUTO)) {
2823 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2824 lp->media = INIT;
2825 lp->tcount++;
2826 next_tick = DE4X5_AUTOSENSE_MS;
2827 }
2828 }
2829 }
2830 break;
2831
2832 case BNC:
2833 case AUI:
2834 case _10Mb: /* Set 10Mb/s */
2835 next_tick = 3000;
2836 if (!lp->tx_enable) {
2837 SET_10Mb;
2838 de4x5_init_connection(dev);
2839 } else {
2840 if (!lp->linkOK && (lp->autosense == AUTO)) {
2841 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2842 lp->media = INIT;
2843 lp->tcount++;
2844 next_tick = DE4X5_AUTOSENSE_MS;
2845 }
2846 }
2847 }
2848 break;
2849
2850 case NC:
2851 if (lp->media != lp->c_media) {
2852 de4x5_dbg_media(dev);
2853 lp->c_media = lp->media;
2854 }
2855 lp->media = INIT;
2856 lp->tx_enable = FALSE;
2857 break;
2858 }
2859
2860 return next_tick;
2861 }
2862
2863 /*
2864 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2865 ** changing how I figure out the media - but trying to keep it backwards
2866 ** compatible with the de500-xa and de500-aa.
2867 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2868 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2869 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2870 ** active.
2871 ** When autonegotiation is working, the ANS part searches the SROM for
2872 ** the highest common speed (TP) link that both can run and if that can
2873 ** be full duplex. That infoblock is executed and then the link speed set.
2874 **
2875 ** Only _10Mb and _100Mb are tested here.
2876 */
2877 static int
2878 dc2114x_autoconf(struct device *dev)
2879 {
2880 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2881 u_long iobase = dev->base_addr;
2882 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2883 int next_tick = DE4X5_AUTOSENSE_MS;
2884
2885 switch (lp->media) {
2886 case INIT:
2887 if (lp->timeout < 0) {
2888 DISABLE_IRQs;
2889 lp->tx_enable = FALSE;
2890 lp->linkOK = 0;
2891 lp->timeout = -1;
2892 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2893 if (lp->params.autosense & ~AUTO) {
2894 srom_map_media(dev); /* Fixed media requested */
2895 if (lp->media != lp->params.autosense) {
2896 lp->tcount++;
2897 lp->media = INIT;
2898 return next_tick;
2899 }
2900 lp->media = INIT;
2901 }
2902 }
2903 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2904 next_tick &= ~TIMER_CB;
2905 } else {
2906 if (lp->autosense == _100Mb) {
2907 lp->media = _100Mb;
2908 } else if (lp->autosense == _10Mb) {
2909 lp->media = _10Mb;
2910 } else if (lp->autosense == TP) {
2911 lp->media = TP;
2912 } else if (lp->autosense == BNC) {
2913 lp->media = BNC;
2914 } else if (lp->autosense == AUI) {
2915 lp->media = AUI;
2916 } else {
2917 lp->media = SPD_DET;
2918 if ((lp->infoblock_media == ANS) &&
2919 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2920 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2921 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2922 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2923 lp->media = ANS;
2924 }
2925 }
2926 lp->local_state = 0;
2927 next_tick = dc2114x_autoconf(dev);
2928 }
2929 break;
2930
2931 case ANS:
2932 switch (lp->local_state) {
2933 case 0:
2934 if (lp->timeout < 0) {
2935 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2936 }
2937 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2938 if (cr < 0) {
2939 next_tick = cr & ~TIMER_CB;
2940 } else {
2941 if (cr) {
2942 lp->local_state = 0;
2943 lp->media = SPD_DET;
2944 } else {
2945 lp->local_state++;
2946 }
2947 next_tick = dc2114x_autoconf(dev);
2948 }
2949 break;
2950
2951 case 1:
2952 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2953 next_tick = sr & ~TIMER_CB;
2954 } else {
2955 lp->media = SPD_DET;
2956 lp->local_state = 0;
2957 if (sr) { /* Success! */
2958 lp->tmp = MII_SR_ASSC;
2959 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2960 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2961 if (!(anlpa & MII_ANLPA_RF) &&
2962 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2963 if (cap & MII_ANA_100M) {
2964 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2965 lp->media = _100Mb;
2966 } else if (cap & MII_ANA_10M) {
2967 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2968 lp->media = _10Mb;
2969 }
2970 }
2971 } /* Auto Negotiation failed to finish */
2972 next_tick = dc2114x_autoconf(dev);
2973 } /* Auto Negotiation failed to start */
2974 break;
2975 }
2976 break;
2977
2978 case AUI:
2979 if (!lp->tx_enable) {
2980 if (lp->timeout < 0) {
2981 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2982 outl(omr & ~OMR_FDX, DE4X5_OMR);
2983 }
2984 irqs = 0;
2985 irq_mask = 0;
2986 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
2987 if (sts < 0) {
2988 next_tick = sts & ~TIMER_CB;
2989 } else {
2990 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2991 lp->media = BNC;
2992 next_tick = dc2114x_autoconf(dev);
2993 } else {
2994 lp->local_state = 1;
2995 de4x5_init_connection(dev);
2996 }
2997 }
2998 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2999 lp->media = AUI_SUSPECT;
3000 next_tick = 3000;
3001 }
3002 break;
3003
3004 case AUI_SUSPECT:
3005 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3006 break;
3007
3008 case BNC:
3009 switch (lp->local_state) {
3010 case 0:
3011 if (lp->timeout < 0) {
3012 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3013 outl(omr & ~OMR_FDX, DE4X5_OMR);
3014 }
3015 irqs = 0;
3016 irq_mask = 0;
3017 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3018 if (sts < 0) {
3019 next_tick = sts & ~TIMER_CB;
3020 } else {
3021 lp->local_state++; /* Ensure media connected */
3022 next_tick = dc2114x_autoconf(dev);
3023 }
3024 break;
3025
3026 case 1:
3027 if (!lp->tx_enable) {
3028 if ((sts = ping_media(dev, 3000)) < 0) {
3029 next_tick = sts & ~TIMER_CB;
3030 } else {
3031 if (sts) {
3032 lp->local_state = 0;
3033 lp->tcount++;
3034 lp->media = INIT;
3035 } else {
3036 de4x5_init_connection(dev);
3037 }
3038 }
3039 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3040 lp->media = BNC_SUSPECT;
3041 next_tick = 3000;
3042 }
3043 break;
3044 }
3045 break;
3046
3047 case BNC_SUSPECT:
3048 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3049 break;
3050
3051 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3052 if (srom_map_media(dev) < 0) {
3053 lp->tcount++;
3054 lp->media = INIT;
3055 return next_tick;
3056 }
3057 if (lp->media == _100Mb) {
3058 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3059 lp->media = SPD_DET;
3060 return (slnk & ~TIMER_CB);
3061 }
3062 } else {
3063 if (wait_for_link(dev) < 0) {
3064 lp->media = SPD_DET;
3065 return PDET_LINK_WAIT;
3066 }
3067 }
3068 if (lp->media == ANS) { /* Do MII parallel detection */
3069 if (is_spd_100(dev)) {
3070 lp->media = _100Mb;
3071 } else {
3072 lp->media = _10Mb;
3073 }
3074 next_tick = dc2114x_autoconf(dev);
3075 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3076 ((lp->media == _10Mb) && is_10_up(dev)) ||
3077 (lp->media == TP) ||
3078 (lp->media == BNC) || (lp->media == AUI)) {
3079 next_tick = dc2114x_autoconf(dev);
3080 } else {
3081 lp->tcount++;
3082 lp->media = INIT;
3083 }
3084 break;
3085
3086 case _10Mb:
3087 next_tick = 3000;
3088 if (!lp->tx_enable) {
3089 SET_10Mb;
3090 de4x5_init_connection(dev);
3091 } else {
3092 if (!lp->linkOK && (lp->autosense == AUTO)) {
3093 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3094 lp->media = INIT;
3095 lp->tcount++;
3096 next_tick = DE4X5_AUTOSENSE_MS;
3097 }
3098 }
3099 }
3100 break;
3101
3102 case _100Mb:
3103 next_tick = 3000;
3104 if (!lp->tx_enable) {
3105 SET_100Mb;
3106 de4x5_init_connection(dev);
3107 } else {
3108 if (!lp->linkOK && (lp->autosense == AUTO)) {
3109 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3110 lp->media = INIT;
3111 lp->tcount++;
3112 next_tick = DE4X5_AUTOSENSE_MS;
3113 }
3114 }
3115 }
3116 break;
3117
3118 default:
3119 lp->tcount++;
3120 printk("Huh?: media:%02x\n", lp->media);
3121 lp->media = INIT;
3122 break;
3123 }
3124
3125 return next_tick;
3126 }
3127
3128 static int
3129 srom_autoconf(struct device *dev)
3130 {
3131 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3132
3133 return lp->infoleaf_fn(dev);
3134 }
3135
3136 /*
3137 ** This mapping keeps the original media codes and FDX flag unchanged.
3138 ** While it isn't strictly necessary, it helps me for the moment...
3139 ** The early return avoids a media state / SROM media space clash.
3140 */
3141 static int
3142 srom_map_media(struct device *dev)
3143 {
3144 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3145
3146 lp->fdx = 0;
3147 if (lp->infoblock_media == lp->media)
3148 return 0;
3149
3150 switch(lp->infoblock_media) {
3151 case SROM_10BASETF:
3152 if (!lp->params.fdx) return -1;
3153 lp->fdx = TRUE;
3154 case SROM_10BASET:
3155 if (lp->params.fdx && !lp->fdx) return -1;
3156 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3157 lp->media = _10Mb;
3158 } else {
3159 lp->media = TP;
3160 }
3161 break;
3162
3163 case SROM_10BASE2:
3164 lp->media = BNC;
3165 break;
3166
3167 case SROM_10BASE5:
3168 lp->media = AUI;
3169 break;
3170
3171 case SROM_100BASETF:
3172 if (!lp->params.fdx) return -1;
3173 lp->fdx = TRUE;
3174 case SROM_100BASET:
3175 if (lp->params.fdx && !lp->fdx) return -1;
3176 lp->media = _100Mb;
3177 break;
3178
3179 case SROM_100BASET4:
3180 lp->media = _100Mb;
3181 break;
3182
3183 case SROM_100BASEFF:
3184 if (!lp->params.fdx) return -1;
3185 lp->fdx = TRUE;
3186 case SROM_100BASEF:
3187 if (lp->params.fdx && !lp->fdx) return -1;
3188 lp->media = _100Mb;
3189 break;
3190
3191 case ANS:
3192 lp->media = ANS;
3193 break;
3194
3195 default:
3196 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3197 lp->infoblock_media);
3198 return -1;
3199 break;
3200 }
3201
3202 return 0;
3203 }
3204
3205 static void
3206 de4x5_init_connection(struct device *dev)
3207 {
3208 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3209 u_long iobase = dev->base_addr;
3210
3211 if (lp->media != lp->c_media) {
3212 de4x5_dbg_media(dev);
3213 lp->c_media = lp->media; /* Stop scrolling media messages */
3214 }
3215
3216 cli();
3217 de4x5_rst_desc_ring(dev);
3218 de4x5_setup_intr(dev);
3219 lp->tx_enable = YES;
3220 dev->tbusy = 0;
3221 sti();
3222 outl(POLL_DEMAND, DE4X5_TPD);
3223 mark_bh(NET_BH);
3224
3225 return;
3226 }
3227
3228 /*
3229 ** General PHY reset function. Some MII devices don't reset correctly
3230 ** since their MII address pins can float at voltages that are dependent
3231 ** on the signal pin use. Do a double reset to ensure a reset.
3232 */
3233 static int
3234 de4x5_reset_phy(struct device *dev)
3235 {
3236 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3237 u_long iobase = dev->base_addr;
3238 int next_tick = 0;
3239
3240 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3241 if (lp->timeout < 0) {
3242 if (lp->useSROM) {
3243 if (lp->phy[lp->active].rst) {
3244 srom_exec(dev, lp->phy[lp->active].rst);
3245 srom_exec(dev, lp->phy[lp->active].rst);
3246 } else if (lp->rst) { /* Type 5 infoblock reset */
3247 srom_exec(dev, lp->rst);
3248 srom_exec(dev, lp->rst);
3249 }
3250 } else {
3251 PHY_HARD_RESET;
3252 }
3253 if (lp->useMII) {
3254 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3255 }
3256 }
3257 if (lp->useMII) {
3258 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3259 }
3260 } else if (lp->chipset == DC21140) {
3261 PHY_HARD_RESET;
3262 }
3263
3264 return next_tick;
3265 }
3266
3267 static int
3268 test_media(struct device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3269 {
3270 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3271 u_long iobase = dev->base_addr;
3272 s32 sts, csr12;
3273
3274 if (lp->timeout < 0) {
3275 lp->timeout = msec/100;
3276 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3277 reset_init_sia(dev, csr13, csr14, csr15);
3278 }
3279
3280 /* set up the interrupt mask */
3281 outl(irq_mask, DE4X5_IMR);
3282
3283 /* clear all pending interrupts */
3284 sts = inl(DE4X5_STS);
3285 outl(sts, DE4X5_STS);
3286
3287 /* clear csr12 NRA and SRA bits */
3288 if ((lp->chipset == DC21041) || lp->useSROM) {
3289 csr12 = inl(DE4X5_SISR);
3290 outl(csr12, DE4X5_SISR);
3291 }
3292 }
3293
3294 sts = inl(DE4X5_STS) & ~TIMER_CB;
3295
3296 if (!(sts & irqs) && --lp->timeout) {
3297 sts = 100 | TIMER_CB;
3298 } else {
3299 lp->timeout = -1;
3300 }
3301
3302 return sts;
3303 }
3304
3305 static int
3306 test_tp(struct device *dev, s32 msec)
3307 {
3308 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3309 u_long iobase = dev->base_addr;
3310 int sisr;
3311
3312 if (lp->timeout < 0) {
3313 lp->timeout = msec/100;
3314 }
3315
3316 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3317
3318 if (sisr && --lp->timeout) {
3319 sisr = 100 | TIMER_CB;
3320 } else {
3321 lp->timeout = -1;
3322 }
3323
3324 return sisr;
3325 }
3326
3327 /*
3328 ** Samples the 100Mb Link State Signal. The sample interval is important
3329 ** because too fast a rate can give erroneous results and confuse the
3330 ** speed sense algorithm.
3331 */
3332 #define SAMPLE_INTERVAL 500 /* ms */
3333 #define SAMPLE_DELAY 2000 /* ms */
3334 static int
3335 test_for_100Mb(struct device *dev, int msec)
3336 {
3337 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3338 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3339
3340 if (lp->timeout < 0) {
3341 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3342 if (msec > SAMPLE_DELAY) {
3343 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3344 gep = SAMPLE_DELAY | TIMER_CB;
3345 return gep;
3346 } else {
3347 lp->timeout = msec/SAMPLE_INTERVAL;
3348 }
3349 }
3350
3351 if (lp->phy[lp->active].id || lp->useSROM) {
3352 gep = is_100_up(dev) | is_spd_100(dev);
3353 } else {
3354 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3355 }
3356 if (!(gep & ret) && --lp->timeout) {
3357 gep = SAMPLE_INTERVAL | TIMER_CB;
3358 } else {
3359 lp->timeout = -1;
3360 }
3361
3362 return gep;
3363 }
3364
3365 static int
3366 wait_for_link(struct device *dev)
3367 {
3368 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3369
3370 if (lp->timeout < 0) {
3371 lp->timeout = 1;
3372 }
3373
3374 if (lp->timeout--) {
3375 return TIMER_CB;
3376 } else {
3377 lp->timeout = -1;
3378 }
3379
3380 return 0;
3381 }
3382
3383 /*
3384 **
3385 **
3386 */
3387 static int
3388 test_mii_reg(struct device *dev, int reg, int mask, int pol, long msec)
3389 {
3390 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3391 int test;
3392 u_long iobase = dev->base_addr;
3393
3394 if (lp->timeout < 0) {
3395 lp->timeout = msec/100;
3396 }
3397
3398 if (pol) pol = ~0;
3399 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3400 test = (reg ^ pol) & mask;
3401
3402 if (test && --lp->timeout) {
3403 reg = 100 | TIMER_CB;
3404 } else {
3405 lp->timeout = -1;
3406 }
3407
3408 return reg;
3409 }
3410
3411 static int
3412 is_spd_100(struct device *dev)
3413 {
3414 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3415 u_long iobase = dev->base_addr;
3416 int spd;
3417
3418 if (lp->useMII) {
3419 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3420 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3421 spd &= lp->phy[lp->active].spd.mask;
3422 } else if (!lp->useSROM) { /* de500-xa */
3423 spd = ((~gep_rd(dev)) & GEP_SLNK);
3424 } else {
3425 if ((lp->ibn == 2) || !lp->asBitValid)
3426 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3427
3428 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3429 (lp->linkOK & ~lp->asBitValid);
3430 }
3431
3432 return spd;
3433 }
3434
3435 static int
3436 is_100_up(struct device *dev)
3437 {
3438 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3439 u_long iobase = dev->base_addr;
3440
3441 if (lp->useMII) {
3442 /* Double read for sticky bits & temporary drops */
3443 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3444 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3445 } else if (!lp->useSROM) { /* de500-xa */
3446 return ((~gep_rd(dev)) & GEP_SLNK);
3447 } else {
3448 if ((lp->ibn == 2) || !lp->asBitValid)
3449 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3450
3451 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3452 (lp->linkOK & ~lp->asBitValid));
3453 }
3454 }
3455
3456 static int
3457 is_10_up(struct device *dev)
3458 {
3459 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3460 u_long iobase = dev->base_addr;
3461
3462 if (lp->useMII) {
3463 /* Double read for sticky bits & temporary drops */
3464 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3465 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3466 } else if (!lp->useSROM) { /* de500-xa */
3467 return ((~gep_rd(dev)) & GEP_LNP);
3468 } else {
3469 if ((lp->ibn == 2) || !lp->asBitValid)
3470 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3471 (~inl(DE4X5_SISR)&SISR_LS10):
3472 0);
3473
3474 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3475 (lp->linkOK & ~lp->asBitValid));
3476 }
3477 }
3478
3479 static int
3480 is_anc_capable(struct device *dev)
3481 {
3482 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3483 u_long iobase = dev->base_addr;
3484
3485 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3486 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3487 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3488 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3489 } else {
3490 return 0;
3491 }
3492 }
3493
3494 /*
3495 ** Send a packet onto the media and watch for send errors that indicate the
3496 ** media is bad or unconnected.
3497 */
3498 static int
3499 ping_media(struct device *dev, int msec)
3500 {
3501 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3502 u_long iobase = dev->base_addr;
3503 int sisr;
3504
3505 if (lp->timeout < 0) {
3506 lp->timeout = msec/100;
3507
3508 lp->tmp = lp->tx_new; /* Remember the ring position */
3509 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), NULL);
3510 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3511 outl(POLL_DEMAND, DE4X5_TPD);
3512 }
3513
3514 sisr = inl(DE4X5_SISR);
3515
3516 if ((!(sisr & SISR_NCR)) &&
3517 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3518 (--lp->timeout)) {
3519 sisr = 100 | TIMER_CB;
3520 } else {
3521 if ((!(sisr & SISR_NCR)) &&
3522 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3523 lp->timeout) {
3524 sisr = 0;
3525 } else {
3526 sisr = 1;
3527 }
3528 lp->timeout = -1;
3529 }
3530
3531 return sisr;
3532 }
3533
3534 /*
3535 ** This function does 2 things: on Intels it kmalloc's another buffer to
3536 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3537 ** into which the packet is copied.
3538 */
3539 static struct sk_buff *
3540 de4x5_alloc_rx_buff(struct device *dev, int index, int len)
3541 {
3542 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3543 struct sk_buff *p;
3544
3545 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3546 struct sk_buff *ret;
3547 u_long i=0, tmp;
3548
3549 p = dev_alloc_skb(IEEE802_3_SZ + ALIGN + 2);
3550 if (!p) return NULL;
3551
3552 p->dev = dev;
3553 tmp = virt_to_bus(p->data);
3554 i = ((tmp + ALIGN) & ~ALIGN) - tmp;
3555 skb_reserve(p, i);
3556 lp->rx_ring[index].buf = tmp + i;
3557
3558 ret = lp->rx_skb[index];
3559 lp->rx_skb[index] = p;
3560
3561 if ((u_long) ret > 1) {
3562 skb_put(ret, len);
3563 }
3564
3565 return ret;
3566
3567 #else
3568 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3569
3570 p = dev_alloc_skb(len + 2);
3571 if (!p) return NULL;
3572
3573 p->dev = dev;
3574 skb_reserve(p, 2); /* Align */
3575 if (index < lp->rx_old) { /* Wrapped buffer */
3576 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3577 memcpy(skb_put(p,tlen),
3578 bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),tlen);
3579 memcpy(skb_put(p,len-tlen),
3580 bus_to_virt(le32_to_cpu(lp->rx_ring[0].buf)), len-tlen);
3581 } else { /* Linear buffer */
3582 memcpy(skb_put(p,len),
3583 bus_to_virt(le32_to_cpu(lp->rx_ring[lp->rx_old].buf)),len);
3584 }
3585
3586 return p;
3587 #endif
3588 }
3589
3590 static void
3591 de4x5_free_rx_buffs(struct device *dev)
3592 {
3593 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3594 int i;
3595
3596 for (i=0; i<lp->rxRingSize; i++) {
3597 if ((u_long) lp->rx_skb[i] > 1) {
3598 dev_kfree_skb(lp->rx_skb[i]);
3599 }
3600 lp->rx_ring[i].status = 0;
3601 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3602 }
3603
3604 return;
3605 }
3606
3607 static void
3608 de4x5_free_tx_buffs(struct device *dev)
3609 {
3610 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3611 int i;
3612
3613 for (i=0; i<lp->txRingSize; i++) {
3614 if (lp->tx_skb[i]) {
3615 dev_kfree_skb(lp->tx_skb[i]);
3616 lp->tx_skb[i] = NULL;
3617 }
3618 lp->tx_ring[i].status = 0;
3619 }
3620
3621 /* Unload the locally queued packets */
3622 while (lp->cache.skb) {
3623 dev_kfree_skb(de4x5_get_cache(dev));
3624 }
3625
3626 return;
3627 }
3628
3629 /*
3630 ** When a user pulls a connection, the DECchip can end up in a
3631 ** 'running - waiting for end of transmission' state. This means that we
3632 ** have to perform a chip soft reset to ensure that we can synchronize
3633 ** the hardware and software and make any media probes using a loopback
3634 ** packet meaningful.
3635 */
3636 static void
3637 de4x5_save_skbs(struct device *dev)
3638 {
3639 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3640 u_long iobase = dev->base_addr;
3641 s32 omr;
3642
3643 if (!lp->cache.save_cnt) {
3644 STOP_DE4X5;
3645 de4x5_tx(dev); /* Flush any sent skb's */
3646 de4x5_free_tx_buffs(dev);
3647 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3648 de4x5_sw_reset(dev);
3649 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3650 lp->cache.save_cnt++;
3651 START_DE4X5;
3652 }
3653
3654 return;
3655 }
3656
3657 static void
3658 de4x5_rst_desc_ring(struct device *dev)
3659 {
3660 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3661 u_long iobase = dev->base_addr;
3662 int i;
3663 s32 omr;
3664
3665 if (lp->cache.save_cnt) {
3666 STOP_DE4X5;
3667 outl(virt_to_bus(lp->rx_ring), DE4X5_RRBA);
3668 outl(virt_to_bus(lp->tx_ring), DE4X5_TRBA);
3669
3670 lp->rx_new = lp->rx_old = 0;
3671 lp->tx_new = lp->tx_old = 0;
3672
3673 for (i = 0; i < lp->rxRingSize; i++) {
3674 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3675 }
3676
3677 for (i = 0; i < lp->txRingSize; i++) {
3678 lp->tx_ring[i].status = cpu_to_le32(0);
3679 }
3680
3681 barrier();
3682 lp->cache.save_cnt--;
3683 START_DE4X5;
3684 }
3685
3686 return;
3687 }
3688
3689 static void
3690 de4x5_cache_state(struct device *dev, int flag)
3691 {
3692 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3693 u_long iobase = dev->base_addr;
3694
3695 switch(flag) {
3696 case DE4X5_SAVE_STATE:
3697 lp->cache.csr0 = inl(DE4X5_BMR);
3698 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3699 lp->cache.csr7 = inl(DE4X5_IMR);
3700 break;
3701
3702 case DE4X5_RESTORE_STATE:
3703 outl(lp->cache.csr0, DE4X5_BMR);
3704 outl(lp->cache.csr6, DE4X5_OMR);
3705 outl(lp->cache.csr7, DE4X5_IMR);
3706 if (lp->chipset == DC21140) {
3707 gep_wr(lp->cache.gepc, dev);
3708 gep_wr(lp->cache.gep, dev);
3709 } else {
3710 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3711 lp->cache.csr15);
3712 }
3713 break;
3714 }
3715
3716 return;
3717 }
3718
3719 static void
3720 de4x5_put_cache(struct device *dev, struct sk_buff *skb)
3721 {
3722 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3723 struct sk_buff *p;
3724
3725 if (lp->cache.skb) {
3726 for (p=lp->cache.skb; p->next; p=p->next);
3727 p->next = skb;
3728 } else {
3729 lp->cache.skb = skb;
3730 }
3731 skb->next = NULL;
3732
3733 return;
3734 }
3735
3736 static void
3737 de4x5_putb_cache(struct device *dev, struct sk_buff *skb)
3738 {
3739 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3740 struct sk_buff *p = lp->cache.skb;
3741
3742 lp->cache.skb = skb;
3743 skb->next = p;
3744
3745 return;
3746 }
3747
3748 static struct sk_buff *
3749 de4x5_get_cache(struct device *dev)
3750 {
3751 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3752 struct sk_buff *p = lp->cache.skb;
3753
3754 if (p) {
3755 lp->cache.skb = p->next;
3756 p->next = NULL;
3757 }
3758
3759 return p;
3760 }
3761
3762 /*
3763 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3764 ** is received and the auto-negotiation status is NWAY OK.
3765 */
3766 static int
3767 test_ans(struct device *dev, s32 irqs, s32 irq_mask, s32 msec)
3768 {
3769 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3770 u_long iobase = dev->base_addr;
3771 s32 sts, ans;
3772
3773 if (lp->timeout < 0) {
3774 lp->timeout = msec/100;
3775 outl(irq_mask, DE4X5_IMR);
3776
3777 /* clear all pending interrupts */
3778 sts = inl(DE4X5_STS);
3779 outl(sts, DE4X5_STS);
3780 }
3781
3782 ans = inl(DE4X5_SISR) & SISR_ANS;
3783 sts = inl(DE4X5_STS) & ~TIMER_CB;
3784
3785 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3786 sts = 100 | TIMER_CB;
3787 } else {
3788 lp->timeout = -1;
3789 }
3790
3791 return sts;
3792 }
3793
3794 static void
3795 de4x5_setup_intr(struct device *dev)
3796 {
3797 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3798 u_long iobase = dev->base_addr;
3799 s32 imr, sts;
3800
3801 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3802 imr = 0;
3803 UNMASK_IRQs;
3804 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3805 outl(sts, DE4X5_STS);
3806 ENABLE_IRQs;
3807 }
3808
3809 return;
3810 }
3811
3812 /*
3813 **
3814 */
3815 static void
3816 reset_init_sia(struct device *dev, s32 csr13, s32 csr14, s32 csr15)
3817 {
3818 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
3819 u_long iobase = dev->base_addr;
3820
3821 RESET_SIA;
3822 if (lp->useSROM) {
3823 if (lp->ibn == 3) {
3824 srom_exec(dev, lp->phy[lp->active].rst);
3825 srom_exec(dev, lp->phy[lp->active].gep);
3826 outl(1, DE4X5_SICR);
3827 return;
3828 } else {
3829 csr15 = lp->cache.csr15;
3830 csr14 = lp->cache.csr14;
3831 csr13 = lp->cache.csr13;
3832 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3833 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3834 }
3835 } else {
3836 outl(csr15, DE4X5_SIGR);
3837 }
3838 outl(csr14, DE4X5_STRR);
3839 outl(csr13, DE4X5_SICR);
3840
3841 de4x5_ms_delay(10);
3842
3843 return;
3844 }
3845
3846 /*
3847 ** Create a loopback ethernet packet
3848 */
3849 static void
3850 create_packet(struct device *dev, char *frame, int len)
3851 {
3852 int i;
3853 char *buf = frame;
3854
3855 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3856 *buf++ = dev->dev_addr[i];
3857 }
3858 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3859 *buf++ = dev->dev_addr[i];
3860 }
3861
3862 *buf++ = 0; /* Packet length (2 bytes) */
3863 *buf++ = 1;
3864
3865 return;
3866 }
3867
3868 /*
3869 ** Known delay in microseconds
3870 */
3871 static void
3872 de4x5_us_delay(u32 usec)
3873 {
3874 udelay(usec);
3875
3876 return;
3877 }
3878
3879 /*
3880 ** Known delay in milliseconds, in millisecond steps.
3881 */
3882 static void
3883 de4x5_ms_delay(u32 msec)
3884 {
3885 u_int i;
3886
3887 for (i=0; i<msec; i++) {
3888 de4x5_us_delay(1000);
3889 }
3890
3891 return;
3892 }
3893
3894
3895 /*
3896 ** Look for a particular board name in the EISA configuration space
3897 */
3898 static int
3899 EISA_signature(char *name, s32 eisa_id)
3900 {
3901 static c_char *signatures[] = DE4X5_SIGNATURE;
3902 char ManCode[DE4X5_STRLEN];
3903 union {
3904 s32 ID;
3905 char Id[4];
3906 } Eisa;
3907 int i, status = 0, siglen = sizeof(signatures)/sizeof(c_char *);
3908
3909 *name = '\0';
3910 Eisa.ID = inl(eisa_id);
3911
3912 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
3913 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
3914 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
3915 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
3916 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
3917 ManCode[5]='\0';
3918
3919 for (i=0;i<siglen;i++) {
3920 if (strstr(ManCode, signatures[i]) != NULL) {
3921 strcpy(name,ManCode);
3922 status = 1;
3923 break;
3924 }
3925 }
3926
3927 return status; /* return the device name string */
3928 }
3929
3930 /*
3931 ** Look for a particular board name in the PCI configuration space
3932 */
3933 static int
3934 PCI_signature(char *name, struct bus_type *lp)
3935 {
3936 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
3937 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3938
3939 if (lp->chipset == DC21040) {
3940 strcpy(name, "DE434/5");
3941 return status;
3942 } else { /* Search for a DEC name in the SROM */
3943 int i = *((char *)&lp->srom + 19) * 3;
3944 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3945 }
3946 name[8] = '\0';
3947 for (i=0; i<siglen; i++) {
3948 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3949 }
3950 if (i == siglen) {
3951 if (dec_only) {
3952 *name = '\0';
3953 } else { /* Use chip name to avoid confusion */
3954 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3955 ((lp->chipset == DC21041) ? "DC21041" :
3956 ((lp->chipset == DC21140) ? "DC21140" :
3957 ((lp->chipset == DC21142) ? "DC21142" :
3958 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3959 )))))));
3960 }
3961 if (lp->chipset != DC21041) {
3962 useSROM = TRUE; /* card is not recognisably DEC */
3963 }
3964 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3965 useSROM = TRUE;
3966 }
3967
3968 return status;
3969 }
3970
3971 /*
3972 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3973 ** the DC21040, else read the SROM for the other chips.
3974 ** The SROM may not be present in a multi-MAC card, so first read the
3975 ** MAC address and check for a bad address. If there is a bad one then exit
3976 ** immediately with the prior srom contents intact (the h/w address will
3977 ** be fixed up later).
3978 */
3979 static void
3980 DevicePresent(u_long aprom_addr)
3981 {
3982 int i, j=0;
3983 struct bus_type *lp = &bus;
3984
3985 if (lp->chipset == DC21040) {
3986 if (lp->bus == EISA) {
3987 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3988 } else {
3989 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3990 }
3991 } else { /* Read new srom */
3992 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
3993 for (i=0; i<(ETH_ALEN>>1); i++) {
3994 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3995 *p = le16_to_cpu(tmp);
3996 j += *p++;
3997 }
3998 if ((j == 0) || (j == 0x2fffd)) {
3999 return;
4000 }
4001
4002 p=(short *)&lp->srom;
4003 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4004 tmp = srom_rd(aprom_addr, i);
4005 *p++ = le16_to_cpu(tmp);
4006 }
4007 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4008 }
4009
4010 return;
4011 }
4012
4013 /*
4014 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4015 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4016 ** it...from depca.c.
4017 */
4018 static void
4019 enet_addr_rst(u_long aprom_addr)
4020 {
4021 union {
4022 struct {
4023 u32 a;
4024 u32 b;
4025 } llsig;
4026 char Sig[sizeof(u32) << 1];
4027 } dev;
4028 short sigLength=0;
4029 s8 data;
4030 int i, j;
4031
4032 dev.llsig.a = ETH_PROM_SIG;
4033 dev.llsig.b = ETH_PROM_SIG;
4034 sigLength = sizeof(u32) << 1;
4035
4036 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4037 data = inb(aprom_addr);
4038 if (dev.Sig[j] == data) { /* track signature */
4039 j++;
4040 } else { /* lost signature; begin search again */
4041 if (data == dev.Sig[0]) { /* rare case.... */
4042 j=1;
4043 } else {
4044 j=0;
4045 }
4046 }
4047 }
4048
4049 return;
4050 }
4051
4052 /*
4053 ** For the bad status case and no SROM, then add one to the previous
4054 ** address. However, need to add one backwards in case we have 0xff
4055 ** as one or more of the bytes. Only the last 3 bytes should be checked
4056 ** as the first three are invariant - assigned to an organisation.
4057 */
4058 static int
4059 get_hw_addr(struct device *dev)
4060 {
4061 u_long iobase = dev->base_addr;
4062 int broken, i, k, tmp, status = 0;
4063 u_short j,chksum;
4064 struct bus_type *lp = &bus;
4065
4066 broken = de4x5_bad_srom(lp);
4067
4068 for (i=0,k=0,j=0;j<3;j++) {
4069 k <<= 1;
4070 if (k > 0xffff) k-=0xffff;
4071
4072 if (lp->bus == PCI) {
4073 if (lp->chipset == DC21040) {
4074 while ((tmp = inl(DE4X5_APROM)) < 0);
4075 k += (u_char) tmp;
4076 dev->dev_addr[i++] = (u_char) tmp;
4077 while ((tmp = inl(DE4X5_APROM)) < 0);
4078 k += (u_short) (tmp << 8);
4079 dev->dev_addr[i++] = (u_char) tmp;
4080 } else if (!broken) {
4081 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4082 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4083 } else if ((broken == SMC) || (broken == ACCTON)) {
4084 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4085 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4086 }
4087 } else {
4088 k += (u_char) (tmp = inb(EISA_APROM));
4089 dev->dev_addr[i++] = (u_char) tmp;
4090 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4091 dev->dev_addr[i++] = (u_char) tmp;
4092 }
4093
4094 if (k > 0xffff) k-=0xffff;
4095 }
4096 if (k == 0xffff) k=0;
4097
4098 if (lp->bus == PCI) {
4099 if (lp->chipset == DC21040) {
4100 while ((tmp = inl(DE4X5_APROM)) < 0);
4101 chksum = (u_char) tmp;
4102 while ((tmp = inl(DE4X5_APROM)) < 0);
4103 chksum |= (u_short) (tmp << 8);
4104 if ((k != chksum) && (dec_only)) status = -1;
4105 }
4106 } else {
4107 chksum = (u_char) inb(EISA_APROM);
4108 chksum |= (u_short) (inb(EISA_APROM) << 8);
4109 if ((k != chksum) && (dec_only)) status = -1;
4110 }
4111
4112 /* If possible, try to fix a broken card - SMC only so far */
4113 srom_repair(dev, broken);
4114
4115 #ifdef CONFIG_PMAC
4116 /* If the address starts with 00 a0, we have to bit-reverse
4117 each byte of the address. */
4118 if (dev->dev_addr[0] == 0 && dev->dev_addr[1] == 0xa0) {
4119 for (i = 0; i < ETH_ALEN; ++i) {
4120 int x = dev->dev_addr[i];
4121 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4122 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4123 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4124 }
4125 }
4126 #endif /* CONFIG_PMAC */
4127
4128 /* Test for a bad enet address */
4129 status = test_bad_enet(dev, status);
4130
4131 return status;
4132 }
4133
4134 /*
4135 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4136 ** didn't seem to work here...?
4137 */
4138 static int
4139 de4x5_bad_srom(struct bus_type *lp)
4140 {
4141 int i, status = 0;
4142
4143 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4144 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4145 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4146 if (i == 0) {
4147 status = SMC;
4148 } else if (i == 1) {
4149 status = ACCTON;
4150 }
4151 break;
4152 }
4153 }
4154
4155 return status;
4156 }
4157
4158 static int
4159 de4x5_strncmp(char *a, char *b, int n)
4160 {
4161 int ret=0;
4162
4163 for (;n && !ret;n--) {
4164 ret = *a++ - *b++;
4165 }
4166
4167 return ret;
4168 }
4169
4170 static void
4171 srom_repair(struct device *dev, int card)
4172 {
4173 struct bus_type *lp = &bus;
4174
4175 switch(card) {
4176 case SMC:
4177 memset((char *)&bus.srom, 0, sizeof(struct de4x5_srom));
4178 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4179 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4180 useSROM = TRUE;
4181 break;
4182 }
4183
4184 return;
4185 }
4186
4187 /*
4188 ** Assume that the irq's do not follow the PCI spec - this is seems
4189 ** to be true so far (2 for 2).
4190 */
4191 static int
4192 test_bad_enet(struct device *dev, int status)
4193 {
4194 struct bus_type *lp = &bus;
4195 int i, tmp;
4196
4197 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4198 if ((tmp == 0) || (tmp == 0x5fa)) {
4199 if ((lp->chipset == last.chipset) &&
4200 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4201 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4202 for (i=ETH_ALEN-1; i>2; --i) {
4203 dev->dev_addr[i] += 1;
4204 if (dev->dev_addr[i] != 0) break;
4205 }
4206 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4207 dev->irq = last.irq;
4208
4209 status = 0;
4210 }
4211 } else if (!status) {
4212 last.chipset = lp->chipset;
4213 last.bus = lp->bus_num;
4214 last.irq = dev->irq;
4215 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4216 }
4217
4218 return status;
4219 }
4220
4221 /*
4222 ** SROM Read
4223 */
4224 static short
4225 srom_rd(u_long addr, u_char offset)
4226 {
4227 sendto_srom(SROM_RD | SROM_SR, addr);
4228
4229 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4230 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4231 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4232
4233 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4234 }
4235
4236 static void
4237 srom_latch(u_int command, u_long addr)
4238 {
4239 sendto_srom(command, addr);
4240 sendto_srom(command | DT_CLK, addr);
4241 sendto_srom(command, addr);
4242
4243 return;
4244 }
4245
4246 static void
4247 srom_command(u_int command, u_long addr)
4248 {
4249 srom_latch(command, addr);
4250 srom_latch(command, addr);
4251 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4252
4253 return;
4254 }
4255
4256 static void
4257 srom_address(u_int command, u_long addr, u_char offset)
4258 {
4259 int i;
4260 char a;
4261
4262 a = (char)(offset << 2);
4263 for (i=0; i<6; i++, a <<= 1) {
4264 srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
4265 }
4266 de4x5_us_delay(1);
4267
4268 i = (getfrom_srom(addr) >> 3) & 0x01;
4269
4270 return;
4271 }
4272
4273 static short
4274 srom_data(u_int command, u_long addr)
4275 {
4276 int i;
4277 short word = 0;
4278 s32 tmp;
4279
4280 for (i=0; i<16; i++) {
4281 sendto_srom(command | DT_CLK, addr);
4282 tmp = getfrom_srom(addr);
4283 sendto_srom(command, addr);
4284
4285 word = (word << 1) | ((tmp >> 3) & 0x01);
4286 }
4287
4288 sendto_srom(command & 0x0000ff00, addr);
4289
4290 return word;
4291 }
4292
4293 /*
4294 static void
4295 srom_busy(u_int command, u_long addr)
4296 {
4297 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4298
4299 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4300 de4x5_ms_delay(1);
4301 }
4302
4303 sendto_srom(command & 0x0000ff00, addr);
4304
4305 return;
4306 }
4307 */
4308
4309 static void
4310 sendto_srom(u_int command, u_long addr)
4311 {
4312 outl(command, addr);
4313 udelay(1);
4314
4315 return;
4316 }
4317
4318 static int
4319 getfrom_srom(u_long addr)
4320 {
4321 s32 tmp;
4322
4323 tmp = inl(addr);
4324 udelay(1);
4325
4326 return tmp;
4327 }
4328
4329 static int
4330 srom_infoleaf_info(struct device *dev)
4331 {
4332 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4333 int i, count;
4334 u_char *p;
4335
4336 /* Find the infoleaf decoder function that matches this chipset */
4337 for (i=0; i<INFOLEAF_SIZE; i++) {
4338 if (lp->chipset == infoleaf_array[i].chipset) break;
4339 }
4340 if (i == INFOLEAF_SIZE) {
4341 lp->useSROM = FALSE;
4342 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4343 dev->name);
4344 return -ENXIO;
4345 }
4346
4347 lp->infoleaf_fn = infoleaf_array[i].fn;
4348
4349 /* Find the information offset that this function should use */
4350 count = *((u_char *)&lp->srom + 19);
4351 p = (u_char *)&lp->srom + 26;
4352
4353 if (count > 1) {
4354 for (i=count; i; --i, p+=3) {
4355 if (lp->device == *p) break;
4356 }
4357 if (i == 0) {
4358 lp->useSROM = FALSE;
4359 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4360 dev->name, lp->device);
4361 return -ENXIO;
4362 }
4363 }
4364
4365 lp->infoleaf_offset = TWIDDLE(p+1);
4366
4367 return 0;
4368 }
4369
4370 /*
4371 ** This routine loads any type 1 or 3 MII info into the mii device
4372 ** struct and executes any type 5 code to reset PHY devices for this
4373 ** controller.
4374 ** The info for the MII devices will be valid since the index used
4375 ** will follow the discovery process from MII address 1-31 then 0.
4376 */
4377 static void
4378 srom_init(struct device *dev)
4379 {
4380 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4381 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4382 u_char count;
4383
4384 p+=2;
4385 if (lp->chipset == DC21140) {
4386 lp->cache.gepc = (*p++ | GEP_CTRL);
4387 gep_wr(lp->cache.gepc, dev);
4388 }
4389
4390 /* Block count */
4391 count = *p++;
4392
4393 /* Jump the infoblocks to find types */
4394 for (;count; --count) {
4395 if (*p < 128) {
4396 p += COMPACT_LEN;
4397 } else if (*(p+1) == 5) {
4398 type5_infoblock(dev, 1, p);
4399 p += ((*p & BLOCK_LEN) + 1);
4400 } else if (*(p+1) == 4) {
4401 p += ((*p & BLOCK_LEN) + 1);
4402 } else if (*(p+1) == 3) {
4403 type3_infoblock(dev, 1, p);
4404 p += ((*p & BLOCK_LEN) + 1);
4405 } else if (*(p+1) == 2) {
4406 p += ((*p & BLOCK_LEN) + 1);
4407 } else if (*(p+1) == 1) {
4408 type1_infoblock(dev, 1, p);
4409 p += ((*p & BLOCK_LEN) + 1);
4410 } else {
4411 p += ((*p & BLOCK_LEN) + 1);
4412 }
4413 }
4414
4415 return;
4416 }
4417
4418 /*
4419 ** A generic routine that writes GEP control, data and reset information
4420 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4421 */
4422 static void
4423 srom_exec(struct device *dev, u_char *p)
4424 {
4425 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4426 u_long iobase = dev->base_addr;
4427 u_char count = (p ? *p++ : 0);
4428 u_short *w = (u_short *)p;
4429
4430 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4431
4432 if (lp->chipset != DC21140) RESET_SIA;
4433
4434 while (count--) {
4435 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4436 *p++ : TWIDDLE(w++)), dev);
4437 mdelay(2); /* 2ms per action */
4438 }
4439
4440 if (lp->chipset != DC21140) {
4441 outl(lp->cache.csr14, DE4X5_STRR);
4442 outl(lp->cache.csr13, DE4X5_SICR);
4443 }
4444
4445 return;
4446 }
4447
4448 /*
4449 ** Basically this function is a NOP since it will never be called,
4450 ** unless I implement the DC21041 SROM functions. There's no need
4451 ** since the existing code will be satisfactory for all boards.
4452 */
4453 static int
4454 dc21041_infoleaf(struct device *dev)
4455 {
4456 return DE4X5_AUTOSENSE_MS;
4457 }
4458
4459 static int
4460 dc21140_infoleaf(struct device *dev)
4461 {
4462 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4463 u_char count = 0;
4464 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4465 int next_tick = DE4X5_AUTOSENSE_MS;
4466
4467 /* Read the connection type */
4468 p+=2;
4469
4470 /* GEP control */
4471 lp->cache.gepc = (*p++ | GEP_CTRL);
4472
4473 /* Block count */
4474 count = *p++;
4475
4476 /* Recursively figure out the info blocks */
4477 if (*p < 128) {
4478 next_tick = dc_infoblock[COMPACT](dev, count, p);
4479 } else {
4480 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4481 }
4482
4483 if (lp->tcount == count) {
4484 lp->media = NC;
4485 if (lp->media != lp->c_media) {
4486 de4x5_dbg_media(dev);
4487 lp->c_media = lp->media;
4488 }
4489 lp->media = INIT;
4490 lp->tcount = 0;
4491 lp->tx_enable = FALSE;
4492 }
4493
4494 return next_tick & ~TIMER_CB;
4495 }
4496
4497 static int
4498 dc21142_infoleaf(struct device *dev)
4499 {
4500 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4501 u_char count = 0;
4502 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4503 int next_tick = DE4X5_AUTOSENSE_MS;
4504
4505 /* Read the connection type */
4506 p+=2;
4507
4508 /* Block count */
4509 count = *p++;
4510
4511 /* Recursively figure out the info blocks */
4512 if (*p < 128) {
4513 next_tick = dc_infoblock[COMPACT](dev, count, p);
4514 } else {
4515 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4516 }
4517
4518 if (lp->tcount == count) {
4519 lp->media = NC;
4520 if (lp->media != lp->c_media) {
4521 de4x5_dbg_media(dev);
4522 lp->c_media = lp->media;
4523 }
4524 lp->media = INIT;
4525 lp->tcount = 0;
4526 lp->tx_enable = FALSE;
4527 }
4528
4529 return next_tick & ~TIMER_CB;
4530 }
4531
4532 static int
4533 dc21143_infoleaf(struct device *dev)
4534 {
4535 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4536 u_char count = 0;
4537 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4538 int next_tick = DE4X5_AUTOSENSE_MS;
4539
4540 /* Read the connection type */
4541 p+=2;
4542
4543 /* Block count */
4544 count = *p++;
4545
4546 /* Recursively figure out the info blocks */
4547 if (*p < 128) {
4548 next_tick = dc_infoblock[COMPACT](dev, count, p);
4549 } else {
4550 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4551 }
4552 if (lp->tcount == count) {
4553 lp->media = NC;
4554 if (lp->media != lp->c_media) {
4555 de4x5_dbg_media(dev);
4556 lp->c_media = lp->media;
4557 }
4558 lp->media = INIT;
4559 lp->tcount = 0;
4560 lp->tx_enable = FALSE;
4561 }
4562
4563 return next_tick & ~TIMER_CB;
4564 }
4565
4566 /*
4567 ** The compact infoblock is only designed for DC21140[A] chips, so
4568 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4569 */
4570 static int
4571 compact_infoblock(struct device *dev, u_char count, u_char *p)
4572 {
4573 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4574 u_char flags, csr6;
4575
4576 /* Recursively figure out the info blocks */
4577 if (--count > lp->tcount) {
4578 if (*(p+COMPACT_LEN) < 128) {
4579 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4580 } else {
4581 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4582 }
4583 }
4584
4585 if ((lp->media == INIT) && (lp->timeout < 0)) {
4586 lp->ibn = COMPACT;
4587 lp->active = 0;
4588 gep_wr(lp->cache.gepc, dev);
4589 lp->infoblock_media = (*p++) & COMPACT_MC;
4590 lp->cache.gep = *p++;
4591 csr6 = *p++;
4592 flags = *p++;
4593
4594 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4595 lp->defMedium = (flags & 0x40) ? -1 : 0;
4596 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4597 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4598 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4599 lp->useMII = FALSE;
4600
4601 de4x5_switch_mac_port(dev);
4602 }
4603
4604 return dc21140m_autoconf(dev);
4605 }
4606
4607 /*
4608 ** This block describes non MII media for the DC21140[A] only.
4609 */
4610 static int
4611 type0_infoblock(struct device *dev, u_char count, u_char *p)
4612 {
4613 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4614 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4615
4616 /* Recursively figure out the info blocks */
4617 if (--count > lp->tcount) {
4618 if (*(p+len) < 128) {
4619 return dc_infoblock[COMPACT](dev, count, p+len);
4620 } else {
4621 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4622 }
4623 }
4624
4625 if ((lp->media == INIT) && (lp->timeout < 0)) {
4626 lp->ibn = 0;
4627 lp->active = 0;
4628 gep_wr(lp->cache.gepc, dev);
4629 p+=2;
4630 lp->infoblock_media = (*p++) & BLOCK0_MC;
4631 lp->cache.gep = *p++;
4632 csr6 = *p++;
4633 flags = *p++;
4634
4635 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4636 lp->defMedium = (flags & 0x40) ? -1 : 0;
4637 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4638 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4639 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4640 lp->useMII = FALSE;
4641
4642 de4x5_switch_mac_port(dev);
4643 }
4644
4645 return dc21140m_autoconf(dev);
4646 }
4647
4648 /* These functions are under construction! */
4649
4650 static int
4651 type1_infoblock(struct device *dev, u_char count, u_char *p)
4652 {
4653 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4654 u_char len = (*p & BLOCK_LEN)+1;
4655
4656 /* Recursively figure out the info blocks */
4657 if (--count > lp->tcount) {
4658 if (*(p+len) < 128) {
4659 return dc_infoblock[COMPACT](dev, count, p+len);
4660 } else {
4661 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4662 }
4663 }
4664
4665 p += 2;
4666 if (lp->state == INITIALISED) {
4667 lp->ibn = 1;
4668 lp->active = *p++;
4669 lp->phy[lp->active].gep = (*p ? p : 0); p += (*p + 1);
4670 lp->phy[lp->active].rst = (*p ? p : 0); p += (*p + 1);
4671 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4672 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4673 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4674 lp->phy[lp->active].ttm = TWIDDLE(p);
4675 return 0;
4676 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4677 lp->ibn = 1;
4678 lp->active = *p;
4679 lp->infoblock_csr6 = OMR_MII_100;
4680 lp->useMII = TRUE;
4681 lp->infoblock_media = ANS;
4682
4683 de4x5_switch_mac_port(dev);
4684 }
4685
4686 return dc21140m_autoconf(dev);
4687 }
4688
4689 static int
4690 type2_infoblock(struct device *dev, u_char count, u_char *p)
4691 {
4692 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4693 u_char len = (*p & BLOCK_LEN)+1;
4694
4695 /* Recursively figure out the info blocks */
4696 if (--count > lp->tcount) {
4697 if (*(p+len) < 128) {
4698 return dc_infoblock[COMPACT](dev, count, p+len);
4699 } else {
4700 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4701 }
4702 }
4703
4704 if ((lp->media == INIT) && (lp->timeout < 0)) {
4705 lp->ibn = 2;
4706 lp->active = 0;
4707 p += 2;
4708 lp->infoblock_media = (*p) & MEDIA_CODE;
4709
4710 if ((*p++) & EXT_FIELD) {
4711 lp->cache.csr13 = TWIDDLE(p); p += 2;
4712 lp->cache.csr14 = TWIDDLE(p); p += 2;
4713 lp->cache.csr15 = TWIDDLE(p); p += 2;
4714 } else {
4715 lp->cache.csr13 = CSR13;
4716 lp->cache.csr14 = CSR14;
4717 lp->cache.csr15 = CSR15;
4718 }
4719 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4720 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4721 lp->infoblock_csr6 = OMR_SIA;
4722 lp->useMII = FALSE;
4723
4724 de4x5_switch_mac_port(dev);
4725 }
4726
4727 return dc2114x_autoconf(dev);
4728 }
4729
4730 static int
4731 type3_infoblock(struct device *dev, u_char count, u_char *p)
4732 {
4733 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4734 u_char len = (*p & BLOCK_LEN)+1;
4735
4736 /* Recursively figure out the info blocks */
4737 if (--count > lp->tcount) {
4738 if (*(p+len) < 128) {
4739 return dc_infoblock[COMPACT](dev, count, p+len);
4740 } else {
4741 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4742 }
4743 }
4744
4745 p += 2;
4746 if (lp->state == INITIALISED) {
4747 lp->ibn = 3;
4748 lp->active = *p++;
4749 lp->phy[lp->active].gep = (*p ? p : 0); p += (2 * (*p) + 1);
4750 lp->phy[lp->active].rst = (*p ? p : 0); p += (2 * (*p) + 1);
4751 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4752 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4753 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4754 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4755 lp->phy[lp->active].mci = *p;
4756 return 0;
4757 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4758 lp->ibn = 3;
4759 lp->active = *p;
4760 lp->infoblock_csr6 = OMR_MII_100;
4761 lp->useMII = TRUE;
4762 lp->infoblock_media = ANS;
4763
4764 de4x5_switch_mac_port(dev);
4765 }
4766
4767 return dc2114x_autoconf(dev);
4768 }
4769
4770 static int
4771 type4_infoblock(struct device *dev, u_char count, u_char *p)
4772 {
4773 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4774 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4775
4776 /* Recursively figure out the info blocks */
4777 if (--count > lp->tcount) {
4778 if (*(p+len) < 128) {
4779 return dc_infoblock[COMPACT](dev, count, p+len);
4780 } else {
4781 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4782 }
4783 }
4784
4785 if ((lp->media == INIT) && (lp->timeout < 0)) {
4786 lp->ibn = 4;
4787 lp->active = 0;
4788 p+=2;
4789 lp->infoblock_media = (*p++) & MEDIA_CODE;
4790 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4791 lp->cache.csr14 = CSR14;
4792 lp->cache.csr15 = CSR15;
4793 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4794 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4795 csr6 = *p++;
4796 flags = *p++;
4797
4798 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4799 lp->defMedium = (flags & 0x40) ? -1 : 0;
4800 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4801 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4802 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4803 lp->useMII = FALSE;
4804
4805 de4x5_switch_mac_port(dev);
4806 }
4807
4808 return dc2114x_autoconf(dev);
4809 }
4810
4811 /*
4812 ** This block type provides information for resetting external devices
4813 ** (chips) through the General Purpose Register.
4814 */
4815 static int
4816 type5_infoblock(struct device *dev, u_char count, u_char *p)
4817 {
4818 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
4819 u_char len = (*p & BLOCK_LEN)+1;
4820
4821 /* Recursively figure out the info blocks */
4822 if (--count > lp->tcount) {
4823 if (*(p+len) < 128) {
4824 return dc_infoblock[COMPACT](dev, count, p+len);
4825 } else {
4826 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4827 }
4828 }
4829
4830 /* Must be initializing to run this code */
4831 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4832 p+=2;
4833 lp->rst = p;
4834 srom_exec(dev, lp->rst);
4835 }
4836
4837 return DE4X5_AUTOSENSE_MS;
4838 }
4839
4840 /*
4841 ** MII Read/Write
4842 */
4843
4844 static int
4845 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4846 {
4847 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4848 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4849 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4850 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4851 mii_address(phyreg, ioaddr); /* PHY Register to read */
4852 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4853
4854 return mii_rdata(ioaddr); /* Read data */
4855 }
4856
4857 static void
4858 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4859 {
4860 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4861 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4862 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4863 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4864 mii_address(phyreg, ioaddr); /* PHY Register to write */
4865 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4866 data = mii_swap(data, 16); /* Swap data bit ordering */
4867 mii_wdata(data, 16, ioaddr); /* Write data */
4868
4869 return;
4870 }
4871
4872 static int
4873 mii_rdata(u_long ioaddr)
4874 {
4875 int i;
4876 s32 tmp = 0;
4877
4878 for (i=0; i<16; i++) {
4879 tmp <<= 1;
4880 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4881 }
4882
4883 return tmp;
4884 }
4885
4886 static void
4887 mii_wdata(int data, int len, u_long ioaddr)
4888 {
4889 int i;
4890
4891 for (i=0; i<len; i++) {
4892 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4893 data >>= 1;
4894 }
4895
4896 return;
4897 }
4898
4899 static void
4900 mii_address(u_char addr, u_long ioaddr)
4901 {
4902 int i;
4903
4904 addr = mii_swap(addr, 5);
4905 for (i=0; i<5; i++) {
4906 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4907 addr >>= 1;
4908 }
4909
4910 return;
4911 }
4912
4913 static void
4914 mii_ta(u_long rw, u_long ioaddr)
4915 {
4916 if (rw == MII_STWR) {
4917 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4918 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4919 } else {
4920 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4921 }
4922
4923 return;
4924 }
4925
4926 static int
4927 mii_swap(int data, int len)
4928 {
4929 int i, tmp = 0;
4930
4931 for (i=0; i<len; i++) {
4932 tmp <<= 1;
4933 tmp |= (data & 1);
4934 data >>= 1;
4935 }
4936
4937 return tmp;
4938 }
4939
4940 static void
4941 sendto_mii(u32 command, int data, u_long ioaddr)
4942 {
4943 u32 j;
4944
4945 j = (data & 1) << 17;
4946 outl(command | j, ioaddr);
4947 udelay(1);
4948 outl(command | MII_MDC | j, ioaddr);
4949 udelay(1);
4950
4951 return;
4952 }
4953
4954 static int
4955 getfrom_mii(u32 command, u_long ioaddr)
4956 {
4957 outl(command, ioaddr);
4958 udelay(1);
4959 outl(command | MII_MDC, ioaddr);
4960 udelay(1);
4961
4962 return ((inl(ioaddr) >> 19) & 1);
4963 }
4964
4965 /*
4966 ** Here's 3 ways to calculate the OUI from the ID registers.
4967 */
4968 static int
4969 mii_get_oui(u_char phyaddr, u_long ioaddr)
4970 {
4971 /*
4972 union {
4973 u_short reg;
4974 u_char breg[2];
4975 } a;
4976 int i, r2, r3, ret=0;*/
4977 int r2, r3;
4978
4979 /* Read r2 and r3 */
4980 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4981 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4982 /* SEEQ and Cypress way * /
4983 / * Shuffle r2 and r3 * /
4984 a.reg=0;
4985 r3 = ((r3>>10)|(r2<<6))&0x0ff;
4986 r2 = ((r2>>2)&0x3fff);
4987
4988 / * Bit reverse r3 * /
4989 for (i=0;i<8;i++) {
4990 ret<<=1;
4991 ret |= (r3&1);
4992 r3>>=1;
4993 }
4994
4995 / * Bit reverse r2 * /
4996 for (i=0;i<16;i++) {
4997 a.reg<<=1;
4998 a.reg |= (r2&1);
4999 r2>>=1;
5000 }
5001
5002 / * Swap r2 bytes * /
5003 i=a.breg[0];
5004 a.breg[0]=a.breg[1];
5005 a.breg[1]=i;
5006
5007 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5008 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5009 return r2; /* (I did it) My way */
5010 }
5011
5012 /*
5013 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5014 */
5015 static int
5016 mii_get_phy(struct device *dev)
5017 {
5018 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5019 u_long iobase = dev->base_addr;
5020 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5021 int id;
5022
5023 lp->active = 0;
5024 lp->useMII = TRUE;
5025
5026 /* Search the MII address space for possible PHY devices */
5027 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(++i)%DE4X5_MAX_MII) {
5028 lp->phy[lp->active].addr = i;
5029 if (i==0) n++; /* Count cycles */
5030 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5031 id = mii_get_oui(i, DE4X5_MII);
5032 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5033 for (j=0; j<limit; j++) { /* Search PHY table */
5034 if (id != phy_info[j].id) continue; /* ID match? */
5035 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5036 if (k < DE4X5_MAX_PHY) {
5037 memcpy((char *)&lp->phy[k],
5038 (char *)&phy_info[j], sizeof(struct phy_table));
5039 lp->phy[k].addr = i;
5040 lp->mii_cnt++;
5041 lp->active++;
5042 } else {
5043 goto purgatory; /* Stop the search */
5044 }
5045 break;
5046 }
5047 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5048 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5049 lp->phy[k].addr = i;
5050 lp->phy[k].id = id;
5051 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5052 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5053 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5054 lp->mii_cnt++;
5055 lp->active++;
5056 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5057 j = de4x5_debug;
5058 de4x5_debug |= DEBUG_MII;
5059 de4x5_dbg_mii(dev, k);
5060 de4x5_debug = j;
5061 printk("\n");
5062 }
5063 }
5064 purgatory:
5065 lp->active = 0;
5066 if (lp->phy[0].id) { /* Reset the PHY devices */
5067 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5068 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5069 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5070
5071 de4x5_dbg_mii(dev, k);
5072 }
5073 }
5074 if (!lp->mii_cnt) lp->useMII = FALSE;
5075
5076 return lp->mii_cnt;
5077 }
5078
5079 static char *
5080 build_setup_frame(struct device *dev, int mode)
5081 {
5082 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5083 int i;
5084 char *pa = lp->setup_frame;
5085
5086 /* Initialise the setup frame */
5087 if (mode == ALL) {
5088 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5089 }
5090
5091 if (lp->setup_f == HASH_PERF) {
5092 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5093 *(pa + i) = dev->dev_addr[i]; /* Host address */
5094 if (i & 0x01) pa += 2;
5095 }
5096 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5097 } else {
5098 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5099 *(pa + (i&1)) = dev->dev_addr[i];
5100 if (i & 0x01) pa += 4;
5101 }
5102 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5103 *(pa + (i&1)) = (char) 0xff;
5104 if (i & 0x01) pa += 4;
5105 }
5106 }
5107
5108 return pa; /* Points to the next entry */
5109 }
5110
5111 static void
5112 enable_ast(struct device *dev, u32 time_out)
5113 {
5114 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5115
5116 return;
5117 }
5118
5119 static void
5120 disable_ast(struct device *dev)
5121 {
5122 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5123
5124 del_timer(&lp->timer);
5125
5126 return;
5127 }
5128
5129 static long
5130 de4x5_switch_mac_port(struct device *dev)
5131 {
5132 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5133 u_long iobase = dev->base_addr;
5134 s32 omr;
5135
5136 STOP_DE4X5;
5137
5138 /* Assert the OMR_PS bit in CSR6 */
5139 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5140 OMR_FDX));
5141 omr |= lp->infoblock_csr6;
5142 if (omr & OMR_PS) omr |= OMR_HBD;
5143 outl(omr, DE4X5_OMR);
5144
5145 /* Soft Reset */
5146 RESET_DE4X5;
5147
5148 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5149 if (lp->chipset == DC21140) {
5150 gep_wr(lp->cache.gepc, dev);
5151 gep_wr(lp->cache.gep, dev);
5152 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5153 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5154 }
5155
5156 /* Restore CSR6 */
5157 outl(omr, DE4X5_OMR);
5158
5159 /* Reset CSR8 */
5160 inl(DE4X5_MFC);
5161
5162 return omr;
5163 }
5164
5165 static void
5166 gep_wr(s32 data, struct device *dev)
5167 {
5168 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5169 u_long iobase = dev->base_addr;
5170
5171 if (lp->chipset == DC21140) {
5172 outl(data, DE4X5_GEP);
5173 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5174 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5175 }
5176
5177 return;
5178 }
5179
5180 static int
5181 gep_rd(struct device *dev)
5182 {
5183 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5184 u_long iobase = dev->base_addr;
5185
5186 if (lp->chipset == DC21140) {
5187 return inl(DE4X5_GEP);
5188 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5189 return (inl(DE4X5_SIGR) & 0x000fffff);
5190 }
5191
5192 return 0;
5193 }
5194
5195 static void
5196 timeout(struct device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5197 {
5198 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5199 int dt;
5200
5201 /* First, cancel any pending timer events */
5202 del_timer(&lp->timer);
5203
5204 /* Convert msec to ticks */
5205 dt = (msec * HZ) / 1000;
5206 if (dt==0) dt=1;
5207
5208 /* Set up timer */
5209 lp->timer.expires = jiffies + dt;
5210 lp->timer.function = fn;
5211 lp->timer.data = data;
5212 add_timer(&lp->timer);
5213
5214 return;
5215 }
5216
5217 static void
5218 yawn(struct device *dev, int state)
5219 {
5220 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5221 u_long iobase = dev->base_addr;
5222
5223 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5224
5225 if(lp->bus == EISA) {
5226 switch(state) {
5227 case WAKEUP:
5228 outb(WAKEUP, PCI_CFPM);
5229 de4x5_ms_delay(10);
5230 break;
5231
5232 case SNOOZE:
5233 outb(SNOOZE, PCI_CFPM);
5234 break;
5235
5236 case SLEEP:
5237 outl(0, DE4X5_SICR);
5238 outb(SLEEP, PCI_CFPM);
5239 break;
5240 }
5241 } else {
5242 switch(state) {
5243 case WAKEUP:
5244 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5245 PCI_CFDA_PSM, WAKEUP);
5246 de4x5_ms_delay(10);
5247 break;
5248
5249 case SNOOZE:
5250 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5251 PCI_CFDA_PSM, SNOOZE);
5252 break;
5253
5254 case SLEEP:
5255 outl(0, DE4X5_SICR);
5256 pcibios_write_config_byte(lp->bus_num, lp->device << 3,
5257 PCI_CFDA_PSM, SLEEP);
5258 break;
5259 }
5260 }
5261
5262 return;
5263 }
5264
5265 static void
5266 de4x5_parse_params(struct device *dev)
5267 {
5268 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5269 char *p, *q, t;
5270
5271 lp->params.fdx = 0;
5272 lp->params.autosense = AUTO;
5273
5274 if (args == NULL) return;
5275
5276 if ((p = strstr(args, dev->name))) {
5277 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5278 t = *q;
5279 *q = '\0';
5280
5281 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5282
5283 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5284 if (strstr(p, "TP")) {
5285 lp->params.autosense = TP;
5286 } else if (strstr(p, "TP_NW")) {
5287 lp->params.autosense = TP_NW;
5288 } else if (strstr(p, "BNC")) {
5289 lp->params.autosense = BNC;
5290 } else if (strstr(p, "AUI")) {
5291 lp->params.autosense = AUI;
5292 } else if (strstr(p, "BNC_AUI")) {
5293 lp->params.autosense = BNC;
5294 } else if (strstr(p, "10Mb")) {
5295 lp->params.autosense = _10Mb;
5296 } else if (strstr(p, "100Mb")) {
5297 lp->params.autosense = _100Mb;
5298 } else if (strstr(p, "AUTO")) {
5299 lp->params.autosense = AUTO;
5300 }
5301 }
5302 *q = t;
5303 }
5304
5305 return;
5306 }
5307
5308 static void
5309 de4x5_dbg_open(struct device *dev)
5310 {
5311 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5312 int i;
5313
5314 if (de4x5_debug & DEBUG_OPEN) {
5315 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5316 printk("\tphysical address: ");
5317 for (i=0;i<6;i++) {
5318 printk("%2.2x:",(short)dev->dev_addr[i]);
5319 }
5320 printk("\n");
5321 printk("Descriptor head addresses:\n");
5322 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5323 printk("Descriptor addresses:\nRX: ");
5324 for (i=0;i<lp->rxRingSize-1;i++){
5325 if (i < 3) {
5326 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5327 }
5328 }
5329 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5330 printk("TX: ");
5331 for (i=0;i<lp->txRingSize-1;i++){
5332 if (i < 3) {
5333 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5334 }
5335 }
5336 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5337 printk("Descriptor buffers:\nRX: ");
5338 for (i=0;i<lp->rxRingSize-1;i++){
5339 if (i < 3) {
5340 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5341 }
5342 }
5343 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5344 printk("TX: ");
5345 for (i=0;i<lp->txRingSize-1;i++){
5346 if (i < 3) {
5347 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5348 }
5349 }
5350 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5351 printk("Ring size: \nRX: %d\nTX: %d\n",
5352 (short)lp->rxRingSize,
5353 (short)lp->txRingSize);
5354 }
5355
5356 return;
5357 }
5358
5359 static void
5360 de4x5_dbg_mii(struct device *dev, int k)
5361 {
5362 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5363 u_long iobase = dev->base_addr;
5364
5365 if (de4x5_debug & DEBUG_MII) {
5366 printk("\nMII device address: %d\n", lp->phy[k].addr);
5367 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5368 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5369 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5370 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5371 if (lp->phy[k].id != BROADCOM_T4) {
5372 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5373 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5374 }
5375 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5376 if (lp->phy[k].id != BROADCOM_T4) {
5377 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5378 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5379 } else {
5380 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5381 }
5382 }
5383
5384 return;
5385 }
5386
5387 static void
5388 de4x5_dbg_media(struct device *dev)
5389 {
5390 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5391
5392 if (lp->media != lp->c_media) {
5393 if (de4x5_debug & DEBUG_MEDIA) {
5394 printk("%s: media is %s%s\n", dev->name,
5395 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5396 (lp->media == TP ? "TP" :
5397 (lp->media == ANS ? "TP/Nway" :
5398 (lp->media == BNC ? "BNC" :
5399 (lp->media == AUI ? "AUI" :
5400 (lp->media == BNC_AUI ? "BNC/AUI" :
5401 (lp->media == EXT_SIA ? "EXT SIA" :
5402 (lp->media == _100Mb ? "100Mb/s" :
5403 (lp->media == _10Mb ? "10Mb/s" :
5404 "???"
5405 ))))))))), (lp->fdx?" full duplex.":"."));
5406 }
5407 lp->c_media = lp->media;
5408 }
5409
5410 return;
5411 }
5412
5413 static void
5414 de4x5_dbg_srom(struct de4x5_srom *p)
5415 {
5416 int i;
5417
5418 if (de4x5_debug & DEBUG_SROM) {
5419 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5420 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5421 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5422 printk("SROM version: %02x\n", (u_char)(p->version));
5423 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5424
5425 printk("Hardware Address: ");
5426 for (i=0;i<ETH_ALEN-1;i++) {
5427 printk("%02x:", (u_char)*(p->ieee_addr+i));
5428 }
5429 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5430 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5431 for (i=0; i<64; i++) {
5432 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5433 }
5434 }
5435
5436 return;
5437 }
5438
5439 static void
5440 de4x5_dbg_rx(struct sk_buff *skb, int len)
5441 {
5442 int i, j;
5443
5444 if (de4x5_debug & DEBUG_RX) {
5445 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5446 (u_char)skb->data[0],
5447 (u_char)skb->data[1],
5448 (u_char)skb->data[2],
5449 (u_char)skb->data[3],
5450 (u_char)skb->data[4],
5451 (u_char)skb->data[5],
5452 (u_char)skb->data[6],
5453 (u_char)skb->data[7],
5454 (u_char)skb->data[8],
5455 (u_char)skb->data[9],
5456 (u_char)skb->data[10],
5457 (u_char)skb->data[11],
5458 (u_char)skb->data[12],
5459 (u_char)skb->data[13],
5460 len);
5461 if (de4x5_debug & DEBUG_RX) {
5462 for (j=0; len>0;j+=16, len-=16) {
5463 printk(" %03x: ",j);
5464 for (i=0; i<16 && i<len; i++) {
5465 printk("%02x ",(u_char)skb->data[i+j]);
5466 }
5467 printk("\n");
5468 }
5469 }
5470 }
5471
5472 return;
5473 }
5474
5475 /*
5476 ** Perform IOCTL call functions here. Some are privileged operations and the
5477 ** effective uid is checked in those cases. In the normal course of events
5478 ** this function is only used for my testing.
5479 */
5480 static int
5481 de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
5482 {
5483 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
5484 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
5485 u_long iobase = dev->base_addr;
5486 int i, j, status = 0;
5487 s32 omr;
5488 union {
5489 u8 addr[144];
5490 u16 sval[72];
5491 u32 lval[36];
5492 } tmp;
5493
5494 switch(ioc->cmd) {
5495 case DE4X5_GET_HWADDR: /* Get the hardware address */
5496 ioc->len = ETH_ALEN;
5497 status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
5498 if (status)
5499 break;
5500 for (i=0; i<ETH_ALEN; i++) {
5501 tmp.addr[i] = dev->dev_addr[i];
5502 }
5503 copy_to_user(ioc->data, tmp.addr, ioc->len);
5504
5505 break;
5506 case DE4X5_SET_HWADDR: /* Set the hardware address */
5507 status = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
5508 if (status)
5509 break;
5510 status = -EPERM;
5511 if (!capable(CAP_NET_ADMIN))
5512 break;
5513 status = 0;
5514 copy_from_user(tmp.addr, ioc->data, ETH_ALEN);
5515 for (i=0; i<ETH_ALEN; i++) {
5516 dev->dev_addr[i] = tmp.addr[i];
5517 }
5518 build_setup_frame(dev, PHYS_ADDR_ONLY);
5519 /* Set up the descriptor and give ownership to the card */
5520 while (test_and_set_bit(0, (void *)&dev->tbusy) != 0);
5521 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5522 SETUP_FRAME_LEN, NULL);
5523 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5524 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5525 dev->tbusy = 0; /* Unlock the TX ring */
5526
5527 break;
5528 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5529 if (capable(CAP_NET_ADMIN)) {
5530 omr = inl(DE4X5_OMR);
5531 omr |= OMR_PR;
5532 outl(omr, DE4X5_OMR);
5533 dev->flags |= IFF_PROMISC;
5534 } else {
5535 status = -EPERM;
5536 }
5537
5538 break;
5539 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5540 if (capable(CAP_NET_ADMIN)) {
5541 omr = inl(DE4X5_OMR);
5542 omr &= ~OMR_PR;
5543 outb(omr, DE4X5_OMR);
5544 dev->flags &= ~IFF_PROMISC;
5545 } else {
5546 status = -EPERM;
5547 }
5548
5549 break;
5550 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5551 printk("%s: Boo!\n", dev->name);
5552
5553 break;
5554 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5555 if (capable(CAP_NET_ADMIN)) {
5556 omr = inl(DE4X5_OMR);
5557 omr |= OMR_PM;
5558 outl(omr, DE4X5_OMR);
5559 } else {
5560 status = -EPERM;
5561 }
5562
5563 break;
5564 case DE4X5_GET_STATS: /* Get the driver statistics */
5565 ioc->len = sizeof(lp->pktStats);
5566 status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
5567 if (status)
5568 break;
5569
5570 cli();
5571 copy_to_user(ioc->data, &lp->pktStats, ioc->len);
5572 sti();
5573
5574 break;
5575 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5576 if (capable(CAP_NET_ADMIN)) {
5577 cli();
5578 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5579 sti();
5580 } else {
5581 status = -EPERM;
5582 }
5583
5584 break;
5585 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5586 tmp.addr[0] = inl(DE4X5_OMR);
5587 if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, 1))) {
5588 copy_to_user(ioc->data, tmp.addr, 1);
5589 }
5590
5591 break;
5592 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5593 if (capable(CAP_NET_ADMIN)) {
5594 if (!(status = verify_area(VERIFY_READ, (void *)ioc->data, 1))) {
5595 copy_from_user(tmp.addr, ioc->data, 1);
5596 outl(tmp.addr[0], DE4X5_OMR);
5597 }
5598 } else {
5599 status = -EPERM;
5600 }
5601
5602 break;
5603 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5604 j = 0;
5605 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5606 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5607 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5608 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5609 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5610 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5611 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5612 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5613 ioc->len = j;
5614 if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
5615 copy_to_user(ioc->data, tmp.addr, ioc->len);
5616 }
5617 break;
5618
5619 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5620 /*
5621 case DE4X5_DUMP:
5622 j = 0;
5623 tmp.addr[j++] = dev->irq;
5624 for (i=0; i<ETH_ALEN; i++) {
5625 tmp.addr[j++] = dev->dev_addr[i];
5626 }
5627 tmp.addr[j++] = lp->rxRingSize;
5628 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5629 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5630
5631 for (i=0;i<lp->rxRingSize-1;i++){
5632 if (i < 3) {
5633 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5634 }
5635 }
5636 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5637 for (i=0;i<lp->txRingSize-1;i++){
5638 if (i < 3) {
5639 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5640 }
5641 }
5642 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5643
5644 for (i=0;i<lp->rxRingSize-1;i++){
5645 if (i < 3) {
5646 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5647 }
5648 }
5649 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5650 for (i=0;i<lp->txRingSize-1;i++){
5651 if (i < 3) {
5652 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5653 }
5654 }
5655 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5656
5657 for (i=0;i<lp->rxRingSize;i++){
5658 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5659 }
5660 for (i=0;i<lp->txRingSize;i++){
5661 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5662 }
5663
5664 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5665 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5666 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5667 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5668 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5669 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5670 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5671 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5672 tmp.lval[j>>2] = lp->chipset; j+=4;
5673 if (lp->chipset == DC21140) {
5674 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5675 } else {
5676 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5677 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5678 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5679 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5680 }
5681 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5682 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5683 tmp.lval[j>>2] = lp->active; j+=4;
5684 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5685 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5686 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5687 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5688 if (lp->phy[lp->active].id != BROADCOM_T4) {
5689 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5690 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5691 }
5692 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5693 if (lp->phy[lp->active].id != BROADCOM_T4) {
5694 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5695 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5696 } else {
5697 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5698 }
5699 }
5700
5701 tmp.addr[j++] = lp->txRingSize;
5702 tmp.addr[j++] = dev->tbusy;
5703
5704 ioc->len = j;
5705 if (!(status = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len))) {
5706 copy_to_user(ioc->data, tmp.addr, ioc->len);
5707 }
5708
5709 break;
5710 */
5711 default:
5712 status = -EOPNOTSUPP;
5713 }
5714
5715 return status;
5716 }
5717
5718 #ifdef MODULE
5719 /*
5720 ** Note now that module autoprobing is allowed under EISA and PCI. The
5721 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
5722 ** to "do the right thing".
5723 */
5724 #define LP(a) ((struct de4x5_private *)(a))
5725 static struct device *mdev = NULL;
5726 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
5727 MODULE_PARM(io, "i");
5728
5729 int
5730 init_module(void)
5731 {
5732 int i, num, status = -EIO;
5733 struct device *p;
5734
5735 num = count_adapters();
5736
5737 for (i=0; i<num; i++) {
5738 if ((p = insert_device(NULL, io, de4x5_probe)) == NULL)
5739 return -ENOMEM;
5740
5741 if (!mdev) mdev = p;
5742
5743 if (register_netdev(p) != 0) {
5744 kfree(p);
5745 } else {
5746 status = 0; /* At least one adapter will work */
5747 lastModule = p;
5748 }
5749 }
5750
5751 return status;
5752 }
5753
5754 void
5755 cleanup_module(void)
5756 {
5757 while (mdev != NULL) {
5758 mdev = unlink_modules(mdev);
5759 }
5760
5761 return;
5762 }
5763
5764 static struct device *
5765 unlink_modules(struct device *p)
5766 {
5767 struct device *next = NULL;
5768
5769 if (p->priv) { /* Private areas allocated? */
5770 struct de4x5_private *lp = (struct de4x5_private *)p->priv;
5771
5772 next = lp->next_module;
5773 if (lp->cache.buf) { /* MAC buffers allocated? */
5774 kfree(lp->cache.buf); /* Free the MAC buffers */
5775 }
5776 kfree(lp->cache.priv); /* Free the private area */
5777 release_region(p->base_addr, (lp->bus == PCI ?
5778 DE4X5_PCI_TOTAL_SIZE :
5779 DE4X5_EISA_TOTAL_SIZE));
5780 }
5781 unregister_netdev(p);
5782 kfree(p); /* Free the device structure */
5783
5784 return next;
5785 }
5786
5787 static int
5788 count_adapters(void)
5789 {
5790 int i, j=0;
5791 char name[DE4X5_STRLEN];
5792 u_char pb, dev_fn;
5793 u_short vendor;
5794 u_int class = DE4X5_CLASS_CODE;
5795 u_int device;
5796 struct pci_dev *pdev;
5797
5798 #if !defined(__sparc_v9__) && !defined(__powerpc__)
5799 u_long iobase = 0x1000;
5800
5801 for (i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
5802 if (EISA_signature(name, EISA_ID)) j++;
5803 }
5804 #endif
5805 if (!pcibios_present()) return j;
5806
5807 for (i=0;
5808 (pcibios_find_class(class, i, &pb, &dev_fn)!= PCIBIOS_DEVICE_NOT_FOUND);
5809 i++) {
5810 for (pdev = pci_devices; pdev; pdev = pdev->next) {
5811 if ((pdev->bus->number==pb) && (pdev->devfn==dev_fn)) break;
5812 }
5813
5814 vendor = pdev->vendor;
5815 device = pdev->device << 8;
5816 if (is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x) j++;
5817 }
5818
5819 return j;
5820 }
5821
5822 /*
5823 ** If at end of eth device list and can't use current entry, malloc
5824 ** one up. If memory could not be allocated, print an error message.
5825 */
5826 __initfunc(static struct device *
5827 insert_device(struct device *dev, u_long iobase, int (*init)(struct device *)))
5828 {
5829 struct device *new;
5830
5831 new = (struct device *)kmalloc(sizeof(struct device)+8, GFP_KERNEL);
5832 if (new == NULL) {
5833 printk("de4x5.c: Device not initialised, insufficient memory\n");
5834 return NULL;
5835 } else {
5836 memset((char *)new, 0, sizeof(struct device)+8);
5837 new->name = (char *)(new + 1);
5838 new->base_addr = iobase; /* assign the io address */
5839 new->init = init; /* initialisation routine */
5840 }
5841
5842 return new;
5843 }
5844
5845 #endif /* MODULE */
5846
5847 \f
5848 /*
5849 * Local variables:
5850 * compile-command: "gcc -D__KERNEL__ -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5851 *
5852 * compile-command: "gcc -D__KERNEL__ -DMODULE -I/linux/include -Wall -Wstrict-prototypes -fomit-frame-pointer -fno-strength-reduce -malign-loops=2 -malign-jumps=2 -malign-functions=2 -O2 -m486 -c de4x5.c"
5853 * End:
5854 */
Copy of Dave Jones history.git as used by http://archive.org/details/git-history-of-linux