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Import 2.3.35pre2
[davej-history.git] / drivers / pcmcia / i82365.c
blob8f45713eac68807d4c4d3cb029daa828da49712a
1 /*======================================================================
2
3 Device driver for Intel 82365 and compatible PC Card controllers,
4 and Yenta-compatible PCI-to-CardBus controllers.
5
6 i82365.c 1.265 1999/11/10 18:36:21
7
8 The contents of this file are subject to the Mozilla Public
9 License Version 1.1 (the "License"); you may not use this file
10 except in compliance with the License. You may obtain a copy of
11 the License at http://www.mozilla.org/MPL/
12
13 Software distributed under the License is distributed on an "AS
14 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
15 implied. See the License for the specific language governing
16 rights and limitations under the License.
17
18 The initial developer of the original code is David A. Hinds
19 <dhinds@pcmcia.sourceforge.org>. Portions created by David A. Hinds
20 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
21
22 Alternatively, the contents of this file may be used under the
23 terms of the GNU Public License version 2 (the "GPL"), in which
24 case the provisions of the GPL are applicable instead of the
25 above. If you wish to allow the use of your version of this file
26 only under the terms of the GPL and not to allow others to use
27 your version of this file under the MPL, indicate your decision
28 by deleting the provisions above and replace them with the notice
29 and other provisions required by the GPL. If you do not delete
30 the provisions above, a recipient may use your version of this
31 file under either the MPL or the GPL.
32
33 ======================================================================*/
34
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/config.h>
38 #include <linux/types.h>
39 #include <linux/fcntl.h>
40 #include <linux/string.h>
41 #include <linux/kernel.h>
42 #include <linux/errno.h>
43 #include <linux/timer.h>
44 #include <linux/sched.h>
45 #include <linux/malloc.h>
46 #include <linux/pci.h>
47 #include <linux/ioport.h>
48 #include <linux/delay.h>
49 #include <linux/proc_fs.h>
50 #include <asm/irq.h>
51 #include <asm/io.h>
52 #include <asm/bitops.h>
53 #include <asm/segment.h>
54 #include <asm/system.h>
55
56 #include <pcmcia/version.h>
57 #include <pcmcia/cs_types.h>
58 #include <pcmcia/ss.h>
59 #include <pcmcia/cs.h>
60
61 /* ISA-bus controllers */
62 #include "i82365.h"
63 #include "cirrus.h"
64 #include "vg468.h"
65 #include "ricoh.h"
66 #include "o2micro.h"
67
68 /* PCI-bus controllers */
69 #include "old-yenta.h"
70 #include "ti113x.h"
71 #include "smc34c90.h"
72 #include "topic.h"
73
74 #ifdef PCMCIA_DEBUG
75 static int pc_debug = PCMCIA_DEBUG;
76 MODULE_PARM(pc_debug, "i");
77 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
78 static const char *version =
79 "i82365.c 1.265 1999/11/10 18:36:21 (David Hinds)";
80 #else
81 #define DEBUG(n, args...) do { } while (0)
82 #endif
83
84 static void irq_count(int, void *, struct pt_regs *);
85 static inline int _check_irq(int irq, int flags)
86 {
87 if (request_irq(irq, irq_count, flags, "x", NULL) != 0)
88 return -1;
89 free_irq(irq, NULL);
90 return 0;
91 }
92
93 /*====================================================================*/
94
95 /* Parameters that can be set with 'insmod' */
96
97 #ifdef CONFIG_ISA
98 /* Default base address for i82365sl and other ISA chips */
99 static int i365_base = 0x3e0;
100 /* Should we probe at 0x3e2 for an extra ISA controller? */
101 static int extra_sockets = 0;
102 /* Specify a socket number to ignore */
103 static int ignore = -1;
104 /* Bit map or list of interrupts to choose from */
105 static u_int irq_mask = 0xffff;
106 static int irq_list[16] = { -1 };
107 /* The card status change interrupt -- 0 means autoselect */
108 static int cs_irq = 0;
109 #endif
110
111 /* Probe for safe interrupts? */
112 static int do_scan = 1;
113 /* Poll status interval -- 0 means default to interrupt */
114 static int poll_interval = 0;
115 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
116 static int cycle_time = 120;
117
118 /* Cirrus options */
119 static int has_dma = -1;
120 static int has_led = -1;
121 static int has_ring = -1;
122 static int dynamic_mode = 0;
123 static int freq_bypass = -1;
124 static int setup_time = -1;
125 static int cmd_time = -1;
126 static int recov_time = -1;
127
128 #ifdef CONFIG_ISA
129 /* Vadem options */
130 static int async_clock = -1;
131 static int cable_mode = -1;
132 static int wakeup = 0;
133 #endif
134
135 #ifdef CONFIG_ISA
136 MODULE_PARM(i365_base, "i");
137 MODULE_PARM(ignore, "i");
138 MODULE_PARM(extra_sockets, "i");
139 MODULE_PARM(irq_mask, "i");
140 MODULE_PARM(irq_list, "1-16i");
141 MODULE_PARM(cs_irq, "i");
142 MODULE_PARM(async_clock, "i");
143 MODULE_PARM(cable_mode, "i");
144 MODULE_PARM(wakeup, "i");
145 #endif
146
147 MODULE_PARM(do_scan, "i");
148 MODULE_PARM(poll_interval, "i");
149 MODULE_PARM(cycle_time, "i");
150 MODULE_PARM(has_dma, "i");
151 MODULE_PARM(has_led, "i");
152 MODULE_PARM(has_ring, "i");
153 MODULE_PARM(dynamic_mode, "i");
154 MODULE_PARM(freq_bypass, "i");
155 MODULE_PARM(setup_time, "i");
156 MODULE_PARM(cmd_time, "i");
157 MODULE_PARM(recov_time, "i");
158
159 #ifdef CONFIG_PCI
160 /* Scan PCI bus? */
161 static int do_pci_probe = 1;
162 /* Default memory base address for CardBus controllers */
163 static u_int cb_mem_base[] = { 0x68000000, 0xf8000000 };
164 static int fast_pci = -1;
165 static int hold_time = -1;
166 /* Override BIOS interrupt routing mode? */
167 static int irq_mode = -1;
168 static int has_clkrun = -1;
169 static int clkrun_sel = -1;
170 static int pci_latency = -1;
171 static int cb_latency = -1;
172 static int cb_bus_base = 0;
173 static int cb_bus_step = 2;
174 static int cb_write_post = -1;
175 MODULE_PARM(do_pci_probe, "i");
176 MODULE_PARM(cb_mem_base, "i");
177 MODULE_PARM(fast_pci, "i");
178 MODULE_PARM(hold_time, "i");
179 MODULE_PARM(irq_mode, "i");
180 MODULE_PARM(has_clkrun, "i");
181 MODULE_PARM(clkrun_sel, "i");
182 MODULE_PARM(pci_latency, "i");
183 MODULE_PARM(cb_latency, "i");
184 MODULE_PARM(cb_bus_base, "i");
185 MODULE_PARM(cb_bus_step, "i");
186 MODULE_PARM(cb_write_post, "i");
187 #endif
188
189 #ifdef CONFIG_ISA
190 #ifdef CONFIG_PCI
191 /* PCI card status change interrupts? */
192 static int pci_csc = 0;
193 /* PCI IO card functional interrupts? */
194 static int pci_int = 0;
195 MODULE_PARM(pci_csc, "i");
196 MODULE_PARM(pci_int, "i");
197 #else /* no PCI */
198 #define pci_csc 0
199 #define pci_int 0
200 #endif
201 #else /* no ISA */
202 #ifdef CONFIG_PCI
203 #define pci_csc 0
204 #define pci_int 1
205 #else
206 #error "No bus architectures defined!"
207 #endif
208 #endif
209
210 /*====================================================================*/
211
212 typedef struct cirrus_state_t {
213 u_char misc1, misc2;
214 u_char timer[6];
215 } cirrus_state_t;
216
217 typedef struct vg46x_state_t {
218 u_char ctl, ema;
219 } vg46x_state_t;
220
221 typedef struct ti113x_state_t {
222 u_int sysctl;
223 u_char cardctl, devctl, diag;
224 } ti113x_state_t;
225
226 typedef struct rl5c4xx_state_t {
227 u_short misc, ctl, io, mem;
228 } rl5c4xx_state_t;
229
230 typedef struct o2micro_state_t {
231 u_char mode_a, mode_b, mode_c, mode_d;
232 u_char mhpg, fifo, mode_e;
233 } o2micro_state_t;
234
235 typedef struct topic_state_t {
236 u_char slot, ccr, cdr;
237 u_int rcr;
238 } topic_state_t;
239
240 typedef struct socket_info_t {
241 u_short type, flags;
242 socket_cap_t cap;
243 ioaddr_t ioaddr;
244 u_short psock;
245 u_char cs_irq, intr;
246 void (*handler)(void *info, u_int events);
247 void *info;
248 #ifdef CONFIG_PROC_FS
249 struct proc_dir_entry *proc;
250 #endif
251 #ifdef CONFIG_PCI
252 u_short vendor, device;
253 u_char revision, bus, devfn;
254 u_short bcr;
255 u_char pci_lat, cb_lat, sub_bus;
256 u_char cache, pmcs;
257 u_int cb_phys;
258 char *cb_virt;
259 #endif
260 union {
261 cirrus_state_t cirrus;
262 vg46x_state_t vg46x;
263 #ifdef CONFIG_PCI
264 o2micro_state_t o2micro;
265 ti113x_state_t ti113x;
266 rl5c4xx_state_t rl5c4xx;
267 topic_state_t topic;
268 #endif
269 } state;
270 } socket_info_t;
271
272 /* Where we keep track of our sockets... */
273 static int sockets = 0;
274 static socket_info_t socket[8] = {
275 { 0, }, /* ... */
276 };
277
278 /* Default ISA interrupt mask */
279 #define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */
280
281 #ifdef CONFIG_ISA
282 static int grab_irq;
283 static spinlock_t isa_lock = SPIN_LOCK_UNLOCKED;
284 #define ISA_LOCK(n, f) \
285 if (!(socket[n].flags & IS_CARDBUS)) spin_lock_irqsave(&isa_lock, f)
286 #define ISA_UNLOCK(n, f) \
287 if (!(socket[n].flags & IS_CARDBUS)) spin_unlock_irqrestore(&isa_lock, f)
288 #else
289 #define ISA_LOCK(n, f) do { } while (0)
290 #define ISA_UNLOCK(n, f) do { } while (0)
291 #endif
292
293 static struct timer_list poll_timer;
294
295 /*====================================================================*/
296
297 #ifdef CONFIG_PCI
298
299 #ifndef PCI_VENDOR_ID_INTEL
300 #define PCI_VENDOR_ID_INTEL 0x8086
301 #endif
302 #ifndef PCI_VENDOR_ID_OMEGA
303 #define PCI_VENDOR_ID_OMEGA 0x119b
304 #endif
305 #ifndef PCI_DEVICE_ID_OMEGA_PCMCIA
306 #define PCI_DEVICE_ID_OMEGA_PCMCIA 0x1221
307 #endif
308
309 /* Default settings for PCI command configuration register */
310 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
311 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
312
313 #endif
314
315 /* These definitions must match the pcic table! */
316 typedef enum pcic_id {
317 #ifdef CONFIG_ISA
318 IS_I82365A, IS_I82365B, IS_I82365DF,
319 IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469,
320 IS_PD6710, IS_PD672X, IS_VT83C469,
321 #endif
322 #ifdef CONFIG_PCI
323 IS_PD6729, IS_PD6730, IS_OZ6729, IS_OZ6730,
324 IS_I82092AA, IS_OM82C092G,
325 IS_PD6832, IS_OZ6832, IS_OZ6836, IS_OZ6812,
326 IS_RL5C465, IS_RL5C466, IS_RL5C475, IS_RL5C476, IS_RL5C478,
327 IS_SMC34C90,
328 IS_TI1130, IS_TI1131, IS_TI1250A, IS_TI1220, IS_TI1221, IS_TI1210,
329 IS_TI1251A, IS_TI1251B, IS_TI1450, IS_TI1225, IS_TI1211, IS_TI1420,
330 IS_TOPIC95_A, IS_TOPIC95_B, IS_TOPIC97,
331 IS_UNK_PCI, IS_UNK_CARDBUS
332 #endif
333 } pcic_id;
334
335 /* Flags for classifying groups of controllers */
336 #define IS_VADEM 0x0001
337 #define IS_CIRRUS 0x0002
338 #define IS_TI 0x0004
339 #define IS_O2MICRO 0x0008
340 #define IS_VIA 0x0010
341 #define IS_TOPIC 0x0020
342 #define IS_RICOH 0x0040
343 #define IS_UNKNOWN 0x0400
344 #define IS_VG_PWR 0x0800
345 #define IS_DF_PWR 0x1000
346 #define IS_PCI 0x2000
347 #define IS_CARDBUS 0x4000
348 #define IS_ALIVE 0x8000
349
350 typedef struct pcic_t {
351 char *name;
352 u_short flags;
353 #ifdef CONFIG_PCI
354 u_short vendor, device;
355 #endif
356 } pcic_t;
357
358 static pcic_t pcic[] = {
359 #ifdef CONFIG_ISA
360 { "Intel i82365sl A step", 0 },
361 { "Intel i82365sl B step", 0 },
362 { "Intel i82365sl DF", IS_DF_PWR },
363 { "IBM Clone", 0 },
364 { "Ricoh RF5C296/396", 0 },
365 { "VLSI 82C146", 0 },
366 { "Vadem VG-468", IS_VADEM },
367 { "Vadem VG-469", IS_VADEM|IS_VG_PWR },
368 { "Cirrus PD6710", IS_CIRRUS },
369 { "Cirrus PD672x", IS_CIRRUS },
370 { "VIA VT83C469", IS_CIRRUS|IS_VIA },
371 #endif
372 #ifdef CONFIG_PCI
373 { "Cirrus PD6729", IS_CIRRUS|IS_PCI,
374 PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6729 },
375 { "Cirrus PD6730", IS_CIRRUS|IS_PCI,
376 PCI_VENDOR_ID_CIRRUS, 0xffff },
377 { "O2Micro OZ6729", IS_O2MICRO|IS_PCI|IS_VG_PWR,
378 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6729 },
379 { "O2Micro OZ6730", IS_O2MICRO|IS_PCI|IS_VG_PWR,
380 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6730 },
381 { "Intel 82092AA", IS_PCI,
382 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_OMEGA_PCMCIA },
383 { "Omega Micro 82C092G", IS_PCI,
384 PCI_VENDOR_ID_OMEGA, PCI_DEVICE_ID_OMEGA_PCMCIA },
385 { "Cirrus PD6832", IS_CIRRUS|IS_CARDBUS,
386 PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_6832 },
387 { "O2Micro OZ6832/OZ6833", IS_O2MICRO|IS_CARDBUS|IS_VG_PWR,
388 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6832 },
389 { "O2Micro OZ6836/OZ6860", IS_O2MICRO|IS_CARDBUS|IS_VG_PWR,
390 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6836 },
391 { "O2Micro OZ6812", IS_O2MICRO|IS_CARDBUS|IS_VG_PWR,
392 PCI_VENDOR_ID_O2, PCI_DEVICE_ID_O2_6812 },
393 { "Ricoh RL5C465", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
394 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C465 },
395 { "Ricoh RL5C466", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
396 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C466 },
397 { "Ricoh RL5C475", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
398 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C475 },
399 { "Ricoh RL5C476", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
400 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476 },
401 { "Ricoh RL5C478", IS_RICOH|IS_CARDBUS|IS_DF_PWR,
402 PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C478 },
403 { "SMC 34C90", IS_CARDBUS|IS_DF_PWR,
404 PCI_VENDOR_ID_SMC, PCI_DEVICE_ID_SMC_34C90 },
405 { "TI 1130", IS_TI|IS_CARDBUS|IS_DF_PWR,
406 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1130 },
407 { "TI 1131", IS_TI|IS_CARDBUS|IS_DF_PWR,
408 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1131 },
409 { "TI 1250A", IS_TI|IS_CARDBUS|IS_DF_PWR,
410 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1250A },
411 { "TI 1220", IS_TI|IS_CARDBUS|IS_DF_PWR,
412 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1220 },
413 { "TI 1221", IS_TI|IS_CARDBUS|IS_DF_PWR,
414 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1221 },
415 { "TI 1210", IS_TI|IS_CARDBUS|IS_DF_PWR,
416 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1210 },
417 { "TI 1251A", IS_TI|IS_CARDBUS|IS_DF_PWR,
418 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251A },
419 { "TI 1251B", IS_TI|IS_CARDBUS|IS_DF_PWR,
420 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1251B },
421 { "TI 1450", IS_TI|IS_CARDBUS|IS_DF_PWR,
422 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1450 },
423 { "TI 1225", IS_TI|IS_CARDBUS|IS_DF_PWR,
424 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1225 },
425 { "TI 1211", IS_TI|IS_CARDBUS|IS_DF_PWR,
426 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1211 },
427 { "TI 1420", IS_TI|IS_CARDBUS|IS_DF_PWR,
428 PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420 },
429 { "Toshiba ToPIC95-A", IS_CARDBUS|IS_TOPIC|IS_DF_PWR,
430 PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC95_A },
431 { "Toshiba ToPIC95-B", IS_CARDBUS|IS_TOPIC|IS_DF_PWR,
432 PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC95_B },
433 { "Toshiba ToPIC97", IS_CARDBUS|IS_TOPIC|IS_DF_PWR,
434 PCI_VENDOR_ID_TOSHIBA, PCI_DEVICE_ID_TOSHIBA_TOPIC97 },
435 { "Unknown", IS_PCI|IS_UNKNOWN, 0, 0 },
436 { "Unknown", IS_CARDBUS|IS_DF_PWR|IS_UNKNOWN, 0, 0 }
437 #endif
438 };
439
440 #define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t))
441
442 /*====================================================================*/
443
444 /* Some PCI shortcuts */
445
446 #define pci_readb pcibios_read_config_byte
447 #define pci_writeb pcibios_write_config_byte
448 #define pci_readw pcibios_read_config_word
449 #define pci_writew pcibios_write_config_word
450 #define pci_readl pcibios_read_config_dword
451 #define pci_writel pcibios_write_config_dword
452
453 #define cb_readb(s, r) readb(socket[s].cb_virt + (r))
454 #define cb_readl(s, r) readl(socket[s].cb_virt + (r))
455 #define cb_writeb(s, r, v) writeb(v, socket[s].cb_virt + (r))
456 #define cb_writel(s, r, v) writel(v, socket[s].cb_virt + (r))
457
458 static void cb_get_power(u_short sock, socket_state_t *state);
459 static void cb_set_power(u_short sock, socket_state_t *state);
460
461 /*====================================================================*/
462
463 static u_char i365_get(u_short sock, u_short reg)
464 {
465 #ifdef CONFIG_PCI
466 if (socket[sock].cb_virt)
467 return cb_readb(sock, 0x0800 + reg);
468 else
469 #endif
470 {
471 ioaddr_t port = socket[sock].ioaddr;
472 u_char val;
473 reg = I365_REG(socket[sock].psock, reg);
474 outb(reg, port); val = inb(port+1);
475 return val;
476 }
477 }
478
479 static void i365_set(u_short sock, u_short reg, u_char data)
480 {
481 #ifdef CONFIG_PCI
482 if (socket[sock].cb_virt)
483 cb_writeb(sock, 0x0800 + reg, data);
484 else
485 #endif
486 {
487 ioaddr_t port = socket[sock].ioaddr;
488 u_char val = I365_REG(socket[sock].psock, reg);
489 outb(val, port); outb(data, port+1);
490 }
491 }
492
493 static void i365_bset(u_short sock, u_short reg, u_char mask)
494 {
495 u_char d = i365_get(sock, reg);
496 d |= mask;
497 i365_set(sock, reg, d);
498 }
499
500 static void i365_bclr(u_short sock, u_short reg, u_char mask)
501 {
502 u_char d = i365_get(sock, reg);
503 d &= ~mask;
504 i365_set(sock, reg, d);
505 }
506
507 static void i365_bflip(u_short sock, u_short reg, u_char mask, int b)
508 {
509 u_char d = i365_get(sock, reg);
510 if (b)
511 d |= mask;
512 else
513 d &= ~mask;
514 i365_set(sock, reg, d);
515 }
516
517 static u_short i365_get_pair(u_short sock, u_short reg)
518 {
519 u_short a, b;
520 a = i365_get(sock, reg);
521 b = i365_get(sock, reg+1);
522 return (a + (b<<8));
523 }
524
525 static void i365_set_pair(u_short sock, u_short reg, u_short data)
526 {
527 i365_set(sock, reg, data & 0xff);
528 i365_set(sock, reg+1, data >> 8);
529 }
530
531 /*======================================================================
532
533 Code to save and restore global state information for Cirrus
534 PD67xx controllers, and to set and report global configuration
535 options.
536
537 The VIA controllers also use these routines, as they are mostly
538 Cirrus lookalikes, without the timing registers.
539
540 ======================================================================*/
541
542 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
543
544 static void cirrus_get_state(u_short s)
545 {
546 int i;
547 cirrus_state_t *p = &socket[s].state.cirrus;
548 p->misc1 = i365_get(s, PD67_MISC_CTL_1);
549 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
550 p->misc2 = i365_get(s, PD67_MISC_CTL_2);
551 for (i = 0; i < 6; i++)
552 p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i);
553 }
554
555 static void cirrus_set_state(u_short s)
556 {
557 int i;
558 u_char misc;
559 cirrus_state_t *p = &socket[s].state.cirrus;
560
561 misc = i365_get(s, PD67_MISC_CTL_2);
562 i365_set(s, PD67_MISC_CTL_2, p->misc2);
563 if (misc & PD67_MC2_SUSPEND) mdelay(50);
564 misc = i365_get(s, PD67_MISC_CTL_1);
565 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
566 i365_set(s, PD67_MISC_CTL_1, misc | p->misc1);
567 for (i = 0; i < 6; i++)
568 i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]);
569 }
570
571 #ifdef CONFIG_PCI
572 static int cirrus_set_irq_mode(u_short s, int pcsc, int pint)
573 {
574 flip(socket[s].bcr, PD6832_BCR_MGMT_IRQ_ENA, !pcsc);
575 return 0;
576 }
577 #endif /* CONFIG_PCI */
578
579 static u_int __init cirrus_set_opts(u_short s, char *buf)
580 {
581 socket_info_t *t = &socket[s];
582 cirrus_state_t *p = &socket[s].state.cirrus;
583 u_int mask = 0xffff;
584
585 if (has_ring == -1) has_ring = 1;
586 flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring);
587 flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
588 if (p->misc2 & PD67_MC2_IRQ15_RI)
589 strcat(buf, " [ring]");
590 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
591 strcat(buf, " [dyn mode]");
592 if (p->misc1 & PD67_MC1_INPACK_ENA)
593 strcat(buf, " [inpack]");
594 if (!(t->flags & (IS_PCI | IS_CARDBUS))) {
595 if (p->misc2 & PD67_MC2_IRQ15_RI)
596 mask &= ~0x8000;
597 if (has_led > 0) {
598 strcat(buf, " [led]");
599 mask &= ~0x1000;
600 }
601 if (has_dma > 0) {
602 strcat(buf, " [dma]");
603 mask &= ~0x0600;
604 flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
605 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
606 strcat(buf, " [freq bypass]");
607 }
608 #ifdef CONFIG_PCI
609 } else {
610 p->misc1 &= ~PD67_MC1_MEDIA_ENA;
611 flip(p->misc2, PD67_MC2_FAST_PCI, fast_pci);
612 if (p->misc2 & PD67_MC2_IRQ15_RI)
613 mask &= (socket[s].type == IS_PD6730) ? ~0x0400 : ~0x8000;
614 #endif
615 }
616 if (!(t->flags & IS_VIA)) {
617 if (setup_time >= 0)
618 p->timer[0] = p->timer[3] = setup_time;
619 if (cmd_time > 0) {
620 p->timer[1] = cmd_time;
621 p->timer[4] = cmd_time*2+4;
622 }
623 if (p->timer[1] == 0) {
624 p->timer[1] = 6; p->timer[4] = 16;
625 if (p->timer[0] == 0)
626 p->timer[0] = p->timer[3] = 1;
627 }
628 if (recov_time >= 0)
629 p->timer[2] = p->timer[5] = recov_time;
630 buf += strlen(buf);
631 sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1],
632 p->timer[2], p->timer[3], p->timer[4], p->timer[5]);
633 }
634 return mask;
635 }
636
637 /*======================================================================
638
639 Code to save and restore global state information for Vadem VG468
640 and VG469 controllers, and to set and report global configuration
641 options.
642
643 ======================================================================*/
644
645 #ifdef CONFIG_ISA
646
647 static void vg46x_get_state(u_short s)
648 {
649 vg46x_state_t *p = &socket[s].state.vg46x;
650 p->ctl = i365_get(s, VG468_CTL);
651 if (socket[s].type == IS_VG469)
652 p->ema = i365_get(s, VG469_EXT_MODE);
653 }
654
655 static void vg46x_set_state(u_short s)
656 {
657 vg46x_state_t *p = &socket[s].state.vg46x;
658 i365_set(s, VG468_CTL, p->ctl);
659 if (socket[s].type == IS_VG469)
660 i365_set(s, VG469_EXT_MODE, p->ema);
661 }
662
663 static u_int __init vg46x_set_opts(u_short s, char *buf)
664 {
665 vg46x_state_t *p = &socket[s].state.vg46x;
666
667 flip(p->ctl, VG468_CTL_ASYNC, async_clock);
668 flip(p->ema, VG469_MODE_CABLE, cable_mode);
669 if (p->ctl & VG468_CTL_ASYNC)
670 strcat(buf, " [async]");
671 if (p->ctl & VG468_CTL_INPACK)
672 strcat(buf, " [inpack]");
673 if (socket[s].type == IS_VG469) {
674 u_char vsel = i365_get(s, VG469_VSELECT);
675 if (vsel & VG469_VSEL_EXT_STAT) {
676 strcat(buf, " [ext mode]");
677 if (vsel & VG469_VSEL_EXT_BUS)
678 strcat(buf, " [isa buf]");
679 }
680 if (p->ema & VG469_MODE_CABLE)
681 strcat(buf, " [cable]");
682 if (p->ema & VG469_MODE_COMPAT)
683 strcat(buf, " [c step]");
684 }
685 return 0xffff;
686 }
687
688 #endif
689
690 /*======================================================================
691
692 Code to save and restore global state information for TI 1130 and
693 TI 1131 controllers, and to set and report global configuration
694 options.
695
696 ======================================================================*/
697
698 #ifdef CONFIG_PCI
699
700 static void ti113x_get_state(u_short s)
701 {
702 socket_info_t *t = &socket[s];
703 ti113x_state_t *p = &socket[s].state.ti113x;
704 pci_readl(t->bus, t->devfn, TI113X_SYSTEM_CONTROL, &p->sysctl);
705 pci_readb(t->bus, t->devfn, TI113X_CARD_CONTROL, &p->cardctl);
706 pci_readb(t->bus, t->devfn, TI113X_DEVICE_CONTROL, &p->devctl);
707 pci_readb(t->bus, t->devfn, TI1250_DIAGNOSTIC, &p->diag);
708 }
709
710 static void ti113x_set_state(u_short s)
711 {
712 socket_info_t *t = &socket[s];
713 ti113x_state_t *p = &socket[s].state.ti113x;
714 pci_writel(t->bus, t->devfn, TI113X_SYSTEM_CONTROL, p->sysctl);
715 pci_writeb(t->bus, t->devfn, TI113X_CARD_CONTROL, p->cardctl);
716 pci_writeb(t->bus, t->devfn, TI113X_DEVICE_CONTROL, p->devctl);
717 pci_writeb(t->bus, t->devfn, TI1250_MULTIMEDIA_CTL, 0);
718 pci_writeb(t->bus, t->devfn, TI1250_DIAGNOSTIC, p->diag);
719 i365_set_pair(s, TI113X_IO_OFFSET(0), 0);
720 i365_set_pair(s, TI113X_IO_OFFSET(1), 0);
721 }
722
723 static int ti113x_set_irq_mode(u_short s, int pcsc, int pint)
724 {
725 socket_info_t *t = &socket[s];
726 ti113x_state_t *p = &t->state.ti113x;
727 t->intr = (pcsc) ? I365_INTR_ENA : 0;
728 if (t->type <= IS_TI1131) {
729 p->cardctl &= ~(TI113X_CCR_PCI_IRQ_ENA |
730 TI113X_CCR_PCI_IREQ | TI113X_CCR_PCI_CSC);
731 if (pcsc)
732 p->cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_CSC;
733 if (pint)
734 p->cardctl |= TI113X_CCR_PCI_IRQ_ENA | TI113X_CCR_PCI_IREQ;
735 } else if (t->type == IS_TI1250A) {
736 p->diag &= TI1250_DIAG_PCI_CSC | TI1250_DIAG_PCI_IREQ;
737 if (pcsc)
738 p->diag |= TI1250_DIAG_PCI_CSC;
739 if (pint)
740 p->diag |= TI1250_DIAG_PCI_IREQ;
741 }
742 return 0;
743 }
744
745 static u_int __init ti113x_set_opts(u_short s, char *buf)
746 {
747 socket_info_t *t = &socket[s];
748 ti113x_state_t *p = &t->state.ti113x;
749 u_int mask = 0xffff;
750 int old = (t->type <= IS_TI1131);
751
752 flip(p->sysctl, TI113X_SCR_CLKRUN_ENA, has_clkrun);
753 flip(p->sysctl, TI113X_SCR_CLKRUN_SEL, clkrun_sel);
754 flip(p->cardctl, TI113X_CCR_RIENB, has_ring);
755 p->cardctl &= ~TI113X_CCR_ZVENABLE;
756 switch (irq_mode) {
757 case 1:
758 p->devctl &= ~TI113X_DCR_IMODE_MASK;
759 p->devctl |= TI113X_DCR_IMODE_ISA;
760 break;
761 case 2:
762 p->devctl &= ~TI113X_DCR_IMODE_MASK;
763 p->devctl |= TI113X_DCR_IMODE_SERIAL;
764 break;
765 case 3:
766 p->devctl &= ~TI113X_DCR_IMODE_MASK;
767 p->devctl |= TI12XX_DCR_IMODE_ALL_SERIAL;
768 break;
769 default:
770 if ((p->devctl & TI113X_DCR_IMODE_MASK) == 0)
771 p->devctl |= TI113X_DCR_IMODE_ISA;
772 }
773 if (p->cardctl & TI113X_CCR_RIENB) {
774 strcat(buf, " [ring]");
775 if (old) mask &= ~0x8000;
776 }
777 if (old && (p->sysctl & TI113X_SCR_CLKRUN_ENA)) {
778 if (p->sysctl & TI113X_SCR_CLKRUN_SEL) {
779 strcat(buf, " [clkrun irq 12]");
780 mask &= ~0x1000;
781 } else {
782 strcat(buf, " [clkrun irq 10]");
783 mask &= ~0x0400;
784 }
785 }
786 if (p->sysctl & TI113X_SCR_PWRSAVINGS)
787 strcat(buf, " [pwr save]");
788 switch (p->devctl & TI113X_DCR_IMODE_MASK) {
789 case TI12XX_DCR_IMODE_PCI_ONLY:
790 strcat(buf, " [pci only]");
791 mask = 0;
792 break;
793 case TI113X_DCR_IMODE_ISA:
794 strcat(buf, " [isa irq]");
795 if (old) mask &= ~0x0018;
796 break;
797 case TI113X_DCR_IMODE_SERIAL:
798 strcat(buf, " [pci + serial irq]");
799 mask = 0xffff;
800 break;
801 case TI12XX_DCR_IMODE_ALL_SERIAL:
802 strcat(buf, " [serial pci & irq]");
803 mask = 0xffff;
804 break;
805 }
806 return mask;
807 }
808
809 #endif
810
811 /*======================================================================
812
813 Code to save and restore global state information for the Ricoh
814 RL5C4XX controllers, and to set and report global configuration
815 options.
816
817 ======================================================================*/
818
819 #ifdef CONFIG_PCI
820
821 static void rl5c4xx_get_state(u_short s)
822 {
823 socket_info_t *t = &socket[s];
824 rl5c4xx_state_t *p = &socket[s].state.rl5c4xx;
825 pci_readw(t->bus, t->devfn, RL5C4XX_MISC, &p->misc);
826 pci_readw(t->bus, t->devfn, RL5C4XX_16BIT_CTL, &p->ctl);
827 pci_readw(t->bus, t->devfn, RL5C4XX_16BIT_IO_0, &p->io);
828 pci_readw(t->bus, t->devfn, RL5C4XX_16BIT_MEM_0, &p->mem);
829 }
830
831 static void rl5c4xx_set_state(u_short s)
832 {
833 socket_info_t *t = &socket[s];
834 rl5c4xx_state_t *p = &socket[s].state.rl5c4xx;
835 pci_writew(t->bus, t->devfn, RL5C4XX_MISC, p->misc);
836 pci_writew(t->bus, t->devfn, RL5C4XX_16BIT_CTL, p->ctl);
837 pci_writew(t->bus, t->devfn, RL5C4XX_16BIT_IO_0, p->io);
838 pci_writew(t->bus, t->devfn, RL5C4XX_16BIT_MEM_0, p->mem);
839 }
840
841 static u_int __init rl5c4xx_set_opts(u_short s, char *buf)
842 {
843 rl5c4xx_state_t *p = &socket[s].state.rl5c4xx;
844 u_int mask = 0xffff;
845 int old = (socket[s].type < IS_RL5C475);
846
847 p->ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
848 if (old) p->ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
849
850 if (setup_time >= 0) {
851 p->io = (p->io & ~RL5C4XX_SETUP_MASK) +
852 ((setup_time+1) << RL5C4XX_SETUP_SHIFT);
853 p->mem = (p->mem & ~RL5C4XX_SETUP_MASK) +
854 (setup_time << RL5C4XX_SETUP_SHIFT);
855 }
856 if (cmd_time >= 0) {
857 p->io = (p->io & ~RL5C4XX_CMD_MASK) +
858 (cmd_time << RL5C4XX_CMD_SHIFT);
859 p->mem = (p->mem & ~RL5C4XX_CMD_MASK) +
860 (cmd_time << RL5C4XX_CMD_SHIFT);
861 }
862 if (hold_time >= 0) {
863 p->io = (p->io & ~RL5C4XX_HOLD_MASK) +
864 (hold_time << RL5C4XX_HOLD_SHIFT);
865 p->mem = (p->mem & ~RL5C4XX_HOLD_MASK) +
866 (hold_time << RL5C4XX_HOLD_SHIFT);
867 }
868 if (!old) {
869 switch (irq_mode) {
870 case 1:
871 p->misc &= ~RL5C47X_MISC_SRIRQ_ENA; break;
872 case 2:
873 p->misc |= RL5C47X_MISC_SRIRQ_ENA; break;
874 }
875 if (p->misc & RL5C47X_MISC_SRIRQ_ENA)
876 sprintf(buf, " [serial irq]");
877 else
878 sprintf(buf, " [isa irq]");
879 buf += strlen(buf);
880 }
881 sprintf(buf, " [io %d/%d/%d] [mem %d/%d/%d]",
882 (p->io & RL5C4XX_SETUP_MASK) >> RL5C4XX_SETUP_SHIFT,
883 (p->io & RL5C4XX_CMD_MASK) >> RL5C4XX_CMD_SHIFT,
884 (p->io & RL5C4XX_HOLD_MASK) >> RL5C4XX_HOLD_SHIFT,
885 (p->mem & RL5C4XX_SETUP_MASK) >> RL5C4XX_SETUP_SHIFT,
886 (p->mem & RL5C4XX_CMD_MASK) >> RL5C4XX_CMD_SHIFT,
887 (p->mem & RL5C4XX_HOLD_MASK) >> RL5C4XX_HOLD_SHIFT);
888 return mask;
889 }
890
891 #endif
892
893 /*======================================================================
894
895 Code to save and restore global state information for O2Micro
896 controllers, and to set and report global configuration options.
897
898 ======================================================================*/
899
900 #ifdef CONFIG_PCI
901
902 static void o2micro_get_state(u_short s)
903 {
904 socket_info_t *t = &socket[s];
905 o2micro_state_t *p = &socket[s].state.o2micro;
906 if ((t->revision == 0x34) || (t->revision == 0x62) ||
907 (t->type == IS_OZ6812)) {
908 p->mode_a = i365_get(s, O2_MODE_A_2);
909 p->mode_b = i365_get(s, O2_MODE_B_2);
910 } else {
911 p->mode_a = i365_get(s, O2_MODE_A);
912 p->mode_b = i365_get(s, O2_MODE_B);
913 }
914 p->mode_c = i365_get(s, O2_MODE_C);
915 p->mode_d = i365_get(s, O2_MODE_D);
916 if (t->flags & IS_CARDBUS) {
917 p->mhpg = i365_get(s, O2_MHPG_DMA);
918 p->fifo = i365_get(s, O2_FIFO_ENA);
919 p->mode_e = i365_get(s, O2_MODE_E);
920 }
921 }
922
923 static void o2micro_set_state(u_short s)
924 {
925 socket_info_t *t = &socket[s];
926 o2micro_state_t *p = &socket[s].state.o2micro;
927 if ((t->revision == 0x34) || (t->revision == 0x62) ||
928 (t->type == IS_OZ6812)) {
929 i365_set(s, O2_MODE_A_2, p->mode_a);
930 i365_set(s, O2_MODE_B_2, p->mode_b);
931 } else {
932 i365_set(s, O2_MODE_A, p->mode_a);
933 i365_set(s, O2_MODE_B, p->mode_b);
934 }
935 i365_set(s, O2_MODE_C, p->mode_c);
936 i365_set(s, O2_MODE_D, p->mode_d);
937 if (t->flags & IS_CARDBUS) {
938 i365_set(s, O2_MHPG_DMA, p->mhpg);
939 i365_set(s, O2_FIFO_ENA, p->fifo);
940 i365_set(s, O2_MODE_E, p->mode_e);
941 }
942 }
943
944 static u_int __init o2micro_set_opts(u_short s, char *buf)
945 {
946 socket_info_t *t = &socket[s];
947 o2micro_state_t *p = &socket[s].state.o2micro;
948 u_int mask = 0xffff;
949
950 p->mode_b = (p->mode_b & ~O2_MODE_B_IDENT) | O2_MODE_B_ID_CSTEP;
951 flip(p->mode_b, O2_MODE_B_IRQ15_RI, has_ring);
952 p->mode_c &= ~(O2_MODE_C_ZVIDEO | O2_MODE_C_DREQ_MASK);
953 if (t->flags & IS_CARDBUS) {
954 p->mode_d &= ~O2_MODE_D_W97_IRQ;
955 p->mode_e &= ~O2_MODE_E_MHPG_DMA;
956 p->mhpg |= O2_MHPG_CINT_ENA | O2_MHPG_CSC_ENA;
957 p->mhpg &= ~O2_MHPG_CHANNEL;
958 if (t->revision == 0x34)
959 p->mode_c = 0x20;
960 } else {
961 if (p->mode_b & O2_MODE_B_IRQ15_RI) mask &= ~0x8000;
962 }
963 sprintf(buf, " [a %02x] [b %02x] [c %02x] [d %02x]",
964 p->mode_a, p->mode_b, p->mode_c, p->mode_d);
965 if (t->flags & IS_CARDBUS) {
966 buf += strlen(buf);
967 sprintf(buf, " [mhpg %02x] [fifo %02x] [e %02x]",
968 p->mhpg, p->fifo, p->mode_e);
969 }
970 return mask;
971 }
972
973 #endif
974
975 /*======================================================================
976
977 Code to save and restore global state information for the Toshiba
978 ToPIC 95 and 97 controllers, and to set and report global
979 configuration options.
980
981 ======================================================================*/
982
983 #ifdef CONFIG_PCI
984
985 static void topic_get_state(u_short s)
986 {
987 socket_info_t *t = &socket[s];
988 topic_state_t *p = &socket[s].state.topic;
989 pci_readb(t->bus, t->devfn, TOPIC_SLOT_CONTROL, &p->slot);
990 pci_readb(t->bus, t->devfn, TOPIC_CARD_CONTROL, &p->ccr);
991 pci_readb(t->bus, t->devfn, TOPIC_CARD_DETECT, &p->cdr);
992 pci_readl(t->bus, t->devfn, TOPIC_REGISTER_CONTROL, &p->rcr);
993 }
994
995 static void topic_set_state(u_short s)
996 {
997 socket_info_t *t = &socket[s];
998 topic_state_t *p = &socket[s].state.topic;
999 pci_writeb(t->bus, t->devfn, TOPIC_SLOT_CONTROL, p->slot);
1000 pci_writeb(t->bus, t->devfn, TOPIC_CARD_CONTROL, p->ccr);
1001 pci_writeb(t->bus, t->devfn, TOPIC_CARD_DETECT, p->cdr);
1002 pci_writel(t->bus, t->devfn, TOPIC_REGISTER_CONTROL, p->rcr);
1003 }
1004
1005 static int topic_set_irq_mode(u_short s, int pcsc, int pint)
1006 {
1007 if (socket[s].type == IS_TOPIC97) {
1008 topic_state_t *p = &socket[s].state.topic;
1009 flip(p->ccr, TOPIC97_ICR_IRQSEL, pcsc);
1010 return 0;
1011 } else {
1012 /* no ISA card status change irq */
1013 return !pcsc;
1014 }
1015 }
1016
1017 static u_int __init topic_set_opts(u_short s, char *buf)
1018 {
1019 topic_state_t *p = &socket[s].state.topic;
1020
1021 p->slot |= TOPIC_SLOT_SLOTON|TOPIC_SLOT_SLOTEN|TOPIC_SLOT_ID_LOCK;
1022 p->cdr |= TOPIC_CDR_MODE_PC32;
1023 p->cdr &= ~(TOPIC_CDR_SW_DETECT);
1024 sprintf(buf, " [slot 0x%02x] [ccr 0x%02x] [cdr 0x%02x] [rcr 0x%02x]",
1025 p->slot, p->ccr, p->cdr, p->rcr);
1026 return 0xffff;
1027 }
1028
1029 #endif
1030
1031 /*======================================================================
1032
1033 Routines to handle common CardBus options
1034
1035 ======================================================================*/
1036
1037 #ifdef CONFIG_PCI
1038
1039 static void cb_get_state(u_short s)
1040 {
1041 socket_info_t *t = &socket[s];
1042
1043 pci_readb(t->bus, t->devfn, PCI_CACHE_LINE_SIZE, &t->cache);
1044 pci_readb(t->bus, t->devfn, PCI_LATENCY_TIMER, &t->pci_lat);
1045 pci_readb(t->bus, t->devfn, CB_LATENCY_TIMER, &t->cb_lat);
1046 pci_readb(t->bus, t->devfn, CB_CARDBUS_BUS, &t->cap.cardbus);
1047 pci_readb(t->bus, t->devfn, CB_SUBORD_BUS, &t->sub_bus);
1048 pci_readw(t->bus, t->devfn, CB_BRIDGE_CONTROL, &t->bcr);
1049 {
1050 struct pci_dev *pdev = pci_find_slot(t->bus, t->devfn);
1051 t->cap.pci_irq = (pdev) ? pdev->irq : 0;
1052 }
1053 if (t->cap.pci_irq >= NR_IRQS) t->cap.pci_irq = 0;
1054 }
1055
1056 static void cb_set_state(u_short s)
1057 {
1058 socket_info_t *t = &socket[s];
1059 if (t->pmcs)
1060 pci_writew(t->bus, t->devfn, t->pmcs, PCI_PMCS_PWR_STATE_D0);
1061 pci_writel(t->bus, t->devfn, CB_LEGACY_MODE_BASE, 0);
1062 pci_writel(t->bus, t->devfn, PCI_BASE_ADDRESS_0, t->cb_phys);
1063 pci_writew(t->bus, t->devfn, PCI_COMMAND, CMD_DFLT);
1064 pci_writeb(t->bus, t->devfn, PCI_CACHE_LINE_SIZE, t->cache);
1065 pci_writeb(t->bus, t->devfn, PCI_LATENCY_TIMER, t->pci_lat);
1066 pci_writeb(t->bus, t->devfn, CB_LATENCY_TIMER, t->cb_lat);
1067 pci_writeb(t->bus, t->devfn, CB_CARDBUS_BUS, t->cap.cardbus);
1068 pci_writeb(t->bus, t->devfn, CB_SUBORD_BUS, t->sub_bus);
1069 pci_writew(t->bus, t->devfn, CB_BRIDGE_CONTROL, t->bcr);
1070 }
1071
1072 static int cb_get_irq_mode(u_short s)
1073 {
1074 return (!(socket[s].bcr & CB_BCR_ISA_IRQ));
1075 }
1076
1077 static int cb_set_irq_mode(u_short s, int pcsc, int pint)
1078 {
1079 socket_info_t *t = &socket[s];
1080 flip(t->bcr, CB_BCR_ISA_IRQ, !(pint));
1081 if (t->flags & IS_CIRRUS)
1082 return cirrus_set_irq_mode(s, pcsc, pint);
1083 else if (t->flags & IS_TI)
1084 return ti113x_set_irq_mode(s, pcsc, pint);
1085 else if (t->flags & IS_TOPIC)
1086 return topic_set_irq_mode(s, pcsc, pint);
1087 return 0;
1088 }
1089
1090 static void __init pci_scan(u_short sock);
1091
1092 static void __init cb_set_opts(u_short s, char *buf)
1093 {
1094 socket_info_t *t = &socket[s];
1095 t->bcr |= CB_BCR_WRITE_POST;
1096 /* some TI1130's seem to exhibit problems with write posting */
1097 if (((t->type == IS_TI1130) && (t->revision == 4) &&
1098 (cb_write_post < 0)) || (cb_write_post == 0))
1099 t->bcr &= ~CB_BCR_WRITE_POST;
1100 if (t->cache == 0) t->cache = 8;
1101 if (pci_latency >= 0) t->pci_lat = pci_latency;
1102 if (t->pci_lat == 0) t->pci_lat = 0xa8;
1103 if (cb_latency >= 0) t->cb_lat = cb_latency;
1104 if (t->cb_lat == 0) t->cb_lat = 0xb0;
1105 if ((t->cap.pci_irq == 0) && (pci_csc || pci_int) && do_scan)
1106 pci_scan(s);
1107 if (t->cap.pci_irq == 0)
1108 strcat(buf, " [no pci irq]");
1109 else
1110 sprintf(buf, " [pci irq %d]", t->cap.pci_irq);
1111 buf += strlen(buf);
1112 if ((cb_bus_base > 0) || (t->cap.cardbus == 0)) {
1113 if (cb_bus_base <= 0) cb_bus_base = 0x20;
1114 t->cap.cardbus = cb_bus_base;
1115 t->sub_bus = cb_bus_base+cb_bus_step;
1116 cb_bus_base += cb_bus_step+1;
1117 }
1118 if (!(t->flags & IS_TOPIC))
1119 t->cap.features |= SS_CAP_PAGE_REGS;
1120 sprintf(buf, " [lat %d/%d] [bus %d/%d]",
1121 t->pci_lat, t->cb_lat, t->cap.cardbus, t->sub_bus);
1122 }
1123
1124 #endif
1125
1126 /*======================================================================
1127
1128 Generic routines to get and set controller options
1129
1130 ======================================================================*/
1131
1132 static void get_bridge_state(u_short s)
1133 {
1134 socket_info_t *t = &socket[s];
1135 if (t->flags & IS_CIRRUS)
1136 cirrus_get_state(s);
1137 #ifdef CONFIG_ISA
1138 else if (t->flags & IS_VADEM)
1139 vg46x_get_state(s);
1140 #endif
1141 #ifdef CONFIG_PCI
1142 else if (t->flags & IS_O2MICRO)
1143 o2micro_get_state(s);
1144 else if (t->flags & IS_TI)
1145 ti113x_get_state(s);
1146 else if (t->flags & IS_RICOH)
1147 rl5c4xx_get_state(s);
1148 else if (t->flags & IS_TOPIC)
1149 topic_get_state(s);
1150 if (t->flags & IS_CARDBUS)
1151 cb_get_state(s);
1152 #endif
1153 }
1154
1155 static void set_bridge_state(u_short s)
1156 {
1157 socket_info_t *t = &socket[s];
1158 #ifdef CONFIG_PCI
1159 if (t->flags & IS_CARDBUS)
1160 cb_set_state(s);
1161 #endif
1162 if (t->flags & IS_CIRRUS)
1163 cirrus_set_state(s);
1164 else {
1165 i365_set(s, I365_GBLCTL, 0x00);
1166 i365_set(s, I365_GENCTL, 0x00);
1167 }
1168 i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr);
1169 #ifdef CONFIG_ISA
1170 if (t->flags & IS_VADEM)
1171 vg46x_set_state(s);
1172 #endif
1173 #ifdef CONFIG_PCI
1174 if (t->flags & IS_O2MICRO)
1175 o2micro_set_state(s);
1176 else if (t->flags & IS_TI)
1177 ti113x_set_state(s);
1178 else if (t->flags & IS_RICOH)
1179 rl5c4xx_set_state(s);
1180 else if (t->flags & IS_TOPIC)
1181 topic_set_state(s);
1182 #endif
1183 }
1184
1185 static u_int __init set_bridge_opts(u_short s, u_short ns)
1186 {
1187 u_short i;
1188 u_int m = 0xffff;
1189 char buf[128];
1190
1191 for (i = s; i < s+ns; i++) {
1192 if (socket[i].flags & IS_ALIVE) {
1193 printk(KERN_INFO " host opts [%d]: already alive!\n", i);
1194 continue;
1195 }
1196 buf[0] = '\0';
1197 get_bridge_state(i);
1198 if (socket[i].flags & IS_CIRRUS)
1199 m = cirrus_set_opts(i, buf);
1200 #ifdef CONFIG_ISA
1201 else if (socket[i].flags & IS_VADEM)
1202 m = vg46x_set_opts(i, buf);
1203 #endif
1204 #ifdef CONFIG_PCI
1205 else if (socket[i].flags & IS_O2MICRO)
1206 m = o2micro_set_opts(i, buf);
1207 else if (socket[i].flags & IS_TI)
1208 m = ti113x_set_opts(i, buf);
1209 else if (socket[i].flags & IS_RICOH)
1210 m = rl5c4xx_set_opts(i, buf);
1211 else if (socket[i].flags & IS_TOPIC)
1212 m = topic_set_opts(i, buf);
1213 if (socket[i].flags & IS_CARDBUS)
1214 cb_set_opts(i, buf+strlen(buf));
1215 #endif
1216 set_bridge_state(i);
1217 printk(KERN_INFO " host opts [%d]:%s\n", i,
1218 (*buf) ? buf : " none");
1219 }
1220 #ifdef CONFIG_PCI
1221 /* Mask out all PCI interrupts */
1222 for (i = 0; i < sockets; i++)
1223 m &= ~(1<<socket[i].cap.pci_irq);
1224 {
1225 struct pci_dev *p;
1226 for (p = pci_devices; p; p = p->next)
1227 m &= ~(1<<p->irq);
1228 }
1229 #endif
1230 return m;
1231 }
1232
1233 /*======================================================================
1234
1235 Interrupt testing code, for ISA and PCI interrupts
1236
1237 ======================================================================*/
1238
1239 static volatile u_int irq_hits;
1240 static u_short irq_sock;
1241
1242 static void irq_count(int irq, void *dev, struct pt_regs *regs)
1243 {
1244 #ifdef CONFIG_PCI
1245 if (socket[irq_sock].flags & IS_CARDBUS) {
1246 cb_writel(irq_sock, CB_SOCKET_EVENT, -1);
1247 } else
1248 #endif
1249 i365_get(irq_sock, I365_CSC);
1250 irq_hits++;
1251 DEBUG(2, "-> hit on irq %d\n", irq);
1252 }
1253
1254 static u_int __init test_irq(u_short sock, int irq, int pci)
1255 {
1256 u_char csc = (pci) ? 0 : irq;
1257 DEBUG(2, " testing %s irq %d\n", pci ? "PCI" : "ISA", irq);
1258
1259 if (request_irq(irq, irq_count, (pci?SA_SHIRQ:0), "scan", NULL) != 0)
1260 return 1;
1261 irq_hits = 0; irq_sock = sock;
1262 __set_current_state(TASK_UNINTERRUPTIBLE);
1263 schedule_timeout(HZ/100);
1264 if (irq_hits) {
1265 free_irq(irq, NULL);
1266 DEBUG(2, " spurious hit!\n");
1267 return 1;
1268 }
1269
1270 /* Generate one interrupt */
1271 #ifdef CONFIG_PCI
1272 if (socket[sock].flags & IS_CARDBUS) {
1273 cb_writel(sock, CB_SOCKET_EVENT, -1);
1274 i365_set(sock, I365_CSCINT, I365_CSC_STSCHG | (csc << 4));
1275 cb_writel(sock, CB_SOCKET_EVENT, -1);
1276 cb_writel(sock, CB_SOCKET_MASK, CB_SM_CSTSCHG);
1277 cb_writel(sock, CB_SOCKET_FORCE, CB_SE_CSTSCHG);
1278 udelay(1000);
1279 cb_writel(sock, CB_SOCKET_EVENT, -1);
1280 cb_writel(sock, CB_SOCKET_MASK, 0);
1281 } else
1282 #endif
1283 {
1284 i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (csc << 4));
1285 i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ);
1286 udelay(1000);
1287 }
1288
1289 free_irq(irq, NULL);
1290
1291 /* mask all interrupts */
1292 i365_set(sock, I365_CSCINT, 0);
1293 DEBUG(2, " hits = %d\n", irq_hits);
1294
1295 return (irq_hits != 1);
1296 }
1297
1298 #ifdef CONFIG_ISA
1299
1300 static u_int __init isa_scan(u_short sock, u_int mask0)
1301 {
1302 u_int mask1 = 0;
1303 int i;
1304
1305 #ifdef __alpha__
1306 #define PIC 0x4d0
1307 /* Don't probe level-triggered interrupts -- reserved for PCI */
1308 mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8));
1309 #endif
1310
1311 #ifdef CONFIG_PCI
1312 /* Only scan if we can select ISA csc irq's */
1313 if (!(socket[sock].flags & IS_CARDBUS) ||
1314 (cb_set_irq_mode(sock, 0, 0) == 0))
1315 #endif
1316 if (do_scan) {
1317 set_bridge_state(sock);
1318 i365_set(sock, I365_CSCINT, 0);
1319 for (i = 0; i < 16; i++)
1320 if ((mask0 & (1 << i)) && (test_irq(sock, i, 0) == 0))
1321 mask1 |= (1 << i);
1322 for (i = 0; i < 16; i++)
1323 if ((mask1 & (1 << i)) && (test_irq(sock, i, 0) != 0))
1324 mask1 ^= (1 << i);
1325 }
1326
1327 printk(KERN_INFO " ISA irqs (");
1328 if (mask1) {
1329 printk("scanned");
1330 } else {
1331 /* Fallback: just find interrupts that aren't in use */
1332 for (i = 0; i < 16; i++)
1333 if ((mask0 & (1 << i)) && (_check_irq(i, 0) == 0))
1334 mask1 |= (1 << i);
1335 printk("default");
1336 /* If scan failed, default to polled status */
1337 if (!cs_irq && (poll_interval == 0)) poll_interval = HZ;
1338 }
1339 printk(") = ");
1340
1341 for (i = 0; i < 16; i++)
1342 if (mask1 & (1<<i))
1343 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i);
1344 if (mask1 == 0) printk("none!");
1345
1346 return mask1;
1347 }
1348
1349 #endif /* CONFIG_ISA */
1350
1351 #ifdef CONFIG_PCI
1352
1353 static void __init pci_scan(u_short sock)
1354 {
1355 u_int i;
1356
1357 cb_set_irq_mode(sock, 1, 0);
1358 set_bridge_state(sock);
1359 i365_set(sock, I365_CSCINT, 0);
1360 /* Only probe irq's 9..11, to be conservative */
1361 for (i = 9; i < 12; i++) {
1362 if ((test_irq(sock, i, 1) == 0) &&
1363 (test_irq(sock, i, 1) == 0))
1364 break;
1365 }
1366 if (i < 12) socket[sock].cap.pci_irq = i;
1367 }
1368
1369 #endif /* CONFIG_PCI */
1370
1371 /*====================================================================*/
1372
1373 /* Time conversion functions */
1374
1375 static int to_cycles(int ns)
1376 {
1377 return ns/cycle_time;
1378 }
1379
1380 static int to_ns(int cycles)
1381 {
1382 return cycle_time*cycles;
1383 }
1384
1385 /*====================================================================*/
1386
1387 #ifdef CONFIG_ISA
1388
1389 static int __init identify(u_short port, u_short sock)
1390 {
1391 u_char val;
1392 int type = -1;
1393
1394 /* Use the next free entry in the socket table */
1395 socket[sockets].ioaddr = port;
1396 socket[sockets].psock = sock;
1397
1398 /* Wake up a sleepy Cirrus controller */
1399 if (wakeup) {
1400 i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND);
1401 /* Pause at least 50 ms */
1402 mdelay(50);
1403 }
1404
1405 if ((val = i365_get(sockets, I365_IDENT)) & 0x70)
1406 return -1;
1407 switch (val) {
1408 case 0x82:
1409 type = IS_I82365A; break;
1410 case 0x83:
1411 type = IS_I82365B; break;
1412 case 0x84:
1413 type = IS_I82365DF; break;
1414 case 0x88: case 0x89: case 0x8a:
1415 type = IS_IBM; break;
1416 }
1417
1418 /* Check for Vadem VG-468 chips */
1419 outb(0x0e, port);
1420 outb(0x37, port);
1421 i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV);
1422 val = i365_get(sockets, I365_IDENT);
1423 if (val & I365_IDENT_VADEM) {
1424 i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV);
1425 type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468;
1426 }
1427
1428 /* Check for Ricoh chips */
1429 val = i365_get(sockets, RF5C_CHIP_ID);
1430 if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396))
1431 type = IS_RF5Cx96;
1432
1433 /* Check for Cirrus CL-PD67xx chips */
1434 i365_set(sockets, PD67_CHIP_INFO, 0);
1435 val = i365_get(sockets, PD67_CHIP_INFO);
1436 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
1437 val = i365_get(sockets, PD67_CHIP_INFO);
1438 if ((val & PD67_INFO_CHIP_ID) == 0) {
1439 type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
1440 i365_set(sockets, PD67_EXT_INDEX, 0xe5);
1441 if (i365_get(sockets, PD67_EXT_INDEX) != 0xe5)
1442 type = IS_VT83C469;
1443 }
1444 }
1445 return type;
1446 } /* identify */
1447
1448 #endif
1449
1450 /*======================================================================
1451
1452 See if a card is present, powered up, in IO mode, and already
1453 bound to a (non PC Card) Linux driver. We leave these alone.
1454
1455 We make an exception for cards that seem to be serial devices.
1456
1457 ======================================================================*/
1458
1459 static int __init is_alive(u_short sock)
1460 {
1461 u_char stat;
1462 u_short start, stop;
1463
1464 stat = i365_get(sock, I365_STATUS);
1465 start = i365_get_pair(sock, I365_IO(0)+I365_W_START);
1466 stop = i365_get_pair(sock, I365_IO(0)+I365_W_STOP);
1467 if ((stat & I365_CS_DETECT) && (stat & I365_CS_POWERON) &&
1468 (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) &&
1469 (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(0)) &&
1470 (check_region(start, stop-start+1) != 0) &&
1471 ((start & 0xfeef) != 0x02e8))
1472 return 1;
1473 else
1474 return 0;
1475 }
1476
1477 /*====================================================================*/
1478
1479 static void __init add_socket(u_short port, int psock, int type)
1480 {
1481 socket[sockets].ioaddr = port;
1482 socket[sockets].psock = psock;
1483 socket[sockets].type = type;
1484 socket[sockets].flags = pcic[type].flags;
1485 if (is_alive(sockets))
1486 socket[sockets].flags |= IS_ALIVE;
1487 sockets++;
1488 }
1489
1490 static void __init add_pcic(int ns, int type)
1491 {
1492 u_int mask = 0, i, base;
1493 int use_pci = 0, isa_irq = 0;
1494 socket_info_t *t = &socket[sockets-ns];
1495
1496 base = sockets-ns;
1497 if (t->ioaddr > 0) request_region(t->ioaddr, 2, "i82365");
1498
1499 if (base == 0) printk("\n");
1500 printk(KERN_INFO " %s", pcic[type].name);
1501 #ifdef CONFIG_PCI
1502 if (t->flags & IS_UNKNOWN)
1503 printk(" [0x%04x 0x%04x]", t->vendor, t->device);
1504 if (t->flags & IS_CARDBUS)
1505 printk(" PCI-to-CardBus at bus %d slot %d, mem 0x%08x",
1506 t->bus, PCI_SLOT(t->devfn), t->cb_phys);
1507 else if (t->flags & IS_PCI)
1508 printk(" PCI-to-PCMCIA at bus %d slot %d, port %#x",
1509 t->bus, PCI_SLOT(t->devfn), t->ioaddr);
1510 else
1511 #endif
1512 printk(" ISA-to-PCMCIA at port %#x ofs 0x%02x",
1513 t->ioaddr, t->psock*0x40);
1514 printk(", %d socket%s\n", ns, ((ns > 1) ? "s" : ""));
1515
1516 #ifdef CONFIG_ISA
1517 /* Set host options, build basic interrupt mask */
1518 if (irq_list[0] == -1)
1519 mask = irq_mask;
1520 else
1521 for (i = mask = 0; i < 16; i++)
1522 mask |= (1<<irq_list[i]);
1523 #endif
1524 mask &= I365_MASK & set_bridge_opts(base, ns);
1525 #ifdef CONFIG_ISA
1526 /* Scan for ISA interrupts */
1527 mask = isa_scan(base, mask);
1528 #else
1529 printk(KERN_INFO " PCI card interrupts,");
1530 #endif
1531
1532 #ifdef CONFIG_PCI
1533 /* Can we use a PCI interrupt for card status changes? */
1534 if (pci_csc && t->cap.pci_irq) {
1535 for (i = 0; i < ns; i++)
1536 if (_check_irq(t[i].cap.pci_irq, SA_SHIRQ)) break;
1537 if (i == ns) {
1538 use_pci = 1;
1539 printk(" PCI status changes\n");
1540 }
1541 }
1542 #endif
1543
1544 #ifdef CONFIG_ISA
1545 /* Poll if only two interrupts available */
1546 if (!use_pci && !poll_interval) {
1547 u_int tmp = (mask & 0xff20);
1548 tmp = tmp & (tmp-1);
1549 if ((tmp & (tmp-1)) == 0)
1550 poll_interval = HZ;
1551 }
1552 /* Only try an ISA cs_irq if this is the first controller */
1553 if (!use_pci && !grab_irq && (cs_irq || !poll_interval)) {
1554 /* Avoid irq 12 unless it is explicitly requested */
1555 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12));
1556 for (cs_irq = 15; cs_irq > 0; cs_irq--)
1557 if ((cs_mask & (1 << cs_irq)) &&
1558 (_check_irq(cs_irq, 0) == 0))
1559 break;
1560 if (cs_irq) {
1561 grab_irq = 1;
1562 isa_irq = cs_irq;
1563 printk(" status change on irq %d\n", cs_irq);
1564 }
1565 }
1566 #endif
1567
1568 if (!use_pci && !isa_irq) {
1569 if (poll_interval == 0)
1570 poll_interval = HZ;
1571 printk(" polling interval = %d ms\n",
1572 poll_interval * 1000 / HZ);
1573
1574 }
1575
1576 /* Update socket interrupt information, capabilities */
1577 for (i = 0; i < ns; i++) {
1578 t[i].cap.features |= SS_CAP_PCCARD;
1579 t[i].cap.map_size = 0x1000;
1580 t[i].cap.irq_mask = mask;
1581 if (pci_int && t[i].cap.pci_irq)
1582 t[i].cap.irq_mask |= (1 << t[i].cap.pci_irq);
1583 t[i].cs_irq = isa_irq;
1584 #ifdef CONFIG_PCI
1585 if (t[i].flags & IS_CARDBUS) {
1586 t[i].cap.features |= SS_CAP_CARDBUS;
1587 cb_set_irq_mode(i, pci_csc && t[i].cap.pci_irq,
1588 pci_int && t[i].cap.pci_irq);
1589 }
1590 #endif
1591 }
1592
1593 } /* add_pcic */
1594
1595 /*====================================================================*/
1596
1597 #ifdef CONFIG_PCI
1598
1599 typedef struct pci_dev *pci_id_t;
1600 static int __init pci_lookup(u_int class, pci_id_t *id,
1601 u_char *bus, u_char *devfn)
1602 {
1603 if ((*id = pci_find_class(class<<8, *id)) != NULL) {
1604 *bus = (*id)->bus->number;
1605 *devfn = (*id)->devfn;
1606 return 0;
1607 } else return -1;
1608 }
1609
1610 static void __init add_pci_bridge(int type, u_char bus, u_char devfn,
1611 u_short v, u_short d)
1612 {
1613 socket_info_t *s = &socket[sockets];
1614 u_short i, ns;
1615 u_int addr;
1616
1617 if (type == PCIC_COUNT) type = IS_UNK_PCI;
1618 pci_readl(bus, devfn, PCI_BASE_ADDRESS_0, &addr);
1619 addr &= ~0x1;
1620 pci_writew(bus, devfn, PCI_COMMAND, CMD_DFLT);
1621 for (i = ns = 0; i < ((type == IS_I82092AA) ? 4 : 2); i++) {
1622 s->bus = bus; s->devfn = devfn;
1623 s->vendor = v; s->device = d;
1624 add_socket(addr, i, type);
1625 ns++; s++;
1626 }
1627 add_pcic(ns, type);
1628 }
1629
1630 static void __init add_cb_bridge(int type, u_char bus, u_char devfn,
1631 u_short v, u_short d0)
1632 {
1633 socket_info_t *s = &socket[sockets];
1634 u_short d, ns, i;
1635 u_char a, b, r, max;
1636
1637 /* PCI bus enumeration is broken on some systems */
1638 for (ns = 0; ns < sockets; ns++)
1639 if ((socket[ns].bus == bus) && (socket[ns].devfn == devfn))
1640 return;
1641
1642 if (type == PCIC_COUNT) type = IS_UNK_CARDBUS;
1643 pci_readb(bus, devfn, PCI_HEADER_TYPE, &a);
1644 pci_readb(bus, devfn, PCI_CLASS_REVISION, &r);
1645 max = (a & 0x80) ? 8 : 1;
1646 for (ns = 0; ns < max; ns++, s++, devfn++) {
1647 if (pci_readw(bus, devfn, PCI_DEVICE_ID, &d) || (d != d0))
1648 break;
1649 s->bus = bus; s->devfn = devfn;
1650 s->vendor = v; s->device = d; s->revision = r;
1651
1652 /* Check for power management capabilities */
1653 pci_readb(bus, devfn, PCI_STATUS, &a);
1654 if (a & PCI_STATUS_CAPLIST) {
1655 pci_readb(bus, devfn, PCI_CB_CAPABILITY_POINTER, &b);
1656 while (b != 0) {
1657 pci_readb(bus, devfn, b+PCI_CAPABILITY_ID, &a);
1658 if (a == PCI_CAPABILITY_PM) {
1659 s->pmcs = b + PCI_PM_CONTROL_STATUS;
1660 break;
1661 }
1662 pci_readb(bus, devfn, b+PCI_NEXT_CAPABILITY, &b);
1663 }
1664 }
1665 /* If capability exists, make sure we're in D0 state */
1666 if (s->pmcs)
1667 pci_writew(bus, devfn, s->pmcs, PCI_PMCS_PWR_STATE_D0);
1668
1669 /* Map CardBus registers if they are not already mapped */
1670 pci_writel(bus, devfn, CB_LEGACY_MODE_BASE, 0);
1671 pci_readl(bus, devfn, PCI_BASE_ADDRESS_0, &s->cb_phys);
1672 if (s->cb_phys == 0) {
1673 pci_writew(bus, devfn, PCI_COMMAND, CMD_DFLT);
1674 for (i = 0; i < sizeof(cb_mem_base)/sizeof(u_int); i++) {
1675 s->cb_phys = cb_mem_base[i];
1676 s->cb_virt = ioremap(s->cb_phys, 0x1000);
1677 pci_writel(bus, devfn, PCI_BASE_ADDRESS_0, s->cb_phys);
1678 /* Simple sanity checks */
1679 if (!(readb(s->cb_virt+0x800+I365_IDENT) & 0x70) &&
1680 !(readb(s->cb_virt+0x800+I365_CSC) &&
1681 readb(s->cb_virt+0x800+I365_CSC) &&
1682 readb(s->cb_virt+0x800+I365_CSC)))
1683 break;
1684 iounmap(s->cb_virt);
1685 }
1686 if (i == sizeof(cb_mem_base)/sizeof(u_int)) {
1687 pci_writel(bus, devfn, PCI_BASE_ADDRESS_0, 0);
1688 s->cb_phys = 0; s->cb_virt = NULL;
1689 printk("\n");
1690 printk(KERN_NOTICE " Bridge register mapping failed:"
1691 " check cb_mem_base setting\n");
1692 break;
1693 }
1694 cb_mem_base[0] = cb_mem_base[i] + PAGE_SIZE;
1695 } else {
1696 s->cb_virt = ioremap(s->cb_phys, 0x1000);
1697 }
1698
1699 request_mem_region(s->cb_phys, 0x1000, "i82365");
1700 add_socket(0, 0, type);
1701 }
1702 if (ns == 0) return;
1703
1704 s -= ns;
1705 if (ns == 2) {
1706 /* Nasty special check for bad bus mapping */
1707 pci_readb(bus, s[0].devfn, CB_CARDBUS_BUS, &a);
1708 pci_readb(bus, s[1].devfn, CB_CARDBUS_BUS, &b);
1709 if (a == b) {
1710 pci_writeb(bus, s[0].devfn, CB_CARDBUS_BUS, 0);
1711 pci_writeb(bus, s[1].devfn, CB_CARDBUS_BUS, 0);
1712 }
1713 }
1714 add_pcic(ns, type);
1715
1716 /* Re-do card voltage detection, if needed: this checks for
1717 card presence with no voltage detect bits set */
1718 for (a = sockets-ns; a < sockets; a++)
1719 if (!(cb_readl(a, CB_SOCKET_STATE) & 0x3c86))
1720 cb_writel(a, CB_SOCKET_FORCE, CB_SF_CVSTEST);
1721 for (i = 0; i < 200; i++) {
1722 for (a = sockets-ns; a < sockets; a++)
1723 if (!(cb_readl(a, CB_SOCKET_STATE) & 0x3c86)) break;
1724 if (a == sockets) break;
1725 __set_current_state(TASK_UNINTERRUPTIBLE);
1726 schedule_timeout(HZ/20);
1727 }
1728 if (i == 200)
1729 printk(KERN_NOTICE "i82365: card voltage interrogation"
1730 " timed out!\n");
1731
1732 /* Set up PCI bus bridge structures if needed */
1733 for (a = 0; a < ns; a++) {
1734 struct pci_dev *self = pci_find_slot(bus, s[a].devfn);
1735 struct pci_bus *child, *parent = self->bus;
1736 for (child = parent->children; child; child = child->next)
1737 if (child->number == s[a].cap.cardbus) break;
1738 if (!child) {
1739 child = kmalloc(sizeof(struct pci_bus), GFP_KERNEL);
1740 memset(child, 0, sizeof(struct pci_bus));
1741 child->self = self;
1742 child->primary = bus;
1743 child->number = child->secondary = s[a].cap.cardbus;
1744 child->subordinate = s[a].sub_bus;
1745 child->parent = parent;
1746 child->ops = parent->ops;
1747 child->next = parent->children;
1748 }
1749 s[a].cap.cb_bus = parent->children = child;
1750 }
1751 }
1752
1753 static void __init pci_probe(u_int class, void (add_fn)
1754 (int, u_char, u_char, u_short, u_short))
1755 {
1756 u_short i, v, d;
1757 u_char bus, devfn;
1758 pci_id_t id;
1759
1760 id = 0;
1761 while (pci_lookup(class, &id, &bus, &devfn) == 0) {
1762 if (PCI_FUNC(devfn) != 0) continue;
1763 pci_readw(bus, devfn, PCI_VENDOR_ID, &v);
1764 pci_readw(bus, devfn, PCI_DEVICE_ID, &d);
1765 for (i = 0; i < PCIC_COUNT; i++)
1766 if ((pcic[i].vendor == v) && (pcic[i].device == d)) break;
1767 add_fn(i, bus, devfn, v, d);
1768 }
1769 }
1770
1771 #endif /* CONFIG_PCI */
1772
1773 /*====================================================================*/
1774
1775 #ifdef CONFIG_ISA
1776
1777 static void __init isa_probe(void)
1778 {
1779 int i, j, sock, k, ns, id;
1780 ioaddr_t port;
1781
1782 if (check_region(i365_base, 2) != 0) {
1783 if (sockets == 0)
1784 printk("port conflict at %#x\n", i365_base);
1785 return;
1786 }
1787
1788 id = identify(i365_base, 0);
1789 if ((id == IS_I82365DF) && (identify(i365_base, 1) != id)) {
1790 for (i = 0; i < 4; i++) {
1791 if (i == ignore) continue;
1792 port = i365_base + ((i & 1) << 2) + ((i & 2) << 1);
1793 sock = (i & 1) << 1;
1794 if (identify(port, sock) == IS_I82365DF) {
1795 add_socket(port, sock, IS_VLSI);
1796 add_pcic(1, IS_VLSI);
1797 }
1798 }
1799 } else {
1800 for (i = 0; i < (extra_sockets ? 8 : 4); i += 2) {
1801 port = i365_base + 2*(i>>2);
1802 sock = (i & 3);
1803 id = identify(port, sock);
1804 if (id < 0) continue;
1805
1806 for (j = ns = 0; j < 2; j++) {
1807 /* Does the socket exist? */
1808 if ((ignore == i+j) || (identify(port, sock+j) < 0))
1809 continue;
1810 /* Check for bad socket decode */
1811 for (k = 0; k <= sockets; k++)
1812 i365_set(k, I365_MEM(0)+I365_W_OFF, k);
1813 for (k = 0; k <= sockets; k++)
1814 if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k)
1815 break;
1816 if (k <= sockets) break;
1817 add_socket(port, sock+j, id); ns++;
1818 }
1819 if (ns != 0) add_pcic(ns, id);
1820 }
1821 }
1822 }
1823
1824 #endif
1825
1826 /*====================================================================*/
1827
1828 static void pcic_interrupt(int irq, void *dev,
1829 struct pt_regs *regs)
1830 {
1831 int i, j, csc;
1832 u_int events, active;
1833 #ifdef CONFIG_ISA
1834 u_long flags = 0;
1835 #endif
1836
1837 DEBUG(4, "i82365: pcic_interrupt(%d)\n", irq);
1838
1839 for (j = 0; j < 20; j++) {
1840 active = 0;
1841 for (i = 0; i < sockets; i++) {
1842 if ((socket[i].cs_irq != irq) &&
1843 (socket[i].cap.pci_irq != irq))
1844 continue;
1845 ISA_LOCK(i, flags);
1846 csc = i365_get(i, I365_CSC);
1847 #ifdef CONFIG_PCI
1848 if ((socket[i].flags & IS_CARDBUS) &&
1849 (cb_readl(i,CB_SOCKET_EVENT) & (CB_SE_CCD1|CB_SE_CCD2))) {
1850 cb_writel(i, CB_SOCKET_EVENT, CB_SE_CCD1|CB_SE_CCD2);
1851 csc |= I365_CSC_DETECT;
1852 }
1853 #endif
1854 if ((csc == 0) || (!socket[i].handler) ||
1855 (i365_get(i, I365_IDENT) & 0x70)) {
1856 ISA_UNLOCK(i, flags);
1857 continue;
1858 }
1859 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
1860 if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD)
1861 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
1862 else {
1863 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
1864 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
1865 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
1866 }
1867 ISA_UNLOCK(i, flags);
1868 DEBUG(2, "i82365: socket %d event 0x%02x\n", i, events);
1869 if (events)
1870 socket[i].handler(socket[i].info, events);
1871 active |= events;
1872 }
1873 if (!active) break;
1874 }
1875 if (j == 20)
1876 printk(KERN_NOTICE "i82365: infinite loop in interrupt handler\n");
1877
1878 DEBUG(4, "i82365: interrupt done\n");
1879 } /* pcic_interrupt */
1880
1881 static void pcic_interrupt_wrapper(u_long data)
1882 {
1883 pcic_interrupt(0, NULL, NULL);
1884 poll_timer.expires = jiffies + poll_interval;
1885 add_timer(&poll_timer);
1886 }
1887
1888 /*====================================================================*/
1889
1890 static int pcic_register_callback(unsigned int sock, void (*handler)(void *, unsigned int), void * info)
1891 {
1892 socket[sock].handler = handler;
1893 socket[sock].info = info;
1894 if (handler == NULL) {
1895 MOD_DEC_USE_COUNT;
1896 } else {
1897 MOD_INC_USE_COUNT;
1898 }
1899 return 0;
1900 } /* pcic_register_callback */
1901
1902 /*====================================================================*/
1903
1904 static int pcic_inquire_socket(unsigned int sock, socket_cap_t *cap)
1905 {
1906 *cap = socket[sock].cap;
1907 return 0;
1908 } /* pcic_inquire_socket */
1909
1910 /*====================================================================*/
1911
1912 static int i365_get_status(u_short sock, u_int *value)
1913 {
1914 u_int status;
1915
1916 status = i365_get(sock, I365_STATUS);
1917 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT)
1918 ? SS_DETECT : 0;
1919 if (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD)
1920 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
1921 else {
1922 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
1923 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
1924 }
1925 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
1926 *value |= (status & I365_CS_READY) ? SS_READY : 0;
1927 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
1928
1929 #ifdef CONFIG_PCI
1930 if (socket[sock].flags & IS_CARDBUS) {
1931 status = cb_readl(sock, CB_SOCKET_STATE);
1932 #ifndef CONFIG_CARDBUS
1933 *value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
1934 #endif
1935 *value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
1936 *value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
1937 } else if (socket[sock].flags & IS_O2MICRO) {
1938 status = i365_get(sock, O2_MODE_B);
1939 *value |= (status & O2_MODE_B_VS1) ? 0 : SS_3VCARD;
1940 *value |= (status & O2_MODE_B_VS2) ? 0 : SS_XVCARD;
1941 }
1942 #endif
1943 #ifdef CONFIG_ISA
1944 if (socket[sock].type == IS_VG469) {
1945 status = i365_get(sock, VG469_VSENSE);
1946 if (socket[sock].psock & 1) {
1947 *value |= (status & VG469_VSENSE_B_VS1) ? 0 : SS_3VCARD;
1948 *value |= (status & VG469_VSENSE_B_VS2) ? 0 : SS_XVCARD;
1949 } else {
1950 *value |= (status & VG469_VSENSE_A_VS1) ? 0 : SS_3VCARD;
1951 *value |= (status & VG469_VSENSE_A_VS2) ? 0 : SS_XVCARD;
1952 }
1953 }
1954 #endif
1955
1956 DEBUG(1, "i82365: GetStatus(%d) = %#4.4x\n", sock, *value);
1957 return 0;
1958 } /* i365_get_status */
1959
1960 /*====================================================================*/
1961
1962 static int i365_get_socket(u_short sock, socket_state_t *state)
1963 {
1964 socket_info_t *t = &socket[sock];
1965 u_char reg, vcc, vpp;
1966
1967 reg = i365_get(sock, I365_POWER);
1968 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
1969 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
1970 vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK;
1971 state->Vcc = state->Vpp = 0;
1972 #ifdef CONFIG_PCI
1973 if (t->flags & IS_CARDBUS) {
1974 cb_get_power(sock, state);
1975 } else
1976 #endif
1977 if (t->flags & IS_CIRRUS) {
1978 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
1979 if (reg & I365_VCC_5V) state->Vcc = 33;
1980 if (vpp == I365_VPP1_5V) state->Vpp = 33;
1981 } else {
1982 if (reg & I365_VCC_5V) state->Vcc = 50;
1983 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1984 }
1985 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1986 } else if (t->flags & IS_VG_PWR) {
1987 if (i365_get(sock, VG469_VSELECT) & VG469_VSEL_VCC) {
1988 if (reg & I365_VCC_5V) state->Vcc = 33;
1989 if (vpp == I365_VPP1_5V) state->Vpp = 33;
1990 } else {
1991 if (reg & I365_VCC_5V) state->Vcc = 50;
1992 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1993 }
1994 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1995 } else if (t->flags & IS_DF_PWR) {
1996 if (vcc == I365_VCC_3V) state->Vcc = 33;
1997 if (vcc == I365_VCC_5V) state->Vcc = 50;
1998 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1999 if (vpp == I365_VPP1_12V) state->Vpp = 120;
2000 } else {
2001 if (reg & I365_VCC_5V) {
2002 state->Vcc = 50;
2003 if (vpp == I365_VPP1_5V) state->Vpp = 50;
2004 if (vpp == I365_VPP1_12V) state->Vpp = 120;
2005 }
2006 }
2007
2008 /* IO card, RESET flags, IO interrupt */
2009 reg = i365_get(sock, I365_INTCTL);
2010 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
2011 if (reg & I365_PC_IOCARD) state->flags |= SS_IOCARD;
2012 #ifdef CONFIG_PCI
2013 if (cb_get_irq_mode(sock) != 0)
2014 state->io_irq = t->cap.pci_irq;
2015 else
2016 #endif
2017 state->io_irq = reg & I365_IRQ_MASK;
2018
2019 /* speaker control */
2020 if (t->flags & IS_CIRRUS) {
2021 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_SPKR_ENA)
2022 state->flags |= SS_SPKR_ENA;
2023 }
2024
2025 /* Card status change mask */
2026 reg = i365_get(sock, I365_CSCINT);
2027 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
2028 if (state->flags & SS_IOCARD)
2029 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
2030 else {
2031 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
2032 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
2033 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
2034 }
2035
2036 DEBUG(1, "i82365: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
2037 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
2038 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2039 return 0;
2040 } /* i365_get_socket */
2041
2042 /*====================================================================*/
2043
2044 static int i365_set_socket(u_short sock, socket_state_t *state)
2045 {
2046 socket_info_t *t = &socket[sock];
2047 u_char reg;
2048
2049 DEBUG(1, "i82365: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
2050 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
2051 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2052
2053 /* First set global controller options */
2054 #ifdef CONFIG_PCI
2055 if ((t->flags & IS_CARDBUS) && t->cap.pci_irq)
2056 cb_set_irq_mode(sock, pci_csc,
2057 (t->cap.pci_irq == state->io_irq));
2058 t->bcr &= ~CB_BCR_CB_RESET;
2059 #endif
2060 set_bridge_state(sock);
2061
2062 /* IO card, RESET flag, IO interrupt */
2063 reg = t->intr;
2064 if (state->io_irq != t->cap.pci_irq) reg |= state->io_irq;
2065 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
2066 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
2067 i365_set(sock, I365_INTCTL, reg);
2068
2069 reg = I365_PWR_NORESET;
2070 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
2071 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
2072
2073 #ifdef CONFIG_PCI
2074 if (t->flags & IS_CARDBUS) {
2075 cb_set_power(sock, state);
2076 reg |= i365_get(sock, I365_POWER) &
2077 (I365_VCC_MASK|I365_VPP1_MASK);
2078 } else
2079 #endif
2080 if (t->flags & IS_CIRRUS) {
2081 if (state->Vpp != 0) {
2082 if (state->Vpp == 120)
2083 reg |= I365_VPP1_12V;
2084 else if (state->Vpp == state->Vcc)
2085 reg |= I365_VPP1_5V;
2086 else return -EINVAL;
2087 }
2088 if (state->Vcc != 0) {
2089 reg |= I365_VCC_5V;
2090 if (state->Vcc == 33)
2091 i365_bset(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
2092 else if (state->Vcc == 50)
2093 i365_bclr(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
2094 else return -EINVAL;
2095 }
2096 } else if (t->flags & IS_VG_PWR) {
2097 if (state->Vpp != 0) {
2098 if (state->Vpp == 120)
2099 reg |= I365_VPP1_12V;
2100 else if (state->Vpp == state->Vcc)
2101 reg |= I365_VPP1_5V;
2102 else return -EINVAL;
2103 }
2104 if (state->Vcc != 0) {
2105 reg |= I365_VCC_5V;
2106 if (state->Vcc == 33)
2107 i365_bset(sock, VG469_VSELECT, VG469_VSEL_VCC);
2108 else if (state->Vcc == 50)
2109 i365_bclr(sock, VG469_VSELECT, VG469_VSEL_VCC);
2110 else return -EINVAL;
2111 }
2112 } else if (t->flags & IS_DF_PWR) {
2113 switch (state->Vcc) {
2114 case 0: break;
2115 case 33: reg |= I365_VCC_3V; break;
2116 case 50: reg |= I365_VCC_5V; break;
2117 default: return -EINVAL;
2118 }
2119 switch (state->Vpp) {
2120 case 0: break;
2121 case 50: reg |= I365_VPP1_5V; break;
2122 case 120: reg |= I365_VPP1_12V; break;
2123 default: return -EINVAL;
2124 }
2125 } else {
2126 switch (state->Vcc) {
2127 case 0: break;
2128 case 50: reg |= I365_VCC_5V; break;
2129 default: return -EINVAL;
2130 }
2131 switch (state->Vpp) {
2132 case 0: break;
2133 case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break;
2134 case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break;
2135 default: return -EINVAL;
2136 }
2137 }
2138
2139 if (reg != i365_get(sock, I365_POWER))
2140 i365_set(sock, I365_POWER, reg);
2141
2142 /* Chipset-specific functions */
2143 if (t->flags & IS_CIRRUS) {
2144 /* Speaker control */
2145 i365_bflip(sock, PD67_MISC_CTL_1, PD67_MC1_SPKR_ENA,
2146 state->flags & SS_SPKR_ENA);
2147 }
2148
2149 /* Card status change interrupt mask */
2150 reg = t->cs_irq << 4;
2151 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
2152 if (state->flags & SS_IOCARD) {
2153 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
2154 } else {
2155 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
2156 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
2157 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
2158 }
2159 i365_set(sock, I365_CSCINT, reg);
2160 i365_get(sock, I365_CSC);
2161 #ifdef CONFIG_PCI
2162 if (t->flags & IS_CARDBUS) {
2163 if (t->cs_irq || (pci_csc && t->cap.pci_irq))
2164 cb_writel(sock, CB_SOCKET_MASK, CB_SM_CCD);
2165 cb_writel(sock, CB_SOCKET_EVENT, -1);
2166 }
2167 #endif
2168
2169 return 0;
2170 } /* i365_set_socket */
2171
2172 /*====================================================================*/
2173
2174 static int i365_get_io_map(u_short sock, struct pccard_io_map *io)
2175 {
2176 u_char map, ioctl, addr;
2177
2178 map = io->map;
2179 if (map > 1) return -EINVAL;
2180 io->start = i365_get_pair(sock, I365_IO(map)+I365_W_START);
2181 io->stop = i365_get_pair(sock, I365_IO(map)+I365_W_STOP);
2182 ioctl = i365_get(sock, I365_IOCTL);
2183 addr = i365_get(sock, I365_ADDRWIN);
2184 io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
2185 io->flags = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
2186 io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
2187 io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
2188 io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;
2189 DEBUG(1, "i82365: GetIOMap(%d, %d) = %#2.2x, %d ns, "
2190 "%#4.4x-%#4.4x\n", sock, map, io->flags, io->speed,
2191 io->start, io->stop);
2192 return 0;
2193 } /* i365_get_io_map */
2194
2195 /*====================================================================*/
2196
2197 static int i365_set_io_map(u_short sock, struct pccard_io_map *io)
2198 {
2199 u_char map, ioctl;
2200
2201 DEBUG(1, "i82365: SetIOMap(%d, %d, %#2.2x, %d ns, "
2202 "%#4.4x-%#4.4x)\n", sock, io->map, io->flags,
2203 io->speed, io->start, io->stop);
2204 map = io->map;
2205 if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
2206 (io->stop < io->start)) return -EINVAL;
2207 /* Turn off the window before changing anything */
2208 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(map))
2209 i365_bclr(sock, I365_ADDRWIN, I365_ENA_IO(map));
2210 i365_set_pair(sock, I365_IO(map)+I365_W_START, io->start);
2211 i365_set_pair(sock, I365_IO(map)+I365_W_STOP, io->stop);
2212 ioctl = i365_get(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
2213 if (io->speed) ioctl |= I365_IOCTL_WAIT(map);
2214 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
2215 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
2216 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
2217 i365_set(sock, I365_IOCTL, ioctl);
2218 /* Turn on the window if necessary */
2219 if (io->flags & MAP_ACTIVE)
2220 i365_bset(sock, I365_ADDRWIN, I365_ENA_IO(map));
2221 return 0;
2222 } /* i365_set_io_map */
2223
2224 /*====================================================================*/
2225
2226 static int i365_get_mem_map(u_short sock, struct pccard_mem_map *mem)
2227 {
2228 u_short base, i;
2229 u_char map, addr;
2230
2231 map = mem->map;
2232 if (map > 4) return -EINVAL;
2233 addr = i365_get(sock, I365_ADDRWIN);
2234 mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;
2235 base = I365_MEM(map);
2236
2237 i = i365_get_pair(sock, base+I365_W_START);
2238 mem->flags |= (i & I365_MEM_16BIT) ? MAP_16BIT : 0;
2239 mem->flags |= (i & I365_MEM_0WS) ? MAP_0WS : 0;
2240 mem->sys_start += ((u_long)(i & 0x0fff) << 12);
2241
2242 i = i365_get_pair(sock, base+I365_W_STOP);
2243 mem->speed = (i & I365_MEM_WS0) ? 1 : 0;
2244 mem->speed += (i & I365_MEM_WS1) ? 2 : 0;
2245 mem->speed = to_ns(mem->speed);
2246 mem->sys_stop = ((u_long)(i & 0x0fff) << 12) + 0x0fff;
2247
2248 i = i365_get_pair(sock, base+I365_W_OFF);
2249 mem->flags |= (i & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
2250 mem->flags |= (i & I365_MEM_REG) ? MAP_ATTRIB : 0;
2251 mem->card_start = ((u_int)(i & 0x3fff) << 12) + mem->sys_start;
2252 mem->card_start &= 0x3ffffff;
2253
2254 #ifdef CONFIG_PCI
2255 /* Take care of high byte, for PCI controllers */
2256 if (socket[sock].type == IS_PD6729) {
2257 i365_set(sock, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
2258 addr = i365_get(sock, PD67_EXT_DATA) << 24;
2259 } else if (socket[sock].flags & IS_CARDBUS) {
2260 addr = i365_get(sock, CB_MEM_PAGE(map)) << 24;
2261 mem->sys_stop += addr; mem->sys_start += addr;
2262 }
2263 #endif
2264
2265 DEBUG(1, "i82365: GetMemMap(%d, %d) = %#2.2x, %d ns, %#5.5lx-%#5."
2266 "5lx, %#5.5x\n", sock, mem->map, mem->flags, mem->speed,
2267 mem->sys_start, mem->sys_stop, mem->card_start);
2268 return 0;
2269 } /* i365_get_mem_map */
2270
2271 /*====================================================================*/
2272
2273 static int i365_set_mem_map(u_short sock, struct pccard_mem_map *mem)
2274 {
2275 u_short base, i;
2276 u_char map;
2277
2278 DEBUG(1, "i82365: SetMemMap(%d, %d, %#2.2x, %d ns, %#5.5lx-%#5.5"
2279 "lx, %#5.5x)\n", sock, mem->map, mem->flags, mem->speed,
2280 mem->sys_start, mem->sys_stop, mem->card_start);
2281
2282 map = mem->map;
2283 if ((map > 4) || (mem->card_start > 0x3ffffff) ||
2284 (mem->sys_start > mem->sys_stop) || (mem->speed > 1000))
2285 return -EINVAL;
2286 if (!(socket[sock].flags & (IS_PCI | IS_CARDBUS)) &&
2287 ((mem->sys_start > 0xffffff) || (mem->sys_stop > 0xffffff)))
2288 return -EINVAL;
2289
2290 /* Turn off the window before changing anything */
2291 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
2292 i365_bclr(sock, I365_ADDRWIN, I365_ENA_MEM(map));
2293
2294 #ifdef CONFIG_PCI
2295 /* Take care of high byte, for PCI controllers */
2296 if (socket[sock].type == IS_PD6729) {
2297 i365_set(sock, PD67_EXT_INDEX, PD67_MEM_PAGE(map));
2298 i365_set(sock, PD67_EXT_DATA, (mem->sys_start >> 24));
2299 } else if (socket[sock].flags & IS_CARDBUS)
2300 i365_set(sock, CB_MEM_PAGE(map), mem->sys_start >> 24);
2301 #endif
2302
2303 base = I365_MEM(map);
2304 i = (mem->sys_start >> 12) & 0x0fff;
2305 if (mem->flags & MAP_16BIT) i |= I365_MEM_16BIT;
2306 if (mem->flags & MAP_0WS) i |= I365_MEM_0WS;
2307 i365_set_pair(sock, base+I365_W_START, i);
2308
2309 i = (mem->sys_stop >> 12) & 0x0fff;
2310 switch (to_cycles(mem->speed)) {
2311 case 0: break;
2312 case 1: i |= I365_MEM_WS0; break;
2313 case 2: i |= I365_MEM_WS1; break;
2314 default: i |= I365_MEM_WS1 | I365_MEM_WS0; break;
2315 }
2316 i365_set_pair(sock, base+I365_W_STOP, i);
2317
2318 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
2319 if (mem->flags & MAP_WRPROT) i |= I365_MEM_WRPROT;
2320 if (mem->flags & MAP_ATTRIB) i |= I365_MEM_REG;
2321 i365_set_pair(sock, base+I365_W_OFF, i);
2322
2323 /* Turn on the window if necessary */
2324 if (mem->flags & MAP_ACTIVE)
2325 i365_bset(sock, I365_ADDRWIN, I365_ENA_MEM(map));
2326 return 0;
2327 } /* i365_set_mem_map */
2328
2329 /*======================================================================
2330
2331 Power control for Cardbus controllers: used both for 16-bit and
2332 Cardbus cards.
2333
2334 ======================================================================*/
2335
2336 #ifdef CONFIG_PCI
2337
2338 static void cb_get_power(u_short sock, socket_state_t *state)
2339 {
2340 u_int reg = cb_readl(sock, CB_SOCKET_CONTROL);
2341 state->Vcc = state->Vpp = 0;
2342 switch (reg & CB_SC_VCC_MASK) {
2343 case CB_SC_VCC_3V: state->Vcc = 33; break;
2344 case CB_SC_VCC_5V: state->Vcc = 50; break;
2345 }
2346 switch (reg & CB_SC_VPP_MASK) {
2347 case CB_SC_VPP_3V: state->Vpp = 33; break;
2348 case CB_SC_VPP_5V: state->Vpp = 50; break;
2349 case CB_SC_VPP_12V: state->Vpp = 120; break;
2350 }
2351 }
2352
2353 static void cb_set_power(u_short sock, socket_state_t *state)
2354 {
2355 u_int reg = 0;
2356 switch (state->Vcc) {
2357 case 33: reg = CB_SC_VCC_3V; break;
2358 case 50: reg = CB_SC_VCC_5V; break;
2359 default: reg = 0; break;
2360 }
2361 switch (state->Vpp) {
2362 case 33: reg |= CB_SC_VPP_3V; break;
2363 case 50: reg |= CB_SC_VPP_5V; break;
2364 case 120: reg |= CB_SC_VPP_12V; break;
2365 }
2366 if (reg != cb_readl(sock, CB_SOCKET_CONTROL))
2367 cb_writel(sock, CB_SOCKET_CONTROL, reg);
2368 }
2369
2370 #endif
2371
2372 /*======================================================================
2373
2374 All the stuff that is strictly for Cardbus cards goes here.
2375
2376 ======================================================================*/
2377
2378 #ifdef CONFIG_CARDBUS
2379
2380 static int cb_get_status(u_short sock, u_int *value)
2381 {
2382 u_int s;
2383 s = cb_readl(sock, CB_SOCKET_STATE);
2384 *value = ((s & CB_SS_32BIT) ? SS_CARDBUS : 0);
2385 *value |= ((s & CB_SS_CCD1) || (s & CB_SS_CCD2)) ? 0 : SS_DETECT;
2386 *value |= (s & CB_SS_CSTSCHG) ? SS_STSCHG : 0;
2387 *value |= (s & CB_SS_PWRCYCLE) ? (SS_POWERON|SS_READY) : 0;
2388 *value |= (s & CB_SS_3VCARD) ? SS_3VCARD : 0;
2389 *value |= (s & CB_SS_XVCARD) ? SS_XVCARD : 0;
2390 DEBUG(1, "yenta: GetStatus(%d) = %#4.4x\n", sock, *value);
2391 return 0;
2392 } /* cb_get_status */
2393
2394 static int cb_get_socket(u_short sock, socket_state_t *state)
2395 {
2396 socket_info_t *s = &socket[sock];
2397 u_short bcr;
2398
2399 cb_get_power(sock, state);
2400 pci_readw(s->bus, s->devfn, CB_BRIDGE_CONTROL, &bcr);
2401 state->flags |= (bcr & CB_BCR_CB_RESET) ? SS_RESET : 0;
2402 if (cb_get_irq_mode(sock) != 0)
2403 state->io_irq = s->cap.pci_irq;
2404 else
2405 state->io_irq = i365_get(sock, I365_INTCTL) & I365_IRQ_MASK;
2406 DEBUG(1, "yenta: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
2407 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
2408 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2409 return 0;
2410 } /* cb_get_socket */
2411
2412 static int cb_set_socket(u_short sock, socket_state_t *state)
2413 {
2414 socket_info_t *s = &socket[sock];
2415 u_int reg;
2416
2417 DEBUG(1, "yenta: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
2418 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
2419 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
2420
2421 /* First set global controller options */
2422 if (s->cap.pci_irq)
2423 cb_set_irq_mode(sock, pci_csc,
2424 (s->cap.pci_irq == state->io_irq));
2425 s->bcr &= ~CB_BCR_CB_RESET;
2426 s->bcr |= (state->flags & SS_RESET) ? CB_BCR_CB_RESET : 0;
2427 set_bridge_state(sock);
2428
2429 cb_set_power(sock, state);
2430
2431 /* Handle IO interrupt using ISA routing */
2432 reg = s->intr;
2433 if (state->io_irq != s->cap.pci_irq) reg |= state->io_irq;
2434 i365_set(sock, I365_INTCTL, reg);
2435
2436 /* Handle CSC mask */
2437 reg = (socket[sock].cs_irq << 4);
2438 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
2439 i365_set(sock, I365_CSCINT, reg);
2440 i365_get(sock, I365_CSC);
2441 if (s->cs_irq || (pci_csc && s->cap.pci_irq))
2442 cb_writel(sock, CB_SOCKET_MASK, CB_SM_CCD);
2443 cb_writel(sock, CB_SOCKET_EVENT, -1);
2444
2445 return 0;
2446 } /* cb_set_socket */
2447
2448 static int cb_get_bridge(u_short sock, struct cb_bridge_map *m)
2449 {
2450 socket_info_t *s = &socket[sock];
2451 u_char map;
2452
2453 map = m->map;
2454 if (map > 1) return -EINVAL;
2455 m->flags &= MAP_IOSPACE;
2456 map += (m->flags & MAP_IOSPACE) ? 2 : 0;
2457 pci_readl(s->bus, s->devfn, CB_MEM_BASE(map), &m->start);
2458 pci_readl(s->bus, s->devfn, CB_MEM_LIMIT(map), &m->stop);
2459 if (m->start || m->stop) {
2460 m->flags |= MAP_ACTIVE;
2461 m->stop |= (map > 1) ? 3 : 0x0fff;
2462 }
2463 if (map > 1) {
2464 u_short bcr;
2465 pci_readw(s->bus, s->devfn, CB_BRIDGE_CONTROL, &bcr);
2466 m->flags |= (bcr & CB_BCR_PREFETCH(map)) ? MAP_PREFETCH : 0;
2467 }
2468 DEBUG(1, "yenta: GetBridge(%d, %d) = %#2.2x, %#4.4x-%#4.4x\n",
2469 sock, map, m->flags, m->start, m->stop);
2470 return 0;
2471 }
2472
2473 static int cb_set_bridge(u_short sock, struct cb_bridge_map *m)
2474 {
2475 socket_info_t *s = &socket[sock];
2476 u_char map;
2477
2478 DEBUG(1, "yenta: SetBridge(%d, %d, %#2.2x, %#4.4x-%#4.4x)\n",
2479 sock, m->map, m->flags, m->start, m->stop);
2480 map = m->map;
2481 if (!(s->flags & IS_CARDBUS) || (map > 1) || (m->stop < m->start))
2482 return -EINVAL;
2483 if (m->flags & MAP_IOSPACE) {
2484 if ((m->stop > 0xffff) || (m->start & 3) ||
2485 ((m->stop & 3) != 3))
2486 return -EINVAL;
2487 map += 2;
2488 } else {
2489 u_short bcr;
2490 if ((m->start & 0x0fff) || ((m->stop & 0x0fff) != 0x0fff))
2491 return -EINVAL;
2492 pci_readw(s->bus, s->devfn, CB_BRIDGE_CONTROL, &bcr);
2493 bcr &= ~CB_BCR_PREFETCH(map);
2494 bcr |= (m->flags & MAP_PREFETCH) ? CB_BCR_PREFETCH(map) : 0;
2495 pci_writew(s->bus, s->devfn, CB_BRIDGE_CONTROL, bcr);
2496 }
2497 if (m->flags & MAP_ACTIVE) {
2498 pci_writel(s->bus, s->devfn, CB_MEM_BASE(map), m->start);
2499 pci_writel(s->bus, s->devfn, CB_MEM_LIMIT(map), m->stop);
2500 } else {
2501 pci_writel(s->bus, s->devfn, CB_IO_BASE(map), 0);
2502 pci_writel(s->bus, s->devfn, CB_IO_LIMIT(map), 0);
2503 }
2504 return 0;
2505 }
2506
2507 #endif /* CONFIG_CARDBUS */
2508
2509 /*======================================================================
2510
2511 Routines for accessing socket information and register dumps via
2512 /proc/bus/pccard/...
2513
2514 ======================================================================*/
2515
2516 #ifdef CONFIG_PROC_FS
2517
2518 static int proc_read_info(char *buf, char **start, off_t pos,
2519 int count, int *eof, void *data)
2520 {
2521 socket_info_t *s = data;
2522 char *p = buf;
2523 p += sprintf(p, "type: %s\npsock: %d\n",
2524 pcic[s->type].name, s->psock);
2525 #ifdef CONFIG_PCI
2526 if (s->flags & (IS_PCI|IS_CARDBUS))
2527 p += sprintf(p, "bus: %02x\ndevfn: %02x.%1x\n",
2528 s->bus, PCI_SLOT(s->devfn), PCI_FUNC(s->devfn));
2529 if (s->flags & IS_CARDBUS)
2530 p += sprintf(p, "cardbus: %02x\n", s->cap.cardbus);
2531 #endif
2532 return (p - buf);
2533 }
2534
2535 static int proc_read_exca(char *buf, char **start, off_t pos,
2536 int count, int *eof, void *data)
2537 {
2538 u_short sock = (socket_info_t *)data - socket;
2539 char *p = buf;
2540 int i, top;
2541
2542 #ifdef CONFIG_ISA
2543 u_long flags = 0;
2544 #endif
2545 ISA_LOCK(sock, flags);
2546 top = 0x40;
2547 if (socket[sock].flags & IS_CARDBUS)
2548 top = (socket[sock].flags & IS_CIRRUS) ? 0x140 : 0x50;
2549 for (i = 0; i < top; i += 4) {
2550 if (i == 0x50) {
2551 p += sprintf(p, "\n");
2552 i = 0x100;
2553 }
2554 p += sprintf(p, "%02x %02x %02x %02x%s",
2555 i365_get(sock,i), i365_get(sock,i+1),
2556 i365_get(sock,i+2), i365_get(sock,i+3),
2557 ((i % 16) == 12) ? "\n" : " ");
2558 }
2559 ISA_UNLOCK(sock, flags);
2560 return (p - buf);
2561 }
2562
2563 #ifdef CONFIG_PCI
2564 static int proc_read_pci(char *buf, char **start, off_t pos,
2565 int count, int *eof, void *data)
2566 {
2567 socket_info_t *s = data;
2568 u_char bus = s->bus, devfn = s->devfn;
2569 char *p = buf;
2570 u_int a, b, c, d;
2571 int i;
2572
2573 for (i = 0; i < 0xc0; i += 0x10) {
2574 pci_readl(bus, devfn, i, &a);
2575 pci_readl(bus, devfn, i+4, &b);
2576 pci_readl(bus, devfn, i+8, &c);
2577 pci_readl(bus, devfn, i+12, &d);
2578 p += sprintf(p, "%08x %08x %08x %08x\n", a, b, c, d);
2579 }
2580 return (p - buf);
2581 }
2582 #endif
2583
2584 #ifdef CONFIG_CARDBUS
2585 static int proc_read_cardbus(char *buf, char **start, off_t pos,
2586 int count, int *eof, void *data)
2587 {
2588 u_short sock = (socket_info_t *)data - socket;
2589 char *p = buf;
2590 int i, top;
2591
2592 top = (socket[sock].flags & IS_O2MICRO) ? 0x30 : 0x20;
2593 for (i = 0; i < top; i += 0x10)
2594 p += sprintf(p, "%08x %08x %08x %08x\n",
2595 cb_readl(sock,i+0x00), cb_readl(sock,i+0x04),
2596 cb_readl(sock,i+0x08), cb_readl(sock,i+0x0c));
2597 return (p - buf);
2598 }
2599 #endif
2600
2601 static void pcic_proc_setup(unsigned int sock, struct proc_dir_entry *base)
2602 {
2603 #ifdef CONFIG_PROC_FS
2604 socket_info_t *s = &socket[sock];
2605
2606 if (s->flags & IS_ALIVE)
2607 return;
2608
2609 create_proc_read_entry("info", 0, base, proc_read_info, s);
2610 create_proc_read_entry("exca", 0, base, proc_read_exca, s);
2611 #ifdef CONFIG_PCI
2612 if (s->flags & (IS_PCI|IS_CARDBUS))
2613 create_proc_read_entry("pci", 0, base, proc_read_pci, s);
2614 #endif
2615 #ifdef CONFIG_CARDBUS
2616 if (s->flags & IS_CARDBUS)
2617 create_proc_read_entry("cardbus", 0, base, proc_read_cardbus, s);
2618 #endif
2619 s->proc = base;
2620 #endif
2621 }
2622
2623 static void pcic_proc_remove(u_short sock)
2624 {
2625 struct proc_dir_entry *base = socket[sock].proc;
2626 if (base == NULL) return;
2627 remove_proc_entry("info", base);
2628 remove_proc_entry("exca", base);
2629 #ifdef CONFIG_PCI
2630 if (socket[sock].flags & (IS_PCI|IS_CARDBUS))
2631 remove_proc_entry("pci", base);
2632 #endif
2633 #ifdef CONFIG_CARDBUS
2634 if (socket[sock].flags & IS_CARDBUS)
2635 remove_proc_entry("cardbus", base);
2636 #endif
2637 }
2638
2639 #endif /* CONFIG_PROC_FS */
2640
2641 /*====================================================================*/
2642
2643 /*
2644 * This looks like a lot of duplication, and it is. What we should REALLY
2645 * have is separate functions for the separate cases, instead of having
2646 * duplicate tests in them - and then have the test in the place that sets
2647 * up the ss_entry function pointer table instead!
2648 *
2649 * For example, the IS_CARDBUS thing is something we know _statically_,
2650 * and as such it is a waste of time and space to test it dynamically.
2651 *
2652 * Much of this goes away by splitting off the cases. One small step at a
2653 * time..
2654 */
2655
2656 #ifdef CONFIG_CARDBUS
2657 #define is_cardbus(sock) ((socket[(sock)].flags & IS_CARDBUS) && (cb_readl((sock), CB_SOCKET_STATE) & CB_SS_32BIT))
2658 #endif
2659
2660 /*
2661 * The locking is rather broken. Why do we only lock for ISA, not for
2662 * all other cases? If there are reasons to lock, we should lock. Not
2663 * this silly conditional.
2664 *
2665 * Plan: make it bug-for-bug compatible with the old stuff, and clean
2666 * it up when the infrastructure is done.
2667 */
2668 #ifdef CONFIG_ISA
2669 #define LOCKED(x) do { \
2670 if (socket[(sock)].flags & IS_CARDBUS) return x; \
2671 do { \
2672 int retval; \
2673 unsigned long flags; \
2674 spin_lock_irqsave(&isa_lock, flags); \
2675 retval = x; \
2676 spin_unlock_irqrestore(&isa_lock, flags); \
2677 return retval; \
2678 } while (0); \
2679 } while (0)
2680 #else
2681 #define LOCKED(x) return x
2682 #endif
2683
2684
2685 static int pcic_get_status(unsigned int sock, u_int *value)
2686 {
2687 if (socket[sock].flags & IS_ALIVE) {
2688 *value = 0;
2689 return -EINVAL;
2690 }
2691
2692 #ifdef CONFIG_CARDBUS
2693 if (is_cardbus(sock))
2694 return cb_get_status(sock, value);
2695 #endif
2696 LOCKED(i365_get_status(sock, value));
2697 }
2698
2699 static int pcic_get_socket(unsigned int sock, socket_state_t *state)
2700 {
2701 if (socket[sock].flags & IS_ALIVE)
2702 return -EINVAL;
2703
2704 #ifdef CONFIG_CARDBUS
2705 if (is_cardbus(sock))
2706 return cb_get_socket(sock, state);
2707 #endif
2708 LOCKED(i365_get_socket(sock, state));
2709 }
2710
2711 static int pcic_set_socket(unsigned int sock, socket_state_t *state)
2712 {
2713 if (socket[sock].flags & IS_ALIVE)
2714 return -EINVAL;
2715
2716 #ifdef CONFIG_CARDBUS
2717 if (is_cardbus(sock))
2718 return cb_set_socket(sock, state);
2719 #endif
2720 LOCKED(i365_set_socket(sock, state));
2721 }
2722
2723 static int pcic_get_io_map(unsigned int sock, struct pccard_io_map *io)
2724 {
2725 if (socket[sock].flags & IS_ALIVE)
2726 return -EINVAL;
2727
2728 LOCKED(i365_get_io_map(sock, io));
2729 }
2730
2731 static int pcic_set_io_map(unsigned int sock, struct pccard_io_map *io)
2732 {
2733 if (socket[sock].flags & IS_ALIVE)
2734 return -EINVAL;
2735
2736 LOCKED(i365_set_io_map(sock, io));
2737 }
2738
2739 static int pcic_get_mem_map(unsigned int sock, struct pccard_mem_map *mem)
2740 {
2741 if (socket[sock].flags & IS_ALIVE)
2742 return -EINVAL;
2743
2744 LOCKED(i365_get_mem_map(sock, mem));
2745 }
2746
2747 static int pcic_set_mem_map(unsigned int sock, struct pccard_mem_map *mem)
2748 {
2749 if (socket[sock].flags & IS_ALIVE)
2750 return -EINVAL;
2751
2752 LOCKED(i365_set_mem_map(sock, mem));
2753 }
2754
2755 static int pcic_get_bridge(unsigned int sock, struct cb_bridge_map *m)
2756 {
2757 #ifdef CONFIG_CARDBUS
2758 return cb_get_bridge(sock, m);
2759 #else
2760 return -EINVAL;
2761 #endif
2762 }
2763
2764 static int pcic_set_bridge(unsigned int sock, struct cb_bridge_map *m)
2765 {
2766 #ifdef CONFIG_CARDBUS
2767 return cb_set_bridge(sock, m);
2768 #else
2769 return -EINVAL;
2770 #endif
2771 }
2772
2773 static struct pccard_operations pcic_operations = {
2774 pcic_register_callback,
2775 pcic_inquire_socket,
2776 pcic_get_status,
2777 pcic_get_socket,
2778 pcic_set_socket,
2779 pcic_get_io_map,
2780 pcic_set_io_map,
2781 pcic_get_mem_map,
2782 pcic_set_mem_map,
2783 pcic_get_bridge,
2784 pcic_set_bridge,
2785 pcic_proc_setup
2786 };
2787
2788 /*====================================================================*/
2789
2790 static int __init init_i82365(void)
2791 {
2792 servinfo_t serv;
2793 pcmcia_get_card_services_info(&serv);
2794 if (serv.Revision != CS_RELEASE_CODE) {
2795 printk(KERN_NOTICE "i82365: Card Services release "
2796 "does not match!\n");
2797 return -1;
2798 }
2799 DEBUG(0, "%s\n", version);
2800 printk(KERN_INFO "Intel PCIC probe: ");
2801 sockets = 0;
2802
2803 #ifdef CONFIG_PCI
2804 if (do_pci_probe && pcibios_present()) {
2805 pci_probe(PCI_CLASS_BRIDGE_CARDBUS, add_cb_bridge);
2806 pci_probe(PCI_CLASS_BRIDGE_PCMCIA, add_pci_bridge);
2807 }
2808 #endif
2809
2810 #ifdef CONFIG_ISA
2811 isa_probe();
2812 #endif
2813
2814 if (sockets == 0) {
2815 printk("not found.\n");
2816 return -ENODEV;
2817 }
2818
2819 /* Set up interrupt handler(s) */
2820 #ifdef CONFIG_ISA
2821 if (grab_irq != 0)
2822 request_irq(cs_irq, pcic_interrupt, 0, "i82365", NULL);
2823 #endif
2824 #ifdef CONFIG_PCI
2825 if (pci_csc) {
2826 u_int i, irq, mask = 0;
2827 for (i = 0; i < sockets; i++) {
2828 irq = socket[i].cap.pci_irq;
2829 if (irq && !(mask & (1<<irq)))
2830 request_irq(irq, pcic_interrupt, SA_SHIRQ, "i82365", NULL);
2831 mask |= (1<<irq);
2832 }
2833 }
2834 #endif
2835
2836 if (register_ss_entry(sockets, &pcic_operations) != 0)
2837 printk(KERN_NOTICE "i82365: register_ss_entry() failed\n");
2838
2839 /* Finally, schedule a polling interrupt */
2840 if (poll_interval != 0) {
2841 poll_timer.function = pcic_interrupt_wrapper;
2842 poll_timer.data = 0;
2843 poll_timer.prev = poll_timer.next = NULL;
2844 poll_timer.expires = jiffies + poll_interval;
2845 add_timer(&poll_timer);
2846 }
2847
2848 return 0;
2849
2850 } /* init_i82365 */
2851
2852 static void __exit exit_i82365(void)
2853 {
2854 int i;
2855 #ifdef CONFIG_PROC_FS
2856 for (i = 0; i < sockets; i++) pcic_proc_remove(i);
2857 #endif
2858 unregister_ss_entry(&pcic_operations);
2859 if (poll_interval != 0)
2860 del_timer(&poll_timer);
2861 #ifdef CONFIG_ISA
2862 if (grab_irq != 0)
2863 free_irq(cs_irq, NULL);
2864 #endif
2865 #ifdef CONFIG_PCI
2866 if (pci_csc) {
2867 u_int irq, mask = 0;
2868 for (i = 0; i < sockets; i++) {
2869 irq = socket[i].cap.pci_irq;
2870 if (irq && !(mask & (1<<irq)))
2871 free_irq(irq, NULL);
2872 mask |= (1<<irq);
2873 }
2874 }
2875 #endif
2876 for (i = 0; i < sockets; i++) {
2877 /* Turn off all interrupt sources! */
2878 i365_set(i, I365_CSCINT, 0);
2879 #ifdef CONFIG_PCI
2880 if (socket[i].flags & IS_CARDBUS)
2881 cb_writel(i, CB_SOCKET_MASK, 0);
2882 if (socket[i].cb_virt) {
2883 iounmap(socket[i].cb_virt);
2884 release_mem_region(socket[i].cb_phys, 0x1000);
2885 } else
2886 #endif
2887 release_region(socket[i].ioaddr, 2);
2888 }
2889 } /* exit_i82365 */
2890
2891 module_init(init_i82365);
2892 module_exit(exit_i82365);
2893
2894 /*====================================================================*/
2895
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