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Ok. I didn't make 2.4.0 in 2000. Tough. I tried, but we had some
[davej-history.git] / drivers / pcmcia / i82365.c
blobb09e1182fff3dd30967aed16b567c1e34fe88ce1
1 /*======================================================================
2
3 Device driver for Intel 82365 and compatible PC Card controllers.
4
5 i82365.c 1.265 1999/11/10 18:36:21
6
7 The contents of this file are subject to the Mozilla Public
8 License Version 1.1 (the "License"); you may not use this file
9 except in compliance with the License. You may obtain a copy of
10 the License at http://www.mozilla.org/MPL/
11
12 Software distributed under the License is distributed on an "AS
13 IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
14 implied. See the License for the specific language governing
15 rights and limitations under the License.
16
17 The initial developer of the original code is David A. Hinds
18 <dhinds@pcmcia.sourceforge.org>. Portions created by David A. Hinds
19 are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
20
21 Alternatively, the contents of this file may be used under the
22 terms of the GNU Public License version 2 (the "GPL"), in which
23 case the provisions of the GPL are applicable instead of the
24 above. If you wish to allow the use of your version of this file
25 only under the terms of the GPL and not to allow others to use
26 your version of this file under the MPL, indicate your decision
27 by deleting the provisions above and replace them with the notice
28 and other provisions required by the GPL. If you do not delete
29 the provisions above, a recipient may use your version of this
30 file under either the MPL or the GPL.
31
32 ======================================================================*/
33
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/config.h>
37 #include <linux/types.h>
38 #include <linux/fcntl.h>
39 #include <linux/string.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/timer.h>
43 #include <linux/sched.h>
44 #include <linux/malloc.h>
45 #include <linux/pci.h>
46 #include <linux/ioport.h>
47 #include <linux/delay.h>
48 #include <linux/proc_fs.h>
49 #include <asm/irq.h>
50 #include <asm/io.h>
51 #include <asm/bitops.h>
52 #include <asm/segment.h>
53 #include <asm/system.h>
54
55 #include <pcmcia/version.h>
56 #include <pcmcia/cs_types.h>
57 #include <pcmcia/ss.h>
58 #include <pcmcia/cs.h>
59
60 /* ISA-bus controllers */
61 #include "i82365.h"
62 #include "cirrus.h"
63 #include "vg468.h"
64 #include "ricoh.h"
65 #include "o2micro.h"
66
67 /* PCI-bus controllers */
68 #include "old-yenta.h"
69 #include "smc34c90.h"
70 #include "topic.h"
71
72 #ifdef PCMCIA_DEBUG
73 static int pc_debug = PCMCIA_DEBUG;
74 MODULE_PARM(pc_debug, "i");
75 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
76 static const char *version =
77 "i82365.c 1.265 1999/11/10 18:36:21 (David Hinds)";
78 #else
79 #define DEBUG(n, args...) do { } while (0)
80 #endif
81
82 static void irq_count(int, void *, struct pt_regs *);
83 static inline int _check_irq(int irq, int flags)
84 {
85 if (request_irq(irq, irq_count, flags, "x", irq_count) != 0)
86 return -1;
87 free_irq(irq, irq_count);
88 return 0;
89 }
90
91 /*====================================================================*/
92
93 /* Parameters that can be set with 'insmod' */
94
95 #ifdef CONFIG_ISA
96 /* Default base address for i82365sl and other ISA chips */
97 static int i365_base = 0x3e0;
98 /* Should we probe at 0x3e2 for an extra ISA controller? */
99 static int extra_sockets = 0;
100 /* Specify a socket number to ignore */
101 static int ignore = -1;
102 /* Bit map or list of interrupts to choose from */
103 static u_int irq_mask = 0xffff;
104 static int irq_list[16] = { -1 };
105 /* The card status change interrupt -- 0 means autoselect */
106 static int cs_irq = 0;
107 #endif
108
109 /* Probe for safe interrupts? */
110 static int do_scan = 1;
111 /* Poll status interval -- 0 means default to interrupt */
112 static int poll_interval = 0;
113 /* External clock time, in nanoseconds. 120 ns = 8.33 MHz */
114 static int cycle_time = 120;
115
116 /* Cirrus options */
117 static int has_dma = -1;
118 static int has_led = -1;
119 static int has_ring = -1;
120 static int dynamic_mode = 0;
121 static int freq_bypass = -1;
122 static int setup_time = -1;
123 static int cmd_time = -1;
124 static int recov_time = -1;
125
126 #ifdef CONFIG_ISA
127 /* Vadem options */
128 static int async_clock = -1;
129 static int cable_mode = -1;
130 static int wakeup = 0;
131 #endif
132
133 #ifdef CONFIG_ISA
134 MODULE_PARM(i365_base, "i");
135 MODULE_PARM(ignore, "i");
136 MODULE_PARM(extra_sockets, "i");
137 MODULE_PARM(irq_mask, "i");
138 MODULE_PARM(irq_list, "1-16i");
139 MODULE_PARM(cs_irq, "i");
140 MODULE_PARM(async_clock, "i");
141 MODULE_PARM(cable_mode, "i");
142 MODULE_PARM(wakeup, "i");
143 #endif
144
145 MODULE_PARM(do_scan, "i");
146 MODULE_PARM(poll_interval, "i");
147 MODULE_PARM(cycle_time, "i");
148 MODULE_PARM(has_dma, "i");
149 MODULE_PARM(has_led, "i");
150 MODULE_PARM(has_ring, "i");
151 MODULE_PARM(dynamic_mode, "i");
152 MODULE_PARM(freq_bypass, "i");
153 MODULE_PARM(setup_time, "i");
154 MODULE_PARM(cmd_time, "i");
155 MODULE_PARM(recov_time, "i");
156
157 /*====================================================================*/
158
159 typedef struct cirrus_state_t {
160 u_char misc1, misc2;
161 u_char timer[6];
162 } cirrus_state_t;
163
164 typedef struct vg46x_state_t {
165 u_char ctl, ema;
166 } vg46x_state_t;
167
168 typedef struct socket_info_t {
169 u_short type, flags;
170 socket_cap_t cap;
171 ioaddr_t ioaddr;
172 u_short psock;
173 u_char cs_irq, intr;
174 void (*handler)(void *info, u_int events);
175 void *info;
176 #ifdef CONFIG_PROC_FS
177 struct proc_dir_entry *proc;
178 #endif
179 union {
180 cirrus_state_t cirrus;
181 vg46x_state_t vg46x;
182 } state;
183 } socket_info_t;
184
185 /* Where we keep track of our sockets... */
186 static int sockets = 0;
187 static socket_info_t socket[8] = {
188 { 0, }, /* ... */
189 };
190
191 /* Default ISA interrupt mask */
192 #define I365_MASK 0xdeb8 /* irq 15,14,12,11,10,9,7,5,4,3 */
193
194 #ifdef CONFIG_ISA
195 static int grab_irq;
196 static spinlock_t isa_lock = SPIN_LOCK_UNLOCKED;
197 #define ISA_LOCK(n, f) spin_lock_irqsave(&isa_lock, f)
198 #define ISA_UNLOCK(n, f) spin_unlock_irqrestore(&isa_lock, f)
199 #else
200 #define ISA_LOCK(n, f) do { } while (0)
201 #define ISA_UNLOCK(n, f) do { } while (0)
202 #endif
203
204 static struct timer_list poll_timer;
205
206 /*====================================================================*/
207
208 /* Default settings for PCI command configuration register */
209 #define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
210 PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
211
212 /* These definitions must match the pcic table! */
213 typedef enum pcic_id {
214 #ifdef CONFIG_ISA
215 IS_I82365A, IS_I82365B, IS_I82365DF,
216 IS_IBM, IS_RF5Cx96, IS_VLSI, IS_VG468, IS_VG469,
217 IS_PD6710, IS_PD672X, IS_VT83C469,
218 #endif
219 } pcic_id;
220
221 /* Flags for classifying groups of controllers */
222 #define IS_VADEM 0x0001
223 #define IS_CIRRUS 0x0002
224 #define IS_TI 0x0004
225 #define IS_O2MICRO 0x0008
226 #define IS_VIA 0x0010
227 #define IS_TOPIC 0x0020
228 #define IS_RICOH 0x0040
229 #define IS_UNKNOWN 0x0400
230 #define IS_VG_PWR 0x0800
231 #define IS_DF_PWR 0x1000
232 #define IS_PCI 0x2000
233 #define IS_ALIVE 0x8000
234
235 typedef struct pcic_t {
236 char *name;
237 u_short flags;
238 } pcic_t;
239
240 static pcic_t pcic[] = {
241 #ifdef CONFIG_ISA
242 { "Intel i82365sl A step", 0 },
243 { "Intel i82365sl B step", 0 },
244 { "Intel i82365sl DF", IS_DF_PWR },
245 { "IBM Clone", 0 },
246 { "Ricoh RF5C296/396", 0 },
247 { "VLSI 82C146", 0 },
248 { "Vadem VG-468", IS_VADEM },
249 { "Vadem VG-469", IS_VADEM|IS_VG_PWR },
250 { "Cirrus PD6710", IS_CIRRUS },
251 { "Cirrus PD672x", IS_CIRRUS },
252 { "VIA VT83C469", IS_CIRRUS|IS_VIA },
253 #endif
254 };
255
256 #define PCIC_COUNT (sizeof(pcic)/sizeof(pcic_t))
257
258 /*====================================================================*/
259
260 static u_char i365_get(u_short sock, u_short reg)
261 {
262 {
263 ioaddr_t port = socket[sock].ioaddr;
264 u_char val;
265 reg = I365_REG(socket[sock].psock, reg);
266 outb(reg, port); val = inb(port+1);
267 return val;
268 }
269 }
270
271 static void i365_set(u_short sock, u_short reg, u_char data)
272 {
273 {
274 ioaddr_t port = socket[sock].ioaddr;
275 u_char val = I365_REG(socket[sock].psock, reg);
276 outb(val, port); outb(data, port+1);
277 }
278 }
279
280 static void i365_bset(u_short sock, u_short reg, u_char mask)
281 {
282 u_char d = i365_get(sock, reg);
283 d |= mask;
284 i365_set(sock, reg, d);
285 }
286
287 static void i365_bclr(u_short sock, u_short reg, u_char mask)
288 {
289 u_char d = i365_get(sock, reg);
290 d &= ~mask;
291 i365_set(sock, reg, d);
292 }
293
294 static void i365_bflip(u_short sock, u_short reg, u_char mask, int b)
295 {
296 u_char d = i365_get(sock, reg);
297 if (b)
298 d |= mask;
299 else
300 d &= ~mask;
301 i365_set(sock, reg, d);
302 }
303
304 static u_short i365_get_pair(u_short sock, u_short reg)
305 {
306 u_short a, b;
307 a = i365_get(sock, reg);
308 b = i365_get(sock, reg+1);
309 return (a + (b<<8));
310 }
311
312 static void i365_set_pair(u_short sock, u_short reg, u_short data)
313 {
314 i365_set(sock, reg, data & 0xff);
315 i365_set(sock, reg+1, data >> 8);
316 }
317
318 /*======================================================================
319
320 Code to save and restore global state information for Cirrus
321 PD67xx controllers, and to set and report global configuration
322 options.
323
324 The VIA controllers also use these routines, as they are mostly
325 Cirrus lookalikes, without the timing registers.
326
327 ======================================================================*/
328
329 #define flip(v,b,f) (v = ((f)<0) ? v : ((f) ? ((v)|(b)) : ((v)&(~b))))
330
331 static void cirrus_get_state(u_short s)
332 {
333 int i;
334 cirrus_state_t *p = &socket[s].state.cirrus;
335 p->misc1 = i365_get(s, PD67_MISC_CTL_1);
336 p->misc1 &= (PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
337 p->misc2 = i365_get(s, PD67_MISC_CTL_2);
338 for (i = 0; i < 6; i++)
339 p->timer[i] = i365_get(s, PD67_TIME_SETUP(0)+i);
340 }
341
342 static void cirrus_set_state(u_short s)
343 {
344 int i;
345 u_char misc;
346 cirrus_state_t *p = &socket[s].state.cirrus;
347
348 misc = i365_get(s, PD67_MISC_CTL_2);
349 i365_set(s, PD67_MISC_CTL_2, p->misc2);
350 if (misc & PD67_MC2_SUSPEND) mdelay(50);
351 misc = i365_get(s, PD67_MISC_CTL_1);
352 misc &= ~(PD67_MC1_MEDIA_ENA | PD67_MC1_INPACK_ENA);
353 i365_set(s, PD67_MISC_CTL_1, misc | p->misc1);
354 for (i = 0; i < 6; i++)
355 i365_set(s, PD67_TIME_SETUP(0)+i, p->timer[i]);
356 }
357
358 static u_int __init cirrus_set_opts(u_short s, char *buf)
359 {
360 socket_info_t *t = &socket[s];
361 cirrus_state_t *p = &socket[s].state.cirrus;
362 u_int mask = 0xffff;
363
364 if (has_ring == -1) has_ring = 1;
365 flip(p->misc2, PD67_MC2_IRQ15_RI, has_ring);
366 flip(p->misc2, PD67_MC2_DYNAMIC_MODE, dynamic_mode);
367 if (p->misc2 & PD67_MC2_IRQ15_RI)
368 strcat(buf, " [ring]");
369 if (p->misc2 & PD67_MC2_DYNAMIC_MODE)
370 strcat(buf, " [dyn mode]");
371 if (p->misc1 & PD67_MC1_INPACK_ENA)
372 strcat(buf, " [inpack]");
373 if (!(t->flags & IS_PCI)) {
374 if (p->misc2 & PD67_MC2_IRQ15_RI)
375 mask &= ~0x8000;
376 if (has_led > 0) {
377 strcat(buf, " [led]");
378 mask &= ~0x1000;
379 }
380 if (has_dma > 0) {
381 strcat(buf, " [dma]");
382 mask &= ~0x0600;
383 flip(p->misc2, PD67_MC2_FREQ_BYPASS, freq_bypass);
384 if (p->misc2 & PD67_MC2_FREQ_BYPASS)
385 strcat(buf, " [freq bypass]");
386 }
387 }
388 if (!(t->flags & IS_VIA)) {
389 if (setup_time >= 0)
390 p->timer[0] = p->timer[3] = setup_time;
391 if (cmd_time > 0) {
392 p->timer[1] = cmd_time;
393 p->timer[4] = cmd_time*2+4;
394 }
395 if (p->timer[1] == 0) {
396 p->timer[1] = 6; p->timer[4] = 16;
397 if (p->timer[0] == 0)
398 p->timer[0] = p->timer[3] = 1;
399 }
400 if (recov_time >= 0)
401 p->timer[2] = p->timer[5] = recov_time;
402 buf += strlen(buf);
403 sprintf(buf, " [%d/%d/%d] [%d/%d/%d]", p->timer[0], p->timer[1],
404 p->timer[2], p->timer[3], p->timer[4], p->timer[5]);
405 }
406 return mask;
407 }
408
409 /*======================================================================
410
411 Code to save and restore global state information for Vadem VG468
412 and VG469 controllers, and to set and report global configuration
413 options.
414
415 ======================================================================*/
416
417 #ifdef CONFIG_ISA
418
419 static void vg46x_get_state(u_short s)
420 {
421 vg46x_state_t *p = &socket[s].state.vg46x;
422 p->ctl = i365_get(s, VG468_CTL);
423 if (socket[s].type == IS_VG469)
424 p->ema = i365_get(s, VG469_EXT_MODE);
425 }
426
427 static void vg46x_set_state(u_short s)
428 {
429 vg46x_state_t *p = &socket[s].state.vg46x;
430 i365_set(s, VG468_CTL, p->ctl);
431 if (socket[s].type == IS_VG469)
432 i365_set(s, VG469_EXT_MODE, p->ema);
433 }
434
435 static u_int __init vg46x_set_opts(u_short s, char *buf)
436 {
437 vg46x_state_t *p = &socket[s].state.vg46x;
438
439 flip(p->ctl, VG468_CTL_ASYNC, async_clock);
440 flip(p->ema, VG469_MODE_CABLE, cable_mode);
441 if (p->ctl & VG468_CTL_ASYNC)
442 strcat(buf, " [async]");
443 if (p->ctl & VG468_CTL_INPACK)
444 strcat(buf, " [inpack]");
445 if (socket[s].type == IS_VG469) {
446 u_char vsel = i365_get(s, VG469_VSELECT);
447 if (vsel & VG469_VSEL_EXT_STAT) {
448 strcat(buf, " [ext mode]");
449 if (vsel & VG469_VSEL_EXT_BUS)
450 strcat(buf, " [isa buf]");
451 }
452 if (p->ema & VG469_MODE_CABLE)
453 strcat(buf, " [cable]");
454 if (p->ema & VG469_MODE_COMPAT)
455 strcat(buf, " [c step]");
456 }
457 return 0xffff;
458 }
459
460 #endif
461
462
463 /*======================================================================
464
465 Generic routines to get and set controller options
466
467 ======================================================================*/
468
469 static void get_bridge_state(u_short s)
470 {
471 socket_info_t *t = &socket[s];
472 if (t->flags & IS_CIRRUS)
473 cirrus_get_state(s);
474 #ifdef CONFIG_ISA
475 else if (t->flags & IS_VADEM)
476 vg46x_get_state(s);
477 #endif
478 }
479
480 static void set_bridge_state(u_short s)
481 {
482 socket_info_t *t = &socket[s];
483 if (t->flags & IS_CIRRUS)
484 cirrus_set_state(s);
485 else {
486 i365_set(s, I365_GBLCTL, 0x00);
487 i365_set(s, I365_GENCTL, 0x00);
488 }
489 i365_bflip(s, I365_INTCTL, I365_INTR_ENA, t->intr);
490 #ifdef CONFIG_ISA
491 if (t->flags & IS_VADEM)
492 vg46x_set_state(s);
493 #endif
494 }
495
496 static u_int __init set_bridge_opts(u_short s, u_short ns)
497 {
498 u_short i;
499 u_int m = 0xffff;
500 char buf[128];
501
502 for (i = s; i < s+ns; i++) {
503 if (socket[i].flags & IS_ALIVE) {
504 printk(KERN_INFO " host opts [%d]: already alive!\n", i);
505 continue;
506 }
507 buf[0] = '\0';
508 get_bridge_state(i);
509 if (socket[i].flags & IS_CIRRUS)
510 m = cirrus_set_opts(i, buf);
511 #ifdef CONFIG_ISA
512 else if (socket[i].flags & IS_VADEM)
513 m = vg46x_set_opts(i, buf);
514 #endif
515 set_bridge_state(i);
516 printk(KERN_INFO " host opts [%d]:%s\n", i,
517 (*buf) ? buf : " none");
518 }
519 return m;
520 }
521
522 /*======================================================================
523
524 Interrupt testing code, for ISA and PCI interrupts
525
526 ======================================================================*/
527
528 static volatile u_int irq_hits;
529 static u_short irq_sock;
530
531 static void irq_count(int irq, void *dev, struct pt_regs *regs)
532 {
533 i365_get(irq_sock, I365_CSC);
534 irq_hits++;
535 DEBUG(2, "-> hit on irq %d\n", irq);
536 }
537
538 static u_int __init test_irq(u_short sock, int irq)
539 {
540 DEBUG(2, " testing ISA irq %d\n", irq);
541 if (request_irq(irq, irq_count, 0, "scan", irq_count) != 0)
542 return 1;
543 irq_hits = 0; irq_sock = sock;
544 __set_current_state(TASK_UNINTERRUPTIBLE);
545 schedule_timeout(HZ/100);
546 if (irq_hits) {
547 free_irq(irq, irq_count);
548 DEBUG(2, " spurious hit!\n");
549 return 1;
550 }
551
552 /* Generate one interrupt */
553 i365_set(sock, I365_CSCINT, I365_CSC_DETECT | (irq << 4));
554 i365_bset(sock, I365_GENCTL, I365_CTL_SW_IRQ);
555 udelay(1000);
556
557 free_irq(irq, irq_count);
558
559 /* mask all interrupts */
560 i365_set(sock, I365_CSCINT, 0);
561 DEBUG(2, " hits = %d\n", irq_hits);
562
563 return (irq_hits != 1);
564 }
565
566 #ifdef CONFIG_ISA
567
568 static u_int __init isa_scan(u_short sock, u_int mask0)
569 {
570 u_int mask1 = 0;
571 int i;
572
573 #ifdef __alpha__
574 #define PIC 0x4d0
575 /* Don't probe level-triggered interrupts -- reserved for PCI */
576 mask0 &= ~(inb(PIC) | (inb(PIC+1) << 8));
577 #endif
578
579 if (do_scan) {
580 set_bridge_state(sock);
581 i365_set(sock, I365_CSCINT, 0);
582 for (i = 0; i < 16; i++)
583 if ((mask0 & (1 << i)) && (test_irq(sock, i) == 0))
584 mask1 |= (1 << i);
585 for (i = 0; i < 16; i++)
586 if ((mask1 & (1 << i)) && (test_irq(sock, i) != 0))
587 mask1 ^= (1 << i);
588 }
589
590 printk(KERN_INFO " ISA irqs (");
591 if (mask1) {
592 printk("scanned");
593 } else {
594 /* Fallback: just find interrupts that aren't in use */
595 for (i = 0; i < 16; i++)
596 if ((mask0 & (1 << i)) && (_check_irq(i, 0) == 0))
597 mask1 |= (1 << i);
598 printk("default");
599 /* If scan failed, default to polled status */
600 if (!cs_irq && (poll_interval == 0)) poll_interval = HZ;
601 }
602 printk(") = ");
603
604 for (i = 0; i < 16; i++)
605 if (mask1 & (1<<i))
606 printk("%s%d", ((mask1 & ((1<<i)-1)) ? "," : ""), i);
607 if (mask1 == 0) printk("none!");
608
609 return mask1;
610 }
611
612 #endif /* CONFIG_ISA */
613
614 /*====================================================================*/
615
616 /* Time conversion functions */
617
618 static int to_cycles(int ns)
619 {
620 return ns/cycle_time;
621 }
622
623 static int to_ns(int cycles)
624 {
625 return cycle_time*cycles;
626 }
627
628 /*====================================================================*/
629
630 #ifdef CONFIG_ISA
631
632 static int __init identify(u_short port, u_short sock)
633 {
634 u_char val;
635 int type = -1;
636
637 /* Use the next free entry in the socket table */
638 socket[sockets].ioaddr = port;
639 socket[sockets].psock = sock;
640
641 /* Wake up a sleepy Cirrus controller */
642 if (wakeup) {
643 i365_bclr(sockets, PD67_MISC_CTL_2, PD67_MC2_SUSPEND);
644 /* Pause at least 50 ms */
645 mdelay(50);
646 }
647
648 if ((val = i365_get(sockets, I365_IDENT)) & 0x70)
649 return -1;
650 switch (val) {
651 case 0x82:
652 type = IS_I82365A; break;
653 case 0x83:
654 type = IS_I82365B; break;
655 case 0x84:
656 type = IS_I82365DF; break;
657 case 0x88: case 0x89: case 0x8a:
658 type = IS_IBM; break;
659 }
660
661 /* Check for Vadem VG-468 chips */
662 outb(0x0e, port);
663 outb(0x37, port);
664 i365_bset(sockets, VG468_MISC, VG468_MISC_VADEMREV);
665 val = i365_get(sockets, I365_IDENT);
666 if (val & I365_IDENT_VADEM) {
667 i365_bclr(sockets, VG468_MISC, VG468_MISC_VADEMREV);
668 type = ((val & 7) >= 4) ? IS_VG469 : IS_VG468;
669 }
670
671 /* Check for Ricoh chips */
672 val = i365_get(sockets, RF5C_CHIP_ID);
673 if ((val == RF5C_CHIP_RF5C296) || (val == RF5C_CHIP_RF5C396))
674 type = IS_RF5Cx96;
675
676 /* Check for Cirrus CL-PD67xx chips */
677 i365_set(sockets, PD67_CHIP_INFO, 0);
678 val = i365_get(sockets, PD67_CHIP_INFO);
679 if ((val & PD67_INFO_CHIP_ID) == PD67_INFO_CHIP_ID) {
680 val = i365_get(sockets, PD67_CHIP_INFO);
681 if ((val & PD67_INFO_CHIP_ID) == 0) {
682 type = (val & PD67_INFO_SLOTS) ? IS_PD672X : IS_PD6710;
683 i365_set(sockets, PD67_EXT_INDEX, 0xe5);
684 if (i365_get(sockets, PD67_EXT_INDEX) != 0xe5)
685 type = IS_VT83C469;
686 }
687 }
688 return type;
689 } /* identify */
690
691 #endif
692
693 /*======================================================================
694
695 See if a card is present, powered up, in IO mode, and already
696 bound to a (non PC Card) Linux driver. We leave these alone.
697
698 We make an exception for cards that seem to be serial devices.
699
700 ======================================================================*/
701
702 static int __init is_alive(u_short sock)
703 {
704 u_char stat;
705 u_short start, stop;
706
707 stat = i365_get(sock, I365_STATUS);
708 start = i365_get_pair(sock, I365_IO(0)+I365_W_START);
709 stop = i365_get_pair(sock, I365_IO(0)+I365_W_STOP);
710 if ((stat & I365_CS_DETECT) && (stat & I365_CS_POWERON) &&
711 (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD) &&
712 (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(0)) &&
713 (check_region(start, stop-start+1) != 0) &&
714 ((start & 0xfeef) != 0x02e8))
715 return 1;
716 else
717 return 0;
718 }
719
720 /*====================================================================*/
721
722 static void __init add_socket(u_short port, int psock, int type)
723 {
724 socket[sockets].ioaddr = port;
725 socket[sockets].psock = psock;
726 socket[sockets].type = type;
727 socket[sockets].flags = pcic[type].flags;
728 if (is_alive(sockets))
729 socket[sockets].flags |= IS_ALIVE;
730 sockets++;
731 }
732
733 static void __init add_pcic(int ns, int type)
734 {
735 u_int mask = 0, i, base;
736 int use_pci = 0, isa_irq = 0;
737 socket_info_t *t = &socket[sockets-ns];
738
739 base = sockets-ns;
740 if (t->ioaddr > 0) request_region(t->ioaddr, 2, "i82365");
741
742 if (base == 0) printk("\n");
743 printk(KERN_INFO " %s", pcic[type].name);
744 printk(" ISA-to-PCMCIA at port %#x ofs 0x%02x",
745 t->ioaddr, t->psock*0x40);
746 printk(", %d socket%s\n", ns, ((ns > 1) ? "s" : ""));
747
748 #ifdef CONFIG_ISA
749 /* Set host options, build basic interrupt mask */
750 if (irq_list[0] == -1)
751 mask = irq_mask;
752 else
753 for (i = mask = 0; i < 16; i++)
754 mask |= (1<<irq_list[i]);
755 #endif
756 mask &= I365_MASK & set_bridge_opts(base, ns);
757 #ifdef CONFIG_ISA
758 /* Scan for ISA interrupts */
759 mask = isa_scan(base, mask);
760 #else
761 printk(KERN_INFO " PCI card interrupts,");
762 #endif
763
764 #ifdef CONFIG_ISA
765 /* Poll if only two interrupts available */
766 if (!use_pci && !poll_interval) {
767 u_int tmp = (mask & 0xff20);
768 tmp = tmp & (tmp-1);
769 if ((tmp & (tmp-1)) == 0)
770 poll_interval = HZ;
771 }
772 /* Only try an ISA cs_irq if this is the first controller */
773 if (!use_pci && !grab_irq && (cs_irq || !poll_interval)) {
774 /* Avoid irq 12 unless it is explicitly requested */
775 u_int cs_mask = mask & ((cs_irq) ? (1<<cs_irq) : ~(1<<12));
776 for (cs_irq = 15; cs_irq > 0; cs_irq--)
777 if ((cs_mask & (1 << cs_irq)) &&
778 (_check_irq(cs_irq, 0) == 0))
779 break;
780 if (cs_irq) {
781 grab_irq = 1;
782 isa_irq = cs_irq;
783 printk(" status change on irq %d\n", cs_irq);
784 }
785 }
786 #endif
787
788 if (!use_pci && !isa_irq) {
789 if (poll_interval == 0)
790 poll_interval = HZ;
791 printk(" polling interval = %d ms\n",
792 poll_interval * 1000 / HZ);
793
794 }
795
796 /* Update socket interrupt information, capabilities */
797 for (i = 0; i < ns; i++) {
798 t[i].cap.features |= SS_CAP_PCCARD;
799 t[i].cap.map_size = 0x1000;
800 t[i].cap.irq_mask = mask;
801 t[i].cs_irq = isa_irq;
802 }
803
804 } /* add_pcic */
805
806
807 /*====================================================================*/
808
809 #ifdef CONFIG_ISA
810
811 static void __init isa_probe(void)
812 {
813 int i, j, sock, k, ns, id;
814 ioaddr_t port;
815
816 if (check_region(i365_base, 2) != 0) {
817 if (sockets == 0)
818 printk("port conflict at %#x\n", i365_base);
819 return;
820 }
821
822 id = identify(i365_base, 0);
823 if ((id == IS_I82365DF) && (identify(i365_base, 1) != id)) {
824 for (i = 0; i < 4; i++) {
825 if (i == ignore) continue;
826 port = i365_base + ((i & 1) << 2) + ((i & 2) << 1);
827 sock = (i & 1) << 1;
828 if (identify(port, sock) == IS_I82365DF) {
829 add_socket(port, sock, IS_VLSI);
830 add_pcic(1, IS_VLSI);
831 }
832 }
833 } else {
834 for (i = 0; i < (extra_sockets ? 8 : 4); i += 2) {
835 port = i365_base + 2*(i>>2);
836 sock = (i & 3);
837 id = identify(port, sock);
838 if (id < 0) continue;
839
840 for (j = ns = 0; j < 2; j++) {
841 /* Does the socket exist? */
842 if ((ignore == i+j) || (identify(port, sock+j) < 0))
843 continue;
844 /* Check for bad socket decode */
845 for (k = 0; k <= sockets; k++)
846 i365_set(k, I365_MEM(0)+I365_W_OFF, k);
847 for (k = 0; k <= sockets; k++)
848 if (i365_get(k, I365_MEM(0)+I365_W_OFF) != k)
849 break;
850 if (k <= sockets) break;
851 add_socket(port, sock+j, id); ns++;
852 }
853 if (ns != 0) add_pcic(ns, id);
854 }
855 }
856 }
857
858 #endif
859
860 /*====================================================================*/
861
862 static u_int pending_events[8];
863 static spinlock_t pending_event_lock = SPIN_LOCK_UNLOCKED;
864
865 static void pcic_bh(void *dummy)
866 {
867 u_int events;
868 int i;
869
870 for (i=0; i < sockets; i++) {
871 spin_lock_irq(&pending_event_lock);
872 events = pending_events[i];
873 pending_events[i] = 0;
874 spin_unlock_irq(&pending_event_lock);
875 if (socket[i].handler)
876 socket[i].handler(socket[i].info, events);
877 }
878 }
879
880 static struct tq_struct pcic_task = {
881 routine: pcic_bh
882 };
883
884 static void pcic_interrupt(int irq, void *dev,
885 struct pt_regs *regs)
886 {
887 int i, j, csc;
888 u_int events, active;
889 #ifdef CONFIG_ISA
890 u_long flags = 0;
891 #endif
892
893 DEBUG(4, "i82365: pcic_interrupt(%d)\n", irq);
894
895 for (j = 0; j < 20; j++) {
896 active = 0;
897 for (i = 0; i < sockets; i++) {
898 if ((socket[i].cs_irq != irq) &&
899 (socket[i].cap.pci_irq != irq))
900 continue;
901 ISA_LOCK(i, flags);
902 csc = i365_get(i, I365_CSC);
903 if ((csc == 0) || (!socket[i].handler) ||
904 (i365_get(i, I365_IDENT) & 0x70)) {
905 ISA_UNLOCK(i, flags);
906 continue;
907 }
908 events = (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
909 if (i365_get(i, I365_INTCTL) & I365_PC_IOCARD)
910 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
911 else {
912 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
913 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
914 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
915 }
916 ISA_UNLOCK(i, flags);
917 DEBUG(2, "i82365: socket %d event 0x%02x\n", i, events);
918
919 if (events) {
920 spin_lock(&pending_event_lock);
921 pending_events[i] |= events;
922 spin_unlock(&pending_event_lock);
923 schedule_task(&pcic_task);
924 }
925 active |= events;
926 }
927 if (!active) break;
928 }
929 if (j == 20)
930 printk(KERN_NOTICE "i82365: infinite loop in interrupt handler\n");
931
932 DEBUG(4, "i82365: interrupt done\n");
933 } /* pcic_interrupt */
934
935 static void pcic_interrupt_wrapper(u_long data)
936 {
937 pcic_interrupt(0, NULL, NULL);
938 poll_timer.expires = jiffies + poll_interval;
939 add_timer(&poll_timer);
940 }
941
942 /*====================================================================*/
943
944 static int pcic_register_callback(unsigned int sock, void (*handler)(void *, unsigned int), void * info)
945 {
946 socket[sock].handler = handler;
947 socket[sock].info = info;
948 if (handler == NULL) {
949 MOD_DEC_USE_COUNT;
950 } else {
951 MOD_INC_USE_COUNT;
952 }
953 return 0;
954 } /* pcic_register_callback */
955
956 /*====================================================================*/
957
958 static int pcic_inquire_socket(unsigned int sock, socket_cap_t *cap)
959 {
960 *cap = socket[sock].cap;
961 return 0;
962 } /* pcic_inquire_socket */
963
964 /*====================================================================*/
965
966 static int i365_get_status(u_short sock, u_int *value)
967 {
968 u_int status;
969
970 status = i365_get(sock, I365_STATUS);
971 *value = ((status & I365_CS_DETECT) == I365_CS_DETECT)
972 ? SS_DETECT : 0;
973 if (i365_get(sock, I365_INTCTL) & I365_PC_IOCARD)
974 *value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
975 else {
976 *value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
977 *value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
978 }
979 *value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
980 *value |= (status & I365_CS_READY) ? SS_READY : 0;
981 *value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
982
983 #ifdef CONFIG_ISA
984 if (socket[sock].type == IS_VG469) {
985 status = i365_get(sock, VG469_VSENSE);
986 if (socket[sock].psock & 1) {
987 *value |= (status & VG469_VSENSE_B_VS1) ? 0 : SS_3VCARD;
988 *value |= (status & VG469_VSENSE_B_VS2) ? 0 : SS_XVCARD;
989 } else {
990 *value |= (status & VG469_VSENSE_A_VS1) ? 0 : SS_3VCARD;
991 *value |= (status & VG469_VSENSE_A_VS2) ? 0 : SS_XVCARD;
992 }
993 }
994 #endif
995
996 DEBUG(1, "i82365: GetStatus(%d) = %#4.4x\n", sock, *value);
997 return 0;
998 } /* i365_get_status */
999
1000 /*====================================================================*/
1001
1002 static int i365_get_socket(u_short sock, socket_state_t *state)
1003 {
1004 socket_info_t *t = &socket[sock];
1005 u_char reg, vcc, vpp;
1006
1007 reg = i365_get(sock, I365_POWER);
1008 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
1009 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
1010 vcc = reg & I365_VCC_MASK; vpp = reg & I365_VPP1_MASK;
1011 state->Vcc = state->Vpp = 0;
1012 if (t->flags & IS_CIRRUS) {
1013 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_VCC_3V) {
1014 if (reg & I365_VCC_5V) state->Vcc = 33;
1015 if (vpp == I365_VPP1_5V) state->Vpp = 33;
1016 } else {
1017 if (reg & I365_VCC_5V) state->Vcc = 50;
1018 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1019 }
1020 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1021 } else if (t->flags & IS_VG_PWR) {
1022 if (i365_get(sock, VG469_VSELECT) & VG469_VSEL_VCC) {
1023 if (reg & I365_VCC_5V) state->Vcc = 33;
1024 if (vpp == I365_VPP1_5V) state->Vpp = 33;
1025 } else {
1026 if (reg & I365_VCC_5V) state->Vcc = 50;
1027 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1028 }
1029 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1030 } else if (t->flags & IS_DF_PWR) {
1031 if (vcc == I365_VCC_3V) state->Vcc = 33;
1032 if (vcc == I365_VCC_5V) state->Vcc = 50;
1033 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1034 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1035 } else {
1036 if (reg & I365_VCC_5V) {
1037 state->Vcc = 50;
1038 if (vpp == I365_VPP1_5V) state->Vpp = 50;
1039 if (vpp == I365_VPP1_12V) state->Vpp = 120;
1040 }
1041 }
1042
1043 /* IO card, RESET flags, IO interrupt */
1044 reg = i365_get(sock, I365_INTCTL);
1045 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
1046 if (reg & I365_PC_IOCARD) state->flags |= SS_IOCARD;
1047 state->io_irq = reg & I365_IRQ_MASK;
1048
1049 /* speaker control */
1050 if (t->flags & IS_CIRRUS) {
1051 if (i365_get(sock, PD67_MISC_CTL_1) & PD67_MC1_SPKR_ENA)
1052 state->flags |= SS_SPKR_ENA;
1053 }
1054
1055 /* Card status change mask */
1056 reg = i365_get(sock, I365_CSCINT);
1057 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
1058 if (state->flags & SS_IOCARD)
1059 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
1060 else {
1061 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
1062 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
1063 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
1064 }
1065
1066 DEBUG(1, "i82365: GetSocket(%d) = flags %#3.3x, Vcc %d, Vpp %d, "
1067 "io_irq %d, csc_mask %#2.2x\n", sock, state->flags,
1068 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
1069 return 0;
1070 } /* i365_get_socket */
1071
1072 /*====================================================================*/
1073
1074 static int i365_set_socket(u_short sock, socket_state_t *state)
1075 {
1076 socket_info_t *t = &socket[sock];
1077 u_char reg;
1078
1079 DEBUG(1, "i82365: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
1080 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
1081 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
1082
1083 /* First set global controller options */
1084 set_bridge_state(sock);
1085
1086 /* IO card, RESET flag, IO interrupt */
1087 reg = t->intr;
1088 if (state->io_irq != t->cap.pci_irq) reg |= state->io_irq;
1089 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
1090 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
1091 i365_set(sock, I365_INTCTL, reg);
1092
1093 reg = I365_PWR_NORESET;
1094 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
1095 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
1096
1097 if (t->flags & IS_CIRRUS) {
1098 if (state->Vpp != 0) {
1099 if (state->Vpp == 120)
1100 reg |= I365_VPP1_12V;
1101 else if (state->Vpp == state->Vcc)
1102 reg |= I365_VPP1_5V;
1103 else return -EINVAL;
1104 }
1105 if (state->Vcc != 0) {
1106 reg |= I365_VCC_5V;
1107 if (state->Vcc == 33)
1108 i365_bset(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
1109 else if (state->Vcc == 50)
1110 i365_bclr(sock, PD67_MISC_CTL_1, PD67_MC1_VCC_3V);
1111 else return -EINVAL;
1112 }
1113 } else if (t->flags & IS_VG_PWR) {
1114 if (state->Vpp != 0) {
1115 if (state->Vpp == 120)
1116 reg |= I365_VPP1_12V;
1117 else if (state->Vpp == state->Vcc)
1118 reg |= I365_VPP1_5V;
1119 else return -EINVAL;
1120 }
1121 if (state->Vcc != 0) {
1122 reg |= I365_VCC_5V;
1123 if (state->Vcc == 33)
1124 i365_bset(sock, VG469_VSELECT, VG469_VSEL_VCC);
1125 else if (state->Vcc == 50)
1126 i365_bclr(sock, VG469_VSELECT, VG469_VSEL_VCC);
1127 else return -EINVAL;
1128 }
1129 } else if (t->flags & IS_DF_PWR) {
1130 switch (state->Vcc) {
1131 case 0: break;
1132 case 33: reg |= I365_VCC_3V; break;
1133 case 50: reg |= I365_VCC_5V; break;
1134 default: return -EINVAL;
1135 }
1136 switch (state->Vpp) {
1137 case 0: break;
1138 case 50: reg |= I365_VPP1_5V; break;
1139 case 120: reg |= I365_VPP1_12V; break;
1140 default: return -EINVAL;
1141 }
1142 } else {
1143 switch (state->Vcc) {
1144 case 0: break;
1145 case 50: reg |= I365_VCC_5V; break;
1146 default: return -EINVAL;
1147 }
1148 switch (state->Vpp) {
1149 case 0: break;
1150 case 50: reg |= I365_VPP1_5V | I365_VPP2_5V; break;
1151 case 120: reg |= I365_VPP1_12V | I365_VPP2_12V; break;
1152 default: return -EINVAL;
1153 }
1154 }
1155
1156 if (reg != i365_get(sock, I365_POWER))
1157 i365_set(sock, I365_POWER, reg);
1158
1159 /* Chipset-specific functions */
1160 if (t->flags & IS_CIRRUS) {
1161 /* Speaker control */
1162 i365_bflip(sock, PD67_MISC_CTL_1, PD67_MC1_SPKR_ENA,
1163 state->flags & SS_SPKR_ENA);
1164 }
1165
1166 /* Card status change interrupt mask */
1167 reg = t->cs_irq << 4;
1168 if (state->csc_mask & SS_DETECT) reg |= I365_CSC_DETECT;
1169 if (state->flags & SS_IOCARD) {
1170 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
1171 } else {
1172 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
1173 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
1174 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
1175 }
1176 i365_set(sock, I365_CSCINT, reg);
1177 i365_get(sock, I365_CSC);
1178
1179 return 0;
1180 } /* i365_set_socket */
1181
1182 /*====================================================================*/
1183
1184 static int i365_get_io_map(u_short sock, struct pccard_io_map *io)
1185 {
1186 u_char map, ioctl, addr;
1187
1188 map = io->map;
1189 if (map > 1) return -EINVAL;
1190 io->start = i365_get_pair(sock, I365_IO(map)+I365_W_START);
1191 io->stop = i365_get_pair(sock, I365_IO(map)+I365_W_STOP);
1192 ioctl = i365_get(sock, I365_IOCTL);
1193 addr = i365_get(sock, I365_ADDRWIN);
1194 io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
1195 io->flags = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
1196 io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
1197 io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
1198 io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;
1199 DEBUG(1, "i82365: GetIOMap(%d, %d) = %#2.2x, %d ns, "
1200 "%#4.4x-%#4.4x\n", sock, map, io->flags, io->speed,
1201 io->start, io->stop);
1202 return 0;
1203 } /* i365_get_io_map */
1204
1205 /*====================================================================*/
1206
1207 static int i365_set_io_map(u_short sock, struct pccard_io_map *io)
1208 {
1209 u_char map, ioctl;
1210
1211 DEBUG(1, "i82365: SetIOMap(%d, %d, %#2.2x, %d ns, "
1212 "%#4.4x-%#4.4x)\n", sock, io->map, io->flags,
1213 io->speed, io->start, io->stop);
1214 map = io->map;
1215 if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
1216 (io->stop < io->start)) return -EINVAL;
1217 /* Turn off the window before changing anything */
1218 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_IO(map))
1219 i365_bclr(sock, I365_ADDRWIN, I365_ENA_IO(map));
1220 i365_set_pair(sock, I365_IO(map)+I365_W_START, io->start);
1221 i365_set_pair(sock, I365_IO(map)+I365_W_STOP, io->stop);
1222 ioctl = i365_get(sock, I365_IOCTL) & ~I365_IOCTL_MASK(map);
1223 if (io->speed) ioctl |= I365_IOCTL_WAIT(map);
1224 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
1225 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
1226 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
1227 i365_set(sock, I365_IOCTL, ioctl);
1228 /* Turn on the window if necessary */
1229 if (io->flags & MAP_ACTIVE)
1230 i365_bset(sock, I365_ADDRWIN, I365_ENA_IO(map));
1231 return 0;
1232 } /* i365_set_io_map */
1233
1234 /*====================================================================*/
1235
1236 static int i365_get_mem_map(u_short sock, struct pccard_mem_map *mem)
1237 {
1238 u_short base, i;
1239 u_char map, addr;
1240
1241 map = mem->map;
1242 if (map > 4) return -EINVAL;
1243 addr = i365_get(sock, I365_ADDRWIN);
1244 mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;
1245 base = I365_MEM(map);
1246
1247 i = i365_get_pair(sock, base+I365_W_START);
1248 mem->flags |= (i & I365_MEM_16BIT) ? MAP_16BIT : 0;
1249 mem->flags |= (i & I365_MEM_0WS) ? MAP_0WS : 0;
1250 mem->sys_start += ((u_long)(i & 0x0fff) << 12);
1251
1252 i = i365_get_pair(sock, base+I365_W_STOP);
1253 mem->speed = (i & I365_MEM_WS0) ? 1 : 0;
1254 mem->speed += (i & I365_MEM_WS1) ? 2 : 0;
1255 mem->speed = to_ns(mem->speed);
1256 mem->sys_stop = ((u_long)(i & 0x0fff) << 12) + 0x0fff;
1257
1258 i = i365_get_pair(sock, base+I365_W_OFF);
1259 mem->flags |= (i & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
1260 mem->flags |= (i & I365_MEM_REG) ? MAP_ATTRIB : 0;
1261 mem->card_start = ((u_int)(i & 0x3fff) << 12) + mem->sys_start;
1262 mem->card_start &= 0x3ffffff;
1263
1264 DEBUG(1, "i82365: GetMemMap(%d, %d) = %#2.2x, %d ns, %#5.5lx-%#5."
1265 "5lx, %#5.5x\n", sock, mem->map, mem->flags, mem->speed,
1266 mem->sys_start, mem->sys_stop, mem->card_start);
1267 return 0;
1268 } /* i365_get_mem_map */
1269
1270 /*====================================================================*/
1271
1272 static int i365_set_mem_map(u_short sock, struct pccard_mem_map *mem)
1273 {
1274 u_short base, i;
1275 u_char map;
1276
1277 DEBUG(1, "i82365: SetMemMap(%d, %d, %#2.2x, %d ns, %#5.5lx-%#5.5"
1278 "lx, %#5.5x)\n", sock, mem->map, mem->flags, mem->speed,
1279 mem->sys_start, mem->sys_stop, mem->card_start);
1280
1281 map = mem->map;
1282 if ((map > 4) || (mem->card_start > 0x3ffffff) ||
1283 (mem->sys_start > mem->sys_stop) || (mem->speed > 1000))
1284 return -EINVAL;
1285 if (!(socket[sock].flags & IS_PCI) &&
1286 ((mem->sys_start > 0xffffff) || (mem->sys_stop > 0xffffff)))
1287 return -EINVAL;
1288
1289 /* Turn off the window before changing anything */
1290 if (i365_get(sock, I365_ADDRWIN) & I365_ENA_MEM(map))
1291 i365_bclr(sock, I365_ADDRWIN, I365_ENA_MEM(map));
1292
1293 base = I365_MEM(map);
1294 i = (mem->sys_start >> 12) & 0x0fff;
1295 if (mem->flags & MAP_16BIT) i |= I365_MEM_16BIT;
1296 if (mem->flags & MAP_0WS) i |= I365_MEM_0WS;
1297 i365_set_pair(sock, base+I365_W_START, i);
1298
1299 i = (mem->sys_stop >> 12) & 0x0fff;
1300 switch (to_cycles(mem->speed)) {
1301 case 0: break;
1302 case 1: i |= I365_MEM_WS0; break;
1303 case 2: i |= I365_MEM_WS1; break;
1304 default: i |= I365_MEM_WS1 | I365_MEM_WS0; break;
1305 }
1306 i365_set_pair(sock, base+I365_W_STOP, i);
1307
1308 i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
1309 if (mem->flags & MAP_WRPROT) i |= I365_MEM_WRPROT;
1310 if (mem->flags & MAP_ATTRIB) i |= I365_MEM_REG;
1311 i365_set_pair(sock, base+I365_W_OFF, i);
1312
1313 /* Turn on the window if necessary */
1314 if (mem->flags & MAP_ACTIVE)
1315 i365_bset(sock, I365_ADDRWIN, I365_ENA_MEM(map));
1316 return 0;
1317 } /* i365_set_mem_map */
1318
1319 /*======================================================================
1320
1321 Routines for accessing socket information and register dumps via
1322 /proc/bus/pccard/...
1323
1324 ======================================================================*/
1325
1326 #ifdef CONFIG_PROC_FS
1327
1328 static int proc_read_info(char *buf, char **start, off_t pos,
1329 int count, int *eof, void *data)
1330 {
1331 socket_info_t *s = data;
1332 char *p = buf;
1333 p += sprintf(p, "type: %s\npsock: %d\n",
1334 pcic[s->type].name, s->psock);
1335 return (p - buf);
1336 }
1337
1338 static int proc_read_exca(char *buf, char **start, off_t pos,
1339 int count, int *eof, void *data)
1340 {
1341 u_short sock = (socket_info_t *)data - socket;
1342 char *p = buf;
1343 int i, top;
1344
1345 #ifdef CONFIG_ISA
1346 u_long flags = 0;
1347 #endif
1348 ISA_LOCK(sock, flags);
1349 top = 0x40;
1350 for (i = 0; i < top; i += 4) {
1351 if (i == 0x50) {
1352 p += sprintf(p, "\n");
1353 i = 0x100;
1354 }
1355 p += sprintf(p, "%02x %02x %02x %02x%s",
1356 i365_get(sock,i), i365_get(sock,i+1),
1357 i365_get(sock,i+2), i365_get(sock,i+3),
1358 ((i % 16) == 12) ? "\n" : " ");
1359 }
1360 ISA_UNLOCK(sock, flags);
1361 return (p - buf);
1362 }
1363
1364 static void pcic_proc_setup(unsigned int sock, struct proc_dir_entry *base)
1365 {
1366 socket_info_t *s = &socket[sock];
1367
1368 if (s->flags & IS_ALIVE)
1369 return;
1370
1371 create_proc_read_entry("info", 0, base, proc_read_info, s);
1372 create_proc_read_entry("exca", 0, base, proc_read_exca, s);
1373 s->proc = base;
1374 }
1375
1376 static void pcic_proc_remove(u_short sock)
1377 {
1378 struct proc_dir_entry *base = socket[sock].proc;
1379 if (base == NULL) return;
1380 remove_proc_entry("info", base);
1381 remove_proc_entry("exca", base);
1382 }
1383
1384 #else
1385
1386 #define pcic_proc_setup NULL
1387
1388 #endif /* CONFIG_PROC_FS */
1389
1390 /*====================================================================*/
1391
1392 /*
1393 * The locking is rather broken. Why do we only lock for ISA, not for
1394 * all other cases? If there are reasons to lock, we should lock. Not
1395 * this silly conditional.
1396 *
1397 * Plan: make it bug-for-bug compatible with the old stuff, and clean
1398 * it up when the infrastructure is done.
1399 */
1400 #ifdef CONFIG_ISA
1401 #define LOCKED(x) do { \
1402 int retval; \
1403 unsigned long flags; \
1404 spin_lock_irqsave(&isa_lock, flags); \
1405 retval = x; \
1406 spin_unlock_irqrestore(&isa_lock, flags); \
1407 return retval; \
1408 } while (0)
1409 #else
1410 #define LOCKED(x) return x
1411 #endif
1412
1413
1414 static int pcic_get_status(unsigned int sock, u_int *value)
1415 {
1416 if (socket[sock].flags & IS_ALIVE) {
1417 *value = 0;
1418 return -EINVAL;
1419 }
1420
1421 LOCKED(i365_get_status(sock, value));
1422 }
1423
1424 static int pcic_get_socket(unsigned int sock, socket_state_t *state)
1425 {
1426 if (socket[sock].flags & IS_ALIVE)
1427 return -EINVAL;
1428
1429 LOCKED(i365_get_socket(sock, state));
1430 }
1431
1432 static int pcic_set_socket(unsigned int sock, socket_state_t *state)
1433 {
1434 if (socket[sock].flags & IS_ALIVE)
1435 return -EINVAL;
1436
1437 LOCKED(i365_set_socket(sock, state));
1438 }
1439
1440 static int pcic_get_io_map(unsigned int sock, struct pccard_io_map *io)
1441 {
1442 if (socket[sock].flags & IS_ALIVE)
1443 return -EINVAL;
1444
1445 LOCKED(i365_get_io_map(sock, io));
1446 }
1447
1448 static int pcic_set_io_map(unsigned int sock, struct pccard_io_map *io)
1449 {
1450 if (socket[sock].flags & IS_ALIVE)
1451 return -EINVAL;
1452
1453 LOCKED(i365_set_io_map(sock, io));
1454 }
1455
1456 static int pcic_get_mem_map(unsigned int sock, struct pccard_mem_map *mem)
1457 {
1458 if (socket[sock].flags & IS_ALIVE)
1459 return -EINVAL;
1460
1461 LOCKED(i365_get_mem_map(sock, mem));
1462 }
1463
1464 static int pcic_set_mem_map(unsigned int sock, struct pccard_mem_map *mem)
1465 {
1466 if (socket[sock].flags & IS_ALIVE)
1467 return -EINVAL;
1468
1469 LOCKED(i365_set_mem_map(sock, mem));
1470 }
1471
1472 static int pcic_init(unsigned int s)
1473 {
1474 int i;
1475 pccard_io_map io = { 0, 0, 0, 0, 1 };
1476 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
1477
1478 mem.sys_stop = 0x1000;
1479 pcic_set_socket(s, &dead_socket);
1480 for (i = 0; i < 2; i++) {
1481 io.map = i;
1482 pcic_set_io_map(s, &io);
1483 }
1484 for (i = 0; i < 5; i++) {
1485 mem.map = i;
1486 pcic_set_mem_map(s, &mem);
1487 }
1488 return 0;
1489 }
1490
1491 static int pcic_suspend(unsigned int sock)
1492 {
1493 return pcic_set_socket(sock, &dead_socket);
1494 }
1495
1496 static struct pccard_operations pcic_operations = {
1497 pcic_init,
1498 pcic_suspend,
1499 pcic_register_callback,
1500 pcic_inquire_socket,
1501 pcic_get_status,
1502 pcic_get_socket,
1503 pcic_set_socket,
1504 pcic_get_io_map,
1505 pcic_set_io_map,
1506 pcic_get_mem_map,
1507 pcic_set_mem_map,
1508 pcic_proc_setup
1509 };
1510
1511 /*====================================================================*/
1512
1513 static int __init init_i82365(void)
1514 {
1515 servinfo_t serv;
1516 pcmcia_get_card_services_info(&serv);
1517 if (serv.Revision != CS_RELEASE_CODE) {
1518 printk(KERN_NOTICE "i82365: Card Services release "
1519 "does not match!\n");
1520 return -1;
1521 }
1522 DEBUG(0, "%s\n", version);
1523 printk(KERN_INFO "Intel PCIC probe: ");
1524 sockets = 0;
1525
1526 #ifdef CONFIG_ISA
1527 isa_probe();
1528 #endif
1529
1530 if (sockets == 0) {
1531 printk("not found.\n");
1532 return -ENODEV;
1533 }
1534
1535 /* Set up interrupt handler(s) */
1536 #ifdef CONFIG_ISA
1537 if (grab_irq != 0)
1538 request_irq(cs_irq, pcic_interrupt, 0, "i82365", pcic_interrupt);
1539 #endif
1540
1541 if (register_ss_entry(sockets, &pcic_operations) != 0)
1542 printk(KERN_NOTICE "i82365: register_ss_entry() failed\n");
1543
1544 /* Finally, schedule a polling interrupt */
1545 if (poll_interval != 0) {
1546 poll_timer.function = pcic_interrupt_wrapper;
1547 poll_timer.data = 0;
1548 init_timer(&poll_timer);
1549 poll_timer.expires = jiffies + poll_interval;
1550 add_timer(&poll_timer);
1551 }
1552
1553 return 0;
1554
1555 } /* init_i82365 */
1556
1557 static void __exit exit_i82365(void)
1558 {
1559 int i;
1560 #ifdef CONFIG_PROC_FS
1561 for (i = 0; i < sockets; i++) pcic_proc_remove(i);
1562 #endif
1563 unregister_ss_entry(&pcic_operations);
1564 if (poll_interval != 0)
1565 del_timer(&poll_timer);
1566 #ifdef CONFIG_ISA
1567 if (grab_irq != 0)
1568 free_irq(cs_irq, pcic_interrupt);
1569 #endif
1570 for (i = 0; i < sockets; i++) {
1571 /* Turn off all interrupt sources! */
1572 i365_set(i, I365_CSCINT, 0);
1573 release_region(socket[i].ioaddr, 2);
1574 }
1575 } /* exit_i82365 */
1576
1577 module_init(init_i82365);
1578 module_exit(exit_i82365);
1579
1580 /*====================================================================*/
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