Linux 2.3.7pre1
[davej-history.git] / drivers / char / synclink.c
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1 /*
2 * linux/drivers/char/synclink.c
4 * ==FILEDATE 19990610==
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
36 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
37 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
38 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
39 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
40 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
41 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
42 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
44 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
45 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
46 * OF THE POSSIBILITY OF SUCH DAMAGE.
49 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
50 #define BREAKPOINT() asm(" int $3");
52 #define MAX_ISA_DEVICES 10
54 #include <linux/config.h>
55 #include <linux/module.h>
56 #include <linux/version.h>
57 #include <linux/errno.h>
58 #include <linux/signal.h>
59 #include <linux/sched.h>
60 #include <linux/timer.h>
61 #include <linux/interrupt.h>
62 #include <linux/pci.h>
63 #include <linux/tty.h>
64 #include <linux/tty_flip.h>
65 #include <linux/serial.h>
66 #include <linux/major.h>
67 #include <linux/string.h>
68 #include <linux/fcntl.h>
69 #include <linux/ptrace.h>
70 #include <linux/ioport.h>
71 #include <linux/mm.h>
72 #include <linux/malloc.h>
74 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
75 #include <linux/vmalloc.h>
76 #include <linux/init.h>
77 #include <asm/serial.h>
78 #else
79 #include <linux/bios32.h>
80 #endif
82 #include <linux/delay.h>
83 #include <linux/ioctl.h>
85 #include <asm/system.h>
86 #include <asm/io.h>
87 #include <asm/irq.h>
88 #include <asm/dma.h>
89 #include <asm/bitops.h>
90 #include <asm/types.h>
91 #include <linux/termios.h>
92 #include <linux/tqueue.h>
94 #if LINUX_VERSION_CODE >= VERSION(2,1,4)
95 #include <asm/segment.h>
96 #define GET_USER(error,value,addr) error = get_user(value,addr)
97 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
98 #define PUT_USER(error,value,addr) error = put_user(value,addr)
99 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
101 #if LINUX_VERSION_CODE >= VERSION(2,1,5)
102 #include <asm/uaccess.h>
103 #endif
105 #else /* 2.0.x and 2.1.x before 2.1.4 */
107 #define GET_USER(error,value,addr) \
108 do { \
109 error = verify_area (VERIFY_READ, (void *) addr, sizeof (value)); \
110 if (error == 0) \
111 value = get_user(addr); \
112 } while (0)
114 #define COPY_FROM_USER(error,dest,src,size) \
115 do { \
116 error = verify_area (VERIFY_READ, (void *) src, size); \
117 if (error == 0) \
118 memcpy_fromfs (dest, src, size); \
119 } while (0)
121 #define PUT_USER(error,value,addr) \
122 do { \
123 error = verify_area (VERIFY_WRITE, (void *) addr, sizeof (value)); \
124 if (error == 0) \
125 put_user (value, addr); \
126 } while (0)
128 #define COPY_TO_USER(error,dest,src,size) \
129 do { \
130 error = verify_area (VERIFY_WRITE, (void *) dest, size); \
131 if (error == 0) \
132 memcpy_tofs (dest, src, size); \
133 } while (0)
135 #endif
137 #if LINUX_VERSION_CODE < VERSION(2,1,0)
139 * This is used to figure out the divisor speeds and the timeouts
141 static int baud_table[] = {
142 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800,
143 9600, 19200, 38400, 57600, 115200, 230400, 460800, 0 };
145 #define __init
146 #define ioremap(a,b) vremap((a),(b))
147 #define iounmap(a) vfree((a))
148 #define SERIAL_TYPE_NORMAL 1
149 #define SERIAL_TYPE_CALLOUT 2
150 typedef int spinlock_t;
151 #define spin_lock_irqsave(a,b) {save_flags((b));cli();}
152 #define spin_unlock_irqrestore(a,b) {restore_flags((b));}
153 #define spin_lock(a)
154 #define spin_unlock(a)
155 #define schedule_timeout(a){current->timeout = jiffies + (a); schedule();}
156 #define signal_pending(a) ((a)->signal & ~(a)->blocked)
157 #endif
161 #include "linux/synclink.h"
163 #define RCLRVALUE 0xffff
165 MGSL_PARAMS default_params = {
166 MGSL_MODE_HDLC, /* unsigned long mode */
167 0, /* unsigned char loopback; */
168 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
169 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
170 0, /* unsigned long clock_speed; */
171 0xff, /* unsigned char addr_filter; */
172 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
173 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
174 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
175 9600, /* unsigned long data_rate; */
176 8, /* unsigned char data_bits; */
177 1, /* unsigned char stop_bits; */
178 ASYNC_PARITY_NONE /* unsigned char parity; */
181 #define SHARED_MEM_ADDRESS_SIZE 0x40000
182 #define BUFFERLISTSIZE (PAGE_SIZE)
183 #define DMABUFFERSIZE (PAGE_SIZE)
184 #define MAXRXFRAMES 7
186 typedef struct _DMABUFFERENTRY
188 u32 phys_addr; /* 32-bit flat physical address of data buffer */
189 u16 count; /* buffer size/data count */
190 u16 status; /* Control/status field */
191 u16 rcc; /* character count field */
192 u16 reserved; /* padding required by 16C32 */
193 u32 link; /* 32-bit flat link to next buffer entry */
194 char *virt_addr; /* virtual address of data buffer */
195 u32 phys_entry; /* physical address of this buffer entry */
196 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
198 /* The queue of BH actions to be performed */
200 #define BH_TYPE_RECEIVE_DATA 1
201 #define BH_TYPE_RECEIVE_STATUS 2
202 #define BH_TYPE_RECEIVE_DMA 3
203 #define BH_TYPE_TRANSMIT_DATA 4
204 #define BH_TYPE_TRANSMIT_STATUS 5
205 #define BH_TYPE_STATUS 6
207 typedef struct _BH_EVENT {
208 unsigned char type; /* Set by interrupt routines to reqst */
209 u16 status;
210 struct _BH_EVENT *link;
212 } BH_EVENT, *BH_QUEUE; /* Queue of BH actions to be done. */
214 #define MAX_BH_QUEUE_ENTRIES 200
215 #define IO_PIN_SHUTDOWN_LIMIT (MAX_BH_QUEUE_ENTRIES/4)
217 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
219 struct _input_signal_events {
220 int ri_up;
221 int ri_down;
222 int dsr_up;
223 int dsr_down;
224 int dcd_up;
225 int dcd_down;
226 int cts_up;
227 int cts_down;
231 * Device instance data structure
234 struct mgsl_struct {
235 int magic;
236 int flags;
237 int count; /* count of opens */
238 int line;
239 unsigned short close_delay;
240 unsigned short closing_wait; /* time to wait before closing */
242 struct mgsl_icount icount;
244 struct termios normal_termios;
245 struct termios callout_termios;
247 struct tty_struct *tty;
248 int timeout;
249 int x_char; /* xon/xoff character */
250 int blocked_open; /* # of blocked opens */
251 long session; /* Session of opening process */
252 long pgrp; /* pgrp of opening process */
253 u16 read_status_mask;
254 u16 ignore_status_mask;
255 unsigned char *xmit_buf;
256 int xmit_head;
257 int xmit_tail;
258 int xmit_cnt;
260 wait_queue_head_t open_wait;
261 wait_queue_head_t close_wait;
263 wait_queue_head_t status_event_wait_q;
264 wait_queue_head_t event_wait_q;
265 struct timer_list tx_timer; /* HDLC transmit timeout timer */
266 struct mgsl_struct *next_device; /* device list link */
268 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
269 struct tq_struct task; /* task structure for scheduling bh */
271 u32 EventMask; /* event trigger mask */
272 u32 RecordedEvents; /* pending events */
274 u32 max_frame_size; /* as set by device config */
276 BH_EVENT bh_queue[MAX_BH_QUEUE_ENTRIES]; /* Pointer to alloc'ed block */
277 BH_QUEUE bh_queue_head; /* Queue of BH actions */
278 BH_QUEUE bh_queue_tail; /* Tail of above for perf. */
279 BH_QUEUE free_bh_queue_head; /* Queue of Free BH */
280 BH_QUEUE free_bh_queue_tail; /* Tail of above for perf. */
281 BH_QUEUE bh_action; /* Action for BH */
282 int bh_running; /* Protection from multiple */
283 int isr_overflow;
284 int bh_requested;
286 int dcd_chkcount; /* check counts to prevent */
287 int cts_chkcount; /* too many IRQs if a signal */
288 int dsr_chkcount; /* is floating */
289 int ri_chkcount;
291 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
292 unsigned long buffer_list_phys;
294 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
295 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
296 unsigned int current_rx_buffer;
298 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
299 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
301 int rx_enabled;
302 int rx_overflow;
304 int tx_enabled;
305 int tx_active;
306 u32 idle_mode;
308 u16 cmr_value;
310 char device_name[25]; /* device instance name */
312 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
313 unsigned char bus; /* expansion bus number (zero based) */
314 unsigned char function; /* PCI device number */
316 unsigned int io_base; /* base I/O address of adapter */
317 unsigned int io_addr_size; /* size of the I/O address range */
318 int io_addr_requested; /* nonzero if I/O address requested */
320 unsigned int irq_level; /* interrupt level */
321 unsigned long irq_flags;
322 int irq_requested; /* nonzero if IRQ requested */
324 unsigned int dma_level; /* DMA channel */
325 int dma_requested; /* nonzero if dma channel requested */
327 u16 mbre_bit;
328 u16 loopback_bits;
329 u16 usc_idle_mode;
331 MGSL_PARAMS params; /* communications parameters */
333 unsigned char serial_signals; /* current serial signal states */
335 int irq_occurred; /* for diagnostics use */
336 unsigned int init_error; /* Initialization startup error (DIAGS) */
337 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
339 u32 last_mem_alloc;
340 unsigned char* memory_base; /* shared memory address (PCI only) */
341 u32 phys_memory_base;
343 unsigned char* lcr_base; /* local config registers (PCI only) */
344 u32 phys_lcr_base;
345 u32 lcr_offset;
347 u32 misc_ctrl_value;
348 char flag_buf[HDLC_MAX_FRAME_SIZE];
349 char char_buf[HDLC_MAX_FRAME_SIZE];
350 BOOLEAN drop_rts_on_tx_done;
352 BOOLEAN loopmode_insert_requested;
353 BOOLEAN loopmode_send_done_requested;
355 struct _input_signal_events input_signal_events;
358 #define MGSL_MAGIC 0x5401
361 * The size of the serial xmit buffer is 1 page, or 4096 bytes
363 #define SERIAL_XMIT_SIZE 4096
367 * These macros define the offsets used in calculating the
368 * I/O address of the specified USC registers.
372 #define DCPIN 2 /* Bit 1 of I/O address */
373 #define SDPIN 4 /* Bit 2 of I/O address */
375 #define DCAR 0 /* DMA command/address register */
376 #define CCAR SDPIN /* channel command/address register */
377 #define DATAREG DCPIN + SDPIN /* serial data register */
378 #define MSBONLY 0x41
379 #define LSBONLY 0x40
382 * These macros define the register address (ordinal number)
383 * used for writing address/value pairs to the USC.
386 #define CMR 0x02 /* Channel mode Register */
387 #define CCSR 0x04 /* Channel Command/status Register */
388 #define CCR 0x06 /* Channel Control Register */
389 #define PSR 0x08 /* Port status Register */
390 #define PCR 0x0a /* Port Control Register */
391 #define TMDR 0x0c /* Test mode Data Register */
392 #define TMCR 0x0e /* Test mode Control Register */
393 #define CMCR 0x10 /* Clock mode Control Register */
394 #define HCR 0x12 /* Hardware Configuration Register */
395 #define IVR 0x14 /* Interrupt Vector Register */
396 #define IOCR 0x16 /* Input/Output Control Register */
397 #define ICR 0x18 /* Interrupt Control Register */
398 #define DCCR 0x1a /* Daisy Chain Control Register */
399 #define MISR 0x1c /* Misc Interrupt status Register */
400 #define SICR 0x1e /* status Interrupt Control Register */
401 #define RDR 0x20 /* Receive Data Register */
402 #define RMR 0x22 /* Receive mode Register */
403 #define RCSR 0x24 /* Receive Command/status Register */
404 #define RICR 0x26 /* Receive Interrupt Control Register */
405 #define RSR 0x28 /* Receive Sync Register */
406 #define RCLR 0x2a /* Receive count Limit Register */
407 #define RCCR 0x2c /* Receive Character count Register */
408 #define TC0R 0x2e /* Time Constant 0 Register */
409 #define TDR 0x30 /* Transmit Data Register */
410 #define TMR 0x32 /* Transmit mode Register */
411 #define TCSR 0x34 /* Transmit Command/status Register */
412 #define TICR 0x36 /* Transmit Interrupt Control Register */
413 #define TSR 0x38 /* Transmit Sync Register */
414 #define TCLR 0x3a /* Transmit count Limit Register */
415 #define TCCR 0x3c /* Transmit Character count Register */
416 #define TC1R 0x3e /* Time Constant 1 Register */
420 * MACRO DEFINITIONS FOR DMA REGISTERS
423 #define DCR 0x06 /* DMA Control Register (shared) */
424 #define DACR 0x08 /* DMA Array count Register (shared) */
425 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
426 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
427 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
428 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
429 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
431 #define TDMR 0x02 /* Transmit DMA mode Register */
432 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
433 #define TBCR 0x2a /* Transmit Byte count Register */
434 #define TARL 0x2c /* Transmit Address Register (low) */
435 #define TARU 0x2e /* Transmit Address Register (high) */
436 #define NTBCR 0x3a /* Next Transmit Byte count Register */
437 #define NTARL 0x3c /* Next Transmit Address Register (low) */
438 #define NTARU 0x3e /* Next Transmit Address Register (high) */
440 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
441 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
442 #define RBCR 0xaa /* Receive Byte count Register */
443 #define RARL 0xac /* Receive Address Register (low) */
444 #define RARU 0xae /* Receive Address Register (high) */
445 #define NRBCR 0xba /* Next Receive Byte count Register */
446 #define NRARL 0xbc /* Next Receive Address Register (low) */
447 #define NRARU 0xbe /* Next Receive Address Register (high) */
451 * MACRO DEFINITIONS FOR MODEM STATUS BITS
454 #define MODEMSTATUS_DTR 0x80
455 #define MODEMSTATUS_DSR 0x40
456 #define MODEMSTATUS_RTS 0x20
457 #define MODEMSTATUS_CTS 0x10
458 #define MODEMSTATUS_RI 0x04
459 #define MODEMSTATUS_DCD 0x01
463 * Channel Command/Address Register (CCAR) Command Codes
466 #define RTCmd_Null 0x0000
467 #define RTCmd_ResetHighestIus 0x1000
468 #define RTCmd_TriggerChannelLoadDma 0x2000
469 #define RTCmd_TriggerRxDma 0x2800
470 #define RTCmd_TriggerTxDma 0x3000
471 #define RTCmd_TriggerRxAndTxDma 0x3800
472 #define RTCmd_PurgeRxFifo 0x4800
473 #define RTCmd_PurgeTxFifo 0x5000
474 #define RTCmd_PurgeRxAndTxFifo 0x5800
475 #define RTCmd_LoadRcc 0x6800
476 #define RTCmd_LoadTcc 0x7000
477 #define RTCmd_LoadRccAndTcc 0x7800
478 #define RTCmd_LoadTC0 0x8800
479 #define RTCmd_LoadTC1 0x9000
480 #define RTCmd_LoadTC0AndTC1 0x9800
481 #define RTCmd_SerialDataLSBFirst 0xa000
482 #define RTCmd_SerialDataMSBFirst 0xa800
483 #define RTCmd_SelectBigEndian 0xb000
484 #define RTCmd_SelectLittleEndian 0xb800
488 * DMA Command/Address Register (DCAR) Command Codes
491 #define DmaCmd_Null 0x0000
492 #define DmaCmd_ResetTxChannel 0x1000
493 #define DmaCmd_ResetRxChannel 0x1200
494 #define DmaCmd_StartTxChannel 0x2000
495 #define DmaCmd_StartRxChannel 0x2200
496 #define DmaCmd_ContinueTxChannel 0x3000
497 #define DmaCmd_ContinueRxChannel 0x3200
498 #define DmaCmd_PauseTxChannel 0x4000
499 #define DmaCmd_PauseRxChannel 0x4200
500 #define DmaCmd_AbortTxChannel 0x5000
501 #define DmaCmd_AbortRxChannel 0x5200
502 #define DmaCmd_InitTxChannel 0x7000
503 #define DmaCmd_InitRxChannel 0x7200
504 #define DmaCmd_ResetHighestDmaIus 0x8000
505 #define DmaCmd_ResetAllChannels 0x9000
506 #define DmaCmd_StartAllChannels 0xa000
507 #define DmaCmd_ContinueAllChannels 0xb000
508 #define DmaCmd_PauseAllChannels 0xc000
509 #define DmaCmd_AbortAllChannels 0xd000
510 #define DmaCmd_InitAllChannels 0xf000
512 #define TCmd_Null 0x0000
513 #define TCmd_ClearTxCRC 0x2000
514 #define TCmd_SelectTicrTtsaData 0x4000
515 #define TCmd_SelectTicrTxFifostatus 0x5000
516 #define TCmd_SelectTicrIntLevel 0x6000
517 #define TCmd_SelectTicrdma_level 0x7000
518 #define TCmd_SendFrame 0x8000
519 #define TCmd_SendAbort 0x9000
520 #define TCmd_EnableDleInsertion 0xc000
521 #define TCmd_DisableDleInsertion 0xd000
522 #define TCmd_ClearEofEom 0xe000
523 #define TCmd_SetEofEom 0xf000
525 #define RCmd_Null 0x0000
526 #define RCmd_ClearRxCRC 0x2000
527 #define RCmd_EnterHuntmode 0x3000
528 #define RCmd_SelectRicrRtsaData 0x4000
529 #define RCmd_SelectRicrRxFifostatus 0x5000
530 #define RCmd_SelectRicrIntLevel 0x6000
531 #define RCmd_SelectRicrdma_level 0x7000
534 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
537 #define RECEIVE_STATUS BIT5
538 #define RECEIVE_DATA BIT4
539 #define TRANSMIT_STATUS BIT3
540 #define TRANSMIT_DATA BIT2
541 #define IO_PIN BIT1
542 #define MISC BIT0
546 * Receive status Bits in Receive Command/status Register RCSR
549 #define RXSTATUS_SHORT_FRAME BIT8
550 #define RXSTATUS_CODE_VIOLATION BIT8
551 #define RXSTATUS_EXITED_HUNT BIT7
552 #define RXSTATUS_IDLE_RECEIVED BIT6
553 #define RXSTATUS_BREAK_RECEIVED BIT5
554 #define RXSTATUS_ABORT_RECEIVED BIT5
555 #define RXSTATUS_RXBOUND BIT4
556 #define RXSTATUS_CRC_ERROR BIT3
557 #define RXSTATUS_FRAMING_ERROR BIT3
558 #define RXSTATUS_ABORT BIT2
559 #define RXSTATUS_PARITY_ERROR BIT2
560 #define RXSTATUS_OVERRUN BIT1
561 #define RXSTATUS_DATA_AVAILABLE BIT0
562 #define RXSTATUS_ALL 0x01f6
563 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
566 * Values for setting transmit idle mode in
567 * Transmit Control/status Register (TCSR)
569 #define IDLEMODE_FLAGS 0x0000
570 #define IDLEMODE_ALT_ONE_ZERO 0x0100
571 #define IDLEMODE_ZERO 0x0200
572 #define IDLEMODE_ONE 0x0300
573 #define IDLEMODE_ALT_MARK_SPACE 0x0500
574 #define IDLEMODE_SPACE 0x0600
575 #define IDLEMODE_MARK 0x0700
578 * Transmit status Bits in Transmit Command/status Register (TCSR)
581 #define TCSR_PRESERVE 0x0700
583 #define TXSTATUS_PREAMBLE_SENT BIT7
584 #define TXSTATUS_IDLE_SENT BIT6
585 #define TXSTATUS_ABORT_SENT BIT5
586 #define TXSTATUS_EOF_SENT BIT4
587 #define TXSTATUS_EOM_SENT BIT4
588 #define TXSTATUS_CRC_SENT BIT3
589 #define TXSTATUS_ALL_SENT BIT2
590 #define TXSTATUS_UNDERRUN BIT1
591 #define TXSTATUS_FIFO_EMPTY BIT0
592 #define TXSTATUS_ALL 0x00fa
593 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->usc_idle_mode + ((b) & 0x00FF)) )
596 #define MISCSTATUS_RXC_LATCHED BIT15
597 #define MISCSTATUS_RXC BIT14
598 #define MISCSTATUS_TXC_LATCHED BIT13
599 #define MISCSTATUS_TXC BIT12
600 #define MISCSTATUS_RI_LATCHED BIT11
601 #define MISCSTATUS_RI BIT10
602 #define MISCSTATUS_DSR_LATCHED BIT9
603 #define MISCSTATUS_DSR BIT8
604 #define MISCSTATUS_DCD_LATCHED BIT7
605 #define MISCSTATUS_DCD BIT6
606 #define MISCSTATUS_CTS_LATCHED BIT5
607 #define MISCSTATUS_CTS BIT4
608 #define MISCSTATUS_RCC_UNDERRUN BIT3
609 #define MISCSTATUS_DPLL_NO_SYNC BIT2
610 #define MISCSTATUS_BRG1_ZERO BIT1
611 #define MISCSTATUS_BRG0_ZERO BIT0
613 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
614 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
616 #define SICR_RXC_ACTIVE BIT15
617 #define SICR_RXC_INACTIVE BIT14
618 #define SICR_RXC (BIT15+BIT14)
619 #define SICR_TXC_ACTIVE BIT13
620 #define SICR_TXC_INACTIVE BIT12
621 #define SICR_TXC (BIT13+BIT12)
622 #define SICR_RI_ACTIVE BIT11
623 #define SICR_RI_INACTIVE BIT10
624 #define SICR_RI (BIT11+BIT10)
625 #define SICR_DSR_ACTIVE BIT9
626 #define SICR_DSR_INACTIVE BIT8
627 #define SICR_DSR (BIT9+BIT8)
628 #define SICR_DCD_ACTIVE BIT7
629 #define SICR_DCD_INACTIVE BIT6
630 #define SICR_DCD (BIT7+BIT6)
631 #define SICR_CTS_ACTIVE BIT5
632 #define SICR_CTS_INACTIVE BIT4
633 #define SICR_CTS (BIT5+BIT4)
634 #define SICR_RCC_UNDERFLOW BIT3
635 #define SICR_DPLL_NO_SYNC BIT2
636 #define SICR_BRG1_ZERO BIT1
637 #define SICR_BRG0_ZERO BIT0
639 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
640 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
641 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
642 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
643 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
645 #define usc_EnableInterrupts( a, b ) \
646 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
648 #define usc_DisableInterrupts( a, b ) \
649 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
651 #define usc_EnableMasterIrqBit(a) \
652 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
654 #define usc_DisableMasterIrqBit(a) \
655 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
657 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
660 * Transmit status Bits in Transmit Control status Register (TCSR)
661 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
664 #define TXSTATUS_PREAMBLE_SENT BIT7
665 #define TXSTATUS_IDLE_SENT BIT6
666 #define TXSTATUS_ABORT_SENT BIT5
667 #define TXSTATUS_EOF BIT4
668 #define TXSTATUS_CRC_SENT BIT3
669 #define TXSTATUS_ALL_SENT BIT2
670 #define TXSTATUS_UNDERRUN BIT1
671 #define TXSTATUS_FIFO_EMPTY BIT0
673 #define DICR_MASTER BIT15
674 #define DICR_TRANSMIT BIT0
675 #define DICR_RECEIVE BIT1
677 #define usc_EnableDmaInterrupts(a,b) \
678 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
680 #define usc_DisableDmaInterrupts(a,b) \
681 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
683 #define usc_EnableStatusIrqs(a,b) \
684 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
686 #define usc_DisablestatusIrqs(a,b) \
687 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
689 /* Transmit status Bits in Transmit Control status Register (TCSR) */
690 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
693 #define DISABLE_UNCONDITIONAL 0
694 #define DISABLE_END_OF_FRAME 1
695 #define ENABLE_UNCONDITIONAL 2
696 #define ENABLE_AUTO_CTS 3
697 #define ENABLE_AUTO_DCD 3
698 #define usc_EnableTransmitter(a,b) \
699 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
700 #define usc_EnableReceiver(a,b) \
701 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
703 u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
704 void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
705 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
707 u16 usc_InReg( struct mgsl_struct *info, u16 Port );
708 void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
709 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
710 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
711 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
713 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->usc_idle_mode + (b)))
714 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
716 void usc_start_receiver( struct mgsl_struct *info );
717 void usc_stop_receiver( struct mgsl_struct *info );
719 void usc_start_transmitter( struct mgsl_struct *info );
720 void usc_stop_transmitter( struct mgsl_struct *info );
721 void usc_set_txidle( struct mgsl_struct *info );
722 void usc_load_txfifo( struct mgsl_struct *info );
724 void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
725 void usc_enable_loopback( struct mgsl_struct *info, int enable );
727 void usc_get_serial_signals( struct mgsl_struct *info );
728 void usc_set_serial_signals( struct mgsl_struct *info );
730 void usc_reset( struct mgsl_struct *info );
732 void usc_set_sync_mode( struct mgsl_struct *info );
733 void usc_set_sdlc_mode( struct mgsl_struct *info );
734 void usc_set_async_mode( struct mgsl_struct *info );
735 void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
737 void usc_loopback_frame( struct mgsl_struct *info );
739 void mgsl_tx_timeout(unsigned long context);
742 void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
743 void usc_loopmode_insert_request( struct mgsl_struct * info );
744 int usc_loopmode_active( struct mgsl_struct * info);
745 void usc_loopmode_send_done( struct mgsl_struct * info );
746 int usc_loopmode_send_active( struct mgsl_struct * info );
749 * Defines a BUS descriptor value for the PCI adapter
750 * local bus address ranges.
753 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
754 (0x00400020 + \
755 ((WrHold) << 30) + \
756 ((WrDly) << 28) + \
757 ((RdDly) << 26) + \
758 ((Nwdd) << 20) + \
759 ((Nwad) << 15) + \
760 ((Nxda) << 13) + \
761 ((Nrdd) << 11) + \
762 ((Nrad) << 6) )
764 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
767 * Adapter diagnostic routines
769 BOOLEAN mgsl_register_test( struct mgsl_struct *info );
770 BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
771 BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
772 BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
773 int mgsl_adapter_test( struct mgsl_struct *info );
776 * device and resource management routines
778 int mgsl_claim_resources(struct mgsl_struct *info);
779 void mgsl_release_resources(struct mgsl_struct *info);
780 void mgsl_add_device(struct mgsl_struct *info);
781 struct mgsl_struct* mgsl_allocate_device(void);
782 int mgsl_enumerate_devices(void);
785 * DMA buffer manupulation functions.
787 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
788 int mgsl_get_rx_frame( struct mgsl_struct *info );
789 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
790 void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
791 void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
794 * DMA and Shared Memory buffer allocation and formatting
796 int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
797 void mgsl_free_dma_buffers(struct mgsl_struct *info);
798 int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
799 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
800 int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
801 void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
804 * Bottom half interrupt handlers
806 void mgsl_bh_handler(void* Context);
807 void mgsl_bh_receive_dma( struct mgsl_struct *info, unsigned short status );
808 void mgsl_bh_transmit_data( struct mgsl_struct *info, unsigned short Datacount );
809 void mgsl_bh_status_handler( struct mgsl_struct *info, unsigned short status );
811 void mgsl_format_bh_queue( struct mgsl_struct *info );
812 void mgsl_bh_queue_put( struct mgsl_struct *info, unsigned char type, unsigned short status );
813 int mgsl_bh_queue_get( struct mgsl_struct *info );
817 * Interrupt handler routines and dispatch table.
819 void mgsl_isr_null( struct mgsl_struct *info );
820 void mgsl_isr_transmit_data( struct mgsl_struct *info );
821 void mgsl_isr_receive_data( struct mgsl_struct *info );
822 void mgsl_isr_receive_status( struct mgsl_struct *info );
823 void mgsl_isr_transmit_status( struct mgsl_struct *info );
824 void mgsl_isr_io_pin( struct mgsl_struct *info );
825 void mgsl_isr_misc( struct mgsl_struct *info );
826 void mgsl_isr_receive_dma( struct mgsl_struct *info );
828 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
830 isr_dispatch_func UscIsrTable[7] =
832 mgsl_isr_null,
833 mgsl_isr_misc,
834 mgsl_isr_io_pin,
835 mgsl_isr_transmit_data,
836 mgsl_isr_transmit_status,
837 mgsl_isr_receive_data,
838 mgsl_isr_receive_status
842 * ioctl call handlers
844 static int set_modem_info(struct mgsl_struct * info, unsigned int cmd,
845 unsigned int *value);
846 static int get_modem_info(struct mgsl_struct * info, unsigned int *value);
847 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
848 *user_icount);
849 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params);
850 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params);
851 static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode);
852 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
853 static int mgsl_txenable(struct mgsl_struct * info, int enable);
854 static int mgsl_txabort(struct mgsl_struct * info);
855 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
856 static int mgsl_wait_event(struct mgsl_struct * info, int * mask);
857 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
859 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
862 * Global linked list of SyncLink devices
864 struct mgsl_struct *mgsl_device_list = NULL;
865 int mgsl_device_count = 0;
868 * Set this param to non-zero to load eax with the
869 * .text section address and breakpoint on module load.
870 * This is useful for use with gdb and add-symbol-file command.
872 int break_on_load=0;
875 * Driver major number, defaults to zero to get auto
876 * assigned major number. May be forced as module parameter.
878 int ttymajor=0;
880 int cuamajor=0;
883 * Array of user specified options for ISA adapters.
885 static int io[MAX_ISA_DEVICES] = {0,};
886 static int irq[MAX_ISA_DEVICES] = {0,};
887 static int dma[MAX_ISA_DEVICES] = {0,};
888 static int debug_level = 0;
891 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
892 MODULE_PARM(break_on_load,"i");
893 MODULE_PARM(ttymajor,"i");
894 MODULE_PARM(cuamajor,"i");
895 MODULE_PARM(io,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
896 MODULE_PARM(irq,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
897 MODULE_PARM(dma,"1-" __MODULE_STRING(MAX_ISA_DEVICES) "i");
898 MODULE_PARM(debug_level,"i");
899 #endif
901 static char *driver_name = "SyncLink serial driver";
902 static char *driver_version = "1.7";
904 static struct tty_driver serial_driver, callout_driver;
905 static int serial_refcount;
907 /* number of characters left in xmit buffer before we ask for more */
908 #define WAKEUP_CHARS 256
911 static void mgsl_change_params(struct mgsl_struct *info);
912 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
914 static struct tty_struct **serial_table = NULL;
915 static struct termios **serial_termios = NULL;
916 static struct termios **serial_termios_locked = NULL;
918 #ifndef MIN
919 #define MIN(a,b) ((a) < (b) ? (a) : (b))
920 #endif
923 * 1st function defined in .text section. Calling this function in
924 * init_module() followed by a breakpoint allows a remote debugger
925 * (gdb) to get the .text address for the add-symbol-file command.
926 * This allows remote debugging of dynamically loadable modules.
928 void* mgsl_get_text_ptr(void);
929 void* mgsl_get_text_ptr() {return mgsl_get_text_ptr;}
932 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
933 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
934 * and some other program tries to do a serial write at the same time.
935 * Since the lock will only come under contention when the system is
936 * swapping and available memory is low, it makes sense to share one
937 * buffer across all the serial ioports, since it significantly saves
938 * memory if large numbers of serial ports are open.
940 static unsigned char *tmp_buf;
941 static DECLARE_MUTEX(tmp_buf_sem);
943 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
944 kdev_t device, const char *routine)
946 #ifdef MGSL_PARANOIA_CHECK
947 static const char *badmagic =
948 "Warning: bad magic number for mgsl struct (%s) in %s\n";
949 static const char *badinfo =
950 "Warning: null mgsl_struct for (%s) in %s\n";
952 if (!info) {
953 printk(badinfo, kdevname(device), routine);
954 return 1;
956 if (info->magic != MGSL_MAGIC) {
957 printk(badmagic, kdevname(device), routine);
958 return 1;
960 #endif
961 return 0;
964 /* mgsl_stop() throttle (stop) transmitter
966 * Arguments: tty pointer to tty info structure
967 * Return Value: None
969 static void mgsl_stop(struct tty_struct *tty)
971 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
972 unsigned long flags;
974 if (mgsl_paranoia_check(info, tty->device, "mgsl_stop"))
975 return;
977 if ( debug_level >= DEBUG_LEVEL_INFO )
978 printk("mgsl_stop(%s)\n",info->device_name);
980 spin_lock_irqsave(&info->irq_spinlock,flags);
981 if (info->tx_enabled)
982 usc_stop_transmitter(info);
983 spin_unlock_irqrestore(&info->irq_spinlock,flags);
985 } /* end of mgsl_stop() */
987 /* mgsl_start() release (start) transmitter
989 * Arguments: tty pointer to tty info structure
990 * Return Value: None
992 static void mgsl_start(struct tty_struct *tty)
994 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
995 unsigned long flags;
997 if (mgsl_paranoia_check(info, tty->device, "mgsl_start"))
998 return;
1000 if ( debug_level >= DEBUG_LEVEL_INFO )
1001 printk("mgsl_start(%s)\n",info->device_name);
1003 spin_lock_irqsave(&info->irq_spinlock,flags);
1004 if (!info->tx_enabled)
1005 usc_start_transmitter(info);
1006 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1008 } /* end of mgsl_start() */
1011 * Bottom half work queue access functions
1014 /* mgsl_format_bh_queue()
1016 * Initialize the bottom half processing queue
1018 * Arguments: info pointer to device instance data
1019 * Return Value: None
1021 void mgsl_format_bh_queue( struct mgsl_struct *info )
1023 BH_QUEUE bh_queue = info->bh_queue;
1024 int i;
1026 /* go through sequentially tacking the little bits together */
1028 for ( i=0; i < MAX_BH_QUEUE_ENTRIES; i++ ) {
1029 if ( info->free_bh_queue_tail == NULL )
1030 info->free_bh_queue_head = bh_queue;
1031 else
1032 info->free_bh_queue_tail->link = bh_queue;
1033 info->free_bh_queue_tail = bh_queue++;
1036 /* As a safety measure, mark the end of the chain with a NULL */
1037 info->free_bh_queue_tail->link = NULL;
1038 info->isr_overflow=0;
1040 } /* end of mgsl_format_bh_queue() */
1042 /* mgsl_bh_queue_put()
1044 * Add a BH event to the BH queue
1046 * Arguments: info pointer to device instance data
1047 * type BH event type
1048 * status BH event status
1050 * Return Value: None
1052 void mgsl_bh_queue_put( struct mgsl_struct *info, unsigned char type, unsigned short status )
1054 BH_EVENT *event = info->free_bh_queue_head;
1056 if ( event != NULL ) {
1057 /* remove free element from head of free list */
1058 info->free_bh_queue_head = event->link;
1059 event->link = NULL;
1061 /* file out new BH event */
1062 event->type = type;
1063 event->status = status;
1065 /* add element to tail of pending list */
1066 if ( info->bh_queue_head != NULL ){
1067 /* BH queue is not empty, add current element to tail */
1068 info->bh_queue_tail->link = event;
1069 } else {
1070 /* the BH queue is empty so this element becomes the head of queue */
1071 info->bh_queue_head = event;
1074 /* the new element becomes tail of queue */
1075 info->bh_queue_tail = event;
1076 } else {
1077 /* No more free BH action elements in queue. */
1078 /* This happens when too many interrupts are occuring */
1079 /* for the mgsl_bh_handler to process so set a flag. */
1081 info->isr_overflow = 1;
1084 } /* end of mgsl_bh_queue_put() */
1086 /* mgsl_bh_queue_get()
1088 * Free the current work item (if any) and get the
1089 * next work item from the head of the pending work item queue.
1091 * Effects:
1093 * If a BH action element is available on the BH action queue
1094 * then the head of the queue is removed and bh_action
1095 * is set to point to the removed element.
1097 * Arguments: info pointer to device instance data
1098 * Return Value: 1 if BH action removed from queue
1100 int mgsl_bh_queue_get( struct mgsl_struct *info )
1102 unsigned long flags;
1104 spin_lock_irqsave(&info->irq_spinlock,flags);
1106 if ( info->bh_action ) {
1107 /* free the current work item */
1108 if ( info->free_bh_queue_head != NULL ){
1109 /* free queue is not empty, add current element to tail */
1110 info->free_bh_queue_tail->link = info->bh_action;
1111 } else {
1112 /* free queue is empty so this element becomes the head of queue */
1113 info->free_bh_queue_head = info->bh_action;
1116 /* add element to tail of free queue */
1117 info->free_bh_queue_tail = info->bh_action;
1118 info->free_bh_queue_tail->link = NULL;
1121 /* attempt to remove element from head of queue */
1122 info->bh_action = info->bh_queue_head;
1124 if ( info->bh_action != NULL ){
1125 /* BH queue is not empty, remove element from queue head */
1126 info->bh_queue_head = info->bh_action->link;
1127 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1128 return 1;
1131 if ( info->isr_overflow ) {
1132 if (debug_level >= DEBUG_LEVEL_BH)
1133 printk("ISR overflow cleared.\n");
1134 info->isr_overflow=0;
1135 usc_EnableMasterIrqBit(info);
1136 usc_EnableDmaInterrupts(info,DICR_MASTER);
1139 /* Mark BH routine as complete */
1140 info->bh_running = 0;
1141 info->bh_requested = 0;
1143 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1145 return 0;
1147 } /* end of mgsl_bh_queue_get() */
1149 /* mgsl_bh_handler()
1151 * Perform bottom half processing of work items queued by ISR.
1153 * Arguments: Context pointer to device instance data
1154 * Return Value: None
1156 void mgsl_bh_handler(void* Context)
1158 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1160 if (!info)
1161 return;
1163 if ( debug_level >= DEBUG_LEVEL_BH )
1164 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1165 __FILE__,__LINE__,info->device_name);
1167 info->bh_running = 1;
1169 /* Attempt to clear out the BH queue */
1171 while( mgsl_bh_queue_get(info) ) {
1173 /* Process work item */
1174 if ( debug_level >= DEBUG_LEVEL_BH )
1175 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1176 __FILE__,__LINE__,info->bh_action->type);
1178 switch ( info->bh_action->type ) {
1180 case BH_TYPE_RECEIVE_DMA:
1181 mgsl_bh_receive_dma( info, info->bh_action->status );
1182 break;
1184 case BH_TYPE_TRANSMIT_STATUS:
1185 case BH_TYPE_TRANSMIT_DATA:
1186 mgsl_bh_transmit_data( info, info->bh_action->status );
1187 break;
1189 case BH_TYPE_STATUS:
1190 mgsl_bh_status_handler( info, info->bh_action->status );
1191 break;
1193 default:
1194 /* unknown work item ID */
1195 printk("Unknown work item ID=%08X!\n",
1196 info->bh_action->type );
1197 break;
1201 if ( debug_level >= DEBUG_LEVEL_BH )
1202 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1203 __FILE__,__LINE__,info->device_name);
1205 } /* end of mgsl_bh_handler() */
1207 /* mgsl_bh_receive_dma()
1209 * Perform bottom half processing for a receive DMA interrupt
1210 * This occurs in HDLC mode after a DMA buffer has terminated
1211 * or the DMA buffers have been exhausted.
1213 * Arguments:
1215 * info pointer to device instance data
1216 * status status word
1218 * Return Value: None
1220 void mgsl_bh_receive_dma( struct mgsl_struct *info, unsigned short status )
1222 if ( debug_level >= DEBUG_LEVEL_BH )
1223 printk( "%s(%d):mgsl_bh_receive_dma(%s)\n",
1224 __FILE__,__LINE__,info->device_name);
1226 while( mgsl_get_rx_frame(info) );
1228 } /* end of mgsl_bh_receive_dma() */
1230 /* mgsl_bh_transmit_data()
1232 * Process a transmit data interrupt event
1233 * This occurs in asynchronous communications mode.
1235 * Arguments: info pointer to device instance data
1236 * Return Value: None
1238 void mgsl_bh_transmit_data( struct mgsl_struct *info, unsigned short Datacount )
1240 struct tty_struct *tty = info->tty;
1241 unsigned long flags;
1243 if ( debug_level >= DEBUG_LEVEL_BH )
1244 printk( "%s(%d):mgsl_bh_transmit_data() entry on %s\n",
1245 __FILE__,__LINE__,info->device_name);
1247 /* wakeup any waiting write requests */
1248 if (tty) {
1249 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1250 tty->ldisc.write_wakeup) {
1251 if ( debug_level >= DEBUG_LEVEL_BH )
1252 printk( "%s(%d):calling ldisc.write_wakeup on %s\n",
1253 __FILE__,__LINE__,info->device_name);
1254 (tty->ldisc.write_wakeup)(tty);
1256 wake_up_interruptible(&tty->write_wait);
1259 /* if transmitter idle and loopmode_send_done_requested
1260 * then start echoing RxD to TxD
1262 spin_lock_irqsave(&info->irq_spinlock,flags);
1263 if ( !info->tx_active && info->loopmode_send_done_requested )
1264 usc_loopmode_send_done( info );
1265 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1267 } /* End Of mgsl_bh_transmit_data() */
1269 /* mgsl_bh_status_handler()
1271 * Peform bottom half processing for a status interrupt
1273 * This event is generated when a I/O pin (serial signal)
1274 * has a transition. If there is a pending WaitEvent call
1275 * and the status transition is identified in the EventMast
1276 * of the pending call then complete the pending call.
1278 * Arguments:
1280 * info pointer to device instance data
1281 * status status word
1283 * Return Value: None
1285 void mgsl_bh_status_handler( struct mgsl_struct *info, unsigned short status )
1287 if ( debug_level >= DEBUG_LEVEL_BH )
1288 printk( "%s(%d):mgsl_bh_status_handler() entry on %s\n",
1289 __FILE__,__LINE__,info->device_name);
1291 if (status & MISCSTATUS_RI_LATCHED) {
1292 if (info->ri_chkcount)
1293 (info->ri_chkcount)--;
1295 if (status & MISCSTATUS_DSR_LATCHED) {
1296 if (info->dsr_chkcount)
1297 (info->dsr_chkcount)--;
1299 if (status & MISCSTATUS_DCD_LATCHED) {
1300 if (info->dcd_chkcount)
1301 (info->dcd_chkcount)--;
1303 if (status & MISCSTATUS_CTS_LATCHED) {
1304 if (info->cts_chkcount)
1305 (info->cts_chkcount)--;
1308 } /* End Of mgsl_bh_status_handler() */
1310 /* mgsl_isr_receive_status()
1312 * Service a receive status interrupt. The type of status
1313 * interrupt is indicated by the state of the RCSR.
1314 * This is only used for HDLC mode.
1316 * Arguments: info pointer to device instance data
1317 * Return Value: None
1319 void mgsl_isr_receive_status( struct mgsl_struct *info )
1321 u16 status = usc_InReg( info, RCSR );
1323 if ( debug_level >= DEBUG_LEVEL_ISR )
1324 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1325 __FILE__,__LINE__,status);
1327 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1328 info->loopmode_insert_requested &&
1329 usc_loopmode_active(info) )
1331 ++info->icount.rxabort;
1332 info->loopmode_insert_requested = FALSE;
1334 /* clear CMR:13 to start echoing RxD to TxD */
1335 info->cmr_value &= ~BIT13;
1336 usc_OutReg(info, CMR, info->cmr_value);
1338 /* disable received abort irq (no longer required) */
1339 usc_OutReg(info, RICR,
1340 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1343 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1344 if (status & RXSTATUS_EXITED_HUNT)
1345 info->icount.exithunt++;
1346 if (status & RXSTATUS_IDLE_RECEIVED)
1347 info->icount.rxidle++;
1348 wake_up_interruptible(&info->event_wait_q);
1351 if (status & RXSTATUS_OVERRUN){
1352 /* Purge receive FIFO to allow DMA buffer completion
1353 * with overrun status stored in the receive status block.
1355 usc_RCmd( info, RCmd_EnterHuntmode );
1356 usc_RTCmd( info, RTCmd_PurgeRxFifo );
1359 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1360 usc_UnlatchRxstatusBits( info, status );
1362 } /* end of mgsl_isr_receive_status() */
1364 /* mgsl_isr_transmit_status()
1366 * Service a transmit status interrupt
1367 * HDLC mode :end of transmit frame
1368 * Async mode:all data is sent
1369 * transmit status is indicated by bits in the TCSR.
1371 * Arguments: info pointer to device instance data
1372 * Return Value: None
1374 void mgsl_isr_transmit_status( struct mgsl_struct *info )
1376 u16 status = usc_InReg( info, TCSR );
1378 if ( debug_level >= DEBUG_LEVEL_ISR )
1379 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1380 __FILE__,__LINE__,status);
1382 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1383 usc_UnlatchTxstatusBits( info, status );
1385 if ( status & TXSTATUS_EOF_SENT )
1386 info->icount.txok++;
1387 else if ( status & TXSTATUS_UNDERRUN )
1388 info->icount.txunder++;
1389 else if ( status & TXSTATUS_ABORT_SENT )
1390 info->icount.txabort++;
1391 else
1392 info->icount.txunder++;
1394 info->tx_active = 0;
1395 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1396 del_timer(&info->tx_timer);
1398 if ( info->drop_rts_on_tx_done ) {
1399 usc_get_serial_signals( info );
1400 if ( info->serial_signals & SerialSignal_RTS ) {
1401 info->serial_signals &= ~SerialSignal_RTS;
1402 usc_set_serial_signals( info );
1404 info->drop_rts_on_tx_done = 0;
1407 if (info->tty->stopped || info->tty->hw_stopped) {
1408 usc_stop_transmitter(info);
1409 return;
1412 mgsl_bh_queue_put(info, BH_TYPE_TRANSMIT_STATUS, status);
1414 } /* end of mgsl_isr_transmit_status() */
1416 /* mgsl_isr_io_pin()
1418 * Service an Input/Output pin interrupt. The type of
1419 * interrupt is indicated by bits in the MISR
1421 * Arguments: info pointer to device instance data
1422 * Return Value: None
1424 void mgsl_isr_io_pin( struct mgsl_struct *info )
1426 struct mgsl_icount *icount;
1427 u16 status = usc_InReg( info, MISR );
1429 if ( debug_level >= DEBUG_LEVEL_ISR )
1430 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1431 __FILE__,__LINE__,status);
1433 usc_ClearIrqPendingBits( info, IO_PIN );
1434 usc_UnlatchIostatusBits( info, status );
1436 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1437 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1438 icount = &info->icount;
1439 /* update input line counters */
1440 if (status & MISCSTATUS_RI_LATCHED) {
1441 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1442 usc_DisablestatusIrqs(info,SICR_RI);
1443 icount->rng++;
1444 if ( status & MISCSTATUS_RI )
1445 info->input_signal_events.ri_up++;
1446 else
1447 info->input_signal_events.ri_down++;
1449 if (status & MISCSTATUS_DSR_LATCHED) {
1450 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1451 usc_DisablestatusIrqs(info,SICR_DSR);
1452 icount->dsr++;
1453 if ( status & MISCSTATUS_DSR )
1454 info->input_signal_events.dsr_up++;
1455 else
1456 info->input_signal_events.dsr_down++;
1458 if (status & MISCSTATUS_DCD_LATCHED) {
1459 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1460 usc_DisablestatusIrqs(info,SICR_DCD);
1461 icount->dcd++;
1462 if ( status & MISCSTATUS_DCD )
1463 info->input_signal_events.dcd_up++;
1464 else
1465 info->input_signal_events.dcd_down++;
1466 #ifdef CONFIG_HARD_PPS
1467 if ((info->flags & ASYNC_HARDPPS_CD) &&
1468 (status & MISCSTATUS_DCD_LATCHED))
1469 hardpps();
1470 #endif
1472 if (status & MISCSTATUS_CTS_LATCHED)
1474 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1475 usc_DisablestatusIrqs(info,SICR_CTS);
1476 icount->cts++;
1477 if ( status & MISCSTATUS_CTS )
1478 info->input_signal_events.cts_up++;
1479 else
1480 info->input_signal_events.cts_down++;
1482 wake_up_interruptible(&info->status_event_wait_q);
1483 wake_up_interruptible(&info->event_wait_q);
1485 if ( (info->flags & ASYNC_CHECK_CD) &&
1486 (status & MISCSTATUS_DCD_LATCHED) ) {
1487 if ( debug_level >= DEBUG_LEVEL_ISR )
1488 printk("%s CD now %s...", info->device_name,
1489 (status & MISCSTATUS_DCD) ? "on" : "off");
1490 if (status & MISCSTATUS_DCD)
1491 wake_up_interruptible(&info->open_wait);
1492 else if (!((info->flags & ASYNC_CALLOUT_ACTIVE) &&
1493 (info->flags & ASYNC_CALLOUT_NOHUP))) {
1494 if ( debug_level >= DEBUG_LEVEL_ISR )
1495 printk("doing serial hangup...");
1496 if (info->tty)
1497 tty_hangup(info->tty);
1501 if ( (info->flags & ASYNC_CTS_FLOW) &&
1502 (status & MISCSTATUS_CTS_LATCHED) ) {
1503 if (info->tty->hw_stopped) {
1504 if (status & MISCSTATUS_CTS) {
1505 if ( debug_level >= DEBUG_LEVEL_ISR )
1506 printk("CTS tx start...");
1507 info->tty->hw_stopped = 0;
1508 usc_start_transmitter(info);
1509 mgsl_bh_queue_put( info, BH_TYPE_TRANSMIT_DATA, status );
1510 return;
1512 } else {
1513 if (!(status & MISCSTATUS_CTS)) {
1514 if ( debug_level >= DEBUG_LEVEL_ISR )
1515 printk("CTS tx stop...");
1516 info->tty->hw_stopped = 1;
1517 usc_stop_transmitter(info);
1523 mgsl_bh_queue_put(info, BH_TYPE_STATUS, status);
1525 /* for diagnostics set IRQ flag */
1526 if ( status & MISCSTATUS_TXC_LATCHED ){
1527 usc_OutReg( info, SICR,
1528 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1529 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1530 info->irq_occurred = 1;
1533 } /* end of mgsl_isr_io_pin() */
1535 /* mgsl_isr_transmit_data()
1537 * Service a transmit data interrupt (async mode only).
1539 * Arguments: info pointer to device instance data
1540 * Return Value: None
1542 void mgsl_isr_transmit_data( struct mgsl_struct *info )
1544 if ( debug_level >= DEBUG_LEVEL_ISR )
1545 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1546 __FILE__,__LINE__,info->xmit_cnt);
1548 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1550 if (info->tty->stopped || info->tty->hw_stopped) {
1551 usc_stop_transmitter(info);
1552 return;
1555 if ( info->xmit_cnt )
1556 usc_load_txfifo( info );
1557 else
1558 info->tx_active = 0;
1560 if (info->xmit_cnt < WAKEUP_CHARS)
1561 mgsl_bh_queue_put(info, BH_TYPE_TRANSMIT_DATA, (unsigned short)(info->xmit_cnt));
1563 } /* end of mgsl_isr_transmit_data() */
1565 /* mgsl_isr_receive_data()
1567 * Service a receive data interrupt. This occurs
1568 * when operating in asynchronous interrupt transfer mode.
1569 * The receive data FIFO is flushed to the receive data buffers.
1571 * Arguments: info pointer to device instance data
1572 * Return Value: None
1574 void mgsl_isr_receive_data( struct mgsl_struct *info )
1576 int Fifocount;
1577 u16 status;
1578 unsigned char DataByte;
1579 struct tty_struct *tty = info->tty;
1580 struct mgsl_icount *icount = &info->icount;
1582 if ( debug_level >= DEBUG_LEVEL_ISR )
1583 printk("%s(%d):mgsl_isr_receive_data\n",
1584 __FILE__,__LINE__);
1586 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1588 /* select FIFO status for RICR readback */
1589 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1591 /* clear the Wordstatus bit so that status readback */
1592 /* only reflects the status of this byte */
1593 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1595 /* flush the receive FIFO */
1597 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1598 /* read one byte from RxFIFO */
1599 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1600 info->io_base + CCAR );
1601 DataByte = inb( info->io_base + CCAR );
1603 /* get the status of the received byte */
1604 status = usc_InReg(info, RCSR);
1605 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1606 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1607 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1609 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1610 continue;
1612 *tty->flip.char_buf_ptr = DataByte;
1613 icount->rx++;
1615 *tty->flip.flag_buf_ptr = 0;
1616 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1617 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1618 printk("rxerr=%04X\n",status);
1619 /* update error statistics */
1620 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1621 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1622 icount->brk++;
1623 } else if (status & RXSTATUS_PARITY_ERROR)
1624 icount->parity++;
1625 else if (status & RXSTATUS_FRAMING_ERROR)
1626 icount->frame++;
1627 else if (status & RXSTATUS_OVERRUN) {
1628 /* must issue purge fifo cmd before */
1629 /* 16C32 accepts more receive chars */
1630 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1631 icount->overrun++;
1634 /* discard char if tty control flags say so */
1635 if (status & info->ignore_status_mask)
1636 continue;
1638 status &= info->read_status_mask;
1640 if (status & RXSTATUS_BREAK_RECEIVED) {
1641 *tty->flip.flag_buf_ptr = TTY_BREAK;
1642 if (info->flags & ASYNC_SAK)
1643 do_SAK(tty);
1644 } else if (status & RXSTATUS_PARITY_ERROR)
1645 *tty->flip.flag_buf_ptr = TTY_PARITY;
1646 else if (status & RXSTATUS_FRAMING_ERROR)
1647 *tty->flip.flag_buf_ptr = TTY_FRAME;
1648 if (status & RXSTATUS_OVERRUN) {
1649 /* Overrun is special, since it's
1650 * reported immediately, and doesn't
1651 * affect the current character
1653 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1654 tty->flip.count++;
1655 tty->flip.flag_buf_ptr++;
1656 tty->flip.char_buf_ptr++;
1657 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
1660 } /* end of if (error) */
1662 tty->flip.flag_buf_ptr++;
1663 tty->flip.char_buf_ptr++;
1664 tty->flip.count++;
1667 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1668 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1669 __FILE__,__LINE__,tty->flip.count);
1670 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1671 __FILE__,__LINE__,icount->rx,icount->brk,
1672 icount->parity,icount->frame,icount->overrun);
1675 if ( tty->flip.count ) {
1676 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
1677 tty_flip_buffer_push(tty);
1678 #else
1679 queue_task(&tty->flip.tqueue, &tq_timer);
1680 #endif
1684 } /* end of mgsl_isr_receive_data() */
1686 /* mgsl_isr_misc()
1688 * Service a miscellaneos interrupt source.
1690 * Arguments: info pointer to device extension (instance data)
1691 * Return Value: None
1693 void mgsl_isr_misc( struct mgsl_struct *info )
1695 u16 status = usc_InReg( info, MISR );
1697 if ( debug_level >= DEBUG_LEVEL_ISR )
1698 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1699 __FILE__,__LINE__,status);
1701 usc_ClearIrqPendingBits( info, MISC );
1702 usc_UnlatchMiscstatusBits( info, status );
1704 } /* end of mgsl_isr_misc() */
1706 /* mgsl_isr_null()
1708 * Services undefined interrupt vectors from the
1709 * USC. (hence this function SHOULD never be called)
1711 * Arguments: info pointer to device extension (instance data)
1712 * Return Value: None
1714 void mgsl_isr_null( struct mgsl_struct *info )
1717 } /* end of mgsl_isr_null() */
1719 /* mgsl_isr_receive_dma()
1721 * Service a receive DMA channel interrupt.
1722 * For this driver there are two sources of receive DMA interrupts
1723 * as identified in the Receive DMA mode Register (RDMR):
1725 * BIT3 EOA/EOL End of List, all receive buffers in receive
1726 * buffer list have been filled (no more free buffers
1727 * available). The DMA controller has shut down.
1729 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1730 * DMA buffer is terminated in response to completion
1731 * of a good frame or a frame with errors. The status
1732 * of the frame is stored in the buffer entry in the
1733 * list of receive buffer entries.
1735 * Arguments: info pointer to device instance data
1736 * Return Value: None
1738 void mgsl_isr_receive_dma( struct mgsl_struct *info )
1740 u16 status;
1742 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1743 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1745 /* Read the receive DMA status to identify interrupt type. */
1746 /* This also clears the status bits. */
1747 status = usc_InDmaReg( info, RDMR );
1749 if ( debug_level >= DEBUG_LEVEL_ISR )
1750 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1751 __FILE__,__LINE__,info->device_name,status);
1753 /* Post a receive event for BH processing. */
1754 mgsl_bh_queue_put( info, BH_TYPE_RECEIVE_DMA, status );
1756 if ( status & BIT3 ) {
1757 info->rx_overflow = 1;
1758 info->icount.buf_overrun++;
1761 } /* end of mgsl_isr_receive_dma() */
1763 /* mgsl_interrupt()
1765 * Interrupt service routine entry point.
1767 * Arguments:
1769 * irq interrupt number that caused interrupt
1770 * dev_id device ID supplied during interrupt registration
1771 * regs interrupted processor context
1773 * Return Value: None
1775 static void mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1777 struct mgsl_struct * info;
1778 u16 UscVector;
1779 u16 DmaVector;
1781 if ( debug_level >= DEBUG_LEVEL_ISR )
1782 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1783 __FILE__,__LINE__,irq);
1785 info = (struct mgsl_struct *)dev_id;
1786 if (!info)
1787 return;
1789 spin_lock(&info->irq_spinlock);
1791 for(;;) {
1792 /* Read the interrupt vectors from hardware. */
1793 UscVector = usc_InReg(info, IVR) >> 9;
1794 DmaVector = usc_InDmaReg(info, DIVR);
1796 if ( debug_level >= DEBUG_LEVEL_ISR )
1797 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1798 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1800 if ( !UscVector && !DmaVector )
1801 break;
1803 /* Dispatch interrupt vector */
1804 if ( UscVector )
1805 (*UscIsrTable[UscVector])(info);
1806 else
1807 mgsl_isr_receive_dma(info);
1809 if ( info->isr_overflow ) {
1810 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1811 __FILE__,__LINE__,info->device_name, irq);
1812 usc_DisableMasterIrqBit(info);
1813 usc_DisableDmaInterrupts(info,DICR_MASTER);
1814 break;
1818 /* Request bottom half processing if there's something
1819 * for it to do and the bh is not already running
1822 if ( info->bh_queue_head && !info->bh_running && !info->bh_requested ) {
1823 if ( debug_level >= DEBUG_LEVEL_ISR )
1824 printk("%s(%d):%s queueing bh task.\n",
1825 __FILE__,__LINE__,info->device_name);
1826 queue_task(&info->task, &tq_immediate);
1827 mark_bh(IMMEDIATE_BH);
1828 info->bh_requested = 1;
1831 spin_unlock(&info->irq_spinlock);
1833 if ( debug_level >= DEBUG_LEVEL_ISR )
1834 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1835 __FILE__,__LINE__,irq);
1837 } /* end of mgsl_interrupt() */
1839 /* startup()
1841 * Initialize and start device.
1843 * Arguments: info pointer to device instance data
1844 * Return Value: 0 if success, otherwise error code
1846 static int startup(struct mgsl_struct * info)
1848 int retval = 0;
1850 if ( debug_level >= DEBUG_LEVEL_INFO )
1851 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1853 if (info->flags & ASYNC_INITIALIZED)
1854 return 0;
1856 if (!info->xmit_buf) {
1857 /* allocate a page of memory for a transmit buffer */
1858 info->xmit_buf = (unsigned char *)get_free_page(GFP_KERNEL);
1859 if (!info->xmit_buf) {
1860 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1861 __FILE__,__LINE__,info->device_name);
1862 return -ENOMEM;
1866 mgsl_format_bh_queue(info);
1868 init_timer(&info->tx_timer);
1869 info->tx_timer.data = (unsigned long)info;
1870 info->tx_timer.function = mgsl_tx_timeout;
1872 /* Allocate and claim adapter resources */
1873 retval = mgsl_claim_resources(info);
1875 /* perform existance check and diagnostics */
1876 if ( !retval )
1877 retval = mgsl_adapter_test(info);
1879 if ( retval ) {
1880 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
1881 if (capable(CAP_SYS_ADMIN) && info->tty)
1882 #else
1883 if (suser() && info->tty)
1884 #endif
1885 set_bit(TTY_IO_ERROR, &info->tty->flags);
1886 mgsl_release_resources(info);
1887 return retval;
1890 /* program hardware for current parameters */
1891 mgsl_change_params(info);
1893 if (info->tty)
1894 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1896 info->flags |= ASYNC_INITIALIZED;
1898 return 0;
1900 } /* end of startup() */
1902 /* shutdown()
1904 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1906 * Arguments: info pointer to device instance data
1907 * Return Value: None
1909 static void shutdown(struct mgsl_struct * info)
1911 unsigned long flags;
1913 if (!(info->flags & ASYNC_INITIALIZED))
1914 return;
1916 if (debug_level >= DEBUG_LEVEL_INFO)
1917 printk("%s(%d):mgsl_shutdown(%s)\n",
1918 __FILE__,__LINE__, info->device_name );
1920 /* clear status wait queue because status changes */
1921 /* can't happen after shutting down the hardware */
1922 wake_up_interruptible(&info->status_event_wait_q);
1923 wake_up_interruptible(&info->event_wait_q);
1925 if (info->xmit_buf) {
1926 free_page((unsigned long) info->xmit_buf);
1927 info->xmit_buf = 0;
1930 spin_lock_irqsave(&info->irq_spinlock,flags);
1931 usc_DisableMasterIrqBit(info);
1932 usc_stop_receiver(info);
1933 usc_stop_transmitter(info);
1934 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1935 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1936 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1938 /* Disable DMAEN (Port 7, Bit 14) */
1939 /* This disconnects the DMA request signal from the ISA bus */
1940 /* on the ISA adapter. This has no effect for the PCI adapter */
1941 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1943 /* Disable INTEN (Port 6, Bit12) */
1944 /* This disconnects the IRQ request signal to the ISA bus */
1945 /* on the ISA adapter. This has no effect for the PCI adapter */
1946 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1948 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1949 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1950 usc_set_serial_signals(info);
1953 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1955 mgsl_release_resources(info);
1957 if (info->tty)
1958 set_bit(TTY_IO_ERROR, &info->tty->flags);
1960 info->flags &= ~ASYNC_INITIALIZED;
1962 } /* end of shutdown() */
1964 /* mgsl_change_params()
1966 * Reconfigure adapter based on new parameters
1968 * Arguments: info pointer to device instance data
1969 * Return Value: None
1971 static void mgsl_change_params(struct mgsl_struct *info)
1973 unsigned cflag;
1974 unsigned long flags;
1975 int bits_per_char;
1977 if (!info->tty || !info->tty->termios)
1978 return;
1980 if (debug_level >= DEBUG_LEVEL_INFO)
1981 printk("%s(%d):mgsl_change_params(%s)\n",
1982 __FILE__,__LINE__, info->device_name );
1984 cflag = info->tty->termios->c_cflag;
1986 /* if B0 rate (hangup) specified then negate DTR and RTS */
1987 /* otherwise assert DTR and RTS */
1988 if (cflag & CBAUD)
1989 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1990 else
1991 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1993 /* byte size and parity */
1995 switch (cflag & CSIZE) {
1996 case CS5: info->params.data_bits = 5; break;
1997 case CS6: info->params.data_bits = 6; break;
1998 case CS7: info->params.data_bits = 7; break;
1999 case CS8: info->params.data_bits = 8; break;
2000 /* Never happens, but GCC is too dumb to figure it out */
2001 default: info->params.data_bits = 7; break;
2004 if (cflag & CSTOPB)
2005 info->params.stop_bits = 2;
2006 else
2007 info->params.stop_bits = 1;
2009 info->params.parity = ASYNC_PARITY_NONE;
2010 if (cflag & PARENB) {
2011 if (cflag & PARODD)
2012 info->params.parity = ASYNC_PARITY_ODD;
2013 else
2014 info->params.parity = ASYNC_PARITY_EVEN;
2015 #ifdef CMSPAR
2016 if (cflag & CMSPAR)
2017 info->params.parity = ASYNC_PARITY_SPACE;
2018 #endif
2021 /* calculate number of jiffies to transmit a full
2022 * FIFO (32 bytes) at specified data rate
2024 bits_per_char = info->params.data_bits +
2025 info->params.stop_bits + 1;
2027 /* if port data rate is set to 460800 or less then
2028 * allow tty settings to override, otherwise keep the
2029 * current data rate.
2031 if (info->params.data_rate <= 460800) {
2032 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
2033 info->params.data_rate = tty_get_baud_rate(info->tty);
2034 #else
2035 int i = cflag & CBAUD;
2036 if (i & CBAUDEX) {
2037 i &= ~CBAUDEX;
2038 if (i < 1 || i > 4)
2039 info->tty->termios->c_cflag &= ~CBAUDEX;
2040 else
2041 i += 15;
2043 info->params.data_rate = baud_table[i];
2044 #endif
2047 if ( info->params.data_rate ) {
2048 info->timeout = (32*HZ*bits_per_char) /
2049 info->params.data_rate;
2051 info->timeout += HZ/50; /* Add .02 seconds of slop */
2053 if (cflag & CRTSCTS)
2054 info->flags |= ASYNC_CTS_FLOW;
2055 else
2056 info->flags &= ~ASYNC_CTS_FLOW;
2058 if (cflag & CLOCAL)
2059 info->flags &= ~ASYNC_CHECK_CD;
2060 else
2061 info->flags |= ASYNC_CHECK_CD;
2063 /* process tty input control flags */
2065 info->read_status_mask = RXSTATUS_OVERRUN;
2066 if (I_INPCK(info->tty))
2067 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2068 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2069 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2071 if (I_IGNPAR(info->tty))
2072 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2073 if (I_IGNBRK(info->tty)) {
2074 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2075 /* If ignoring parity and break indicators, ignore
2076 * overruns too. (For real raw support).
2078 if (I_IGNPAR(info->tty))
2079 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2082 /* reprogram the hardware */
2084 spin_lock_irqsave(&info->irq_spinlock,flags);
2086 usc_stop_receiver(info);
2087 usc_stop_transmitter(info);
2088 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2090 if ( info->params.mode == MGSL_MODE_HDLC )
2091 usc_set_sync_mode(info);
2092 else
2093 usc_set_async_mode(info);
2095 usc_set_serial_signals(info);
2097 info->dcd_chkcount = 0;
2098 info->cts_chkcount = 0;
2099 info->ri_chkcount = 0;
2100 info->dsr_chkcount = 0;
2102 /* enable modem signal IRQs and read initial signal states */
2103 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
2104 usc_EnableInterrupts(info, IO_PIN);
2105 usc_get_serial_signals(info);
2107 if ( cflag & CREAD )
2108 usc_start_receiver(info);
2110 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2112 } /* end of mgsl_change_params() */
2114 /* mgsl_put_char()
2116 * Add a character to the transmit buffer.
2118 * Arguments: tty pointer to tty information structure
2119 * ch character to add to transmit buffer
2121 * Return Value: None
2123 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2125 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2126 unsigned long flags;
2128 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2129 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2130 __FILE__,__LINE__,ch,info->device_name);
2133 if (mgsl_paranoia_check(info, tty->device, "mgsl_put_char"))
2134 return;
2136 if (!tty || !info->xmit_buf)
2137 return;
2139 spin_lock_irqsave(&info->irq_spinlock,flags);
2141 if ( (info->params.mode != MGSL_MODE_HDLC) ||
2142 !info->tx_active ) {
2144 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2145 info->xmit_buf[info->xmit_head++] = ch;
2146 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2147 info->xmit_cnt++;
2151 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2153 } /* end of mgsl_put_char() */
2155 /* mgsl_flush_chars()
2157 * Enable transmitter so remaining characters in the
2158 * transmit buffer are sent.
2160 * Arguments: tty pointer to tty information structure
2161 * Return Value: None
2163 static void mgsl_flush_chars(struct tty_struct *tty)
2165 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2166 unsigned long flags;
2168 if ( debug_level >= DEBUG_LEVEL_INFO )
2169 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2170 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2172 if (mgsl_paranoia_check(info, tty->device, "mgsl_flush_chars"))
2173 return;
2175 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2176 !info->xmit_buf)
2177 return;
2179 if ( debug_level >= DEBUG_LEVEL_INFO )
2180 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2181 __FILE__,__LINE__,info->device_name );
2183 spin_lock_irqsave(&info->irq_spinlock,flags);
2185 if (!info->tx_active) {
2186 if ( (info->params.mode == MGSL_MODE_HDLC) &&
2187 info->xmit_cnt ) {
2188 /* operating in synchronous (frame oriented) mode */
2189 /* copy data from circular xmit_buf to */
2190 /* transmit DMA buffer. */
2191 mgsl_load_tx_dma_buffer(info,
2192 info->xmit_buf,info->xmit_cnt);
2194 usc_start_transmitter(info);
2197 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2199 } /* end of mgsl_flush_chars() */
2201 /* mgsl_write()
2203 * Send a block of data
2205 * Arguments:
2207 * tty pointer to tty information structure
2208 * from_user flag: 1 = from user process
2209 * buf pointer to buffer containing send data
2210 * count size of send data in bytes
2212 * Return Value: number of characters written
2214 static int mgsl_write(struct tty_struct * tty, int from_user,
2215 const unsigned char *buf, int count)
2217 int c, ret = 0, err;
2218 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2219 unsigned long flags;
2221 if ( debug_level >= DEBUG_LEVEL_INFO )
2222 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2223 __FILE__,__LINE__,info->device_name,count);
2225 if (mgsl_paranoia_check(info, tty->device, "mgsl_write"))
2226 goto cleanup;
2228 if (!tty || !info->xmit_buf || !tmp_buf)
2229 goto cleanup;
2231 if ( info->params.mode == MGSL_MODE_HDLC ) {
2232 /* operating in synchronous (frame oriented) mode */
2234 if (info->tx_active) {
2235 ret = 0; goto cleanup;
2238 /* if operating in HDLC LoopMode and the adapter */
2239 /* has yet to be inserted into the loop, we can't */
2240 /* transmit */
2242 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2243 !usc_loopmode_active(info) )
2245 ret = 0;
2246 goto cleanup;
2249 if ( info->xmit_cnt ) {
2250 /* Send accumulated from send_char() calls */
2251 /* as frame and wait before accepting more data. */
2252 ret = 0;
2254 /* copy data from circular xmit_buf to */
2255 /* transmit DMA buffer. */
2256 mgsl_load_tx_dma_buffer(info,
2257 info->xmit_buf,info->xmit_cnt);
2258 if ( debug_level >= DEBUG_LEVEL_INFO )
2259 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2260 __FILE__,__LINE__,info->device_name);
2261 } else {
2262 if ( debug_level >= DEBUG_LEVEL_INFO )
2263 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2264 __FILE__,__LINE__,info->device_name);
2265 ret = count;
2266 info->xmit_cnt = count;
2267 if (from_user) {
2268 down(&tmp_buf_sem);
2269 COPY_FROM_USER(err,tmp_buf, buf, count);
2270 if (err) {
2271 if ( debug_level >= DEBUG_LEVEL_INFO )
2272 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2273 __FILE__,__LINE__,info->device_name);
2274 ret = -EFAULT;
2275 } else
2276 mgsl_load_tx_dma_buffer(info,tmp_buf,count);
2277 up(&tmp_buf_sem);
2279 else
2280 mgsl_load_tx_dma_buffer(info,buf,count);
2282 } else {
2283 if (from_user) {
2284 down(&tmp_buf_sem);
2285 while (1) {
2286 c = MIN(count,
2287 MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2288 SERIAL_XMIT_SIZE - info->xmit_head));
2289 if (c <= 0)
2290 break;
2292 COPY_FROM_USER(err,tmp_buf, buf, c);
2293 c -= err;
2294 if (!c) {
2295 if (!ret)
2296 ret = -EFAULT;
2297 break;
2299 spin_lock_irqsave(&info->irq_spinlock,flags);
2300 c = MIN(c, MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2301 SERIAL_XMIT_SIZE - info->xmit_head));
2302 memcpy(info->xmit_buf + info->xmit_head, tmp_buf, c);
2303 info->xmit_head = ((info->xmit_head + c) &
2304 (SERIAL_XMIT_SIZE-1));
2305 info->xmit_cnt += c;
2306 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2307 buf += c;
2308 count -= c;
2309 ret += c;
2311 up(&tmp_buf_sem);
2312 } else {
2313 while (1) {
2314 spin_lock_irqsave(&info->irq_spinlock,flags);
2315 c = MIN(count,
2316 MIN(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2317 SERIAL_XMIT_SIZE - info->xmit_head));
2318 if (c <= 0) {
2319 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2320 break;
2322 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2323 info->xmit_head = ((info->xmit_head + c) &
2324 (SERIAL_XMIT_SIZE-1));
2325 info->xmit_cnt += c;
2326 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2327 buf += c;
2328 count -= c;
2329 ret += c;
2334 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2335 spin_lock_irqsave(&info->irq_spinlock,flags);
2336 if (!info->tx_active)
2337 usc_start_transmitter(info);
2338 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2340 cleanup:
2341 if ( debug_level >= DEBUG_LEVEL_INFO )
2342 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2343 __FILE__,__LINE__,info->device_name,ret);
2345 return ret;
2347 } /* end of mgsl_write() */
2349 /* mgsl_write_room()
2351 * Return the count of free bytes in transmit buffer
2353 * Arguments: tty pointer to tty info structure
2354 * Return Value: None
2356 static int mgsl_write_room(struct tty_struct *tty)
2358 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2359 int ret;
2361 if (mgsl_paranoia_check(info, tty->device, "mgsl_write_room"))
2362 return 0;
2363 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2364 if (ret < 0)
2365 ret = 0;
2367 if (debug_level >= DEBUG_LEVEL_INFO)
2368 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2369 __FILE__,__LINE__, info->device_name,ret );
2371 if ( info->params.mode == MGSL_MODE_HDLC ) {
2372 /* operating in synchronous (frame oriented) mode */
2373 if ( info->tx_active )
2374 return 0;
2375 else
2376 return HDLC_MAX_FRAME_SIZE;
2379 return ret;
2381 } /* end of mgsl_write_room() */
2383 /* mgsl_chars_in_buffer()
2385 * Return the count of bytes in transmit buffer
2387 * Arguments: tty pointer to tty info structure
2388 * Return Value: None
2390 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2392 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2394 if (debug_level >= DEBUG_LEVEL_INFO)
2395 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2396 __FILE__,__LINE__, info->device_name );
2398 if (mgsl_paranoia_check(info, tty->device, "mgsl_chars_in_buffer"))
2399 return 0;
2401 if (debug_level >= DEBUG_LEVEL_INFO)
2402 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2403 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2405 if ( info->params.mode == MGSL_MODE_HDLC ) {
2406 /* operating in synchronous (frame oriented) mode */
2407 if ( info->tx_active )
2408 return info->tx_buffer_list[0].rcc;
2409 else
2410 return 0;
2413 return info->xmit_cnt;
2414 } /* end of mgsl_chars_in_buffer() */
2416 /* mgsl_flush_buffer()
2418 * Discard all data in the send buffer
2420 * Arguments: tty pointer to tty info structure
2421 * Return Value: None
2423 static void mgsl_flush_buffer(struct tty_struct *tty)
2425 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2426 unsigned long flags;
2428 if (debug_level >= DEBUG_LEVEL_INFO)
2429 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2430 __FILE__,__LINE__, info->device_name );
2432 if (mgsl_paranoia_check(info, tty->device, "mgsl_flush_buffer"))
2433 return;
2435 spin_lock_irqsave(&info->irq_spinlock,flags);
2436 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2437 del_timer(&info->tx_timer);
2438 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2440 wake_up_interruptible(&tty->write_wait);
2441 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
2442 tty->ldisc.write_wakeup)
2443 (tty->ldisc.write_wakeup)(tty);
2445 } /* end of mgsl_flush_buffer() */
2447 /* mgsl_send_xchar()
2449 * Send a high-priority XON/XOFF character
2451 * Arguments: tty pointer to tty info structure
2452 * ch character to send
2453 * Return Value: None
2455 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2457 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2458 unsigned long flags;
2460 if (debug_level >= DEBUG_LEVEL_INFO)
2461 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2462 __FILE__,__LINE__, info->device_name, ch );
2464 if (mgsl_paranoia_check(info, tty->device, "mgsl_send_xchar"))
2465 return;
2467 info->x_char = ch;
2468 if (ch) {
2469 /* Make sure transmit interrupts are on */
2470 spin_lock_irqsave(&info->irq_spinlock,flags);
2471 if (!info->tx_enabled)
2472 usc_start_transmitter(info);
2473 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2475 } /* end of mgsl_send_xchar() */
2477 /* mgsl_throttle()
2479 * Signal remote device to throttle send data (our receive data)
2481 * Arguments: tty pointer to tty info structure
2482 * Return Value: None
2484 static void mgsl_throttle(struct tty_struct * tty)
2486 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2487 unsigned long flags;
2489 if (debug_level >= DEBUG_LEVEL_INFO)
2490 printk("%s(%d):mgsl_throttle(%s) entry\n",
2491 __FILE__,__LINE__, info->device_name );
2493 if (mgsl_paranoia_check(info, tty->device, "mgsl_throttle"))
2494 return;
2496 if (I_IXOFF(tty))
2497 mgsl_send_xchar(tty, STOP_CHAR(tty));
2499 if (tty->termios->c_cflag & CRTSCTS) {
2500 spin_lock_irqsave(&info->irq_spinlock,flags);
2501 info->serial_signals &= ~SerialSignal_RTS;
2502 usc_set_serial_signals(info);
2503 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2505 } /* end of mgsl_throttle() */
2507 /* mgsl_unthrottle()
2509 * Signal remote device to stop throttling send data (our receive data)
2511 * Arguments: tty pointer to tty info structure
2512 * Return Value: None
2514 static void mgsl_unthrottle(struct tty_struct * tty)
2516 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2517 unsigned long flags;
2519 if (debug_level >= DEBUG_LEVEL_INFO)
2520 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2521 __FILE__,__LINE__, info->device_name );
2523 if (mgsl_paranoia_check(info, tty->device, "mgsl_unthrottle"))
2524 return;
2526 if (I_IXOFF(tty)) {
2527 if (info->x_char)
2528 info->x_char = 0;
2529 else
2530 mgsl_send_xchar(tty, START_CHAR(tty));
2533 if (tty->termios->c_cflag & CRTSCTS) {
2534 spin_lock_irqsave(&info->irq_spinlock,flags);
2535 info->serial_signals |= SerialSignal_RTS;
2536 usc_set_serial_signals(info);
2537 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2540 } /* end of mgsl_unthrottle() */
2542 /* mgsl_get_stats()
2544 * get the current serial parameters information
2546 * Arguments: info pointer to device instance data
2547 * user_icount pointer to buffer to hold returned stats
2549 * Return Value: 0 if success, otherwise error code
2551 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount *user_icount)
2553 int err;
2555 if (debug_level >= DEBUG_LEVEL_INFO)
2556 printk("%s(%d):mgsl_get_params(%s)\n",
2557 __FILE__,__LINE__, info->device_name);
2559 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2560 if (err) {
2561 if ( debug_level >= DEBUG_LEVEL_INFO )
2562 printk( "%s(%d):mgsl_get_stats(%s) user buffer copy failed\n",
2563 __FILE__,__LINE__,info->device_name);
2564 return -EFAULT;
2567 return 0;
2569 } /* end of mgsl_get_stats() */
2571 /* mgsl_get_params()
2573 * get the current serial parameters information
2575 * Arguments: info pointer to device instance data
2576 * user_params pointer to buffer to hold returned params
2578 * Return Value: 0 if success, otherwise error code
2580 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS *user_params)
2582 int err;
2583 if (debug_level >= DEBUG_LEVEL_INFO)
2584 printk("%s(%d):mgsl_get_params(%s)\n",
2585 __FILE__,__LINE__, info->device_name);
2587 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2588 if (err) {
2589 if ( debug_level >= DEBUG_LEVEL_INFO )
2590 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2591 __FILE__,__LINE__,info->device_name);
2592 return -EFAULT;
2595 return 0;
2597 } /* end of mgsl_get_params() */
2599 /* mgsl_set_params()
2601 * set the serial parameters
2603 * Arguments:
2605 * info pointer to device instance data
2606 * new_params user buffer containing new serial params
2608 * Return Value: 0 if success, otherwise error code
2610 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS *new_params)
2612 unsigned long flags;
2613 MGSL_PARAMS tmp_params;
2614 int err;
2616 if (debug_level >= DEBUG_LEVEL_INFO)
2617 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2618 info->device_name );
2619 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2620 if (err) {
2621 if ( debug_level >= DEBUG_LEVEL_INFO )
2622 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2623 __FILE__,__LINE__,info->device_name);
2624 return -EFAULT;
2627 spin_lock_irqsave(&info->irq_spinlock,flags);
2628 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2629 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2631 mgsl_change_params(info);
2633 return 0;
2635 } /* end of mgsl_set_params() */
2637 /* mgsl_get_txidle()
2639 * get the current transmit idle mode
2641 * Arguments: info pointer to device instance data
2642 * idle_mode pointer to buffer to hold returned idle mode
2644 * Return Value: 0 if success, otherwise error code
2646 static int mgsl_get_txidle(struct mgsl_struct * info, int*idle_mode)
2648 int err;
2650 if (debug_level >= DEBUG_LEVEL_INFO)
2651 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2652 __FILE__,__LINE__, info->device_name, info->idle_mode);
2654 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2655 if (err) {
2656 if ( debug_level >= DEBUG_LEVEL_INFO )
2657 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2658 __FILE__,__LINE__,info->device_name);
2659 return -EFAULT;
2662 return 0;
2664 } /* end of mgsl_get_txidle() */
2666 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2668 * Arguments: info pointer to device instance data
2669 * idle_mode new idle mode
2671 * Return Value: 0 if success, otherwise error code
2673 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2675 unsigned long flags;
2677 if (debug_level >= DEBUG_LEVEL_INFO)
2678 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2679 info->device_name, idle_mode );
2681 spin_lock_irqsave(&info->irq_spinlock,flags);
2682 info->idle_mode = idle_mode;
2683 usc_set_txidle( info );
2684 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2685 return 0;
2687 } /* end of mgsl_set_txidle() */
2689 /* mgsl_txenable()
2691 * enable or disable the transmitter
2693 * Arguments:
2695 * info pointer to device instance data
2696 * enable 1 = enable, 0 = disable
2698 * Return Value: 0 if success, otherwise error code
2700 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2702 unsigned long flags;
2704 if (debug_level >= DEBUG_LEVEL_INFO)
2705 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2706 info->device_name, enable);
2708 spin_lock_irqsave(&info->irq_spinlock,flags);
2709 if ( enable ) {
2710 if ( !info->tx_enabled ) {
2712 usc_start_transmitter(info);
2713 /*--------------------------------------------------
2714 * if HDLC/SDLC Loop mode, attempt to insert the
2715 * station in the 'loop' by setting CMR:13. Upon
2716 * receipt of the next GoAhead (RxAbort) sequence,
2717 * the OnLoop indicator (CCSR:7) should go active
2718 * to indicate that we are on the loop
2719 *--------------------------------------------------*/
2720 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2721 usc_loopmode_insert_request( info );
2723 } else {
2724 if ( info->tx_enabled )
2725 usc_stop_transmitter(info);
2727 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2728 return 0;
2730 } /* end of mgsl_txenable() */
2732 /* mgsl_txabort() abort send HDLC frame
2734 * Arguments: info pointer to device instance data
2735 * Return Value: 0 if success, otherwise error code
2737 static int mgsl_txabort(struct mgsl_struct * info)
2739 unsigned long flags;
2741 if (debug_level >= DEBUG_LEVEL_INFO)
2742 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2743 info->device_name);
2745 spin_lock_irqsave(&info->irq_spinlock,flags);
2746 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2748 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2749 usc_loopmode_cancel_transmit( info );
2750 else
2751 usc_TCmd(info,TCmd_SendAbort);
2753 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2754 return 0;
2756 } /* end of mgsl_txabort() */
2758 /* mgsl_rxenable() enable or disable the receiver
2760 * Arguments: info pointer to device instance data
2761 * enable 1 = enable, 0 = disable
2762 * Return Value: 0 if success, otherwise error code
2764 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2766 unsigned long flags;
2768 if (debug_level >= DEBUG_LEVEL_INFO)
2769 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2770 info->device_name, enable);
2772 spin_lock_irqsave(&info->irq_spinlock,flags);
2773 if ( enable ) {
2774 if ( !info->rx_enabled )
2775 usc_start_receiver(info);
2776 } else {
2777 if ( info->rx_enabled )
2778 usc_stop_receiver(info);
2780 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2781 return 0;
2783 } /* end of mgsl_rxenable() */
2785 /* mgsl_wait_event() wait for specified event to occur
2787 * Arguments: info pointer to device instance data
2788 * mask pointer to bitmask of events to wait for
2789 * Return Value: 0 if successful and bit mask updated with
2790 * of events triggerred,
2791 * otherwise error code
2793 static int mgsl_wait_event(struct mgsl_struct * info, int * mask_ptr)
2795 unsigned long flags;
2796 int s;
2797 int rc=0;
2798 u16 regval;
2799 struct mgsl_icount cprev, cnow;
2800 int events = 0;
2801 int mask;
2802 struct _input_signal_events signal_events_prev, signal_events_now;
2804 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2805 if (rc) {
2806 return -EFAULT;
2809 if (debug_level >= DEBUG_LEVEL_INFO)
2810 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2811 info->device_name, mask);
2813 spin_lock_irqsave(&info->irq_spinlock,flags);
2815 usc_get_serial_signals(info);
2816 s = info->serial_signals;
2818 /* note the counters on entry */
2819 cprev = info->icount;
2820 signal_events_prev = info->input_signal_events;
2822 if (mask & MgslEvent_ExitHuntMode) {
2823 /* enable exit hunt mode IRQ */
2824 regval = usc_InReg(info,RICR);
2825 if (!(regval & RXSTATUS_EXITED_HUNT))
2826 usc_OutReg(info, RICR, regval | RXSTATUS_EXITED_HUNT);
2829 if (mask & MgslEvent_IdleReceived) {
2830 /* enable idle mode received IRQ */
2831 regval = usc_InReg(info,RICR);
2832 if (!(regval & RXSTATUS_IDLE_RECEIVED))
2833 usc_OutReg(info, RICR, regval | RXSTATUS_IDLE_RECEIVED);
2836 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2838 /* Determine if any user requested events for input signals is currently TRUE */
2840 events |= (mask & ((s & SerialSignal_DSR) ?
2841 MgslEvent_DsrActive:MgslEvent_DsrInactive));
2843 events |= (mask & ((s & SerialSignal_DCD) ?
2844 MgslEvent_DcdActive:MgslEvent_DcdInactive));
2846 events |= (mask & ((s & SerialSignal_CTS) ?
2847 MgslEvent_CtsActive:MgslEvent_CtsInactive));
2849 events |= (mask & ((s & SerialSignal_RI) ?
2850 MgslEvent_RiActive:MgslEvent_RiInactive));
2853 while(!events) {
2854 /* sleep until event occurs */
2855 interruptible_sleep_on(&info->event_wait_q);
2857 /* see if a signal woke us */
2858 if (signal_pending(current)) {
2859 rc = -ERESTARTSYS;
2860 break;
2863 spin_lock_irqsave(&info->irq_spinlock,flags);
2865 /* get icount and serial signal states */
2866 cnow = info->icount;
2867 signal_events_now = info->input_signal_events;
2868 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2870 if (signal_events_now.dsr_up != signal_events_prev.dsr_up &&
2871 mask & MgslEvent_DsrActive )
2872 events |= MgslEvent_DsrActive;
2874 if (signal_events_now.dsr_down != signal_events_prev.dsr_down &&
2875 mask & MgslEvent_DsrInactive )
2876 events |= MgslEvent_DsrInactive;
2878 if (signal_events_now.dcd_up != signal_events_prev.dcd_up &&
2879 mask & MgslEvent_DcdActive )
2880 events |= MgslEvent_DcdActive;
2882 if (signal_events_now.dcd_down != signal_events_prev.dcd_down &&
2883 mask & MgslEvent_DcdInactive )
2884 events |= MgslEvent_DcdInactive;
2886 if (signal_events_now.cts_up != signal_events_prev.cts_up &&
2887 mask & MgslEvent_CtsActive )
2888 events |= MgslEvent_CtsActive;
2890 if (signal_events_now.cts_down != signal_events_prev.cts_down &&
2891 mask & MgslEvent_CtsInactive )
2892 events |= MgslEvent_CtsInactive;
2894 if (signal_events_now.ri_up != signal_events_prev.ri_up &&
2895 mask & MgslEvent_RiActive )
2896 events |= MgslEvent_RiActive;
2898 if (signal_events_now.ri_down != signal_events_prev.ri_down &&
2899 mask & MgslEvent_RiInactive )
2900 events |= MgslEvent_RiInactive;
2902 if (cnow.exithunt != cprev.exithunt)
2903 events |= (mask & MgslEvent_ExitHuntMode);
2905 if (cnow.rxidle != cprev.rxidle)
2906 events |= (mask & MgslEvent_IdleReceived);
2908 cprev = cnow;
2909 signal_events_prev = signal_events_now;
2912 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2913 spin_lock_irqsave(&info->irq_spinlock,flags);
2914 if (!waitqueue_active(&info->event_wait_q)) {
2915 /* disable enable exit hunt mode/idle rcvd IRQs */
2916 regval = usc_InReg(info,RICR);
2917 usc_OutReg(info, RICR, regval &
2918 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2920 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2923 if ( rc == 0 )
2924 PUT_USER(rc, events, mask_ptr);
2926 return rc;
2928 } /* end of mgsl_wait_event() */
2930 /* get_modem_info()
2932 * Read the state of the serial control and
2933 * status signals and return to caller.
2935 * Arguments: info pointer to device instance data
2936 * value pointer to int to hold returned info
2938 * Return Value: 0 if success, otherwise error code
2940 static int get_modem_info(struct mgsl_struct * info, unsigned int *value)
2942 unsigned int result = 0;
2943 unsigned long flags;
2944 int err;
2946 spin_lock_irqsave(&info->irq_spinlock,flags);
2947 usc_get_serial_signals(info);
2948 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2950 if (info->serial_signals & SerialSignal_RTS)
2951 result |= TIOCM_RTS;
2952 if (info->serial_signals & SerialSignal_DTR)
2953 result |= TIOCM_DTR;
2954 if (info->serial_signals & SerialSignal_DCD)
2955 result |= TIOCM_CAR;
2956 if (info->serial_signals & SerialSignal_RI)
2957 result |= TIOCM_RNG;
2958 if (info->serial_signals & SerialSignal_DSR)
2959 result |= TIOCM_DSR;
2960 if (info->serial_signals & SerialSignal_CTS)
2961 result |= TIOCM_CTS;
2963 if (debug_level >= DEBUG_LEVEL_INFO)
2964 printk("%s(%d):mgsl_get_modem_info %s value=%08X\n",
2965 __FILE__,__LINE__, info->device_name, result );
2967 PUT_USER(err,result,value);
2968 return err;
2969 } /* end of get_modem_info() */
2971 /* set_modem_info()
2973 * Set the state of the modem control signals (DTR/RTS)
2975 * Arguments:
2977 * info pointer to device instance data
2978 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2979 * TIOCMSET = set/clear signal values
2980 * value bit mask for command
2982 * Return Value: 0 if success, otherwise error code
2984 static int set_modem_info(struct mgsl_struct * info, unsigned int cmd,
2985 unsigned int *value)
2987 int error;
2988 unsigned int arg;
2989 unsigned long flags;
2991 if (debug_level >= DEBUG_LEVEL_INFO)
2992 printk("%s(%d):mgsl_set_modem_info %s\n", __FILE__,__LINE__,
2993 info->device_name );
2995 GET_USER(error,arg,value);
2996 if (error)
2997 return error;
2999 switch (cmd) {
3000 case TIOCMBIS:
3001 if (arg & TIOCM_RTS)
3002 info->serial_signals |= SerialSignal_RTS;
3003 if (arg & TIOCM_DTR)
3004 info->serial_signals |= SerialSignal_DTR;
3005 break;
3006 case TIOCMBIC:
3007 if (arg & TIOCM_RTS)
3008 info->serial_signals &= ~SerialSignal_RTS;
3009 if (arg & TIOCM_DTR)
3010 info->serial_signals &= ~SerialSignal_DTR;
3011 break;
3012 case TIOCMSET:
3013 if (arg & TIOCM_RTS)
3014 info->serial_signals |= SerialSignal_RTS;
3015 else
3016 info->serial_signals &= ~SerialSignal_RTS;
3018 if (arg & TIOCM_DTR)
3019 info->serial_signals |= SerialSignal_DTR;
3020 else
3021 info->serial_signals &= ~SerialSignal_DTR;
3022 break;
3023 default:
3024 return -EINVAL;
3027 spin_lock_irqsave(&info->irq_spinlock,flags);
3028 usc_set_serial_signals(info);
3029 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3031 return 0;
3033 } /* end of set_modem_info() */
3035 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
3036 /* mgsl_break() Set or clear transmit break condition
3038 * Arguments: tty pointer to tty instance data
3039 * break_state -1=set break condition, 0=clear
3040 * Return Value: None
3042 static void mgsl_break(struct tty_struct *tty, int break_state)
3044 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3045 unsigned long flags;
3047 if (debug_level >= DEBUG_LEVEL_INFO)
3048 printk("%s(%d):mgsl_break(%s,%d)\n",
3049 __FILE__,__LINE__, info->device_name, break_state);
3051 if (mgsl_paranoia_check(info, tty->device, "mgsl_break"))
3052 return;
3054 spin_lock_irqsave(&info->irq_spinlock,flags);
3055 if (break_state == -1)
3056 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
3057 else
3058 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
3059 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3061 } /* end of mgsl_break() */
3062 #endif
3064 /* mgsl_ioctl() Service an IOCTL request
3066 * Arguments:
3068 * tty pointer to tty instance data
3069 * file pointer to associated file object for device
3070 * cmd IOCTL command code
3071 * arg command argument/context
3073 * Return Value: 0 if success, otherwise error code
3075 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
3076 unsigned int cmd, unsigned long arg)
3078 int error;
3079 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3080 struct mgsl_icount cprev, cnow; /* kernel counter temps */
3081 struct serial_icounter_struct *p_cuser; /* user space */
3082 unsigned long flags;
3084 if (debug_level >= DEBUG_LEVEL_INFO)
3085 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
3086 info->device_name, cmd );
3088 if (mgsl_paranoia_check(info, tty->device, "mgsl_ioctl"))
3089 return -ENODEV;
3091 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3092 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
3093 if (tty->flags & (1 << TTY_IO_ERROR))
3094 return -EIO;
3097 switch (cmd) {
3098 case TIOCMGET:
3099 return get_modem_info(info, (unsigned int *) arg);
3100 case TIOCMBIS:
3101 case TIOCMBIC:
3102 case TIOCMSET:
3103 return set_modem_info(info, cmd, (unsigned int *) arg);
3104 case MGSL_IOCGPARAMS:
3105 return mgsl_get_params(info,(MGSL_PARAMS *)arg);
3106 case MGSL_IOCSPARAMS:
3107 return mgsl_set_params(info,(MGSL_PARAMS *)arg);
3108 case MGSL_IOCGTXIDLE:
3109 return mgsl_get_txidle(info,(int*)arg);
3110 case MGSL_IOCSTXIDLE:
3111 return mgsl_set_txidle(info,(int)arg);
3112 case MGSL_IOCTXENABLE:
3113 return mgsl_txenable(info,(int)arg);
3114 case MGSL_IOCRXENABLE:
3115 return mgsl_rxenable(info,(int)arg);
3116 case MGSL_IOCTXABORT:
3117 return mgsl_txabort(info);
3118 case MGSL_IOCGSTATS:
3119 return mgsl_get_stats(info,(struct mgsl_icount*)arg);
3120 case MGSL_IOCWAITEVENT:
3121 return mgsl_wait_event(info,(int*)arg);
3122 case MGSL_IOCLOOPTXDONE:
3123 return mgsl_loopmode_send_done(info);
3124 case MGSL_IOCCLRMODCOUNT:
3125 while(MOD_IN_USE)
3126 MOD_DEC_USE_COUNT;
3127 return 0;
3129 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
3130 * - mask passed in arg for lines of interest
3131 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
3132 * Caller should use TIOCGICOUNT to see which one it was
3134 case TIOCMIWAIT:
3135 spin_lock_irqsave(&info->irq_spinlock,flags);
3136 /* note the counters on entry */
3137 cprev = info->icount;
3138 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3139 while (1) {
3140 interruptible_sleep_on(&info->status_event_wait_q);
3141 /* see if a signal did it */
3142 if (signal_pending(current))
3143 return -ERESTARTSYS;
3144 save_flags(flags); cli();
3145 cnow = info->icount; /* atomic copy */
3146 restore_flags(flags);
3147 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3148 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
3149 return -EIO; /* no change => error */
3150 if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
3151 ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
3152 ((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
3153 ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
3154 return 0;
3156 cprev = cnow;
3158 /* NOTREACHED */
3161 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3162 * Return: write counters to the user passed counter struct
3163 * NB: both 1->0 and 0->1 transitions are counted except for
3164 * RI where only 0->1 is counted.
3166 case TIOCGICOUNT:
3167 spin_lock_irqsave(&info->irq_spinlock,flags);
3168 cnow = info->icount;
3169 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3170 p_cuser = (struct serial_icounter_struct *) arg;
3171 PUT_USER(error,cnow.cts, &p_cuser->cts);
3172 if (error) return error;
3173 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3174 if (error) return error;
3175 PUT_USER(error,cnow.rng, &p_cuser->rng);
3176 if (error) return error;
3177 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3178 if (error) return error;
3179 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
3180 PUT_USER(error,cnow.rx, &p_cuser->rx);
3181 if (error) return error;
3182 PUT_USER(error,cnow.tx, &p_cuser->tx);
3183 if (error) return error;
3184 PUT_USER(error,cnow.frame, &p_cuser->frame);
3185 if (error) return error;
3186 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3187 if (error) return error;
3188 PUT_USER(error,cnow.parity, &p_cuser->parity);
3189 if (error) return error;
3190 PUT_USER(error,cnow.brk, &p_cuser->brk);
3191 if (error) return error;
3192 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3193 if (error) return error;
3194 #endif
3195 return 0;
3197 default:
3198 return -ENOIOCTLCMD;
3200 return 0;
3203 /* mgsl_set_termios()
3205 * Set new termios settings
3207 * Arguments:
3209 * tty pointer to tty structure
3210 * termios pointer to buffer to hold returned old termios
3212 * Return Value: None
3214 static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3216 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3217 unsigned long flags;
3219 if (debug_level >= DEBUG_LEVEL_INFO)
3220 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3221 tty->driver.name );
3223 /* just return if nothing has changed */
3224 if ((tty->termios->c_cflag == old_termios->c_cflag)
3225 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3226 == RELEVANT_IFLAG(old_termios->c_iflag)))
3227 return;
3229 mgsl_change_params(info);
3231 /* Handle transition to B0 status */
3232 if (old_termios->c_cflag & CBAUD &&
3233 !(tty->termios->c_cflag & CBAUD)) {
3234 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3235 spin_lock_irqsave(&info->irq_spinlock,flags);
3236 usc_set_serial_signals(info);
3237 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3240 /* Handle transition away from B0 status */
3241 if (!(old_termios->c_cflag & CBAUD) &&
3242 tty->termios->c_cflag & CBAUD) {
3243 info->serial_signals |= SerialSignal_DTR;
3244 if (!(tty->termios->c_cflag & CRTSCTS) ||
3245 !test_bit(TTY_THROTTLED, &tty->flags)) {
3246 info->serial_signals |= SerialSignal_RTS;
3248 spin_lock_irqsave(&info->irq_spinlock,flags);
3249 usc_set_serial_signals(info);
3250 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3253 /* Handle turning off CRTSCTS */
3254 if (old_termios->c_cflag & CRTSCTS &&
3255 !(tty->termios->c_cflag & CRTSCTS)) {
3256 tty->hw_stopped = 0;
3257 mgsl_start(tty);
3260 } /* end of mgsl_set_termios() */
3262 /* mgsl_close()
3264 * Called when port is closed. Wait for remaining data to be
3265 * sent. Disable port and free resources.
3267 * Arguments:
3269 * tty pointer to open tty structure
3270 * filp pointer to open file object
3272 * Return Value: None
3274 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3276 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3278 if (!info || mgsl_paranoia_check(info, tty->device, "mgsl_close"))
3279 return;
3281 if (debug_level >= DEBUG_LEVEL_INFO)
3282 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3283 __FILE__,__LINE__, info->device_name, info->count);
3285 if (!info->count || tty_hung_up_p(filp))
3286 goto cleanup;
3288 if ((tty->count == 1) && (info->count != 1)) {
3290 * tty->count is 1 and the tty structure will be freed.
3291 * info->count should be one in this case.
3292 * if it's not, correct it so that the port is shutdown.
3294 printk("mgsl_close: bad refcount; tty->count is 1, "
3295 "info->count is %d\n", info->count);
3296 info->count = 1;
3299 info->count--;
3301 /* if at least one open remaining, leave hardware active */
3302 if (info->count)
3303 goto cleanup;
3305 info->flags |= ASYNC_CLOSING;
3307 /* Save the termios structure, since this port may have
3308 * separate termios for callout and dialin.
3310 if (info->flags & ASYNC_NORMAL_ACTIVE)
3311 info->normal_termios = *tty->termios;
3312 if (info->flags & ASYNC_CALLOUT_ACTIVE)
3313 info->callout_termios = *tty->termios;
3315 /* set tty->closing to notify line discipline to
3316 * only process XON/XOFF characters. Only the N_TTY
3317 * discipline appears to use this (ppp does not).
3319 tty->closing = 1;
3321 /* wait for transmit data to clear all layers */
3323 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3324 if (debug_level >= DEBUG_LEVEL_INFO)
3325 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3326 __FILE__,__LINE__, info->device_name );
3327 tty_wait_until_sent(tty, info->closing_wait);
3330 if (info->flags & ASYNC_INITIALIZED)
3331 mgsl_wait_until_sent(tty, info->timeout);
3333 if (tty->driver.flush_buffer)
3334 tty->driver.flush_buffer(tty);
3336 if (tty->ldisc.flush_buffer)
3337 tty->ldisc.flush_buffer(tty);
3339 shutdown(info);
3341 tty->closing = 0;
3342 info->tty = 0;
3344 if (info->blocked_open) {
3345 if (info->close_delay) {
3346 current->state = TASK_INTERRUPTIBLE;
3347 schedule_timeout(info->close_delay);
3349 wake_up_interruptible(&info->open_wait);
3352 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|
3353 ASYNC_CLOSING);
3355 wake_up_interruptible(&info->close_wait);
3357 cleanup:
3358 if (debug_level >= DEBUG_LEVEL_INFO)
3359 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3360 tty->driver.name, info->count);
3361 if(MOD_IN_USE)
3362 MOD_DEC_USE_COUNT;
3364 } /* end of mgsl_close() */
3366 /* mgsl_wait_until_sent()
3368 * Wait until the transmitter is empty.
3370 * Arguments:
3372 * tty pointer to tty info structure
3373 * timeout time to wait for send completion
3375 * Return Value: None
3377 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3379 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3380 unsigned long orig_jiffies, char_time;
3382 if (!info )
3383 return;
3385 if (debug_level >= DEBUG_LEVEL_INFO)
3386 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3387 __FILE__,__LINE__, info->device_name );
3389 if (mgsl_paranoia_check(info, tty->device, "mgsl_wait_until_sent"))
3390 return;
3392 if (!(info->flags & ASYNC_INITIALIZED))
3393 goto exit;
3395 orig_jiffies = jiffies;
3397 /* Set check interval to 1/5 of estimated time to
3398 * send a character, and make it at least 1. The check
3399 * interval should also be less than the timeout.
3400 * Note: use tight timings here to satisfy the NIST-PCTS.
3403 if ( info->params.data_rate ) {
3404 char_time = info->timeout/(32 * 5);
3405 if (!char_time)
3406 char_time++;
3407 } else
3408 char_time = 1;
3410 if (timeout)
3411 char_time = MIN(char_time, timeout);
3413 if ( info->params.mode == MGSL_MODE_HDLC ) {
3414 while (info->tx_active) {
3415 current->state = TASK_INTERRUPTIBLE;
3416 current->counter = 0; /* make us low-priority */
3417 schedule_timeout(char_time);
3418 if (signal_pending(current))
3419 break;
3420 if (timeout && ((orig_jiffies + timeout) < jiffies))
3421 break;
3423 } else {
3424 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3425 info->tx_enabled) {
3426 current->state = TASK_INTERRUPTIBLE;
3427 current->counter = 0; /* make us low-priority */
3428 schedule_timeout(char_time);
3429 if (signal_pending(current))
3430 break;
3431 if (timeout && ((orig_jiffies + timeout) < jiffies))
3432 break;
3436 current->state = TASK_RUNNING;
3437 exit:
3438 if (debug_level >= DEBUG_LEVEL_INFO)
3439 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3440 __FILE__,__LINE__, info->device_name );
3442 } /* end of mgsl_wait_until_sent() */
3444 /* mgsl_hangup()
3446 * Called by tty_hangup() when a hangup is signaled.
3447 * This is the same as to closing all open files for the port.
3449 * Arguments: tty pointer to associated tty object
3450 * Return Value: None
3452 static void mgsl_hangup(struct tty_struct *tty)
3454 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3456 if (debug_level >= DEBUG_LEVEL_INFO)
3457 printk("%s(%d):mgsl_hangup(%s)\n",
3458 __FILE__,__LINE__, info->device_name );
3460 if (mgsl_paranoia_check(info, tty->device, "mgsl_hangup"))
3461 return;
3463 mgsl_flush_buffer(tty);
3464 shutdown(info);
3466 info->count = 0;
3467 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
3468 info->tty = 0;
3470 wake_up_interruptible(&info->open_wait);
3472 } /* end of mgsl_hangup() */
3474 /* block_til_ready()
3476 * Block the current process until the specified port
3477 * is ready to be opened.
3479 * Arguments:
3481 * tty pointer to tty info structure
3482 * filp pointer to open file object
3483 * info pointer to device instance data
3485 * Return Value: 0 if success, otherwise error code
3487 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3488 struct mgsl_struct *info)
3490 DECLARE_WAITQUEUE(wait, current);
3491 int retval;
3492 int do_clocal = 0, extra_count = 0;
3493 unsigned long flags;
3495 if (debug_level >= DEBUG_LEVEL_INFO)
3496 printk("%s(%d):block_til_ready on %s\n",
3497 __FILE__,__LINE__, tty->driver.name );
3499 if (tty->driver.subtype == SERIAL_TYPE_CALLOUT) {
3500 /* this is a callout device */
3501 /* just verify that normal device is not in use */
3502 if (info->flags & ASYNC_NORMAL_ACTIVE)
3503 return -EBUSY;
3504 if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
3505 (info->flags & ASYNC_SESSION_LOCKOUT) &&
3506 (info->session != current->session))
3507 return -EBUSY;
3508 if ((info->flags & ASYNC_CALLOUT_ACTIVE) &&
3509 (info->flags & ASYNC_PGRP_LOCKOUT) &&
3510 (info->pgrp != current->pgrp))
3511 return -EBUSY;
3512 info->flags |= ASYNC_CALLOUT_ACTIVE;
3513 return 0;
3516 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3517 /* nonblock mode is set or port is not enabled */
3518 /* just verify that callout device is not active */
3519 if (info->flags & ASYNC_CALLOUT_ACTIVE)
3520 return -EBUSY;
3521 info->flags |= ASYNC_NORMAL_ACTIVE;
3522 return 0;
3525 if (info->flags & ASYNC_CALLOUT_ACTIVE) {
3526 if (info->normal_termios.c_cflag & CLOCAL)
3527 do_clocal = 1;
3528 } else {
3529 if (tty->termios->c_cflag & CLOCAL)
3530 do_clocal = 1;
3533 /* Wait for carrier detect and the line to become
3534 * free (i.e., not in use by the callout). While we are in
3535 * this loop, info->count is dropped by one, so that
3536 * mgsl_close() knows when to free things. We restore it upon
3537 * exit, either normal or abnormal.
3540 retval = 0;
3541 add_wait_queue(&info->open_wait, &wait);
3543 if (debug_level >= DEBUG_LEVEL_INFO)
3544 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3545 __FILE__,__LINE__, tty->driver.name, info->count );
3547 save_flags(flags); cli();
3548 if (!tty_hung_up_p(filp)) {
3549 extra_count = 1;
3550 info->count--;
3552 restore_flags(flags);
3553 info->blocked_open++;
3555 while (1) {
3556 if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
3557 (tty->termios->c_cflag & CBAUD)) {
3558 spin_lock_irqsave(&info->irq_spinlock,flags);
3559 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3560 usc_set_serial_signals(info);
3561 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3564 current->state = TASK_INTERRUPTIBLE;
3566 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3567 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3568 -EAGAIN : -ERESTARTSYS;
3569 break;
3572 spin_lock_irqsave(&info->irq_spinlock,flags);
3573 usc_get_serial_signals(info);
3574 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3576 if (!(info->flags & ASYNC_CALLOUT_ACTIVE) &&
3577 !(info->flags & ASYNC_CLOSING) &&
3578 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3579 break;
3582 if (signal_pending(current)) {
3583 retval = -ERESTARTSYS;
3584 break;
3587 if (debug_level >= DEBUG_LEVEL_INFO)
3588 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3589 __FILE__,__LINE__, tty->driver.name, info->count );
3591 schedule();
3594 current->state = TASK_RUNNING;
3595 remove_wait_queue(&info->open_wait, &wait);
3597 if (extra_count)
3598 info->count++;
3599 info->blocked_open--;
3601 if (debug_level >= DEBUG_LEVEL_INFO)
3602 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3603 __FILE__,__LINE__, tty->driver.name, info->count );
3605 if (!retval)
3606 info->flags |= ASYNC_NORMAL_ACTIVE;
3608 return retval;
3610 } /* end of block_til_ready() */
3612 /* mgsl_open()
3614 * Called when a port is opened. Init and enable port.
3615 * Perform serial-specific initialization for the tty structure.
3617 * Arguments: tty pointer to tty info structure
3618 * filp associated file pointer
3620 * Return Value: 0 if success, otherwise error code
3622 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3624 struct mgsl_struct *info;
3625 int retval, line;
3626 unsigned long page;
3628 /* verify range of specified line number */
3629 line = MINOR(tty->device) - tty->driver.minor_start;
3630 if ((line < 0) || (line >= mgsl_device_count)) {
3631 printk("%s(%d):mgsl_open with illegal line #%d.\n",
3632 __FILE__,__LINE__,line);
3633 return -ENODEV;
3636 /* find the info structure for the specified line */
3637 info = mgsl_device_list;
3638 while(info && info->line != line)
3639 info = info->next_device;
3640 if ( !info ){
3641 printk("%s(%d):Can't find specified device on open (line=%d)\n",
3642 __FILE__,__LINE__,line);
3643 return -ENODEV;
3646 tty->driver_data = info;
3647 info->tty = tty;
3648 if (mgsl_paranoia_check(info, tty->device, "mgsl_open"))
3649 return -ENODEV;
3651 if (debug_level >= DEBUG_LEVEL_INFO)
3652 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3653 __FILE__,__LINE__,tty->driver.name, info->count);
3655 MOD_INC_USE_COUNT;
3657 /* If port is closing, signal caller to try again */
3658 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3659 if (info->flags & ASYNC_CLOSING)
3660 interruptible_sleep_on(&info->close_wait);
3661 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3662 -EAGAIN : -ERESTARTSYS);
3663 goto cleanup;
3666 if (!tmp_buf) {
3667 page = get_free_page(GFP_KERNEL);
3668 if (!page) {
3669 retval = -ENOMEM;
3670 goto cleanup;
3672 if (tmp_buf)
3673 free_page(page);
3674 else
3675 tmp_buf = (unsigned char *) page;
3678 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
3679 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3680 #endif
3682 info->count++;
3683 if (info->count == 1) {
3684 /* 1st open on this device, init hardware */
3685 retval = startup(info);
3686 if (retval < 0)
3687 goto cleanup;
3690 retval = block_til_ready(tty, filp, info);
3691 if (retval) {
3692 if (debug_level >= DEBUG_LEVEL_INFO)
3693 printk("%s(%d):block_til_ready(%s) returned %d\n",
3694 __FILE__,__LINE__, info->device_name, retval);
3695 goto cleanup;
3698 if ((info->count == 1) &&
3699 info->flags & ASYNC_SPLIT_TERMIOS) {
3700 if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
3701 *tty->termios = info->normal_termios;
3702 else
3703 *tty->termios = info->callout_termios;
3704 mgsl_change_params(info);
3707 info->session = current->session;
3708 info->pgrp = current->pgrp;
3710 if (debug_level >= DEBUG_LEVEL_INFO)
3711 printk("%s(%d):mgsl_open(%s) success\n",
3712 __FILE__,__LINE__, info->device_name);
3713 retval = 0;
3715 cleanup:
3716 if (retval) {
3717 if(MOD_IN_USE)
3718 MOD_DEC_USE_COUNT;
3719 if(info->count)
3720 info->count--;
3723 return retval;
3725 } /* end of mgsl_open() */
3728 * /proc fs routines....
3731 static inline int line_info(char *buf, struct mgsl_struct *info)
3733 char stat_buf[30];
3734 int ret;
3735 unsigned long flags;
3737 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3738 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3739 info->device_name, info->io_base, info->irq_level,
3740 info->phys_memory_base, info->phys_lcr_base);
3741 } else {
3742 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3743 info->device_name, info->io_base,
3744 info->irq_level, info->dma_level);
3747 /* output current serial signal states */
3748 spin_lock_irqsave(&info->irq_spinlock,flags);
3749 usc_get_serial_signals(info);
3750 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3752 stat_buf[0] = 0;
3753 stat_buf[1] = 0;
3754 if (info->serial_signals & SerialSignal_RTS)
3755 strcat(stat_buf, "|RTS");
3756 if (info->serial_signals & SerialSignal_CTS)
3757 strcat(stat_buf, "|CTS");
3758 if (info->serial_signals & SerialSignal_DTR)
3759 strcat(stat_buf, "|DTR");
3760 if (info->serial_signals & SerialSignal_DSR)
3761 strcat(stat_buf, "|DSR");
3762 if (info->serial_signals & SerialSignal_DCD)
3763 strcat(stat_buf, "|CD");
3764 if (info->serial_signals & SerialSignal_RI)
3765 strcat(stat_buf, "|RI");
3767 if (info->params.mode == MGSL_MODE_HDLC) {
3768 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3769 info->icount.txok, info->icount.rxok);
3770 if (info->icount.txunder)
3771 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3772 if (info->icount.txabort)
3773 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3774 if (info->icount.rxshort)
3775 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3776 if (info->icount.rxlong)
3777 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3778 if (info->icount.rxover)
3779 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3780 if (info->icount.rxcrc)
3781 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
3782 } else {
3783 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3784 info->icount.tx, info->icount.rx);
3785 if (info->icount.frame)
3786 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3787 if (info->icount.parity)
3788 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3789 if (info->icount.brk)
3790 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3791 if (info->icount.overrun)
3792 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3795 /* Append serial signal status to end */
3796 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3798 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d bh_q=%p\n",
3799 info->tx_active,info->bh_requested,info->bh_running,
3800 info->bh_queue_head);
3802 spin_lock_irqsave(&info->irq_spinlock,flags);
3804 u16 Tscr = usc_InReg( info, TCSR );
3805 u16 Tdmr = usc_InDmaReg( info, TDMR );
3806 u16 Ticr = usc_InReg( info, TICR );
3807 u16 Rscr = usc_InReg( info, RCSR );
3808 u16 Rdmr = usc_InDmaReg( info, RDMR );
3809 u16 Ricr = usc_InReg( info, RICR );
3810 u16 Icr = usc_InReg( info, ICR );
3811 u16 Dccr = usc_InReg( info, DCCR );
3812 u16 Tmr = usc_InReg( info, TMR );
3813 u16 Tccr = usc_InReg( info, TCCR );
3814 u16 Ccar = inw( info->io_base + CCAR );
3815 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3816 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3817 Tscr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3819 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3821 return ret;
3823 } /* end of line_info() */
3825 /* mgsl_read_proc()
3827 * Called to print information about devices
3829 * Arguments:
3830 * page page of memory to hold returned info
3831 * start
3832 * off
3833 * count
3834 * eof
3835 * data
3837 * Return Value:
3839 int mgsl_read_proc(char *page, char **start, off_t off, int count,
3840 int *eof, void *data)
3842 int len = 0, l;
3843 off_t begin = 0;
3844 struct mgsl_struct *info;
3846 len += sprintf(page, "synclink driver:%s\n", driver_version);
3848 info = mgsl_device_list;
3849 while( info ) {
3850 l = line_info(page + len, info);
3851 len += l;
3852 if (len+begin > off+count)
3853 goto done;
3854 if (len+begin < off) {
3855 begin += len;
3856 len = 0;
3858 info = info->next_device;
3861 *eof = 1;
3862 done:
3863 if (off >= len+begin)
3864 return 0;
3865 *start = page + (begin-off);
3866 return ((count < begin+len-off) ? count : begin+len-off);
3868 } /* end of mgsl_read_proc() */
3870 /* mgsl_allocate_dma_buffers()
3872 * Allocate and format DMA buffers (ISA adapter)
3873 * or format shared memory buffers (PCI adapter).
3875 * Arguments: info pointer to device instance data
3876 * Return Value: 0 if success, otherwise error
3878 int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3880 unsigned short BuffersPerFrame;
3882 info->last_mem_alloc = 0;
3884 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3886 * The PCI adapter has 256KBytes of shared memory to use.
3887 * This is 64 PAGE_SIZE buffers. 1 is used for the buffer
3888 * list. 2 are used for the transmit and one is left as
3889 * a spare. The 4K buffer list can hold 128 DMA_BUFFER
3890 * structures at 32bytes each.
3893 info->rx_buffer_count = 60;
3894 info->tx_buffer_count = 2;
3895 } else {
3896 /* Calculate the number of PAGE_SIZE buffers needed for */
3897 /* receive and transmit DMA buffers. */
3899 /* Calculate the number of DMA buffers necessary to hold the */
3900 /* largest allowable frame size. Note: If the max frame size is */
3901 /* not an even multiple of the DMA buffer size then we need to */
3902 /* round the buffer count per frame up one. */
3904 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3905 if ( info->max_frame_size % DMABUFFERSIZE )
3906 BuffersPerFrame++;
3908 /* Calculate the number of DMA buffers necessary to */
3909 /* hold 7 max size receive frames and one max size transmit frame. */
3910 /* The receive buffer count is bumped by one so we avoid an */
3911 /* End of List condition if all receive buffers are used when */
3912 /* using linked list DMA buffers. */
3914 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3915 info->tx_buffer_count = BuffersPerFrame;
3918 if ( debug_level >= DEBUG_LEVEL_INFO )
3919 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3920 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3922 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3923 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3924 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0) {
3925 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3926 return -ENOMEM;
3929 mgsl_reset_rx_dma_buffers( info );
3931 return 0;
3933 } /* end of mgsl_allocate_dma_buffers() */
3936 * mgsl_alloc_buffer_list_memory()
3938 * Allocate a common DMA buffer for use as the
3939 * receive and transmit buffer lists.
3941 * A buffer list is a set of buffer entries where each entry contains
3942 * a pointer to an actual buffer and a pointer to the next buffer entry
3943 * (plus some other info about the buffer).
3945 * The buffer entries for a list are built to form a circular list so
3946 * that when the entire list has been traversed you start back at the
3947 * beginning.
3949 * This function allocates memory for just the buffer entries.
3950 * The links (pointer to next entry) are filled in with the physical
3951 * address of the next entry so the adapter can navigate the list
3952 * using bus master DMA. The pointers to the actual buffers are filled
3953 * out later when the actual buffers are allocated.
3955 * Arguments: info pointer to device instance data
3956 * Return Value: 0 if success, otherwise error
3958 int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3960 unsigned int i;
3962 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3963 /* PCI adapter uses shared memory. */
3964 info->buffer_list = info->memory_base + info->last_mem_alloc;
3965 info->buffer_list_phys = info->last_mem_alloc;
3966 info->last_mem_alloc += BUFFERLISTSIZE;
3967 } else {
3968 /* ISA adapter uses system memory. */
3969 /* The buffer lists are allocated as a common buffer that both */
3970 /* the processor and adapter can access. This allows the driver to */
3971 /* inspect portions of the buffer while other portions are being */
3972 /* updated by the adapter using Bus Master DMA. */
3974 info->buffer_list = kmalloc(BUFFERLISTSIZE, GFP_KERNEL | GFP_DMA);
3975 if ( info->buffer_list == NULL )
3976 return -ENOMEM;
3978 info->buffer_list_phys = virt_to_bus(info->buffer_list);
3981 /* We got the memory for the buffer entry lists. */
3982 /* Initialize the memory block to all zeros. */
3983 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3985 /* Save virtual address pointers to the receive and */
3986 /* transmit buffer lists. (Receive 1st). These pointers will */
3987 /* be used by the processor to access the lists. */
3988 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3989 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3990 info->tx_buffer_list += info->rx_buffer_count;
3993 * Build the links for the buffer entry lists such that
3994 * two circular lists are built. (Transmit and Receive).
3996 * Note: the links are physical addresses
3997 * which are read by the adapter to determine the next
3998 * buffer entry to use.
4001 for ( i = 0; i < info->rx_buffer_count; i++ ) {
4002 /* calculate and store physical address of this buffer entry */
4003 info->rx_buffer_list[i].phys_entry =
4004 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
4006 /* calculate and store physical address of */
4007 /* next entry in cirular list of entries */
4009 info->rx_buffer_list[i].link = info->buffer_list_phys;
4011 if ( i < info->rx_buffer_count - 1 )
4012 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
4015 for ( i = 0; i < info->tx_buffer_count; i++ ) {
4016 /* calculate and store physical address of this buffer entry */
4017 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
4018 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
4020 /* calculate and store physical address of */
4021 /* next entry in cirular list of entries */
4023 info->tx_buffer_list[i].link = info->buffer_list_phys +
4024 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
4026 if ( i < info->tx_buffer_count - 1 )
4027 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
4030 return 0;
4032 } /* end of mgsl_alloc_buffer_list_memory() */
4035 * mgsl_free_buffer_list_memory()
4037 * Free the common DMA buffer allocated for use as the
4038 * receive and transmit buffer lists. The associated Memory
4039 * Descriptor List (MDL) is also freed.
4041 * Warning:
4043 * The data transfer buffers associated with the buffer list
4044 * MUST be freed before freeing the buffer list itself because
4045 * the buffer list contains the information necessary to free
4046 * the individual buffers!
4048 * Arguments: info pointer to device extension
4049 * Return Value: None
4051 void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
4053 if ( info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI )
4054 kfree_s(info->buffer_list, BUFFERLISTSIZE);
4056 info->buffer_list = NULL;
4057 info->rx_buffer_list = NULL;
4058 info->tx_buffer_list = NULL;
4060 } /* end of mgsl_free_buffer_list_memory() */
4063 * mgsl_alloc_frame_memory()
4065 * Allocate the frame DMA buffers used by the specified buffer list.
4066 * Each DMA buffer will be one memory page in size. This is necessary
4067 * because memory can fragment enough that it may be impossible
4068 * contiguous pages.
4070 * Arguments:
4072 * info pointer to device instance data
4073 * BufferList pointer to list of buffer entries
4074 * Buffercount count of buffer entries in buffer list
4076 * Return Value: 0 if success, otherwise -ENOMEM
4078 int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
4080 int i;
4081 unsigned long phys_addr;
4083 /* Allocate page sized buffers for the receive buffer list */
4085 for ( i = 0; i < Buffercount; i++ ) {
4086 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4087 /* PCI adapter uses shared memory buffers. */
4088 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
4089 phys_addr = info->last_mem_alloc;
4090 info->last_mem_alloc += DMABUFFERSIZE;
4091 } else {
4092 /* ISA adapter uses system memory. */
4093 BufferList[i].virt_addr =
4094 kmalloc(DMABUFFERSIZE, GFP_KERNEL | GFP_DMA);
4095 if ( BufferList[i].virt_addr == NULL )
4096 return -ENOMEM;
4097 phys_addr = virt_to_bus(BufferList[i].virt_addr);
4099 BufferList[i].phys_addr = phys_addr;
4102 return 0;
4104 } /* end of mgsl_alloc_frame_memory() */
4107 * mgsl_free_frame_memory()
4109 * Free the buffers associated with
4110 * each buffer entry of a buffer list.
4112 * Arguments:
4114 * info pointer to device instance data
4115 * BufferList pointer to list of buffer entries
4116 * Buffercount count of buffer entries in buffer list
4118 * Return Value: None
4120 void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
4122 int i;
4124 if ( BufferList ) {
4125 for ( i = 0 ; i < Buffercount ; i++ ) {
4126 if ( BufferList[i].virt_addr ) {
4127 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
4128 kfree_s(BufferList[i].virt_addr, DMABUFFERSIZE);
4129 BufferList[i].virt_addr = NULL;
4134 } /* end of mgsl_free_frame_memory() */
4136 /* mgsl_free_dma_buffers()
4138 * Free DMA buffers
4140 * Arguments: info pointer to device instance data
4141 * Return Value: None
4143 void mgsl_free_dma_buffers( struct mgsl_struct *info )
4145 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
4146 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
4147 mgsl_free_buffer_list_memory( info );
4149 } /* end of mgsl_free_dma_buffers() */
4151 /* mgsl_claim_resources()
4153 * Claim all resources used by a device
4155 * Arguments: info pointer to device instance data
4156 * Return Value: 0 if success, otherwise -ENODEV
4158 int mgsl_claim_resources(struct mgsl_struct *info)
4160 /* claim 16C32 I/O base address */
4162 if ( check_region(info->io_base,info->io_addr_size) < 0 ) {
4163 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4164 __FILE__,__LINE__,info->device_name, info->io_base );
4165 return -ENODEV;
4167 request_region(info->io_base,info->io_addr_size,"synclink.o");
4168 info->io_addr_requested = 1;
4170 /* claim interrupt level */
4172 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4173 info->device_name, info ) < 0 ) {
4174 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4175 __FILE__,__LINE__,info->device_name, info->irq_level );
4176 mgsl_release_resources( info );
4177 return -ENODEV;
4179 info->irq_requested = 1;
4181 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4182 /* claim shared memory range */
4183 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4184 if (!info->memory_base) {
4185 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4186 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4187 mgsl_release_resources( info );
4188 return -ENODEV;
4191 /* test the shared memory range */
4192 if ( !mgsl_memory_test(info) ) {
4193 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4194 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4195 mgsl_release_resources( info );
4196 return -ENODEV;
4199 /* claim LCR memory range */
4200 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4201 if (!info->lcr_base) {
4202 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4203 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4204 mgsl_release_resources( info );
4205 return -ENODEV;
4208 } else {
4209 /* claim DMA channel */
4211 if (request_dma(info->dma_level,info->device_name) < 0){
4212 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4213 __FILE__,__LINE__,info->device_name, info->dma_level );
4214 mgsl_release_resources( info );
4215 return -ENODEV;
4217 info->dma_requested = 1;
4219 /* ISA adapter uses bus master DMA */
4220 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4221 enable_dma(info->dma_level);
4224 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4225 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4226 __FILE__,__LINE__,info->device_name, info->dma_level );
4227 mgsl_release_resources( info );
4228 return -ENODEV;
4231 return 0;
4233 } /* end of mgsl_claim_resources() */
4235 /* mgsl_release_resources()
4237 * Release all resources used by a device
4239 * Arguments: info pointer to device instance data
4240 * Return Value: None
4242 void mgsl_release_resources(struct mgsl_struct *info)
4244 if ( debug_level >= DEBUG_LEVEL_INFO )
4245 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4246 __FILE__,__LINE__,info->device_name );
4248 if ( info->irq_requested ) {
4249 free_irq(info->irq_level, info);
4250 info->irq_requested = 0;
4253 if ( info->dma_requested ) {
4254 disable_dma(info->dma_level);
4255 free_dma(info->dma_level);
4256 info->dma_requested = 0;
4258 mgsl_free_dma_buffers(info);
4260 if ( info->io_addr_requested ) {
4261 release_region(info->io_base,info->io_addr_size);
4262 info->io_addr_requested = 0;
4265 if (info->memory_base){
4266 iounmap(info->memory_base);
4267 info->memory_base = 0;
4270 if (info->lcr_base){
4271 iounmap(info->lcr_base - info->lcr_offset);
4272 info->lcr_base = 0;
4275 if ( debug_level >= DEBUG_LEVEL_INFO )
4276 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4277 __FILE__,__LINE__,info->device_name );
4279 } /* end of mgsl_release_resources() */
4281 /* mgsl_add_device()
4283 * Add the specified device instance data structure to the
4284 * global linked list of devices and increment the device count.
4286 * Arguments: info pointer to device instance data
4287 * Return Value: None
4289 void mgsl_add_device( struct mgsl_struct *info )
4291 info->next_device = NULL;
4292 info->line = mgsl_device_count;
4293 sprintf(info->device_name,"ttySL%d",info->line);
4295 mgsl_device_count++;
4297 if ( !mgsl_device_list )
4298 mgsl_device_list = info;
4299 else {
4300 struct mgsl_struct *current_dev = mgsl_device_list;
4301 while( current_dev->next_device )
4302 current_dev = current_dev->next_device;
4303 current_dev->next_device = info;
4306 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4307 printk( "SyncLink device %s added:PCI bus IO=%04X IRQ=%d Mem=%08X LCR=%08X\n",
4308 info->device_name, info->io_base, info->irq_level,
4309 info->phys_memory_base, info->phys_lcr_base );
4310 } else {
4311 printk( "SyncLink device %s added:ISA bus IO=%04X IRQ=%d DMA=%d\n",
4312 info->device_name, info->io_base, info->irq_level, info->dma_level );
4315 } /* end of mgsl_add_device() */
4317 /* mgsl_allocate_device()
4319 * Allocate and initialize a device instance structure
4321 * Arguments: None
4322 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4324 struct mgsl_struct* mgsl_allocate_device()
4326 struct mgsl_struct *info;
4328 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4329 GFP_KERNEL);
4331 if (!info) {
4332 printk("Error can't allocate device instance data\n");
4333 } else {
4334 memset(info, 0, sizeof(struct mgsl_struct));
4335 info->magic = MGSL_MAGIC;
4336 info->task.sync = 0;
4337 info->task.routine = mgsl_bh_handler;
4338 info->task.data = info;
4339 info->max_frame_size = 4096;
4340 info->close_delay = 5*HZ/10;
4341 info->closing_wait = 30*HZ;
4342 init_waitqueue_head(&info->open_wait);
4343 init_waitqueue_head(&info->close_wait);
4344 init_waitqueue_head(&info->status_event_wait_q);
4345 init_waitqueue_head(&info->event_wait_q);
4347 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4348 info->idle_mode = HDLC_TXIDLE_FLAGS;
4351 return info;
4353 } /* end of mgsl_allocate_device()*/
4355 /* mgsl_enumerate_devices()
4357 * Enumerate SyncLink serial devices based on user specified
4358 * options for ISA adapters and autodetected PCI adapters.
4360 * Arguments: None
4361 * Return Value: 0 if success, otherwise error code
4363 int mgsl_enumerate_devices()
4365 struct mgsl_struct *info;
4366 int i;
4368 /* Check for user specified ISA devices */
4370 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4371 if ( debug_level >= DEBUG_LEVEL_INFO )
4372 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4373 io[i], irq[i], dma[i] );
4375 info = mgsl_allocate_device();
4376 if ( !info ) {
4377 /* error allocating device instance data */
4378 if ( debug_level >= DEBUG_LEVEL_ERROR )
4379 printk( "can't allocate device instance data.\n");
4380 continue;
4383 /* Copy user configuration info to device instance data */
4384 info->io_base = (unsigned int)io[i];
4385 info->irq_level = (unsigned int)irq[i];
4386 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4387 info->irq_level = irq_cannonicalize(info->irq_level);
4388 #else
4389 if (info->irq_level == 2)
4390 info->irq_level = 9;
4391 #endif
4392 info->dma_level = (unsigned int)dma[i];
4393 info->bus_type = MGSL_BUS_TYPE_ISA;
4394 info->io_addr_size = 16;
4395 info->irq_flags = 0;
4397 /* add new device to device list */
4398 mgsl_add_device( info );
4402 #ifdef CONFIG_PCI
4403 /* Auto detect PCI adapters */
4405 if ( pcibios_present() ) {
4406 unsigned char bus;
4407 unsigned char func;
4408 unsigned int shared_mem_base;
4409 unsigned int lcr_mem_base;
4410 unsigned int io_base;
4411 unsigned char irq_line;
4413 for(i=0;;i++){
4414 if ( PCIBIOS_SUCCESSFUL == pcibios_find_device(
4415 MICROGATE_VENDOR_ID, SYNCLINK_DEVICE_ID, i, &bus, &func) ) {
4417 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4418 struct pci_dev *pdev = pci_find_slot(bus,func);
4419 irq_line = pdev->irq;
4420 #else
4421 if (pcibios_read_config_byte(bus,func,
4422 PCI_INTERRUPT_LINE,&irq_line) ) {
4423 printk( "%s(%d):USC I/O addr not set.\n",
4424 __FILE__,__LINE__);
4425 continue;
4427 #endif
4429 if (pcibios_read_config_dword(bus,func,
4430 PCI_BASE_ADDRESS_3,&shared_mem_base) ) {
4431 printk( "%s(%d):Shared mem addr not set.\n",
4432 __FILE__,__LINE__);
4433 continue;
4436 if (pcibios_read_config_dword(bus,func,
4437 PCI_BASE_ADDRESS_0,&lcr_mem_base) ) {
4438 printk( "%s(%d):LCR mem addr not set.\n",
4439 __FILE__,__LINE__);
4440 continue;
4443 if (pcibios_read_config_dword(bus,func,
4444 PCI_BASE_ADDRESS_2,&io_base) ) {
4445 printk( "%s(%d):USC I/O addr not set.\n",
4446 __FILE__,__LINE__);
4447 continue;
4450 info = mgsl_allocate_device();
4451 if ( !info ) {
4452 /* error allocating device instance data */
4453 if ( debug_level >= DEBUG_LEVEL_ERROR )
4454 printk( "can't allocate device instance data.\n");
4455 continue;
4458 /* Copy user configuration info to device instance data */
4460 info->io_base = io_base & PCI_BASE_ADDRESS_IO_MASK;
4461 info->irq_level = (unsigned int)irq_line;
4462 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4463 info->irq_level = irq_cannonicalize(info->irq_level);
4464 #else
4465 if (info->irq_level == 2)
4466 info->irq_level = 9;
4467 #endif
4468 info->phys_memory_base = shared_mem_base & PCI_BASE_ADDRESS_MEM_MASK;
4470 /* Because veremap only works on page boundaries we must map
4471 * a larger area than is actually implemented for the LCR
4472 * memory range. We map a full page starting at the page boundary.
4474 info->phys_lcr_base = lcr_mem_base & PCI_BASE_ADDRESS_MEM_MASK;
4475 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
4476 info->phys_lcr_base &= ~(PAGE_SIZE-1);
4478 info->bus_type = MGSL_BUS_TYPE_PCI;
4479 info->io_addr_size = 8;
4480 info->irq_flags = SA_SHIRQ;
4481 info->bus = bus;
4482 info->function = func;
4484 /* Store the PCI9050 misc control register value because a flaw
4485 * in the PCI9050 prevents LCR registers from being read if
4486 * BIOS assigns an LCR base address with bit 7 set.
4488 * Only the misc control register is accessed for which only
4489 * write access is needed, so set an initial value and change
4490 * bits to the device instance data as we write the value
4491 * to the actual misc control register.
4493 info->misc_ctrl_value = 0x087e4546;
4495 /* add new device to device list */
4496 mgsl_add_device( info );
4497 } else {
4498 break;
4502 #endif
4505 * Allocate memory to hold the following tty/termios arrays
4506 * with an element for each enumerated device.
4509 serial_table = (struct tty_struct**)kmalloc(sizeof(struct tty_struct*)*mgsl_device_count, GFP_KERNEL);
4510 serial_termios = (struct termios**)kmalloc(sizeof(struct termios*)*mgsl_device_count, GFP_KERNEL);
4511 serial_termios_locked = (struct termios**)kmalloc(sizeof(struct termios*)*mgsl_device_count, GFP_KERNEL);
4513 if (!serial_table || !serial_termios || !serial_termios_locked){
4514 printk("%s(%d):Can't allocate tty/termios arrays.\n",
4515 __FILE__,__LINE__);
4516 return -ENOMEM;
4519 memset(serial_table,0,sizeof(struct tty_struct*)*mgsl_device_count);
4520 memset(serial_termios,0,sizeof(struct termios*)*mgsl_device_count);
4521 memset(serial_termios_locked,0,sizeof(struct termios*)*mgsl_device_count);
4523 return 0;
4525 } /* end of mgsl_enumerate_devices() */
4527 /* mgsl_init()
4529 * Driver initialization entry point.
4531 * Arguments: None
4532 * Return Value: 0 if success, otherwise error code
4534 int __init mgsl_init(void)
4536 struct mgsl_struct *info;
4538 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4539 EXPORT_NO_SYMBOLS;
4540 #else
4541 register_symtab(NULL);
4542 #endif
4544 printk("%s version %s\n", driver_name, driver_version);
4546 /* determine how many SyncLink devices are installed */
4547 mgsl_enumerate_devices();
4548 if ( !mgsl_device_list ) {
4549 printk("%s(%d):No SyncLink devices found.\n",__FILE__,__LINE__);
4550 return -ENODEV;
4553 /* Initialize the tty_driver structure */
4555 memset(&serial_driver, 0, sizeof(struct tty_driver));
4556 serial_driver.magic = TTY_DRIVER_MAGIC;
4557 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4558 serial_driver.driver_name = "synclink";
4559 #endif
4560 serial_driver.name = "ttySL";
4561 serial_driver.major = ttymajor;
4562 serial_driver.minor_start = 64;
4563 serial_driver.num = mgsl_device_count;
4564 serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
4565 serial_driver.subtype = SERIAL_TYPE_NORMAL;
4566 serial_driver.init_termios = tty_std_termios;
4567 serial_driver.init_termios.c_cflag =
4568 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4569 serial_driver.flags = TTY_DRIVER_REAL_RAW;
4570 serial_driver.refcount = &serial_refcount;
4571 serial_driver.table = serial_table;
4572 serial_driver.termios = serial_termios;
4573 serial_driver.termios_locked = serial_termios_locked;
4575 serial_driver.open = mgsl_open;
4576 serial_driver.close = mgsl_close;
4577 serial_driver.write = mgsl_write;
4578 serial_driver.put_char = mgsl_put_char;
4579 serial_driver.flush_chars = mgsl_flush_chars;
4580 serial_driver.write_room = mgsl_write_room;
4581 serial_driver.chars_in_buffer = mgsl_chars_in_buffer;
4582 serial_driver.flush_buffer = mgsl_flush_buffer;
4583 serial_driver.ioctl = mgsl_ioctl;
4584 serial_driver.throttle = mgsl_throttle;
4585 serial_driver.unthrottle = mgsl_unthrottle;
4586 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4587 serial_driver.send_xchar = mgsl_send_xchar;
4588 serial_driver.break_ctl = mgsl_break;
4589 serial_driver.wait_until_sent = mgsl_wait_until_sent;
4590 serial_driver.read_proc = mgsl_read_proc;
4591 #endif
4592 serial_driver.set_termios = mgsl_set_termios;
4593 serial_driver.stop = mgsl_stop;
4594 serial_driver.start = mgsl_start;
4595 serial_driver.hangup = mgsl_hangup;
4598 * The callout device is just like normal device except for
4599 * major number and the subtype code.
4601 callout_driver = serial_driver;
4602 callout_driver.name = "cuaSL";
4603 callout_driver.major = cuamajor;
4604 callout_driver.subtype = SERIAL_TYPE_CALLOUT;
4605 #if LINUX_VERSION_CODE >= VERSION(2,1,0)
4606 callout_driver.read_proc = 0;
4607 callout_driver.proc_entry = 0;
4608 #endif
4610 if (tty_register_driver(&serial_driver) < 0)
4611 printk("%s(%d):Couldn't register serial driver\n",
4612 __FILE__,__LINE__);
4614 if (tty_register_driver(&callout_driver) < 0)
4615 printk("%s(%d):Couldn't register callout driver\n",
4616 __FILE__,__LINE__);
4618 printk("%s version %s, tty major#%d callout major#%d\n",
4619 driver_name, driver_version,
4620 serial_driver.major, callout_driver.major);
4622 /* Propagate these values to all device instances */
4624 info = mgsl_device_list;
4625 while(info){
4626 info->callout_termios = callout_driver.init_termios;
4627 info->normal_termios = serial_driver.init_termios;
4628 info = info->next_device;
4631 return 0;
4633 } /* end of mgsl_init() */
4635 #ifdef MODULE
4636 int init_module(void)
4638 /* Uncomment this to kernel debug module.
4639 * mgsl_get_text_ptr() leaves the .text address in eax
4640 * which can be used with add-symbol-file with gdb.
4642 if (break_on_load) {
4643 mgsl_get_text_ptr();
4644 BREAKPOINT();
4647 return mgsl_init();
4650 void cleanup_module(void)
4652 unsigned long flags;
4653 int rc;
4654 struct mgsl_struct *info;
4656 printk("Unloading %s: version %s\n", driver_name, driver_version);
4657 save_flags(flags);
4658 cli();
4659 if ((rc = tty_unregister_driver(&serial_driver)))
4660 printk("%s(%d) failed to unregister tty driver err=%d\n",
4661 __FILE__,__LINE__,rc);
4662 if ((rc = tty_unregister_driver(&callout_driver)))
4663 printk("%s(%d) failed to unregister callout driver err=%d\n",
4664 __FILE__,__LINE__,rc);
4665 restore_flags(flags);
4667 info = mgsl_device_list;
4668 while(info) {
4669 mgsl_release_resources(info);
4670 info = info->next_device;
4673 if (tmp_buf) {
4674 free_page((unsigned long) tmp_buf);
4675 tmp_buf = NULL;
4678 if (serial_table)
4679 kfree_s(serial_table,sizeof(struct tty_struct*)*mgsl_device_count);
4681 if (serial_termios)
4682 kfree_s(serial_termios,sizeof(struct termios*)*mgsl_device_count);
4684 if (serial_termios_locked)
4685 kfree_s(serial_termios_locked,sizeof(struct termios*)*mgsl_device_count);
4687 } /* end of cleanup_module() */
4689 #endif /* MODULE */
4693 * usc_RTCmd()
4695 * Issue a USC Receive/Transmit command to the
4696 * Channel Command/Address Register (CCAR).
4698 * Notes:
4700 * The command is encoded in the most significant 5 bits <15..11>
4701 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4702 * and Bits <6..0> must be written as zeros.
4704 * Arguments:
4706 * info pointer to device information structure
4707 * Cmd command mask (use symbolic macros)
4709 * Return Value:
4711 * None
4713 void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4715 /* output command to CCAR in bits <15..11> */
4716 /* preserve bits <10..7>, bits <6..0> must be zero */
4718 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4720 /* Read to flush write to CCAR */
4721 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4722 inw( info->io_base + CCAR );
4724 } /* end of usc_RTCmd() */
4727 * usc_DmaCmd()
4729 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4731 * Arguments:
4733 * info pointer to device information structure
4734 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4736 * Return Value:
4738 * None
4740 void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4742 /* write command mask to DCAR */
4743 outw( Cmd + info->mbre_bit, info->io_base );
4745 /* Read to flush write to DCAR */
4746 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4747 inw( info->io_base );
4749 } /* end of usc_DmaCmd() */
4752 * usc_OutDmaReg()
4754 * Write a 16-bit value to a USC DMA register
4756 * Arguments:
4758 * info pointer to device info structure
4759 * RegAddr register address (number) for write
4760 * RegValue 16-bit value to write to register
4762 * Return Value:
4764 * None
4767 void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4769 /* Note: The DCAR is located at the adapter base address */
4770 /* Note: must preserve state of BIT8 in DCAR */
4772 outw( RegAddr + info->mbre_bit, info->io_base );
4773 outw( RegValue, info->io_base );
4775 /* Read to flush write to DCAR */
4776 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4777 inw( info->io_base );
4779 } /* end of usc_OutDmaReg() */
4782 * usc_InDmaReg()
4784 * Read a 16-bit value from a DMA register
4786 * Arguments:
4788 * info pointer to device info structure
4789 * RegAddr register address (number) to read from
4791 * Return Value:
4793 * The 16-bit value read from register
4796 u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4798 /* Note: The DCAR is located at the adapter base address */
4799 /* Note: must preserve state of BIT8 in DCAR */
4801 outw( RegAddr + info->mbre_bit, info->io_base );
4802 return inw( info->io_base );
4804 } /* end of usc_InDmaReg() */
4808 * usc_OutReg()
4810 * Write a 16-bit value to a USC serial channel register
4812 * Arguments:
4814 * info pointer to device info structure
4815 * RegAddr register address (number) to write to
4816 * RegValue 16-bit value to write to register
4818 * Return Value:
4820 * None
4823 void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4825 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4826 outw( RegValue, info->io_base + CCAR );
4828 /* Read to flush write to CCAR */
4829 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4830 inw( info->io_base + CCAR );
4832 } /* end of usc_OutReg() */
4835 * usc_InReg()
4837 * Reads a 16-bit value from a USC serial channel register
4839 * Arguments:
4841 * info pointer to device extension
4842 * RegAddr register address (number) to read from
4844 * Return Value:
4846 * 16-bit value read from register
4848 u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4850 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4851 return inw( info->io_base + CCAR );
4853 } /* end of usc_InReg() */
4855 /* usc_set_sdlc_mode()
4857 * Set up the adapter for SDLC DMA communications.
4859 * Arguments: info pointer to device instance data
4860 * Return Value: NONE
4862 void usc_set_sdlc_mode( struct mgsl_struct *info )
4864 u16 RegValue;
4866 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4869 ** Channel Mode Register (CMR)
4871 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4872 ** <13> 0 0 = Transmit Disabled (initially)
4873 ** <12> 0 1 = Consecutive Idles share common 0
4874 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4875 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4876 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4878 ** 1000 1110 0000 0110 = 0x8e06
4880 RegValue = 0x8e06;
4882 /*--------------------------------------------------
4883 * ignore user options for UnderRun Actions and
4884 * preambles
4885 *--------------------------------------------------*/
4887 else
4889 /* Channel mode Register (CMR)
4891 * <15..14> 00 Tx Sub modes, Underrun Action
4892 * <13> 0 1 = Send Preamble before opening flag
4893 * <12> 0 1 = Consecutive Idles share common 0
4894 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4895 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4896 * <3..0> 0110 Receiver mode = HDLC/SDLC
4898 * 0000 0110 0000 0110 = 0x0606
4901 RegValue = 0x0606;
4903 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4904 RegValue |= BIT14;
4905 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4906 RegValue |= BIT15;
4907 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4908 RegValue |= BIT15 + BIT14;
4910 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4911 RegValue |= BIT13;
4914 if ( info->params.flags & HDLC_FLAG_SHARE_ZERO )
4915 RegValue |= BIT12;
4917 if ( info->params.addr_filter != 0xff )
4919 /* set up receive address filtering */
4920 usc_OutReg( info, RSR, info->params.addr_filter );
4921 RegValue |= BIT4;
4924 usc_OutReg( info, CMR, RegValue );
4925 info->cmr_value = RegValue;
4927 /* Receiver mode Register (RMR)
4929 * <15..13> 000 encoding
4930 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4931 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4932 * <9> 0 1 = Include Receive chars in CRC
4933 * <8> 1 1 = Use Abort/PE bit as abort indicator
4934 * <7..6> 00 Even parity
4935 * <5> 0 parity disabled
4936 * <4..2> 000 Receive Char Length = 8 bits
4937 * <1..0> 00 Disable Receiver
4939 * 0000 0101 0000 0000 = 0x0500
4942 RegValue = 0x0500;
4944 switch ( info->params.encoding ) {
4945 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4946 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4947 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4948 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4949 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4950 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4951 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4954 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
4955 RegValue |= BIT9;
4957 usc_OutReg( info, RMR, RegValue );
4961 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4962 /* When an opening flag of an SDLC frame is recognized the */
4963 /* Receive Character count (RCC) is loaded with the value in */
4964 /* RCLR. The RCC is decremented for each received byte. The */
4965 /* value of RCC is stored after the closing flag of the frame */
4966 /* allowing the frame size to be computed. */
4968 usc_OutReg( info, RCLR, RCLRVALUE );
4970 usc_RCmd( info, RCmd_SelectRicrdma_level );
4972 /* Receive Interrupt Control Register (RICR)
4974 * <15..8> ? RxFIFO DMA Request Level
4975 * <7> 0 Exited Hunt IA (Interrupt Arm)
4976 * <6> 0 Idle Received IA
4977 * <5> 0 Break/Abort IA
4978 * <4> 0 Rx Bound IA
4979 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4980 * <2> 0 Abort/PE IA
4981 * <1> 1 Rx Overrun IA
4982 * <0> 0 Select TC0 value for readback
4984 * 0000 0000 0000 1000 = 0x000a
4987 /* Carry over the Exit Hunt and Idle Received bits */
4988 /* in case they have been armed by usc_ArmEvents. */
4990 RegValue = usc_InReg( info, RICR ) & 0xc0;
4992 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4993 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4994 else
4995 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4997 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4999 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5000 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5002 /* Transmit mode Register (TMR)
5004 * <15..13> 000 encoding
5005 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
5006 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
5007 * <9> 0 1 = Tx CRC Enabled
5008 * <8> 0 1 = Append CRC to end of transmit frame
5009 * <7..6> 00 Transmit parity Even
5010 * <5> 0 Transmit parity Disabled
5011 * <4..2> 000 Tx Char Length = 8 bits
5012 * <1..0> 00 Disable Transmitter
5014 * 0000 0100 0000 0000 = 0x0400
5017 RegValue = 0x0400;
5019 switch ( info->params.encoding ) {
5020 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
5021 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
5022 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
5023 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
5024 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
5025 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
5026 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
5029 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
5030 RegValue |= BIT9 + BIT8;
5032 usc_OutReg( info, TMR, RegValue );
5034 usc_set_txidle( info );
5037 usc_TCmd( info, TCmd_SelectTicrdma_level );
5039 /* Transmit Interrupt Control Register (TICR)
5041 * <15..8> ? Transmit FIFO DMA Level
5042 * <7> 0 Present IA (Interrupt Arm)
5043 * <6> 0 Idle Sent IA
5044 * <5> 1 Abort Sent IA
5045 * <4> 1 EOF/EOM Sent IA
5046 * <3> 0 CRC Sent IA
5047 * <2> 1 1 = Wait for SW Trigger to Start Frame
5048 * <1> 1 Tx Underrun IA
5049 * <0> 0 TC0 constant on read back
5051 * 0000 0000 0011 0110 = 0x0036
5054 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5055 usc_OutReg( info, TICR, 0x0736 );
5056 else
5057 usc_OutReg( info, TICR, 0x1436 );
5059 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5060 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5062 /* Clock mode Control Register (CMCR)
5064 * <15..14> 00 counter 1 Source = Disabled
5065 * <13..12> 00 counter 0 Source = Disabled
5066 * <11..10> 11 BRG1 Input is TxC Pin
5067 * <9..8> 11 BRG0 Input is TxC Pin
5068 * <7..6> 01 DPLL Input is BRG1 Output
5069 * <5..3> XXX TxCLK comes from Port 0
5070 * <2..0> XXX RxCLK comes from Port 1
5072 * 0000 1111 0111 0111 = 0x0f77
5075 RegValue = 0x0f40;
5077 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
5078 RegValue |= 0x0003; /* RxCLK from DPLL */
5079 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
5080 RegValue |= 0x0004; /* RxCLK from BRG0 */
5081 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
5082 RegValue |= 0x0006; /* RxCLK from TXC Input */
5083 else
5084 RegValue |= 0x0007; /* RxCLK from Port1 */
5086 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
5087 RegValue |= 0x0018; /* TxCLK from DPLL */
5088 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
5089 RegValue |= 0x0020; /* TxCLK from BRG0 */
5090 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
5091 RegValue |= 0x0038; /* RxCLK from TXC Input */
5092 else
5093 RegValue |= 0x0030; /* TxCLK from Port0 */
5095 usc_OutReg( info, CMCR, RegValue );
5098 /* Hardware Configuration Register (HCR)
5100 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5101 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5102 * <12> 0 CVOK:0=report code violation in biphase
5103 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5104 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5105 * <7..6> 00 reserved
5106 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5107 * <4> X BRG1 Enable
5108 * <3..2> 00 reserved
5109 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5110 * <0> 0 BRG0 Enable
5113 RegValue = 0x0000;
5115 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
5116 u32 XtalSpeed;
5117 u32 DpllDivisor;
5118 u16 Tc;
5120 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5121 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5123 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5124 XtalSpeed = 11059200;
5125 else
5126 XtalSpeed = 14745600;
5128 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5129 DpllDivisor = 16;
5130 RegValue |= BIT10;
5132 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5133 DpllDivisor = 8;
5134 RegValue |= BIT11;
5136 else
5137 DpllDivisor = 32;
5139 /* Tc = (Xtal/Speed) - 1 */
5140 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5141 /* then rounding up gives a more precise time constant. Instead */
5142 /* of rounding up and then subtracting 1 we just don't subtract */
5143 /* the one in this case. */
5145 /*--------------------------------------------------
5146 * ejz: for DPLL mode, application should use the
5147 * same clock speed as the partner system, even
5148 * though clocking is derived from the input RxData.
5149 * In case the user uses a 0 for the clock speed,
5150 * default to 0xffffffff and don't try to divide by
5151 * zero
5152 *--------------------------------------------------*/
5153 if ( info->params.clock_speed )
5155 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5156 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5157 / info->params.clock_speed) )
5158 Tc--;
5160 else
5161 Tc = -1;
5164 /* Write 16-bit Time Constant for BRG1 */
5165 usc_OutReg( info, TC1R, Tc );
5167 RegValue |= BIT4; /* enable BRG1 */
5169 switch ( info->params.encoding ) {
5170 case HDLC_ENCODING_NRZ:
5171 case HDLC_ENCODING_NRZB:
5172 case HDLC_ENCODING_NRZI_MARK:
5173 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5174 case HDLC_ENCODING_BIPHASE_MARK:
5175 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5176 case HDLC_ENCODING_BIPHASE_LEVEL:
5177 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5181 usc_OutReg( info, HCR, RegValue );
5184 /* Channel Control/status Register (CCSR)
5186 * <15> X RCC FIFO Overflow status (RO)
5187 * <14> X RCC FIFO Not Empty status (RO)
5188 * <13> 0 1 = Clear RCC FIFO (WO)
5189 * <12> X DPLL Sync (RW)
5190 * <11> X DPLL 2 Missed Clocks status (RO)
5191 * <10> X DPLL 1 Missed Clock status (RO)
5192 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5193 * <7> X SDLC Loop On status (RO)
5194 * <6> X SDLC Loop Send status (RO)
5195 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5196 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5197 * <1..0> 00 reserved
5199 * 0000 0000 0010 0000 = 0x0020
5202 usc_OutReg( info, CCSR, 0x1020 );
5205 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5206 usc_OutReg( info, SICR,
5207 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5211 /* enable Master Interrupt Enable bit (MIE) */
5212 usc_EnableMasterIrqBit( info );
5214 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5215 TRANSMIT_STATUS + TRANSMIT_DATA );
5217 info->mbre_bit = 0;
5218 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5219 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5220 info->mbre_bit = BIT8;
5221 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5223 /* Enable DMAEN (Port 7, Bit 14) */
5224 /* This connects the DMA request signal to the ISA bus */
5225 /* on the ISA adapter. This has no effect for the PCI adapter */
5226 usc_OutReg( info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14) );
5228 /* DMA Control Register (DCR)
5230 * <15..14> 10 Priority mode = Alternating Tx/Rx
5231 * 01 Rx has priority
5232 * 00 Tx has priority
5234 * <13> 1 Enable Priority Preempt per DCR<15..14>
5235 * (WARNING DCR<11..10> must be 00 when this is 1)
5236 * 0 Choose activate channel per DCR<11..10>
5238 * <12> 0 Little Endian for Array/List
5239 * <11..10> 00 Both Channels can use each bus grant
5240 * <9..6> 0000 reserved
5241 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5242 * <4> 0 1 = drive D/C and S/D pins
5243 * <3> 1 1 = Add one wait state to all DMA cycles.
5244 * <2> 0 1 = Strobe /UAS on every transfer.
5245 * <1..0> 11 Addr incrementing only affects LS24 bits
5247 * 0110 0000 0000 1011 = 0x600b
5250 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5251 /* PCI adapter does not need DMA wait state */
5252 usc_OutDmaReg( info, DCR, 0xa00b );
5254 else
5255 usc_OutDmaReg( info, DCR, 0x800b );
5258 /* Receive DMA mode Register (RDMR)
5260 * <15..14> 11 DMA mode = Linked List Buffer mode
5261 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5262 * <12> 1 Clear count of List Entry after fetching
5263 * <11..10> 00 Address mode = Increment
5264 * <9> 1 Terminate Buffer on RxBound
5265 * <8> 0 Bus Width = 16bits
5266 * <7..0> ? status Bits (write as 0s)
5268 * 1111 0010 0000 0000 = 0xf200
5271 usc_OutDmaReg( info, RDMR, 0xf200 );
5274 /* Transmit DMA mode Register (TDMR)
5276 * <15..14> 11 DMA mode = Linked List Buffer mode
5277 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5278 * <12> 1 Clear count of List Entry after fetching
5279 * <11..10> 00 Address mode = Increment
5280 * <9> 1 Terminate Buffer on end of frame
5281 * <8> 0 Bus Width = 16bits
5282 * <7..0> ? status Bits (Read Only so write as 0)
5284 * 1111 0010 0000 0000 = 0xf200
5287 usc_OutDmaReg( info, TDMR, 0xf200 );
5290 /* DMA Interrupt Control Register (DICR)
5292 * <15> 1 DMA Interrupt Enable
5293 * <14> 0 1 = Disable IEO from USC
5294 * <13> 0 1 = Don't provide vector during IntAck
5295 * <12> 1 1 = Include status in Vector
5296 * <10..2> 0 reserved, Must be 0s
5297 * <1> 0 1 = Rx DMA Interrupt Enabled
5298 * <0> 0 1 = Tx DMA Interrupt Enabled
5300 * 1001 0000 0000 0000 = 0x9000
5303 usc_OutDmaReg( info, DICR, 0x9000 );
5305 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5306 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5307 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5309 /* Channel Control Register (CCR)
5311 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5312 * <13> 0 Trigger Tx on SW Command Disabled
5313 * <12> 0 Flag Preamble Disabled
5314 * <11..10> 00 Preamble Length
5315 * <9..8> 00 Preamble Pattern
5316 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5317 * <5> 0 Trigger Rx on SW Command Disabled
5318 * <4..0> 0 reserved
5320 * 1000 0000 1000 0000 = 0x8080
5323 RegValue = 0x8080;
5325 switch ( info->params.preamble_length ) {
5326 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5327 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5328 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5331 switch ( info->params.preamble ) {
5332 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5333 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5334 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5335 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5338 usc_OutReg( info, CCR, RegValue );
5342 * Burst/Dwell Control Register
5344 * <15..8> 0x20 Maximum number of transfers per bus grant
5345 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5348 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5349 /* don't limit bus occupancy on PCI adapter */
5350 usc_OutDmaReg( info, BDCR, 0x0000 );
5352 else
5353 usc_OutDmaReg( info, BDCR, 0x2000 );
5355 usc_stop_transmitter(info);
5356 usc_stop_receiver(info);
5358 } /* end of usc_set_sdlc_mode() */
5360 /* usc_enable_loopback()
5362 * Set the 16C32 for internal loopback mode.
5363 * The TxCLK and RxCLK signals are generated from the BRG0 and
5364 * the TxD is looped back to the RxD internally.
5366 * Arguments: info pointer to device instance data
5367 * enable 1 = enable loopback, 0 = disable
5368 * Return Value: None
5370 void usc_enable_loopback(struct mgsl_struct *info, int enable)
5372 if (enable) {
5373 /* blank external TXD output */
5374 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5376 /* Clock mode Control Register (CMCR)
5378 * <15..14> 00 counter 1 Disabled
5379 * <13..12> 00 counter 0 Disabled
5380 * <11..10> 11 BRG1 Input is TxC Pin
5381 * <9..8> 11 BRG0 Input is TxC Pin
5382 * <7..6> 01 DPLL Input is BRG1 Output
5383 * <5..3> 100 TxCLK comes from BRG0
5384 * <2..0> 100 RxCLK comes from BRG0
5386 * 0000 1111 0110 0100 = 0x0f64
5389 usc_OutReg( info, CMCR, 0x0f64 );
5391 /* Write 16-bit Time Constant for BRG0 */
5392 /* use clock speed if available, otherwise use 8 for diagnostics */
5393 if (info->params.clock_speed) {
5394 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5395 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5396 else
5397 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5398 } else
5399 usc_OutReg(info, TC0R, (u16)8);
5401 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5402 mode = Continuous Set Bit 0 to enable BRG0. */
5403 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5405 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5406 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5408 /* set Internal Data loopback mode */
5409 info->loopback_bits = 0x300;
5410 outw( 0x0300, info->io_base + CCAR );
5411 } else {
5412 /* enable external TXD output */
5413 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5415 /* clear Internal Data loopback mode */
5416 info->loopback_bits = 0;
5417 outw( 0,info->io_base + CCAR );
5420 } /* end of usc_enable_loopback() */
5422 /* usc_enable_aux_clock()
5424 * Enabled the AUX clock output at the specified frequency.
5426 * Arguments:
5428 * info pointer to device extension
5429 * data_rate data rate of clock in bits per second
5430 * A data rate of 0 disables the AUX clock.
5432 * Return Value: None
5434 void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5436 u32 XtalSpeed;
5437 u16 Tc;
5439 if ( data_rate ) {
5440 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5441 XtalSpeed = 11059200;
5442 else
5443 XtalSpeed = 14745600;
5446 /* Tc = (Xtal/Speed) - 1 */
5447 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5448 /* then rounding up gives a more precise time constant. Instead */
5449 /* of rounding up and then subtracting 1 we just don't subtract */
5450 /* the one in this case. */
5453 Tc = (u16)(XtalSpeed/data_rate);
5454 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5455 Tc--;
5457 /* Write 16-bit Time Constant for BRG0 */
5458 usc_OutReg( info, TC0R, Tc );
5461 * Hardware Configuration Register (HCR)
5462 * Clear Bit 1, BRG0 mode = Continuous
5463 * Set Bit 0 to enable BRG0.
5466 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5468 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5469 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5470 } else {
5471 /* data rate == 0 so turn off BRG0 */
5472 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5475 } /* end of usc_enable_aux_clock() */
5477 /* usc_stop_receiver()
5479 * Disable USC receiver
5481 * Arguments: info pointer to device instance data
5482 * Return Value: None
5484 void usc_stop_receiver( struct mgsl_struct *info )
5486 if (debug_level >= DEBUG_LEVEL_ISR)
5487 printk("%s(%d):usc_stop_receiver(%s)\n",
5488 __FILE__,__LINE__, info->device_name );
5490 /* Disable receive DMA channel. */
5491 /* This also disables receive DMA channel interrupts */
5492 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5494 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5495 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5496 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5498 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5500 /* This empties the receive FIFO and loads the RCC with RCLR */
5501 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5502 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5504 info->rx_enabled = 0;
5505 info->rx_overflow = 0;
5507 } /* end of stop_receiver() */
5509 /* usc_start_receiver()
5511 * Enable the USC receiver
5513 * Arguments: info pointer to device instance data
5514 * Return Value: None
5516 void usc_start_receiver( struct mgsl_struct *info )
5518 u32 phys_addr;
5520 if (debug_level >= DEBUG_LEVEL_ISR)
5521 printk("%s(%d):usc_start_receiver(%s)\n",
5522 __FILE__,__LINE__, info->device_name );
5524 mgsl_reset_rx_dma_buffers( info );
5525 usc_stop_receiver( info );
5527 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5528 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5530 if ( info->params.mode == MGSL_MODE_HDLC ) {
5531 /* DMA mode Transfers */
5532 /* Program the DMA controller. */
5533 /* Enable the DMA controller end of buffer interrupt. */
5535 /* program 16C32 with physical address of 1st DMA buffer entry */
5536 phys_addr = info->rx_buffer_list[0].phys_entry;
5537 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5538 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5540 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5541 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5542 usc_EnableInterrupts( info, RECEIVE_STATUS );
5544 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5545 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5547 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5548 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5549 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5550 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5551 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5552 else
5553 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5554 } else {
5555 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5556 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5557 usc_EnableInterrupts(info, RECEIVE_DATA);
5559 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5560 usc_RCmd( info, RCmd_EnterHuntmode );
5562 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5565 usc_OutReg( info, CCSR, 0x1020 );
5567 info->rx_enabled = 1;
5569 } /* end of usc_start_receiver() */
5571 /* usc_start_transmitter()
5573 * Enable the USC transmitter and send a transmit frame if
5574 * one is loaded in the DMA buffers.
5576 * Arguments: info pointer to device instance data
5577 * Return Value: None
5579 void usc_start_transmitter( struct mgsl_struct *info )
5581 u32 phys_addr;
5582 unsigned int FrameSize;
5584 if (debug_level >= DEBUG_LEVEL_ISR)
5585 printk("%s(%d):usc_start_transmitter(%s)\n",
5586 __FILE__,__LINE__, info->device_name );
5588 if ( info->xmit_cnt ) {
5590 /* If auto RTS enabled and RTS is inactive, then assert */
5591 /* RTS and set a flag indicating that the driver should */
5592 /* negate RTS when the transmission completes. */
5594 info->drop_rts_on_tx_done = 0;
5596 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5597 usc_get_serial_signals( info );
5598 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5599 info->serial_signals |= SerialSignal_RTS;
5600 usc_set_serial_signals( info );
5601 info->drop_rts_on_tx_done = 1;
5606 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5607 if ( !info->tx_active ) {
5608 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5609 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5610 usc_EnableInterrupts(info, TRANSMIT_DATA);
5611 usc_load_txfifo(info);
5613 } else {
5614 /* Disable transmit DMA controller while programming. */
5615 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5617 /* Transmit DMA buffer is loaded, so program USC */
5618 /* to send the frame contained in the buffers. */
5621 FrameSize = info->tx_buffer_list[0].rcc;
5623 /* Program the Transmit Character Length Register (TCLR) */
5624 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5625 usc_OutReg( info, TCLR, (u16)FrameSize );
5627 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5629 /* Program the address of the 1st DMA Buffer Entry in linked list */
5630 phys_addr = info->tx_buffer_list[0].phys_entry;
5631 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5632 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5634 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5635 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5636 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5638 /* Initialize Transmit DMA Channel */
5639 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5641 usc_TCmd( info, TCmd_SendFrame );
5643 info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
5644 add_timer(&info->tx_timer);
5646 info->tx_active = 1;
5649 if ( !info->tx_enabled ) {
5650 info->tx_enabled = 1;
5651 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5652 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5653 else
5654 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5657 } /* end of usc_start_transmitter() */
5659 /* usc_stop_transmitter()
5661 * Stops the transmitter and DMA
5663 * Arguments: info pointer to device isntance data
5664 * Return Value: None
5666 void usc_stop_transmitter( struct mgsl_struct *info )
5668 if (debug_level >= DEBUG_LEVEL_ISR)
5669 printk("%s(%d):usc_stop_transmitter(%s)\n",
5670 __FILE__,__LINE__, info->device_name );
5672 del_timer(&info->tx_timer);
5674 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5675 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5676 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5678 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5679 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5680 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5682 info->tx_enabled = 0;
5683 info->tx_active = 0;
5685 } /* end of usc_stop_transmitter() */
5687 /* usc_load_txfifo()
5689 * Fill the transmit FIFO until the FIFO is full or
5690 * there is no more data to load.
5692 * Arguments: info pointer to device extension (instance data)
5693 * Return Value: None
5695 void usc_load_txfifo( struct mgsl_struct *info )
5697 int Fifocount;
5698 u8 TwoBytes[2];
5700 if ( !info->xmit_cnt && !info->x_char )
5701 return;
5703 /* Select transmit FIFO status readback in TICR */
5704 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5706 /* load the Transmit FIFO until FIFOs full or all data sent */
5708 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5709 /* there is more space in the transmit FIFO and */
5710 /* there is more data in transmit buffer */
5712 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5713 /* write a 16-bit word from transmit buffer to 16C32 */
5715 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5716 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5717 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5718 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5720 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5722 info->xmit_cnt -= 2;
5723 info->icount.tx += 2;
5724 } else {
5725 /* only 1 byte left to transmit or 1 FIFO slot left */
5727 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5728 info->io_base + CCAR );
5730 if (info->x_char) {
5731 /* transmit pending high priority char */
5732 outw( info->x_char,info->io_base + CCAR );
5733 info->x_char = 0;
5734 } else {
5735 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5736 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5737 info->xmit_cnt--;
5739 info->icount.tx++;
5743 } /* end of usc_load_txfifo() */
5745 /* usc_reset()
5747 * Reset the adapter to a known state and prepare it for further use.
5749 * Arguments: info pointer to device instance data
5750 * Return Value: None
5752 void usc_reset( struct mgsl_struct *info )
5754 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5755 int i;
5756 volatile u32 readval;
5758 /* Set BIT30 of Misc Control Register */
5759 /* (Local Control Register 0x50) to force reset of USC. */
5761 u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5762 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5764 info->misc_ctrl_value |= BIT30;
5765 *MiscCtrl = info->misc_ctrl_value;
5768 * Force at least 170ns delay before clearing
5769 * reset bit. Each read from LCR takes at least
5770 * 30ns so 10 times for 300ns to be safe.
5772 for(i=0;i<10;i++)
5773 readval = *MiscCtrl;
5775 info->misc_ctrl_value &= ~BIT30;
5776 *MiscCtrl = info->misc_ctrl_value;
5778 *LCR0BRDR = BUS_DESCRIPTOR(
5779 1, // Write Strobe Hold (0-3)
5780 2, // Write Strobe Delay (0-3)
5781 2, // Read Strobe Delay (0-3)
5782 0, // NWDD (Write data-data) (0-3)
5783 4, // NWAD (Write Addr-data) (0-31)
5784 0, // NXDA (Read/Write Data-Addr) (0-3)
5785 0, // NRDD (Read Data-Data) (0-3)
5786 5 // NRAD (Read Addr-Data) (0-31)
5788 } else {
5789 /* do HW reset */
5790 outb( 0,info->io_base + 8 );
5793 info->mbre_bit = 0;
5794 info->loopback_bits = 0;
5795 info->usc_idle_mode = 0;
5798 * Program the Bus Configuration Register (BCR)
5800 * <15> 0 Don't use seperate address
5801 * <14..6> 0 reserved
5802 * <5..4> 00 IAckmode = Default, don't care
5803 * <3> 1 Bus Request Totem Pole output
5804 * <2> 1 Use 16 Bit data bus
5805 * <1> 0 IRQ Totem Pole output
5806 * <0> 0 Don't Shift Right Addr
5808 * 0000 0000 0000 1100 = 0x000c
5810 * By writing to io_base + SDPIN the Wait/Ack pin is
5811 * programmed to work as a Wait pin.
5814 outw( 0x000c,info->io_base + SDPIN );
5817 outw( 0,info->io_base );
5818 outw( 0,info->io_base + CCAR );
5820 /* select little endian byte ordering */
5821 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5824 /* Port Control Register (PCR)
5826 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5827 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5828 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5829 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5830 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5831 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5832 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5833 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5835 * 1111 0000 1111 0101 = 0xf0f5
5838 usc_OutReg( info, PCR, 0xf0f5 );
5842 * Input/Output Control Register
5844 * <15..14> 00 CTS is active low input
5845 * <13..12> 00 DCD is active low input
5846 * <11..10> 00 TxREQ pin is input (DSR)
5847 * <9..8> 00 RxREQ pin is input (RI)
5848 * <7..6> 00 TxD is output (Transmit Data)
5849 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5850 * <2..0> 100 RxC is Output (drive with BRG0)
5852 * 0000 0000 0000 0100 = 0x0004
5855 usc_OutReg( info, IOCR, 0x0004 );
5857 } /* end of usc_reset() */
5859 /* usc_set_async_mode()
5861 * Program adapter for asynchronous communications.
5863 * Arguments: info pointer to device instance data
5864 * Return Value: None
5866 void usc_set_async_mode( struct mgsl_struct *info )
5868 u16 RegValue;
5870 /* disable interrupts while programming USC */
5871 usc_DisableMasterIrqBit( info );
5873 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5874 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5876 usc_loopback_frame( info );
5878 /* Channel mode Register (CMR)
5880 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5881 * <13..12> 00 00 = 16X Clock
5882 * <11..8> 0000 Transmitter mode = Asynchronous
5883 * <7..6> 00 reserved?
5884 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5885 * <3..0> 0000 Receiver mode = Asynchronous
5887 * 0000 0000 0000 0000 = 0x0
5890 RegValue = 0;
5891 if ( info->params.stop_bits != 1 )
5892 RegValue |= BIT14;
5893 usc_OutReg( info, CMR, RegValue );
5896 /* Receiver mode Register (RMR)
5898 * <15..13> 000 encoding = None
5899 * <12..08> 00000 reserved (Sync Only)
5900 * <7..6> 00 Even parity
5901 * <5> 0 parity disabled
5902 * <4..2> 000 Receive Char Length = 8 bits
5903 * <1..0> 00 Disable Receiver
5905 * 0000 0000 0000 0000 = 0x0
5908 RegValue = 0;
5910 if ( info->params.data_bits != 8 )
5911 RegValue |= BIT4+BIT3+BIT2;
5913 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5914 RegValue |= BIT5;
5915 if ( info->params.parity != ASYNC_PARITY_ODD )
5916 RegValue |= BIT6;
5919 usc_OutReg( info, RMR, RegValue );
5922 /* Set IRQ trigger level */
5924 usc_RCmd( info, RCmd_SelectRicrIntLevel );
5927 /* Receive Interrupt Control Register (RICR)
5929 * <15..8> ? RxFIFO IRQ Request Level
5931 * Note: For async mode the receive FIFO level must be set
5932 * to 0 to aviod the situation where the FIFO contains fewer bytes
5933 * than the trigger level and no more data is expected.
5935 * <7> 0 Exited Hunt IA (Interrupt Arm)
5936 * <6> 0 Idle Received IA
5937 * <5> 0 Break/Abort IA
5938 * <4> 0 Rx Bound IA
5939 * <3> 0 Queued status reflects oldest byte in FIFO
5940 * <2> 0 Abort/PE IA
5941 * <1> 0 Rx Overrun IA
5942 * <0> 0 Select TC0 value for readback
5944 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5947 usc_OutReg( info, RICR, 0x0000 );
5949 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5950 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
5953 /* Transmit mode Register (TMR)
5955 * <15..13> 000 encoding = None
5956 * <12..08> 00000 reserved (Sync Only)
5957 * <7..6> 00 Transmit parity Even
5958 * <5> 0 Transmit parity Disabled
5959 * <4..2> 000 Tx Char Length = 8 bits
5960 * <1..0> 00 Disable Transmitter
5962 * 0000 0000 0000 0000 = 0x0
5965 RegValue = 0;
5967 if ( info->params.data_bits != 8 )
5968 RegValue |= BIT4+BIT3+BIT2;
5970 if ( info->params.parity != ASYNC_PARITY_NONE ) {
5971 RegValue |= BIT5;
5972 if ( info->params.parity != ASYNC_PARITY_ODD )
5973 RegValue |= BIT6;
5976 usc_OutReg( info, TMR, RegValue );
5978 usc_set_txidle( info );
5981 /* Set IRQ trigger level */
5983 usc_TCmd( info, TCmd_SelectTicrIntLevel );
5986 /* Transmit Interrupt Control Register (TICR)
5988 * <15..8> ? Transmit FIFO IRQ Level
5989 * <7> 0 Present IA (Interrupt Arm)
5990 * <6> 1 Idle Sent IA
5991 * <5> 0 Abort Sent IA
5992 * <4> 0 EOF/EOM Sent IA
5993 * <3> 0 CRC Sent IA
5994 * <2> 0 1 = Wait for SW Trigger to Start Frame
5995 * <1> 0 Tx Underrun IA
5996 * <0> 0 TC0 constant on read back
5998 * 0000 0000 0100 0000 = 0x0040
6001 usc_OutReg( info, TICR, 0x1f40 );
6003 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6004 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6006 usc_enable_async_clock( info, info->params.data_rate );
6009 /* Channel Control/status Register (CCSR)
6011 * <15> X RCC FIFO Overflow status (RO)
6012 * <14> X RCC FIFO Not Empty status (RO)
6013 * <13> 0 1 = Clear RCC FIFO (WO)
6014 * <12> X DPLL in Sync status (RO)
6015 * <11> X DPLL 2 Missed Clocks status (RO)
6016 * <10> X DPLL 1 Missed Clock status (RO)
6017 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6018 * <7> X SDLC Loop On status (RO)
6019 * <6> X SDLC Loop Send status (RO)
6020 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6021 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6022 * <1..0> 00 reserved
6024 * 0000 0000 0010 0000 = 0x0020
6027 usc_OutReg( info, CCSR, 0x0020 );
6029 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6030 RECEIVE_DATA + RECEIVE_STATUS );
6032 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6033 RECEIVE_DATA + RECEIVE_STATUS );
6035 usc_EnableMasterIrqBit( info );
6037 /* Enable INTEN (Port 6, Bit12) */
6038 /* This connects the IRQ request signal to the ISA bus */
6039 /* on the ISA adapter. This has no effect for the PCI adapter */
6040 usc_OutReg( info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
6042 } /* end of usc_set_async_mode() */
6044 /* usc_loopback_frame()
6046 * Loop back a small (2 byte) dummy SDLC frame.
6047 * Interrupts and DMA are NOT used. The purpose of this is to
6048 * clear any 'stale' status info left over from running in async mode.
6050 * The 16C32 shows the strange behaviour of marking the 1st
6051 * received SDLC frame with a CRC error even when there is no
6052 * CRC error. To get around this a small dummy from of 2 bytes
6053 * is looped back when switching from async to sync mode.
6055 * Arguments: info pointer to device instance data
6056 * Return Value: None
6058 void usc_loopback_frame( struct mgsl_struct *info )
6060 int i;
6062 usc_DisableMasterIrqBit( info );
6064 usc_set_sdlc_mode( info );
6065 usc_enable_loopback( info, 1 );
6067 /* Write 16-bit Time Constant for BRG0 */
6068 usc_OutReg( info, TC0R, 0 );
6070 /* Channel Control Register (CCR)
6072 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6073 * <13> 0 Trigger Tx on SW Command Disabled
6074 * <12> 0 Flag Preamble Disabled
6075 * <11..10> 00 Preamble Length = 8-Bits
6076 * <9..8> 01 Preamble Pattern = flags
6077 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6078 * <5> 0 Trigger Rx on SW Command Disabled
6079 * <4..0> 0 reserved
6081 * 0000 0001 0000 0000 = 0x0100
6084 usc_OutReg( info, CCR, 0x0100 );
6086 /* SETUP RECEIVER */
6087 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6088 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6090 /* SETUP TRANSMITTER */
6091 /* Program the Transmit Character Length Register (TCLR) */
6092 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6093 usc_OutReg( info, TCLR, 2 );
6094 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6096 /* unlatch Tx status bits, and start transmit channel. */
6097 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6098 outw(0,info->io_base + DATAREG);
6100 /* ENABLE TRANSMITTER */
6101 usc_TCmd( info, TCmd_SendFrame );
6102 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6104 /* WAIT FOR RECEIVE COMPLETE */
6105 for (i=0 ; i<1000 ; i++)
6106 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6107 break;
6109 /* clear Internal Data loopback mode */
6110 usc_enable_loopback(info, 0);
6112 usc_EnableMasterIrqBit(info);
6114 } /* end of usc_loopback_frame() */
6116 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6118 * Arguments: info pointer to adapter info structure
6119 * Return Value: None
6121 void usc_set_sync_mode( struct mgsl_struct *info )
6123 usc_loopback_frame( info );
6124 usc_set_sdlc_mode( info );
6126 /* Enable INTEN (Port 6, Bit12) */
6127 /* This connects the IRQ request signal to the ISA bus */
6128 /* on the ISA adapter. This has no effect for the PCI adapter */
6129 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6131 usc_enable_aux_clock(info, info->params.clock_speed);
6133 if (info->params.loopback)
6134 usc_enable_loopback(info,1);
6136 } /* end of mgsl_set_sync_mode() */
6138 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6140 * Arguments: info pointer to device instance data
6141 * Return Value: None
6143 void usc_set_txidle( struct mgsl_struct *info )
6145 u16 usc_idle_mode = IDLEMODE_FLAGS;
6147 /* Map API idle mode to USC register bits */
6149 switch( info->idle_mode ){
6150 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6151 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6152 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6153 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6154 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6155 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6156 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6159 info->usc_idle_mode = usc_idle_mode;
6160 usc_OutReg(info, TCSR, usc_idle_mode);
6162 } /* end of usc_set_txidle() */
6164 /* usc_get_serial_signals()
6166 * Query the adapter for the state of the V24 status (input) signals.
6168 * Arguments: info pointer to device instance data
6169 * Return Value: None
6171 void usc_get_serial_signals( struct mgsl_struct *info )
6173 u16 status;
6175 /* clear all serial signals except DTR and RTS */
6176 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6178 /* Read the Misc Interrupt status Register (MISR) to get */
6179 /* the V24 status signals. */
6181 status = usc_InReg( info, MISR );
6183 /* set serial signal bits to reflect MISR */
6185 if ( status & MISCSTATUS_CTS )
6186 info->serial_signals |= SerialSignal_CTS;
6188 if ( status & MISCSTATUS_DCD )
6189 info->serial_signals |= SerialSignal_DCD;
6191 if ( status & MISCSTATUS_RI )
6192 info->serial_signals |= SerialSignal_RI;
6194 if ( status & MISCSTATUS_DSR )
6195 info->serial_signals |= SerialSignal_DSR;
6197 } /* end of usc_get_serial_signals() */
6199 /* usc_set_serial_signals()
6201 * Set the state of DTR and RTS based on contents of
6202 * serial_signals member of device extension.
6204 * Arguments: info pointer to device instance data
6205 * Return Value: None
6207 void usc_set_serial_signals( struct mgsl_struct *info )
6209 u16 Control;
6210 unsigned char V24Out = info->serial_signals;
6212 /* get the current value of the Port Control Register (PCR) */
6214 Control = usc_InReg( info, PCR );
6216 if ( V24Out & SerialSignal_RTS )
6217 Control &= ~(BIT6);
6218 else
6219 Control |= BIT6;
6221 if ( V24Out & SerialSignal_DTR )
6222 Control &= ~(BIT4);
6223 else
6224 Control |= BIT4;
6226 usc_OutReg( info, PCR, Control );
6228 } /* end of usc_set_serial_signals() */
6230 /* usc_enable_async_clock()
6232 * Enable the async clock at the specified frequency.
6234 * Arguments: info pointer to device instance data
6235 * data_rate data rate of clock in bps
6236 * 0 disables the AUX clock.
6237 * Return Value: None
6239 void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6241 if ( data_rate ) {
6243 * Clock mode Control Register (CMCR)
6245 * <15..14> 00 counter 1 Disabled
6246 * <13..12> 00 counter 0 Disabled
6247 * <11..10> 11 BRG1 Input is TxC Pin
6248 * <9..8> 11 BRG0 Input is TxC Pin
6249 * <7..6> 01 DPLL Input is BRG1 Output
6250 * <5..3> 100 TxCLK comes from BRG0
6251 * <2..0> 100 RxCLK comes from BRG0
6253 * 0000 1111 0110 0100 = 0x0f64
6256 usc_OutReg( info, CMCR, 0x0f64 );
6260 * Write 16-bit Time Constant for BRG0
6261 * Time Constant = (ClkSpeed / data_rate) - 1
6262 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6265 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6266 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6267 else
6268 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6272 * Hardware Configuration Register (HCR)
6273 * Clear Bit 1, BRG0 mode = Continuous
6274 * Set Bit 0 to enable BRG0.
6277 usc_OutReg( info, HCR,
6278 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6281 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6283 usc_OutReg( info, IOCR,
6284 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6285 } else {
6286 /* data rate == 0 so turn off BRG0 */
6287 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6290 } /* end of usc_enable_async_clock() */
6293 * Buffer Structures:
6295 * Normal memory access uses virtual addresses that can make discontiguous
6296 * physical memory pages appear to be contiguous in the virtual address
6297 * space (the processors memory mapping handles the conversions).
6299 * DMA transfers require physically contiguous memory. This is because
6300 * the DMA system controller and DMA bus masters deal with memory using
6301 * only physical addresses.
6303 * This causes a problem under Windows NT when large DMA buffers are
6304 * needed. Fragmentation of the nonpaged pool prevents allocations of
6305 * physically contiguous buffers larger than the PAGE_SIZE.
6307 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6308 * allows DMA transfers to physically discontiguous buffers. Information
6309 * about each data transfer buffer is contained in a memory structure
6310 * called a 'buffer entry'. A list of buffer entries is maintained
6311 * to track and control the use of the data transfer buffers.
6313 * To support this strategy we will allocate sufficient PAGE_SIZE
6314 * contiguous memory buffers to allow for the total required buffer
6315 * space.
6317 * The 16C32 accesses the list of buffer entries using Bus Master
6318 * DMA. Control information is read from the buffer entries by the
6319 * 16C32 to control data transfers. status information is written to
6320 * the buffer entries by the 16C32 to indicate the status of completed
6321 * transfers.
6323 * The CPU writes control information to the buffer entries to control
6324 * the 16C32 and reads status information from the buffer entries to
6325 * determine information about received and transmitted frames.
6327 * Because the CPU and 16C32 (adapter) both need simultaneous access
6328 * to the buffer entries, the buffer entry memory is allocated with
6329 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6330 * entry list to PAGE_SIZE.
6332 * The actual data buffers on the other hand will only be accessed
6333 * by the CPU or the adapter but not by both simultaneously. This allows
6334 * Scatter/Gather packet based DMA procedures for using physically
6335 * discontiguous pages.
6339 * mgsl_reset_rx_dma_buffers()
6341 * Set the count for all receive buffers to DMABUFFERSIZE
6342 * and set the current buffer to the first buffer. This effectively
6343 * makes all buffers free and discards any data in buffers.
6345 * Arguments: info pointer to device instance data
6346 * Return Value: None
6348 void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6350 unsigned int i;
6352 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6353 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6354 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6355 // info->rx_buffer_list[i].status = 0;
6358 info->current_rx_buffer = 0;
6360 } /* end of mgsl_reset_rx_dma_buffers() */
6363 * mgsl_free_rx_frame_buffers()
6365 * Free the receive buffers used by a received SDLC
6366 * frame such that the buffers can be reused.
6368 * Arguments:
6370 * info pointer to device instance data
6371 * StartIndex index of 1st receive buffer of frame
6372 * EndIndex index of last receive buffer of frame
6374 * Return Value: None
6376 void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6378 int Done = 0;
6379 DMABUFFERENTRY *pBufEntry;
6380 unsigned int Index;
6382 /* Starting with 1st buffer entry of the frame clear the status */
6383 /* field and set the count field to DMA Buffer Size. */
6385 Index = StartIndex;
6387 while( !Done ) {
6388 pBufEntry = &(info->rx_buffer_list[Index]);
6390 if ( Index == EndIndex ) {
6391 /* This is the last buffer of the frame! */
6392 Done = 1;
6395 /* reset current buffer for reuse */
6396 // pBufEntry->status = 0;
6397 // pBufEntry->count = DMABUFFERSIZE;
6398 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6400 /* advance to next buffer entry in linked list */
6401 Index++;
6402 if ( Index == info->rx_buffer_count )
6403 Index = 0;
6406 /* set current buffer to next buffer after last buffer of frame */
6407 info->current_rx_buffer = Index;
6409 } /* end of free_rx_frame_buffers() */
6411 /* mgsl_get_rx_frame()
6413 * This function attempts to return a received SDLC frame from the
6414 * receive DMA buffers. Only frames received without errors are returned.
6416 * Arguments: info pointer to device extension
6417 * Return Value: 1 if frame returned, otherwise 0
6419 int mgsl_get_rx_frame(struct mgsl_struct *info)
6421 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6422 unsigned short status;
6423 DMABUFFERENTRY *pBufEntry;
6424 unsigned int framesize;
6425 int ReturnCode = 0;
6426 unsigned long flags;
6427 struct tty_struct *tty = info->tty;
6430 * current_rx_buffer points to the 1st buffer of the next available
6431 * receive frame. To find the last buffer of the frame look for
6432 * a non-zero status field in the buffer entries. (The status
6433 * field is set by the 16C32 after completing a receive frame.
6436 StartIndex = EndIndex = info->current_rx_buffer;
6438 while( !info->rx_buffer_list[EndIndex].status ) {
6440 * If the count field of the buffer entry is non-zero then
6441 * this buffer has not been used. (The 16C32 clears the count
6442 * field when it starts using the buffer.) If an unused buffer
6443 * is encountered then there are no frames available.
6446 if ( info->rx_buffer_list[EndIndex].count )
6447 goto Cleanup;
6449 /* advance to next buffer entry in linked list */
6450 EndIndex++;
6451 if ( EndIndex == info->rx_buffer_count )
6452 EndIndex = 0;
6454 /* if entire list searched then no frame available */
6455 if ( EndIndex == StartIndex ) {
6456 /* If this occurs then something bad happened,
6457 * all buffers have been 'used' but none mark
6458 * the end of a frame. Reset buffers and receiver.
6461 if ( info->rx_enabled ){
6462 spin_lock_irqsave(&info->irq_spinlock,flags);
6463 usc_start_receiver(info);
6464 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6466 goto Cleanup;
6471 /* check status of receive frame */
6473 status = info->rx_buffer_list[EndIndex].status;
6475 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6476 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6477 if ( status & RXSTATUS_SHORT_FRAME )
6478 info->icount.rxshort++;
6479 else if ( status & RXSTATUS_ABORT )
6480 info->icount.rxabort++;
6481 else if ( status & RXSTATUS_OVERRUN )
6482 info->icount.rxover++;
6483 else
6484 info->icount.rxcrc++;
6485 framesize = 0;
6486 } else {
6487 /* receive frame has no errors, get frame size.
6488 * The frame size is the starting value of the RCC (which was
6489 * set to 0xffff) minus the ending value of the RCC (decremented
6490 * once for each receive character) minus 2 for the 16-bit CRC.
6493 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6495 /* adjust frame size for CRC if any */
6496 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6497 framesize -= 2;
6500 if ( debug_level >= DEBUG_LEVEL_BH )
6501 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6502 __FILE__,__LINE__,info->device_name,status,framesize);
6504 if ( debug_level >= DEBUG_LEVEL_DATA )
6505 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6506 framesize,0);
6508 if (framesize) {
6509 if (framesize > HDLC_MAX_FRAME_SIZE)
6510 info->icount.rxlong++;
6511 else {
6512 info->icount.rxok++;
6513 pBufEntry = &(info->rx_buffer_list[StartIndex]);
6514 /* Call the line discipline receive callback directly. */
6515 tty->ldisc.receive_buf(tty, pBufEntry->virt_addr, info->flag_buf, framesize);
6518 /* Free the buffers used by this frame. */
6519 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6521 ReturnCode = 1;
6523 Cleanup:
6525 if ( info->rx_enabled && info->rx_overflow ) {
6526 /* The receiver needs to restarted because of
6527 * a receive overflow (buffer or FIFO). If the
6528 * receive buffers are now empty, then restart receiver.
6531 if ( !info->rx_buffer_list[info->current_rx_buffer].status &&
6532 info->rx_buffer_list[info->current_rx_buffer].count ) {
6533 spin_lock_irqsave(&info->irq_spinlock,flags);
6534 usc_start_receiver(info);
6535 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6539 return ReturnCode;
6541 } /* end of mgsl_get_rx_frame() */
6543 /* mgsl_load_tx_dma_buffer()
6545 * Load the transmit DMA buffer with the specified data.
6547 * Arguments:
6549 * info pointer to device extension
6550 * Buffer pointer to buffer containing frame to load
6551 * BufferSize size in bytes of frame in Buffer
6553 * Return Value: None
6555 void mgsl_load_tx_dma_buffer(struct mgsl_struct *info, const char *Buffer,
6556 unsigned int BufferSize)
6558 unsigned short Copycount;
6559 unsigned int i = 0;
6560 DMABUFFERENTRY *pBufEntry;
6562 if ( debug_level >= DEBUG_LEVEL_DATA )
6563 mgsl_trace_block(info,Buffer,BufferSize,1);
6565 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6566 /* set CMR:13 to start transmit when
6567 * next GoAhead (abort) is received
6569 info->cmr_value |= BIT13;
6572 /* Setup the status and RCC (Frame Size) fields of the 1st */
6573 /* buffer entry in the transmit DMA buffer list. */
6575 info->tx_buffer_list[0].status = info->cmr_value & 0xf000;
6576 info->tx_buffer_list[0].rcc = BufferSize;
6577 info->tx_buffer_list[0].count = BufferSize;
6579 /* Copy frame data from 1st source buffer to the DMA buffers. */
6580 /* The frame data may span multiple DMA buffers. */
6582 while( BufferSize ){
6583 /* Get a pointer to next DMA buffer entry. */
6584 pBufEntry = &info->tx_buffer_list[i++];
6586 /* Calculate the number of bytes that can be copied from */
6587 /* the source buffer to this DMA buffer. */
6588 if ( BufferSize > DMABUFFERSIZE )
6589 Copycount = DMABUFFERSIZE;
6590 else
6591 Copycount = BufferSize;
6593 /* Actually copy data from source buffer to DMA buffer. */
6594 /* Also set the data count for this individual DMA buffer. */
6595 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6596 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
6597 else
6598 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
6600 pBufEntry->count = Copycount;
6602 /* Advance source pointer and reduce remaining data count. */
6603 Buffer += Copycount;
6604 BufferSize -= Copycount;
6607 } /* end of mgsl_load_tx_dma_buffer() */
6610 * mgsl_register_test()
6612 * Performs a register test of the 16C32.
6614 * Arguments: info pointer to device instance data
6615 * Return Value: TRUE if test passed, otherwise FALSE
6617 BOOLEAN mgsl_register_test( struct mgsl_struct *info )
6619 static unsigned short BitPatterns[] =
6620 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6621 static unsigned int Patterncount = sizeof(BitPatterns)/sizeof(unsigned short);
6622 unsigned int i;
6623 BOOLEAN rc = TRUE;
6624 unsigned long flags;
6626 spin_lock_irqsave(&info->irq_spinlock,flags);
6627 usc_reset(info);
6628 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6630 /* Verify the reset state of some registers. */
6632 if ( (usc_InReg( info, SICR ) != 0) ||
6633 (usc_InReg( info, IVR ) != 0) ||
6634 (usc_InDmaReg( info, DIVR ) != 0) ){
6635 rc = FALSE;
6638 if ( rc == TRUE ){
6639 /* Write bit patterns to various registers but do it out of */
6640 /* sync, then read back and verify values. */
6642 for ( i = 0 ; i < Patterncount ; i++ ) {
6643 usc_OutReg( info, TC0R, BitPatterns[i] );
6644 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
6645 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
6646 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
6647 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
6648 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
6650 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
6651 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
6652 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
6653 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
6654 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
6655 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
6656 rc = FALSE;
6657 break;
6662 spin_lock_irqsave(&info->irq_spinlock,flags);
6663 usc_reset(info);
6664 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6666 return rc;
6668 } /* end of mgsl_register_test() */
6670 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6672 * Arguments: info pointer to device instance data
6673 * Return Value: TRUE if test passed, otherwise FALSE
6675 BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
6677 unsigned long EndTime;
6678 unsigned long flags;
6680 spin_lock_irqsave(&info->irq_spinlock,flags);
6681 usc_reset(info);
6682 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6685 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
6686 * The ISR sets irq_occurred to 1.
6689 info->irq_occurred = FALSE;
6691 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
6692 /* Enable INTEN (Port 6, Bit12) */
6693 /* This connects the IRQ request signal to the ISA bus */
6694 /* on the ISA adapter. This has no effect for the PCI adapter */
6695 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
6697 usc_EnableMasterIrqBit(info);
6698 usc_EnableInterrupts(info, IO_PIN);
6699 usc_ClearIrqPendingBits(info, IO_PIN);
6701 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
6702 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
6704 EndTime=100;
6705 while( EndTime-- && !info->irq_occurred ) {
6706 current->state = TASK_INTERRUPTIBLE;
6707 schedule_timeout(jiffies_from_ms(10));
6708 current->state = TASK_RUNNING;
6711 spin_lock_irqsave(&info->irq_spinlock,flags);
6712 usc_reset(info);
6713 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6715 if ( !info->irq_occurred )
6716 return FALSE;
6717 else
6718 return TRUE;
6720 } /* end of mgsl_irq_test() */
6722 /* mgsl_dma_test()
6724 * Perform a DMA test of the 16C32. A small frame is
6725 * transmitted via DMA from a transmit buffer to a receive buffer
6726 * using single buffer DMA mode.
6728 * Arguments: info pointer to device instance data
6729 * Return Value: TRUE if test passed, otherwise FALSE
6731 BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
6733 unsigned short FifoLevel;
6734 unsigned long phys_addr;
6735 unsigned int FrameSize;
6736 unsigned int i;
6737 char *TmpPtr;
6738 BOOLEAN rc = TRUE;
6739 volatile unsigned short status;
6740 volatile unsigned long EndTime;
6741 unsigned long flags;
6742 MGSL_PARAMS tmp_params;
6744 /* save current port options */
6745 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
6746 /* load default port options */
6747 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
6749 #define TESTFRAMESIZE 40
6751 spin_lock_irqsave(&info->irq_spinlock,flags);
6753 /* setup 16C32 for SDLC DMA transfer mode */
6755 usc_reset(info);
6756 usc_set_sdlc_mode(info);
6757 usc_enable_loopback(info,1);
6759 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
6760 * field of the buffer entry after fetching buffer address. This
6761 * way we can detect a DMA failure for a DMA read (which should be
6762 * non-destructive to system memory) before we try and write to
6763 * memory (where a failure could corrupt system memory).
6766 /* Receive DMA mode Register (RDMR)
6768 * <15..14> 11 DMA mode = Linked List Buffer mode
6769 * <13> 1 RSBinA/L = store Rx status Block in List entry
6770 * <12> 0 1 = Clear count of List Entry after fetching
6771 * <11..10> 00 Address mode = Increment
6772 * <9> 1 Terminate Buffer on RxBound
6773 * <8> 0 Bus Width = 16bits
6774 * <7..0> ? status Bits (write as 0s)
6776 * 1110 0010 0000 0000 = 0xe200
6779 usc_OutDmaReg( info, RDMR, 0xe200 );
6781 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6784 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
6786 FrameSize = TESTFRAMESIZE;
6788 /* setup 1st transmit buffer entry: */
6789 /* with frame size and transmit control word */
6791 info->tx_buffer_list[0].count = FrameSize;
6792 info->tx_buffer_list[0].rcc = FrameSize;
6793 info->tx_buffer_list[0].status = 0x4000;
6795 /* build a transmit frame in 1st transmit DMA buffer */
6797 TmpPtr = info->tx_buffer_list[0].virt_addr;
6798 for (i = 0; i < FrameSize; i++ )
6799 *TmpPtr++ = i;
6801 /* setup 1st receive buffer entry: */
6802 /* clear status, set max receive buffer size */
6804 info->rx_buffer_list[0].status = 0;
6805 info->rx_buffer_list[0].count = FrameSize + 4;
6807 /* zero out the 1st receive buffer */
6809 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
6811 /* Set count field of next buffer entries to prevent */
6812 /* 16C32 from using buffers after the 1st one. */
6814 info->tx_buffer_list[1].count = 0;
6815 info->rx_buffer_list[1].count = 0;
6818 /***************************/
6819 /* Program 16C32 receiver. */
6820 /***************************/
6822 spin_lock_irqsave(&info->irq_spinlock,flags);
6824 /* setup DMA transfers */
6825 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6827 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
6828 phys_addr = info->rx_buffer_list[0].phys_entry;
6829 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
6830 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
6832 /* Clear the Rx DMA status bits (read RDMR) and start channel */
6833 usc_InDmaReg( info, RDMR );
6834 usc_DmaCmd( info, DmaCmd_InitRxChannel );
6836 /* Enable Receiver (RMR <1..0> = 10) */
6837 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
6839 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6842 /*************************************************************/
6843 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
6844 /*************************************************************/
6846 /* Wait 100ms for interrupt. */
6847 EndTime = jiffies + jiffies_from_ms(100);
6849 for(;;) {
6850 if ( jiffies > EndTime ) {
6851 rc = FALSE;
6852 break;
6855 spin_lock_irqsave(&info->irq_spinlock,flags);
6856 status = usc_InDmaReg( info, RDMR );
6857 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6859 if ( !(status & BIT4) && (status & BIT5) ) {
6860 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
6861 /* BUSY (BIT 5) is active (channel still active). */
6862 /* This means the buffer entry read has completed. */
6863 break;
6868 /******************************/
6869 /* Program 16C32 transmitter. */
6870 /******************************/
6872 spin_lock_irqsave(&info->irq_spinlock,flags);
6874 /* Program the Transmit Character Length Register (TCLR) */
6875 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6877 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
6878 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6880 /* Program the address of the 1st DMA Buffer Entry in linked list */
6882 phys_addr = info->tx_buffer_list[0].phys_entry;
6883 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
6884 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
6886 /* unlatch Tx status bits, and start transmit channel. */
6888 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0700) | 0xfa) );
6889 usc_DmaCmd( info, DmaCmd_InitTxChannel );
6891 /* wait for DMA controller to fill transmit FIFO */
6893 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
6895 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6898 /**********************************/
6899 /* WAIT FOR TRANSMIT FIFO TO FILL */
6900 /**********************************/
6902 /* Wait 100ms */
6903 EndTime = jiffies + jiffies_from_ms(100);
6905 for(;;) {
6906 if ( jiffies > EndTime ) {
6907 rc = FALSE;
6908 break;
6911 spin_lock_irqsave(&info->irq_spinlock,flags);
6912 FifoLevel = usc_InReg(info, TICR) >> 8;
6913 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6915 if ( FifoLevel < 16 )
6916 break;
6917 else
6918 if ( FrameSize < 32 ) {
6919 /* This frame is smaller than the entire transmit FIFO */
6920 /* so wait for the entire frame to be loaded. */
6921 if ( FifoLevel <= (32 - FrameSize) )
6922 break;
6927 if ( rc == TRUE )
6929 /* Enable 16C32 transmitter. */
6931 spin_lock_irqsave(&info->irq_spinlock,flags);
6933 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
6934 usc_TCmd( info, TCmd_SendFrame );
6935 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
6937 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6940 /******************************/
6941 /* WAIT FOR TRANSMIT COMPLETE */
6942 /******************************/
6944 /* Wait 100ms */
6945 EndTime = jiffies + jiffies_from_ms(100);
6947 /* While timer not expired wait for transmit complete */
6949 spin_lock_irqsave(&info->irq_spinlock,flags);
6950 status = usc_InReg( info, TCSR );
6951 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6953 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
6954 if ( jiffies > EndTime ) {
6955 rc = FALSE;
6956 break;
6959 spin_lock_irqsave(&info->irq_spinlock,flags);
6960 status = usc_InReg( info, TCSR );
6961 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6966 if ( rc == TRUE ){
6967 /* CHECK FOR TRANSMIT ERRORS */
6968 if ( status & (BIT5 + BIT1) )
6969 rc = FALSE;
6972 if ( rc == TRUE ) {
6973 /* WAIT FOR RECEIVE COMPLETE */
6975 /* Wait 100ms */
6976 EndTime = jiffies + jiffies_from_ms(100);
6978 /* Wait for 16C32 to write receive status to buffer entry. */
6979 status=info->rx_buffer_list[0].status;
6980 while ( status == 0 ) {
6981 if ( jiffies > EndTime ) {
6982 printk(KERN_ERR"mark 4\n");
6983 rc = FALSE;
6984 break;
6986 status=info->rx_buffer_list[0].status;
6991 if ( rc == TRUE ) {
6992 /* CHECK FOR RECEIVE ERRORS */
6993 status = info->rx_buffer_list[0].status;
6995 if ( status & (BIT8 + BIT3 + BIT1) ) {
6996 /* receive error has occured */
6997 rc = FALSE;
6998 } else {
6999 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7000 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7001 rc = FALSE;
7006 usc_reset( info );
7008 /* restore current port options */
7009 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7011 return rc;
7013 } /* end of mgsl_dma_test() */
7015 /* mgsl_adapter_test()
7017 * Perform the register, IRQ, and DMA tests for the 16C32.
7019 * Arguments: info pointer to device instance data
7020 * Return Value: 0 if success, otherwise -ENODEV
7022 int mgsl_adapter_test( struct mgsl_struct *info )
7024 if ( debug_level >= DEBUG_LEVEL_INFO )
7025 printk( "%s(%d):Testing device %s\n",
7026 __FILE__,__LINE__,info->device_name );
7028 if ( !mgsl_register_test( info ) ) {
7029 info->init_error = DiagStatus_AddressFailure;
7030 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7031 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7032 return -ENODEV;
7035 if ( !mgsl_irq_test( info ) ) {
7036 info->init_error = DiagStatus_IrqFailure;
7037 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7038 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7039 return -ENODEV;
7042 if ( !mgsl_dma_test( info ) ) {
7043 info->init_error = DiagStatus_DmaFailure;
7044 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7045 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7046 return -ENODEV;
7049 if ( debug_level >= DEBUG_LEVEL_INFO )
7050 printk( "%s(%d):device %s passed diagnostics\n",
7051 __FILE__,__LINE__,info->device_name );
7053 return 0;
7055 } /* end of mgsl_adapter_test() */
7057 /* mgsl_memory_test()
7059 * Test the shared memory on a PCI adapter.
7061 * Arguments: info pointer to device instance data
7062 * Return Value: TRUE if test passed, otherwise FALSE
7064 BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7066 static unsigned long BitPatterns[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7067 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7068 unsigned long Patterncount = sizeof(BitPatterns)/sizeof(unsigned long);
7069 unsigned long i;
7070 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7071 unsigned long * TestAddr;
7073 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7074 return TRUE;
7076 TestAddr = (unsigned long *)info->memory_base;
7078 /* Test data lines with test pattern at one location. */
7080 for ( i = 0 ; i < Patterncount ; i++ ) {
7081 *TestAddr = BitPatterns[i];
7082 if ( *TestAddr != BitPatterns[i] )
7083 return FALSE;
7086 /* Test address lines with incrementing pattern over */
7087 /* entire address range. */
7089 for ( i = 0 ; i < TestLimit ; i++ ) {
7090 *TestAddr = i * 4;
7091 TestAddr++;
7094 TestAddr = (unsigned long *)info->memory_base;
7096 for ( i = 0 ; i < TestLimit ; i++ ) {
7097 if ( *TestAddr != i * 4 )
7098 return FALSE;
7099 TestAddr++;
7102 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7104 return TRUE;
7106 } /* End Of mgsl_memory_test() */
7109 #pragma optimize( "", off )
7110 /* mgsl_load_pci_memory()
7112 * Load a large block of data into the PCI shared memory.
7113 * Use this instead of memcpy() or memmove() to move data
7114 * into the PCI shared memory.
7116 * Notes:
7118 * This function prevents the PCI9050 interface chip from hogging
7119 * the adapter local bus, which can starve the 16C32 by preventing
7120 * 16C32 bus master cycles.
7122 * The PCI9050 documentation says that the 9050 will always release
7123 * control of the local bus after completing the current read
7124 * or write operation.
7126 * It appears that as long as the PCI9050 write FIFO is full, the
7127 * PCI9050 treats all of the writes as a single burst transaction
7128 * and will not release the bus. This causes DMA latency problems
7129 * at high speeds when copying large data blocks to the shared
7130 * memory.
7132 * This function in effect, breaks the a large shared memory write
7133 * into multiple transations by interleaving a shared memory read
7134 * which will flush the write FIFO and 'complete' the write
7135 * transation. This allows any pending DMA request to gain control
7136 * of the local bus in a timely fasion.
7138 * Arguments:
7140 * TargetPtr pointer to target address in PCI shared memory
7141 * SourcePtr pointer to source buffer for data
7142 * count count in bytes of data to copy
7144 * Return Value: None
7146 void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7147 unsigned short count )
7149 /*******************************************************/
7150 /* A load interval of 16 allows for 4 32-bit writes at */
7151 /* 60ns each for a maximum latency of 240ns on the */
7152 /* local bus. */
7153 /*******************************************************/
7155 #define PCI_LOAD_INTERVAL 64
7157 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7158 unsigned short Index;
7159 unsigned long Dummy;
7161 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7163 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7164 Dummy = *((unsigned long *)TargetPtr);
7165 TargetPtr += PCI_LOAD_INTERVAL;
7166 SourcePtr += PCI_LOAD_INTERVAL;
7169 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7171 } /* End Of mgsl_load_pci_memory() */
7172 #pragma optimize( "", on )
7174 void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7176 int i;
7177 int linecount;
7178 if (xmit)
7179 printk("%s tx data:\n",info->device_name);
7180 else
7181 printk("%s rx data:\n",info->device_name);
7183 while(count) {
7184 if (count > 16)
7185 linecount = 16;
7186 else
7187 linecount = count;
7189 for(i=0;i<linecount;i++)
7190 printk("%02X ",(unsigned char)data[i]);
7191 for(;i<17;i++)
7192 printk(" ");
7193 for(i=0;i<linecount;i++) {
7194 if (data[i]>=040 && data[i]<=0176)
7195 printk("%c",data[i]);
7196 else
7197 printk(".");
7199 printk("\n");
7201 data += linecount;
7202 count -= linecount;
7204 } /* end of mgsl_trace_block() */
7206 /* mgsl_tx_timeout()
7208 * called when HDLC frame times out
7209 * update stats and do tx completion processing
7211 * Arguments: context pointer to device instance data
7212 * Return Value: None
7214 void mgsl_tx_timeout(unsigned long context)
7216 struct mgsl_struct *info = (struct mgsl_struct*)context;
7217 unsigned long flags;
7219 if ( debug_level >= DEBUG_LEVEL_INFO )
7220 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7221 __FILE__,__LINE__,info->device_name);
7222 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
7223 info->icount.txtimeout++;
7225 spin_lock_irqsave(&info->irq_spinlock,flags);
7226 info->tx_active = 0;
7227 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7229 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7230 usc_loopmode_cancel_transmit( info );
7232 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7234 mgsl_bh_transmit_data(info,0);
7236 } /* end of mgsl_tx_timeout() */
7238 /* signal that there are no more frames to send, so that
7239 * line is 'released' by echoing RxD to TxD when current
7240 * transmission is complete (or immediately if no tx in progress).
7242 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7244 unsigned long flags;
7246 spin_lock_irqsave(&info->irq_spinlock,flags);
7247 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7248 if (info->tx_active)
7249 info->loopmode_send_done_requested = TRUE;
7250 else
7251 usc_loopmode_send_done(info);
7253 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7255 return 0;
7258 /* release the line by echoing RxD to TxD
7259 * upon completion of a transmit frame
7261 void usc_loopmode_send_done( struct mgsl_struct * info )
7263 info->loopmode_send_done_requested = FALSE;
7264 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7265 info->cmr_value &= ~BIT13;
7266 usc_OutReg(info, CMR, info->cmr_value);
7269 /* abort a transmit in progress while in HDLC LoopMode
7271 void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7273 /* reset tx dma channel and purge TxFifo */
7274 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7275 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7276 usc_loopmode_send_done( info );
7279 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7280 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7281 * we must clear CMR:13 to begin repeating TxData to RxData
7283 void usc_loopmode_insert_request( struct mgsl_struct * info )
7285 info->loopmode_insert_requested = TRUE;
7287 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7288 * begin repeating TxData on RxData (complete insertion)
7290 usc_OutReg( info, RICR,
7291 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7293 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7294 info->cmr_value |= BIT13;
7295 usc_OutReg(info, CMR, info->cmr_value);
7298 /* return 1 if station is inserted into the loop, otherwise 0
7300 int usc_loopmode_active( struct mgsl_struct * info)
7302 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7305 /* return 1 if USC is in loop send mode, otherwise 0
7307 int usc_loopmode_send_active( struct mgsl_struct * info )
7309 return usc_InReg( info, CCSR ) & BIT6 ? 1 : 0 ;