2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 3.2 2000/11/06 22:34:38 paul Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
56 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
57 #define BREAKPOINT() asm(" int $3");
59 #define MAX_ISA_DEVICES 10
60 #define MAX_PCI_DEVICES 10
61 #define MAX_TOTAL_DEVICES 20
63 #include <linux/config.h>
64 #include <linux/module.h>
65 #include <linux/version.h>
66 #include <linux/errno.h>
67 #include <linux/signal.h>
68 #include <linux/sched.h>
69 #include <linux/timer.h>
70 #include <linux/interrupt.h>
71 #include <linux/pci.h>
72 #include <linux/tty.h>
73 #include <linux/tty_flip.h>
74 #include <linux/serial.h>
75 #include <linux/major.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/ioport.h>
81 #include <linux/malloc.h>
83 #include <linux/netdevice.h>
85 #include <linux/vmalloc.h>
86 #include <linux/init.h>
87 #include <asm/serial.h>
89 #include <linux/delay.h>
90 #include <linux/ioctl.h>
92 #include <asm/system.h>
96 #include <asm/bitops.h>
97 #include <asm/types.h>
98 #include <linux/termios.h>
99 #include <linux/tqueue.h>
101 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
102 #define CONFIG_SYNCLINK_SYNCPPP 1
105 #ifdef CONFIG_SYNCLINK_SYNCPPP
106 #include "../net/wan/syncppp.h"
109 #include <asm/segment.h>
110 #define GET_USER(error,value,addr) error = get_user(value,addr)
111 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
112 #define PUT_USER(error,value,addr) error = put_user(value,addr)
113 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
115 #include <asm/uaccess.h>
117 #include "linux/synclink.h"
119 #define RCLRVALUE 0xffff
121 MGSL_PARAMS default_params
= {
122 MGSL_MODE_HDLC
, /* unsigned long mode */
123 0, /* unsigned char loopback; */
124 HDLC_FLAG_UNDERRUN_ABORT15
, /* unsigned short flags; */
125 HDLC_ENCODING_NRZI_SPACE
, /* unsigned char encoding; */
126 0, /* unsigned long clock_speed; */
127 0xff, /* unsigned char addr_filter; */
128 HDLC_CRC_16_CCITT
, /* unsigned short crc_type; */
129 HDLC_PREAMBLE_LENGTH_8BITS
, /* unsigned char preamble_length; */
130 HDLC_PREAMBLE_PATTERN_NONE
, /* unsigned char preamble; */
131 9600, /* unsigned long data_rate; */
132 8, /* unsigned char data_bits; */
133 1, /* unsigned char stop_bits; */
134 ASYNC_PARITY_NONE
/* unsigned char parity; */
137 #define SHARED_MEM_ADDRESS_SIZE 0x40000
138 #define BUFFERLISTSIZE (PAGE_SIZE)
139 #define DMABUFFERSIZE (PAGE_SIZE)
140 #define MAXRXFRAMES 7
142 typedef struct _DMABUFFERENTRY
144 u32 phys_addr
; /* 32-bit flat physical address of data buffer */
145 u16 count
; /* buffer size/data count */
146 u16 status
; /* Control/status field */
147 u16 rcc
; /* character count field */
148 u16 reserved
; /* padding required by 16C32 */
149 u32 link
; /* 32-bit flat link to next buffer entry */
150 char *virt_addr
; /* virtual address of data buffer */
151 u32 phys_entry
; /* physical address of this buffer entry */
152 } DMABUFFERENTRY
, *DMAPBUFFERENTRY
;
154 /* The queue of BH actions to be performed */
157 #define BH_TRANSMIT 2
160 #define IO_PIN_SHUTDOWN_LIMIT 100
162 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
164 struct _input_signal_events
{
176 * Device instance data structure
180 void *if_ptr
; /* General purpose pointer (used by SPPP) */
183 int count
; /* count of opens */
185 unsigned short close_delay
;
186 unsigned short closing_wait
; /* time to wait before closing */
188 struct mgsl_icount icount
;
190 struct termios normal_termios
;
191 struct termios callout_termios
;
193 struct tty_struct
*tty
;
195 int x_char
; /* xon/xoff character */
196 int blocked_open
; /* # of blocked opens */
197 long session
; /* Session of opening process */
198 long pgrp
; /* pgrp of opening process */
199 u16 read_status_mask
;
200 u16 ignore_status_mask
;
201 unsigned char *xmit_buf
;
206 wait_queue_head_t open_wait
;
207 wait_queue_head_t close_wait
;
209 wait_queue_head_t status_event_wait_q
;
210 wait_queue_head_t event_wait_q
;
211 struct timer_list tx_timer
; /* HDLC transmit timeout timer */
212 struct mgsl_struct
*next_device
; /* device list link */
214 spinlock_t irq_spinlock
; /* spinlock for synchronizing with ISR */
215 struct tq_struct task
; /* task structure for scheduling bh */
217 u32 EventMask
; /* event trigger mask */
218 u32 RecordedEvents
; /* pending events */
220 u32 max_frame_size
; /* as set by device config */
224 int bh_running
; /* Protection from multiple */
228 int dcd_chkcount
; /* check counts to prevent */
229 int cts_chkcount
; /* too many IRQs if a signal */
230 int dsr_chkcount
; /* is floating */
233 char *buffer_list
; /* virtual address of Rx & Tx buffer lists */
234 unsigned long buffer_list_phys
;
236 unsigned int rx_buffer_count
; /* count of total allocated Rx buffers */
237 DMABUFFERENTRY
*rx_buffer_list
; /* list of receive buffer entries */
238 unsigned int current_rx_buffer
;
240 unsigned int tx_buffer_count
; /* count of total allocated Tx buffers */
241 DMABUFFERENTRY
*tx_buffer_list
; /* list of transmit buffer entries */
243 unsigned char *intermediate_rxbuffer
;
255 char device_name
[25]; /* device instance name */
257 unsigned int bus_type
; /* expansion bus type (ISA,EISA,PCI) */
258 unsigned char bus
; /* expansion bus number (zero based) */
259 unsigned char function
; /* PCI device number */
261 unsigned int io_base
; /* base I/O address of adapter */
262 unsigned int io_addr_size
; /* size of the I/O address range */
263 int io_addr_requested
; /* nonzero if I/O address requested */
265 unsigned int irq_level
; /* interrupt level */
266 unsigned long irq_flags
;
267 int irq_requested
; /* nonzero if IRQ requested */
269 unsigned int dma_level
; /* DMA channel */
270 int dma_requested
; /* nonzero if dma channel requested */
276 MGSL_PARAMS params
; /* communications parameters */
278 unsigned char serial_signals
; /* current serial signal states */
280 int irq_occurred
; /* for diagnostics use */
281 unsigned int init_error
; /* Initialization startup error (DIAGS) */
282 int fDiagnosticsmode
; /* Driver in Diagnostic mode? (DIAGS) */
285 unsigned char* memory_base
; /* shared memory address (PCI only) */
286 u32 phys_memory_base
;
287 int shared_mem_requested
;
289 unsigned char* lcr_base
; /* local config registers (PCI only) */
292 int lcr_mem_requested
;
295 char flag_buf
[MAX_ASYNC_BUFFER_SIZE
];
296 char char_buf
[MAX_ASYNC_BUFFER_SIZE
];
297 BOOLEAN drop_rts_on_tx_done
;
299 BOOLEAN loopmode_insert_requested
;
300 BOOLEAN loopmode_send_done_requested
;
302 struct _input_signal_events input_signal_events
;
304 /* SPPP/Cisco HDLC device parts */
308 #ifdef CONFIG_SYNCLINK_SYNCPPP
309 struct ppp_device pppdev
;
311 struct net_device
*netdev
;
312 struct net_device_stats netstats
;
313 struct net_device netdevice
;
317 #define MGSL_MAGIC 0x5401
320 * The size of the serial xmit buffer is 1 page, or 4096 bytes
322 #ifndef SERIAL_XMIT_SIZE
323 #define SERIAL_XMIT_SIZE 4096
327 * These macros define the offsets used in calculating the
328 * I/O address of the specified USC registers.
332 #define DCPIN 2 /* Bit 1 of I/O address */
333 #define SDPIN 4 /* Bit 2 of I/O address */
335 #define DCAR 0 /* DMA command/address register */
336 #define CCAR SDPIN /* channel command/address register */
337 #define DATAREG DCPIN + SDPIN /* serial data register */
342 * These macros define the register address (ordinal number)
343 * used for writing address/value pairs to the USC.
346 #define CMR 0x02 /* Channel mode Register */
347 #define CCSR 0x04 /* Channel Command/status Register */
348 #define CCR 0x06 /* Channel Control Register */
349 #define PSR 0x08 /* Port status Register */
350 #define PCR 0x0a /* Port Control Register */
351 #define TMDR 0x0c /* Test mode Data Register */
352 #define TMCR 0x0e /* Test mode Control Register */
353 #define CMCR 0x10 /* Clock mode Control Register */
354 #define HCR 0x12 /* Hardware Configuration Register */
355 #define IVR 0x14 /* Interrupt Vector Register */
356 #define IOCR 0x16 /* Input/Output Control Register */
357 #define ICR 0x18 /* Interrupt Control Register */
358 #define DCCR 0x1a /* Daisy Chain Control Register */
359 #define MISR 0x1c /* Misc Interrupt status Register */
360 #define SICR 0x1e /* status Interrupt Control Register */
361 #define RDR 0x20 /* Receive Data Register */
362 #define RMR 0x22 /* Receive mode Register */
363 #define RCSR 0x24 /* Receive Command/status Register */
364 #define RICR 0x26 /* Receive Interrupt Control Register */
365 #define RSR 0x28 /* Receive Sync Register */
366 #define RCLR 0x2a /* Receive count Limit Register */
367 #define RCCR 0x2c /* Receive Character count Register */
368 #define TC0R 0x2e /* Time Constant 0 Register */
369 #define TDR 0x30 /* Transmit Data Register */
370 #define TMR 0x32 /* Transmit mode Register */
371 #define TCSR 0x34 /* Transmit Command/status Register */
372 #define TICR 0x36 /* Transmit Interrupt Control Register */
373 #define TSR 0x38 /* Transmit Sync Register */
374 #define TCLR 0x3a /* Transmit count Limit Register */
375 #define TCCR 0x3c /* Transmit Character count Register */
376 #define TC1R 0x3e /* Time Constant 1 Register */
380 * MACRO DEFINITIONS FOR DMA REGISTERS
383 #define DCR 0x06 /* DMA Control Register (shared) */
384 #define DACR 0x08 /* DMA Array count Register (shared) */
385 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
386 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
387 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
388 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
389 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
391 #define TDMR 0x02 /* Transmit DMA mode Register */
392 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
393 #define TBCR 0x2a /* Transmit Byte count Register */
394 #define TARL 0x2c /* Transmit Address Register (low) */
395 #define TARU 0x2e /* Transmit Address Register (high) */
396 #define NTBCR 0x3a /* Next Transmit Byte count Register */
397 #define NTARL 0x3c /* Next Transmit Address Register (low) */
398 #define NTARU 0x3e /* Next Transmit Address Register (high) */
400 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
401 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
402 #define RBCR 0xaa /* Receive Byte count Register */
403 #define RARL 0xac /* Receive Address Register (low) */
404 #define RARU 0xae /* Receive Address Register (high) */
405 #define NRBCR 0xba /* Next Receive Byte count Register */
406 #define NRARL 0xbc /* Next Receive Address Register (low) */
407 #define NRARU 0xbe /* Next Receive Address Register (high) */
411 * MACRO DEFINITIONS FOR MODEM STATUS BITS
414 #define MODEMSTATUS_DTR 0x80
415 #define MODEMSTATUS_DSR 0x40
416 #define MODEMSTATUS_RTS 0x20
417 #define MODEMSTATUS_CTS 0x10
418 #define MODEMSTATUS_RI 0x04
419 #define MODEMSTATUS_DCD 0x01
423 * Channel Command/Address Register (CCAR) Command Codes
426 #define RTCmd_Null 0x0000
427 #define RTCmd_ResetHighestIus 0x1000
428 #define RTCmd_TriggerChannelLoadDma 0x2000
429 #define RTCmd_TriggerRxDma 0x2800
430 #define RTCmd_TriggerTxDma 0x3000
431 #define RTCmd_TriggerRxAndTxDma 0x3800
432 #define RTCmd_PurgeRxFifo 0x4800
433 #define RTCmd_PurgeTxFifo 0x5000
434 #define RTCmd_PurgeRxAndTxFifo 0x5800
435 #define RTCmd_LoadRcc 0x6800
436 #define RTCmd_LoadTcc 0x7000
437 #define RTCmd_LoadRccAndTcc 0x7800
438 #define RTCmd_LoadTC0 0x8800
439 #define RTCmd_LoadTC1 0x9000
440 #define RTCmd_LoadTC0AndTC1 0x9800
441 #define RTCmd_SerialDataLSBFirst 0xa000
442 #define RTCmd_SerialDataMSBFirst 0xa800
443 #define RTCmd_SelectBigEndian 0xb000
444 #define RTCmd_SelectLittleEndian 0xb800
448 * DMA Command/Address Register (DCAR) Command Codes
451 #define DmaCmd_Null 0x0000
452 #define DmaCmd_ResetTxChannel 0x1000
453 #define DmaCmd_ResetRxChannel 0x1200
454 #define DmaCmd_StartTxChannel 0x2000
455 #define DmaCmd_StartRxChannel 0x2200
456 #define DmaCmd_ContinueTxChannel 0x3000
457 #define DmaCmd_ContinueRxChannel 0x3200
458 #define DmaCmd_PauseTxChannel 0x4000
459 #define DmaCmd_PauseRxChannel 0x4200
460 #define DmaCmd_AbortTxChannel 0x5000
461 #define DmaCmd_AbortRxChannel 0x5200
462 #define DmaCmd_InitTxChannel 0x7000
463 #define DmaCmd_InitRxChannel 0x7200
464 #define DmaCmd_ResetHighestDmaIus 0x8000
465 #define DmaCmd_ResetAllChannels 0x9000
466 #define DmaCmd_StartAllChannels 0xa000
467 #define DmaCmd_ContinueAllChannels 0xb000
468 #define DmaCmd_PauseAllChannels 0xc000
469 #define DmaCmd_AbortAllChannels 0xd000
470 #define DmaCmd_InitAllChannels 0xf000
472 #define TCmd_Null 0x0000
473 #define TCmd_ClearTxCRC 0x2000
474 #define TCmd_SelectTicrTtsaData 0x4000
475 #define TCmd_SelectTicrTxFifostatus 0x5000
476 #define TCmd_SelectTicrIntLevel 0x6000
477 #define TCmd_SelectTicrdma_level 0x7000
478 #define TCmd_SendFrame 0x8000
479 #define TCmd_SendAbort 0x9000
480 #define TCmd_EnableDleInsertion 0xc000
481 #define TCmd_DisableDleInsertion 0xd000
482 #define TCmd_ClearEofEom 0xe000
483 #define TCmd_SetEofEom 0xf000
485 #define RCmd_Null 0x0000
486 #define RCmd_ClearRxCRC 0x2000
487 #define RCmd_EnterHuntmode 0x3000
488 #define RCmd_SelectRicrRtsaData 0x4000
489 #define RCmd_SelectRicrRxFifostatus 0x5000
490 #define RCmd_SelectRicrIntLevel 0x6000
491 #define RCmd_SelectRicrdma_level 0x7000
494 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
497 #define RECEIVE_STATUS BIT5
498 #define RECEIVE_DATA BIT4
499 #define TRANSMIT_STATUS BIT3
500 #define TRANSMIT_DATA BIT2
506 * Receive status Bits in Receive Command/status Register RCSR
509 #define RXSTATUS_SHORT_FRAME BIT8
510 #define RXSTATUS_CODE_VIOLATION BIT8
511 #define RXSTATUS_EXITED_HUNT BIT7
512 #define RXSTATUS_IDLE_RECEIVED BIT6
513 #define RXSTATUS_BREAK_RECEIVED BIT5
514 #define RXSTATUS_ABORT_RECEIVED BIT5
515 #define RXSTATUS_RXBOUND BIT4
516 #define RXSTATUS_CRC_ERROR BIT3
517 #define RXSTATUS_FRAMING_ERROR BIT3
518 #define RXSTATUS_ABORT BIT2
519 #define RXSTATUS_PARITY_ERROR BIT2
520 #define RXSTATUS_OVERRUN BIT1
521 #define RXSTATUS_DATA_AVAILABLE BIT0
522 #define RXSTATUS_ALL 0x01f6
523 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
526 * Values for setting transmit idle mode in
527 * Transmit Control/status Register (TCSR)
529 #define IDLEMODE_FLAGS 0x0000
530 #define IDLEMODE_ALT_ONE_ZERO 0x0100
531 #define IDLEMODE_ZERO 0x0200
532 #define IDLEMODE_ONE 0x0300
533 #define IDLEMODE_ALT_MARK_SPACE 0x0500
534 #define IDLEMODE_SPACE 0x0600
535 #define IDLEMODE_MARK 0x0700
536 #define IDLEMODE_MASK 0x0700
539 * IUSC revision identifiers
541 #define IUSC_SL1660 0x4d44
542 #define IUSC_PRE_SL1660 0x4553
545 * Transmit status Bits in Transmit Command/status Register (TCSR)
548 #define TCSR_PRESERVE 0x0F00
550 #define TCSR_UNDERWAIT BIT11
551 #define TXSTATUS_PREAMBLE_SENT BIT7
552 #define TXSTATUS_IDLE_SENT BIT6
553 #define TXSTATUS_ABORT_SENT BIT5
554 #define TXSTATUS_EOF_SENT BIT4
555 #define TXSTATUS_EOM_SENT BIT4
556 #define TXSTATUS_CRC_SENT BIT3
557 #define TXSTATUS_ALL_SENT BIT2
558 #define TXSTATUS_UNDERRUN BIT1
559 #define TXSTATUS_FIFO_EMPTY BIT0
560 #define TXSTATUS_ALL 0x00fa
561 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
564 #define MISCSTATUS_RXC_LATCHED BIT15
565 #define MISCSTATUS_RXC BIT14
566 #define MISCSTATUS_TXC_LATCHED BIT13
567 #define MISCSTATUS_TXC BIT12
568 #define MISCSTATUS_RI_LATCHED BIT11
569 #define MISCSTATUS_RI BIT10
570 #define MISCSTATUS_DSR_LATCHED BIT9
571 #define MISCSTATUS_DSR BIT8
572 #define MISCSTATUS_DCD_LATCHED BIT7
573 #define MISCSTATUS_DCD BIT6
574 #define MISCSTATUS_CTS_LATCHED BIT5
575 #define MISCSTATUS_CTS BIT4
576 #define MISCSTATUS_RCC_UNDERRUN BIT3
577 #define MISCSTATUS_DPLL_NO_SYNC BIT2
578 #define MISCSTATUS_BRG1_ZERO BIT1
579 #define MISCSTATUS_BRG0_ZERO BIT0
581 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
582 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
584 #define SICR_RXC_ACTIVE BIT15
585 #define SICR_RXC_INACTIVE BIT14
586 #define SICR_RXC (BIT15+BIT14)
587 #define SICR_TXC_ACTIVE BIT13
588 #define SICR_TXC_INACTIVE BIT12
589 #define SICR_TXC (BIT13+BIT12)
590 #define SICR_RI_ACTIVE BIT11
591 #define SICR_RI_INACTIVE BIT10
592 #define SICR_RI (BIT11+BIT10)
593 #define SICR_DSR_ACTIVE BIT9
594 #define SICR_DSR_INACTIVE BIT8
595 #define SICR_DSR (BIT9+BIT8)
596 #define SICR_DCD_ACTIVE BIT7
597 #define SICR_DCD_INACTIVE BIT6
598 #define SICR_DCD (BIT7+BIT6)
599 #define SICR_CTS_ACTIVE BIT5
600 #define SICR_CTS_INACTIVE BIT4
601 #define SICR_CTS (BIT5+BIT4)
602 #define SICR_RCC_UNDERFLOW BIT3
603 #define SICR_DPLL_NO_SYNC BIT2
604 #define SICR_BRG1_ZERO BIT1
605 #define SICR_BRG0_ZERO BIT0
607 void usc_DisableMasterIrqBit( struct mgsl_struct
*info
);
608 void usc_EnableMasterIrqBit( struct mgsl_struct
*info
);
609 void usc_EnableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
610 void usc_DisableInterrupts( struct mgsl_struct
*info
, u16 IrqMask
);
611 void usc_ClearIrqPendingBits( struct mgsl_struct
*info
, u16 IrqMask
);
613 #define usc_EnableInterrupts( a, b ) \
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
616 #define usc_DisableInterrupts( a, b ) \
617 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
619 #define usc_EnableMasterIrqBit(a) \
620 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
622 #define usc_DisableMasterIrqBit(a) \
623 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
625 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
628 * Transmit status Bits in Transmit Control status Register (TCSR)
629 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
632 #define TXSTATUS_PREAMBLE_SENT BIT7
633 #define TXSTATUS_IDLE_SENT BIT6
634 #define TXSTATUS_ABORT_SENT BIT5
635 #define TXSTATUS_EOF BIT4
636 #define TXSTATUS_CRC_SENT BIT3
637 #define TXSTATUS_ALL_SENT BIT2
638 #define TXSTATUS_UNDERRUN BIT1
639 #define TXSTATUS_FIFO_EMPTY BIT0
641 #define DICR_MASTER BIT15
642 #define DICR_TRANSMIT BIT0
643 #define DICR_RECEIVE BIT1
645 #define usc_EnableDmaInterrupts(a,b) \
646 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
648 #define usc_DisableDmaInterrupts(a,b) \
649 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
651 #define usc_EnableStatusIrqs(a,b) \
652 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
654 #define usc_DisablestatusIrqs(a,b) \
655 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
657 /* Transmit status Bits in Transmit Control status Register (TCSR) */
658 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
661 #define DISABLE_UNCONDITIONAL 0
662 #define DISABLE_END_OF_FRAME 1
663 #define ENABLE_UNCONDITIONAL 2
664 #define ENABLE_AUTO_CTS 3
665 #define ENABLE_AUTO_DCD 3
666 #define usc_EnableTransmitter(a,b) \
667 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
668 #define usc_EnableReceiver(a,b) \
669 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
671 u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 Port
);
672 void usc_OutDmaReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
673 void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
);
675 u16
usc_InReg( struct mgsl_struct
*info
, u16 Port
);
676 void usc_OutReg( struct mgsl_struct
*info
, u16 Port
, u16 Value
);
677 void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
);
678 void usc_RCmd( struct mgsl_struct
*info
, u16 Cmd
);
679 void usc_TCmd( struct mgsl_struct
*info
, u16 Cmd
);
681 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
682 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
684 void usc_process_rxoverrun_sync( struct mgsl_struct
*info
);
685 void usc_start_receiver( struct mgsl_struct
*info
);
686 void usc_stop_receiver( struct mgsl_struct
*info
);
688 void usc_start_transmitter( struct mgsl_struct
*info
);
689 void usc_stop_transmitter( struct mgsl_struct
*info
);
690 void usc_set_txidle( struct mgsl_struct
*info
);
691 void usc_load_txfifo( struct mgsl_struct
*info
);
693 void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 DataRate
);
694 void usc_enable_loopback( struct mgsl_struct
*info
, int enable
);
696 void usc_get_serial_signals( struct mgsl_struct
*info
);
697 void usc_set_serial_signals( struct mgsl_struct
*info
);
699 void usc_reset( struct mgsl_struct
*info
);
701 void usc_set_sync_mode( struct mgsl_struct
*info
);
702 void usc_set_sdlc_mode( struct mgsl_struct
*info
);
703 void usc_set_async_mode( struct mgsl_struct
*info
);
704 void usc_enable_async_clock( struct mgsl_struct
*info
, u32 DataRate
);
706 void usc_loopback_frame( struct mgsl_struct
*info
);
708 void mgsl_tx_timeout(unsigned long context
);
711 void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
);
712 void usc_loopmode_insert_request( struct mgsl_struct
* info
);
713 int usc_loopmode_active( struct mgsl_struct
* info
);
714 void usc_loopmode_send_done( struct mgsl_struct
* info
);
715 int usc_loopmode_send_active( struct mgsl_struct
* info
);
717 int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
);
719 #ifdef CONFIG_SYNCLINK_SYNCPPP
720 /* SPPP/HDLC stuff */
721 void mgsl_sppp_init(struct mgsl_struct
*info
);
722 void mgsl_sppp_delete(struct mgsl_struct
*info
);
723 int mgsl_sppp_open(struct net_device
*d
);
724 int mgsl_sppp_close(struct net_device
*d
);
725 void mgsl_sppp_tx_timeout(struct net_device
*d
);
726 int mgsl_sppp_tx(struct sk_buff
*skb
, struct net_device
*d
);
727 void mgsl_sppp_rx_done(struct mgsl_struct
*info
, char *buf
, int size
);
728 void mgsl_sppp_tx_done(struct mgsl_struct
*info
);
729 int mgsl_sppp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
);
730 struct net_device_stats
*mgsl_net_stats(struct net_device
*dev
);
734 * Defines a BUS descriptor value for the PCI adapter
735 * local bus address ranges.
738 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
749 void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
);
752 * Adapter diagnostic routines
754 BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
);
755 BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
);
756 BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
);
757 BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
);
758 int mgsl_adapter_test( struct mgsl_struct
*info
);
761 * device and resource management routines
763 int mgsl_claim_resources(struct mgsl_struct
*info
);
764 void mgsl_release_resources(struct mgsl_struct
*info
);
765 void mgsl_add_device(struct mgsl_struct
*info
);
766 struct mgsl_struct
* mgsl_allocate_device(void);
767 int mgsl_enum_isa_devices(void);
770 * DMA buffer manupulation functions.
772 void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
);
773 int mgsl_get_rx_frame( struct mgsl_struct
*info
);
774 void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
);
775 void mgsl_load_tx_dma_buffer( struct mgsl_struct
*info
, const char *Buffer
, unsigned int BufferSize
);
776 void mgsl_load_pci_memory(char* TargetPtr
, const char* SourcePtr
, unsigned short count
);
779 * DMA and Shared Memory buffer allocation and formatting
781 int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
);
782 void mgsl_free_dma_buffers(struct mgsl_struct
*info
);
783 int mgsl_alloc_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
784 void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
,int Buffercount
);
785 int mgsl_alloc_buffer_list_memory(struct mgsl_struct
*info
);
786 void mgsl_free_buffer_list_memory(struct mgsl_struct
*info
);
787 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
788 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
);
791 * Bottom half interrupt handlers
793 void mgsl_bh_handler(void* Context
);
794 void mgsl_bh_receive(struct mgsl_struct
*info
);
795 void mgsl_bh_transmit(struct mgsl_struct
*info
);
796 void mgsl_bh_status(struct mgsl_struct
*info
);
799 * Interrupt handler routines and dispatch table.
801 void mgsl_isr_null( struct mgsl_struct
*info
);
802 void mgsl_isr_transmit_data( struct mgsl_struct
*info
);
803 void mgsl_isr_receive_data( struct mgsl_struct
*info
);
804 void mgsl_isr_receive_status( struct mgsl_struct
*info
);
805 void mgsl_isr_transmit_status( struct mgsl_struct
*info
);
806 void mgsl_isr_io_pin( struct mgsl_struct
*info
);
807 void mgsl_isr_misc( struct mgsl_struct
*info
);
808 void mgsl_isr_receive_dma( struct mgsl_struct
*info
);
810 typedef void (*isr_dispatch_func
)(struct mgsl_struct
*);
812 isr_dispatch_func UscIsrTable
[7] =
817 mgsl_isr_transmit_data
,
818 mgsl_isr_transmit_status
,
819 mgsl_isr_receive_data
,
820 mgsl_isr_receive_status
824 * ioctl call handlers
826 static int set_modem_info(struct mgsl_struct
* info
, unsigned int cmd
,
827 unsigned int *value
);
828 static int get_modem_info(struct mgsl_struct
* info
, unsigned int *value
);
829 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
831 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS
*user_params
);
832 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS
*new_params
);
833 static int mgsl_get_txidle(struct mgsl_struct
* info
, int*idle_mode
);
834 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
);
835 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
);
836 static int mgsl_txabort(struct mgsl_struct
* info
);
837 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
);
838 static int mgsl_wait_event(struct mgsl_struct
* info
, int * mask
);
839 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
);
841 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
844 * Global linked list of SyncLink devices
846 struct mgsl_struct
*mgsl_device_list
= NULL
;
847 int mgsl_device_count
= 0;
850 * Set this param to non-zero to load eax with the
851 * .text section address and breakpoint on module load.
852 * This is useful for use with gdb and add-symbol-file command.
857 * Driver major number, defaults to zero to get auto
858 * assigned major number. May be forced as module parameter.
865 * Array of user specified options for ISA adapters.
867 static int io
[MAX_ISA_DEVICES
] = {0,};
868 static int irq
[MAX_ISA_DEVICES
] = {0,};
869 static int dma
[MAX_ISA_DEVICES
] = {0,};
870 static int debug_level
= 0;
871 static int maxframe
[MAX_TOTAL_DEVICES
] = {0,};
872 static int dosyncppp
[MAX_TOTAL_DEVICES
] = {0,};
874 MODULE_PARM(break_on_load
,"i");
875 MODULE_PARM(ttymajor
,"i");
876 MODULE_PARM(cuamajor
,"i");
877 MODULE_PARM(io
,"1-" __MODULE_STRING(MAX_ISA_DEVICES
) "i");
878 MODULE_PARM(irq
,"1-" __MODULE_STRING(MAX_ISA_DEVICES
) "i");
879 MODULE_PARM(dma
,"1-" __MODULE_STRING(MAX_ISA_DEVICES
) "i");
880 MODULE_PARM(debug_level
,"i");
881 MODULE_PARM(maxframe
,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES
) "i");
882 MODULE_PARM(dosyncppp
,"1-" __MODULE_STRING(MAX_TOTAL_DEVICES
) "i");
884 static char *driver_name
= "SyncLink serial driver";
885 static char *driver_version
= "3.2";
887 static int __init
synclink_init_one (struct pci_dev
*dev
,
888 const struct pci_device_id
*ent
);
889 static void __exit
synclink_remove_one (struct pci_dev
*dev
);
891 static struct pci_device_id synclink_pci_tbl
[] __devinitdata
= {
892 { PCI_VENDOR_ID_MICROGATE
, PCI_DEVICE_ID_MICROGATE_USC
, PCI_ANY_ID
, PCI_ANY_ID
, },
893 { 0, }, /* terminate list */
895 MODULE_DEVICE_TABLE(pci
, synclink_pci_tbl
);
897 static struct pci_driver synclink_pci_driver
= {
899 id_table
: synclink_pci_tbl
,
900 probe
: synclink_init_one
,
901 remove
: synclink_remove_one
,
904 static struct tty_driver serial_driver
, callout_driver
;
905 static int serial_refcount
;
907 /* number of characters left in xmit buffer before we ask for more */
908 #define WAKEUP_CHARS 256
911 static void mgsl_change_params(struct mgsl_struct
*info
);
912 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
);
914 static struct tty_struct
*serial_table
[MAX_TOTAL_DEVICES
];
915 static struct termios
*serial_termios
[MAX_TOTAL_DEVICES
];
916 static struct termios
*serial_termios_locked
[MAX_TOTAL_DEVICES
];
919 #define MIN(a,b) ((a) < (b) ? (a) : (b))
923 * 1st function defined in .text section. Calling this function in
924 * init_module() followed by a breakpoint allows a remote debugger
925 * (gdb) to get the .text address for the add-symbol-file command.
926 * This allows remote debugging of dynamically loadable modules.
928 void* mgsl_get_text_ptr(void);
929 void* mgsl_get_text_ptr() {return mgsl_get_text_ptr
;}
932 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
933 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
934 * and some other program tries to do a serial write at the same time.
935 * Since the lock will only come under contention when the system is
936 * swapping and available memory is low, it makes sense to share one
937 * buffer across all the serial ioports, since it significantly saves
938 * memory if large numbers of serial ports are open.
940 static unsigned char *tmp_buf
;
941 static DECLARE_MUTEX(tmp_buf_sem
);
943 static inline int mgsl_paranoia_check(struct mgsl_struct
*info
,
944 kdev_t device
, const char *routine
)
946 #ifdef MGSL_PARANOIA_CHECK
947 static const char *badmagic
=
948 "Warning: bad magic number for mgsl struct (%s) in %s\n";
949 static const char *badinfo
=
950 "Warning: null mgsl_struct for (%s) in %s\n";
953 printk(badinfo
, kdevname(device
), routine
);
956 if (info
->magic
!= MGSL_MAGIC
) {
957 printk(badmagic
, kdevname(device
), routine
);
964 /* mgsl_stop() throttle (stop) transmitter
966 * Arguments: tty pointer to tty info structure
969 static void mgsl_stop(struct tty_struct
*tty
)
971 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
974 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_stop"))
977 if ( debug_level
>= DEBUG_LEVEL_INFO
)
978 printk("mgsl_stop(%s)\n",info
->device_name
);
980 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
981 if (info
->tx_enabled
)
982 usc_stop_transmitter(info
);
983 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
985 } /* end of mgsl_stop() */
987 /* mgsl_start() release (start) transmitter
989 * Arguments: tty pointer to tty info structure
992 static void mgsl_start(struct tty_struct
*tty
)
994 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
997 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_start"))
1000 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1001 printk("mgsl_start(%s)\n",info
->device_name
);
1003 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1004 if (!info
->tx_enabled
)
1005 usc_start_transmitter(info
);
1006 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1008 } /* end of mgsl_start() */
1011 * Bottom half work queue access functions
1014 /* mgsl_bh_action() Return next bottom half action to perform.
1015 * Return Value: BH action code or 0 if nothing to do.
1017 int mgsl_bh_action(struct mgsl_struct
*info
)
1019 unsigned long flags
;
1022 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1024 if (info
->pending_bh
& BH_RECEIVE
) {
1025 info
->pending_bh
&= ~BH_RECEIVE
;
1027 } else if (info
->pending_bh
& BH_TRANSMIT
) {
1028 info
->pending_bh
&= ~BH_TRANSMIT
;
1030 } else if (info
->pending_bh
& BH_STATUS
) {
1031 info
->pending_bh
&= ~BH_STATUS
;
1036 /* Mark BH routine as complete */
1037 info
->bh_running
= 0;
1038 info
->bh_requested
= 0;
1041 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1047 * Perform bottom half processing of work items queued by ISR.
1049 void mgsl_bh_handler(void* Context
)
1051 struct mgsl_struct
*info
= (struct mgsl_struct
*)Context
;
1057 if ( debug_level
>= DEBUG_LEVEL_BH
)
1058 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1059 __FILE__
,__LINE__
,info
->device_name
);
1061 info
->bh_running
= 1;
1063 while((action
= mgsl_bh_action(info
)) != 0) {
1065 /* Process work item */
1066 if ( debug_level
>= DEBUG_LEVEL_BH
)
1067 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1068 __FILE__
,__LINE__
,action
);
1073 mgsl_bh_receive(info
);
1076 mgsl_bh_transmit(info
);
1079 mgsl_bh_status(info
);
1082 /* unknown work item ID */
1083 printk("Unknown work item ID=%08X!\n", action
);
1088 if ( debug_level
>= DEBUG_LEVEL_BH
)
1089 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1090 __FILE__
,__LINE__
,info
->device_name
);
1093 void mgsl_bh_receive(struct mgsl_struct
*info
)
1095 if ( debug_level
>= DEBUG_LEVEL_BH
)
1096 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1097 __FILE__
,__LINE__
,info
->device_name
);
1099 while( mgsl_get_rx_frame(info
) );
1102 void mgsl_bh_transmit(struct mgsl_struct
*info
)
1104 struct tty_struct
*tty
= info
->tty
;
1105 unsigned long flags
;
1107 if ( debug_level
>= DEBUG_LEVEL_BH
)
1108 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1109 __FILE__
,__LINE__
,info
->device_name
);
1112 if ((tty
->flags
& (1 << TTY_DO_WRITE_WAKEUP
)) &&
1113 tty
->ldisc
.write_wakeup
) {
1114 if ( debug_level
>= DEBUG_LEVEL_BH
)
1115 printk( "%s(%d):calling ldisc.write_wakeup on %s\n",
1116 __FILE__
,__LINE__
,info
->device_name
);
1117 (tty
->ldisc
.write_wakeup
)(tty
);
1119 wake_up_interruptible(&tty
->write_wait
);
1122 /* if transmitter idle and loopmode_send_done_requested
1123 * then start echoing RxD to TxD
1125 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1126 if ( !info
->tx_active
&& info
->loopmode_send_done_requested
)
1127 usc_loopmode_send_done( info
);
1128 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1131 void mgsl_bh_status(struct mgsl_struct
*info
)
1133 if ( debug_level
>= DEBUG_LEVEL_BH
)
1134 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1135 __FILE__
,__LINE__
,info
->device_name
);
1137 info
->ri_chkcount
= 0;
1138 info
->dsr_chkcount
= 0;
1139 info
->dcd_chkcount
= 0;
1140 info
->cts_chkcount
= 0;
1143 /* mgsl_isr_receive_status()
1145 * Service a receive status interrupt. The type of status
1146 * interrupt is indicated by the state of the RCSR.
1147 * This is only used for HDLC mode.
1149 * Arguments: info pointer to device instance data
1150 * Return Value: None
1152 void mgsl_isr_receive_status( struct mgsl_struct
*info
)
1154 u16 status
= usc_InReg( info
, RCSR
);
1156 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1157 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1158 __FILE__
,__LINE__
,status
);
1160 if ( (status
& RXSTATUS_ABORT_RECEIVED
) &&
1161 info
->loopmode_insert_requested
&&
1162 usc_loopmode_active(info
) )
1164 ++info
->icount
.rxabort
;
1165 info
->loopmode_insert_requested
= FALSE
;
1167 /* clear CMR:13 to start echoing RxD to TxD */
1168 info
->cmr_value
&= ~BIT13
;
1169 usc_OutReg(info
, CMR
, info
->cmr_value
);
1171 /* disable received abort irq (no longer required) */
1172 usc_OutReg(info
, RICR
,
1173 (usc_InReg(info
, RICR
) & ~RXSTATUS_ABORT_RECEIVED
));
1176 if (status
& (RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
)) {
1177 if (status
& RXSTATUS_EXITED_HUNT
)
1178 info
->icount
.exithunt
++;
1179 if (status
& RXSTATUS_IDLE_RECEIVED
)
1180 info
->icount
.rxidle
++;
1181 wake_up_interruptible(&info
->event_wait_q
);
1184 if (status
& RXSTATUS_OVERRUN
){
1185 info
->icount
.rxover
++;
1186 usc_process_rxoverrun_sync( info
);
1189 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
1190 usc_UnlatchRxstatusBits( info
, status
);
1192 } /* end of mgsl_isr_receive_status() */
1194 /* mgsl_isr_transmit_status()
1196 * Service a transmit status interrupt
1197 * HDLC mode :end of transmit frame
1198 * Async mode:all data is sent
1199 * transmit status is indicated by bits in the TCSR.
1201 * Arguments: info pointer to device instance data
1202 * Return Value: None
1204 void mgsl_isr_transmit_status( struct mgsl_struct
*info
)
1206 u16 status
= usc_InReg( info
, TCSR
);
1208 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1209 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1210 __FILE__
,__LINE__
,status
);
1212 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
1213 usc_UnlatchTxstatusBits( info
, status
);
1215 if ( status
& (TXSTATUS_UNDERRUN
| TXSTATUS_ABORT_SENT
) )
1217 /* finished sending HDLC abort. This may leave */
1218 /* the TxFifo with data from the aborted frame */
1219 /* so purge the TxFifo. Also shutdown the DMA */
1220 /* channel in case there is data remaining in */
1221 /* the DMA buffer */
1222 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
1223 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
1226 if ( status
& TXSTATUS_EOF_SENT
)
1227 info
->icount
.txok
++;
1228 else if ( status
& TXSTATUS_UNDERRUN
)
1229 info
->icount
.txunder
++;
1230 else if ( status
& TXSTATUS_ABORT_SENT
)
1231 info
->icount
.txabort
++;
1233 info
->icount
.txunder
++;
1235 info
->tx_active
= 0;
1236 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1237 del_timer(&info
->tx_timer
);
1239 if ( info
->drop_rts_on_tx_done
) {
1240 usc_get_serial_signals( info
);
1241 if ( info
->serial_signals
& SerialSignal_RTS
) {
1242 info
->serial_signals
&= ~SerialSignal_RTS
;
1243 usc_set_serial_signals( info
);
1245 info
->drop_rts_on_tx_done
= 0;
1248 #ifdef CONFIG_SYNCLINK_SYNCPPP
1250 mgsl_sppp_tx_done(info
);
1254 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1255 usc_stop_transmitter(info
);
1258 info
->pending_bh
|= BH_TRANSMIT
;
1261 } /* end of mgsl_isr_transmit_status() */
1263 /* mgsl_isr_io_pin()
1265 * Service an Input/Output pin interrupt. The type of
1266 * interrupt is indicated by bits in the MISR
1268 * Arguments: info pointer to device instance data
1269 * Return Value: None
1271 void mgsl_isr_io_pin( struct mgsl_struct
*info
)
1273 struct mgsl_icount
*icount
;
1274 u16 status
= usc_InReg( info
, MISR
);
1276 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1277 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1278 __FILE__
,__LINE__
,status
);
1280 usc_ClearIrqPendingBits( info
, IO_PIN
);
1281 usc_UnlatchIostatusBits( info
, status
);
1283 if (status
& (MISCSTATUS_CTS_LATCHED
| MISCSTATUS_DCD_LATCHED
|
1284 MISCSTATUS_DSR_LATCHED
| MISCSTATUS_RI_LATCHED
) ) {
1285 icount
= &info
->icount
;
1286 /* update input line counters */
1287 if (status
& MISCSTATUS_RI_LATCHED
) {
1288 if ((info
->ri_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1289 usc_DisablestatusIrqs(info
,SICR_RI
);
1291 if ( status
& MISCSTATUS_RI
)
1292 info
->input_signal_events
.ri_up
++;
1294 info
->input_signal_events
.ri_down
++;
1296 if (status
& MISCSTATUS_DSR_LATCHED
) {
1297 if ((info
->dsr_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1298 usc_DisablestatusIrqs(info
,SICR_DSR
);
1300 if ( status
& MISCSTATUS_DSR
)
1301 info
->input_signal_events
.dsr_up
++;
1303 info
->input_signal_events
.dsr_down
++;
1305 if (status
& MISCSTATUS_DCD_LATCHED
) {
1306 if ((info
->dcd_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1307 usc_DisablestatusIrqs(info
,SICR_DCD
);
1309 if (status
& MISCSTATUS_DCD
) {
1310 info
->input_signal_events
.dcd_up
++;
1311 #ifdef CONFIG_SYNCLINK_SYNCPPP
1313 sppp_reopen(info
->netdev
);
1316 info
->input_signal_events
.dcd_down
++;
1317 #ifdef CONFIG_HARD_PPS
1318 if ((info
->flags
& ASYNC_HARDPPS_CD
) &&
1319 (status
& MISCSTATUS_DCD_LATCHED
))
1323 if (status
& MISCSTATUS_CTS_LATCHED
)
1325 if ((info
->cts_chkcount
)++ >= IO_PIN_SHUTDOWN_LIMIT
)
1326 usc_DisablestatusIrqs(info
,SICR_CTS
);
1328 if ( status
& MISCSTATUS_CTS
)
1329 info
->input_signal_events
.cts_up
++;
1331 info
->input_signal_events
.cts_down
++;
1333 wake_up_interruptible(&info
->status_event_wait_q
);
1334 wake_up_interruptible(&info
->event_wait_q
);
1336 if ( (info
->flags
& ASYNC_CHECK_CD
) &&
1337 (status
& MISCSTATUS_DCD_LATCHED
) ) {
1338 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1339 printk("%s CD now %s...", info
->device_name
,
1340 (status
& MISCSTATUS_DCD
) ? "on" : "off");
1341 if (status
& MISCSTATUS_DCD
)
1342 wake_up_interruptible(&info
->open_wait
);
1343 else if (!((info
->flags
& ASYNC_CALLOUT_ACTIVE
) &&
1344 (info
->flags
& ASYNC_CALLOUT_NOHUP
))) {
1345 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1346 printk("doing serial hangup...");
1348 tty_hangup(info
->tty
);
1352 if ( (info
->flags
& ASYNC_CTS_FLOW
) &&
1353 (status
& MISCSTATUS_CTS_LATCHED
) ) {
1354 if (info
->tty
->hw_stopped
) {
1355 if (status
& MISCSTATUS_CTS
) {
1356 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1357 printk("CTS tx start...");
1359 info
->tty
->hw_stopped
= 0;
1360 usc_start_transmitter(info
);
1361 info
->pending_bh
|= BH_TRANSMIT
;
1365 if (!(status
& MISCSTATUS_CTS
)) {
1366 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1367 printk("CTS tx stop...");
1369 info
->tty
->hw_stopped
= 1;
1370 usc_stop_transmitter(info
);
1376 info
->pending_bh
|= BH_STATUS
;
1378 /* for diagnostics set IRQ flag */
1379 if ( status
& MISCSTATUS_TXC_LATCHED
){
1380 usc_OutReg( info
, SICR
,
1381 (unsigned short)(usc_InReg(info
,SICR
) & ~(SICR_TXC_ACTIVE
+SICR_TXC_INACTIVE
)) );
1382 usc_UnlatchIostatusBits( info
, MISCSTATUS_TXC_LATCHED
);
1383 info
->irq_occurred
= 1;
1386 } /* end of mgsl_isr_io_pin() */
1388 /* mgsl_isr_transmit_data()
1390 * Service a transmit data interrupt (async mode only).
1392 * Arguments: info pointer to device instance data
1393 * Return Value: None
1395 void mgsl_isr_transmit_data( struct mgsl_struct
*info
)
1397 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1398 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1399 __FILE__
,__LINE__
,info
->xmit_cnt
);
1401 usc_ClearIrqPendingBits( info
, TRANSMIT_DATA
);
1403 if (info
->tty
->stopped
|| info
->tty
->hw_stopped
) {
1404 usc_stop_transmitter(info
);
1408 if ( info
->xmit_cnt
)
1409 usc_load_txfifo( info
);
1411 info
->tx_active
= 0;
1413 if (info
->xmit_cnt
< WAKEUP_CHARS
)
1414 info
->pending_bh
|= BH_TRANSMIT
;
1416 } /* end of mgsl_isr_transmit_data() */
1418 /* mgsl_isr_receive_data()
1420 * Service a receive data interrupt. This occurs
1421 * when operating in asynchronous interrupt transfer mode.
1422 * The receive data FIFO is flushed to the receive data buffers.
1424 * Arguments: info pointer to device instance data
1425 * Return Value: None
1427 void mgsl_isr_receive_data( struct mgsl_struct
*info
)
1431 unsigned char DataByte
;
1432 struct tty_struct
*tty
= info
->tty
;
1433 struct mgsl_icount
*icount
= &info
->icount
;
1435 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1436 printk("%s(%d):mgsl_isr_receive_data\n",
1439 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
);
1441 /* select FIFO status for RICR readback */
1442 usc_RCmd( info
, RCmd_SelectRicrRxFifostatus
);
1444 /* clear the Wordstatus bit so that status readback */
1445 /* only reflects the status of this byte */
1446 usc_OutReg( info
, RICR
+LSBONLY
, (u16
)(usc_InReg(info
, RICR
+LSBONLY
) & ~BIT3
));
1448 /* flush the receive FIFO */
1450 while( (Fifocount
= (usc_InReg(info
,RICR
) >> 8)) ) {
1451 /* read one byte from RxFIFO */
1452 outw( (inw(info
->io_base
+ CCAR
) & 0x0780) | (RDR
+LSBONLY
),
1453 info
->io_base
+ CCAR
);
1454 DataByte
= inb( info
->io_base
+ CCAR
);
1456 /* get the status of the received byte */
1457 status
= usc_InReg(info
, RCSR
);
1458 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1459 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) )
1460 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
1462 if (tty
->flip
.count
>= TTY_FLIPBUF_SIZE
)
1465 *tty
->flip
.char_buf_ptr
= DataByte
;
1468 *tty
->flip
.flag_buf_ptr
= 0;
1469 if ( status
& (RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
+
1470 RXSTATUS_OVERRUN
+ RXSTATUS_BREAK_RECEIVED
) ) {
1471 printk("rxerr=%04X\n",status
);
1472 /* update error statistics */
1473 if ( status
& RXSTATUS_BREAK_RECEIVED
) {
1474 status
&= ~(RXSTATUS_FRAMING_ERROR
+ RXSTATUS_PARITY_ERROR
);
1476 } else if (status
& RXSTATUS_PARITY_ERROR
)
1478 else if (status
& RXSTATUS_FRAMING_ERROR
)
1480 else if (status
& RXSTATUS_OVERRUN
) {
1481 /* must issue purge fifo cmd before */
1482 /* 16C32 accepts more receive chars */
1483 usc_RTCmd(info
,RTCmd_PurgeRxFifo
);
1487 /* discard char if tty control flags say so */
1488 if (status
& info
->ignore_status_mask
)
1491 status
&= info
->read_status_mask
;
1493 if (status
& RXSTATUS_BREAK_RECEIVED
) {
1494 *tty
->flip
.flag_buf_ptr
= TTY_BREAK
;
1495 if (info
->flags
& ASYNC_SAK
)
1497 } else if (status
& RXSTATUS_PARITY_ERROR
)
1498 *tty
->flip
.flag_buf_ptr
= TTY_PARITY
;
1499 else if (status
& RXSTATUS_FRAMING_ERROR
)
1500 *tty
->flip
.flag_buf_ptr
= TTY_FRAME
;
1501 if (status
& RXSTATUS_OVERRUN
) {
1502 /* Overrun is special, since it's
1503 * reported immediately, and doesn't
1504 * affect the current character
1506 if (tty
->flip
.count
< TTY_FLIPBUF_SIZE
) {
1508 tty
->flip
.flag_buf_ptr
++;
1509 tty
->flip
.char_buf_ptr
++;
1510 *tty
->flip
.flag_buf_ptr
= TTY_OVERRUN
;
1513 } /* end of if (error) */
1515 tty
->flip
.flag_buf_ptr
++;
1516 tty
->flip
.char_buf_ptr
++;
1520 if ( debug_level
>= DEBUG_LEVEL_ISR
) {
1521 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1522 __FILE__
,__LINE__
,tty
->flip
.count
);
1523 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1524 __FILE__
,__LINE__
,icount
->rx
,icount
->brk
,
1525 icount
->parity
,icount
->frame
,icount
->overrun
);
1528 if ( tty
->flip
.count
)
1529 tty_flip_buffer_push(tty
);
1534 * Service a miscellaneos interrupt source.
1536 * Arguments: info pointer to device extension (instance data)
1537 * Return Value: None
1539 void mgsl_isr_misc( struct mgsl_struct
*info
)
1541 u16 status
= usc_InReg( info
, MISR
);
1543 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1544 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1545 __FILE__
,__LINE__
,status
);
1547 usc_ClearIrqPendingBits( info
, MISC
);
1548 usc_UnlatchMiscstatusBits( info
, status
);
1550 } /* end of mgsl_isr_misc() */
1554 * Services undefined interrupt vectors from the
1555 * USC. (hence this function SHOULD never be called)
1557 * Arguments: info pointer to device extension (instance data)
1558 * Return Value: None
1560 void mgsl_isr_null( struct mgsl_struct
*info
)
1563 } /* end of mgsl_isr_null() */
1565 /* mgsl_isr_receive_dma()
1567 * Service a receive DMA channel interrupt.
1568 * For this driver there are two sources of receive DMA interrupts
1569 * as identified in the Receive DMA mode Register (RDMR):
1571 * BIT3 EOA/EOL End of List, all receive buffers in receive
1572 * buffer list have been filled (no more free buffers
1573 * available). The DMA controller has shut down.
1575 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1576 * DMA buffer is terminated in response to completion
1577 * of a good frame or a frame with errors. The status
1578 * of the frame is stored in the buffer entry in the
1579 * list of receive buffer entries.
1581 * Arguments: info pointer to device instance data
1582 * Return Value: None
1584 void mgsl_isr_receive_dma( struct mgsl_struct
*info
)
1588 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1589 usc_OutDmaReg( info
, CDIR
, BIT9
+BIT1
);
1591 /* Read the receive DMA status to identify interrupt type. */
1592 /* This also clears the status bits. */
1593 status
= usc_InDmaReg( info
, RDMR
);
1595 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1596 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1597 __FILE__
,__LINE__
,info
->device_name
,status
);
1599 info
->pending_bh
|= BH_RECEIVE
;
1601 if ( status
& BIT3
) {
1602 info
->rx_overflow
= 1;
1603 info
->icount
.buf_overrun
++;
1606 } /* end of mgsl_isr_receive_dma() */
1610 * Interrupt service routine entry point.
1614 * irq interrupt number that caused interrupt
1615 * dev_id device ID supplied during interrupt registration
1616 * regs interrupted processor context
1618 * Return Value: None
1620 static void mgsl_interrupt(int irq
, void *dev_id
, struct pt_regs
* regs
)
1622 struct mgsl_struct
* info
;
1626 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1627 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1628 __FILE__
,__LINE__
,irq
);
1630 info
= (struct mgsl_struct
*)dev_id
;
1634 spin_lock(&info
->irq_spinlock
);
1637 /* Read the interrupt vectors from hardware. */
1638 UscVector
= usc_InReg(info
, IVR
) >> 9;
1639 DmaVector
= usc_InDmaReg(info
, DIVR
);
1641 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1642 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1643 __FILE__
,__LINE__
,info
->device_name
,UscVector
,DmaVector
);
1645 if ( !UscVector
&& !DmaVector
)
1648 /* Dispatch interrupt vector */
1650 (*UscIsrTable
[UscVector
])(info
);
1652 mgsl_isr_receive_dma(info
);
1654 if ( info
->isr_overflow
) {
1655 printk(KERN_ERR
"%s(%d):%s isr overflow irq=%d\n",
1656 __FILE__
,__LINE__
,info
->device_name
, irq
);
1657 usc_DisableMasterIrqBit(info
);
1658 usc_DisableDmaInterrupts(info
,DICR_MASTER
);
1663 /* Request bottom half processing if there's something
1664 * for it to do and the bh is not already running
1667 if ( info
->pending_bh
&& !info
->bh_running
&& !info
->bh_requested
) {
1668 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1669 printk("%s(%d):%s queueing bh task.\n",
1670 __FILE__
,__LINE__
,info
->device_name
);
1671 queue_task(&info
->task
, &tq_immediate
);
1672 mark_bh(IMMEDIATE_BH
);
1673 info
->bh_requested
= 1;
1676 spin_unlock(&info
->irq_spinlock
);
1678 if ( debug_level
>= DEBUG_LEVEL_ISR
)
1679 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1680 __FILE__
,__LINE__
,irq
);
1682 } /* end of mgsl_interrupt() */
1686 * Initialize and start device.
1688 * Arguments: info pointer to device instance data
1689 * Return Value: 0 if success, otherwise error code
1691 static int startup(struct mgsl_struct
* info
)
1695 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1696 printk("%s(%d):mgsl_startup(%s)\n",__FILE__
,__LINE__
,info
->device_name
);
1698 if (info
->flags
& ASYNC_INITIALIZED
)
1701 if (!info
->xmit_buf
) {
1702 /* allocate a page of memory for a transmit buffer */
1703 info
->xmit_buf
= (unsigned char *)get_free_page(GFP_KERNEL
);
1704 if (!info
->xmit_buf
) {
1705 printk(KERN_ERR
"%s(%d):%s can't allocate transmit buffer\n",
1706 __FILE__
,__LINE__
,info
->device_name
);
1711 info
->pending_bh
= 0;
1713 init_timer(&info
->tx_timer
);
1714 info
->tx_timer
.data
= (unsigned long)info
;
1715 info
->tx_timer
.function
= mgsl_tx_timeout
;
1717 /* Allocate and claim adapter resources */
1718 retval
= mgsl_claim_resources(info
);
1720 /* perform existance check and diagnostics */
1722 retval
= mgsl_adapter_test(info
);
1725 if (capable(CAP_SYS_ADMIN
) && info
->tty
)
1726 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1727 mgsl_release_resources(info
);
1731 /* program hardware for current parameters */
1732 mgsl_change_params(info
);
1735 clear_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1737 info
->flags
|= ASYNC_INITIALIZED
;
1741 } /* end of startup() */
1745 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1747 * Arguments: info pointer to device instance data
1748 * Return Value: None
1750 static void shutdown(struct mgsl_struct
* info
)
1752 unsigned long flags
;
1754 if (!(info
->flags
& ASYNC_INITIALIZED
))
1757 if (debug_level
>= DEBUG_LEVEL_INFO
)
1758 printk("%s(%d):mgsl_shutdown(%s)\n",
1759 __FILE__
,__LINE__
, info
->device_name
);
1761 /* clear status wait queue because status changes */
1762 /* can't happen after shutting down the hardware */
1763 wake_up_interruptible(&info
->status_event_wait_q
);
1764 wake_up_interruptible(&info
->event_wait_q
);
1766 del_timer(&info
->tx_timer
);
1768 if (info
->xmit_buf
) {
1769 free_page((unsigned long) info
->xmit_buf
);
1773 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1774 usc_DisableMasterIrqBit(info
);
1775 usc_stop_receiver(info
);
1776 usc_stop_transmitter(info
);
1777 usc_DisableInterrupts(info
,RECEIVE_DATA
+ RECEIVE_STATUS
+
1778 TRANSMIT_DATA
+ TRANSMIT_STATUS
+ IO_PIN
+ MISC
);
1779 usc_DisableDmaInterrupts(info
,DICR_MASTER
+ DICR_TRANSMIT
+ DICR_RECEIVE
);
1781 /* Disable DMAEN (Port 7, Bit 14) */
1782 /* This disconnects the DMA request signal from the ISA bus */
1783 /* on the ISA adapter. This has no effect for the PCI adapter */
1784 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) | BIT14
));
1786 /* Disable INTEN (Port 6, Bit12) */
1787 /* This disconnects the IRQ request signal to the ISA bus */
1788 /* on the ISA adapter. This has no effect for the PCI adapter */
1789 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) | BIT12
));
1791 if (!info
->tty
|| info
->tty
->termios
->c_cflag
& HUPCL
) {
1792 info
->serial_signals
&= ~(SerialSignal_DTR
+ SerialSignal_RTS
);
1793 usc_set_serial_signals(info
);
1796 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1798 mgsl_release_resources(info
);
1801 set_bit(TTY_IO_ERROR
, &info
->tty
->flags
);
1803 info
->flags
&= ~ASYNC_INITIALIZED
;
1805 } /* end of shutdown() */
1807 static void mgsl_program_hw(struct mgsl_struct
*info
)
1809 unsigned long flags
;
1811 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1813 usc_stop_receiver(info
);
1814 usc_stop_transmitter(info
);
1815 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
1817 if (info
->params
.mode
== MGSL_MODE_HDLC
|| info
->netcount
)
1818 usc_set_sync_mode(info
);
1820 usc_set_async_mode(info
);
1822 usc_set_serial_signals(info
);
1824 info
->dcd_chkcount
= 0;
1825 info
->cts_chkcount
= 0;
1826 info
->ri_chkcount
= 0;
1827 info
->dsr_chkcount
= 0;
1829 usc_EnableStatusIrqs(info
,SICR_CTS
+SICR_DSR
+SICR_DCD
+SICR_RI
);
1830 usc_EnableInterrupts(info
, IO_PIN
);
1831 usc_get_serial_signals(info
);
1833 if (info
->netcount
|| info
->tty
->termios
->c_cflag
& CREAD
)
1834 usc_start_receiver(info
);
1836 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1839 /* Reconfigure adapter based on new parameters
1841 static void mgsl_change_params(struct mgsl_struct
*info
)
1846 if (!info
->tty
|| !info
->tty
->termios
)
1849 if (debug_level
>= DEBUG_LEVEL_INFO
)
1850 printk("%s(%d):mgsl_change_params(%s)\n",
1851 __FILE__
,__LINE__
, info
->device_name
);
1853 cflag
= info
->tty
->termios
->c_cflag
;
1855 /* if B0 rate (hangup) specified then negate DTR and RTS */
1856 /* otherwise assert DTR and RTS */
1858 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
1860 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
1862 /* byte size and parity */
1864 switch (cflag
& CSIZE
) {
1865 case CS5
: info
->params
.data_bits
= 5; break;
1866 case CS6
: info
->params
.data_bits
= 6; break;
1867 case CS7
: info
->params
.data_bits
= 7; break;
1868 case CS8
: info
->params
.data_bits
= 8; break;
1869 /* Never happens, but GCC is too dumb to figure it out */
1870 default: info
->params
.data_bits
= 7; break;
1874 info
->params
.stop_bits
= 2;
1876 info
->params
.stop_bits
= 1;
1878 info
->params
.parity
= ASYNC_PARITY_NONE
;
1879 if (cflag
& PARENB
) {
1881 info
->params
.parity
= ASYNC_PARITY_ODD
;
1883 info
->params
.parity
= ASYNC_PARITY_EVEN
;
1886 info
->params
.parity
= ASYNC_PARITY_SPACE
;
1890 /* calculate number of jiffies to transmit a full
1891 * FIFO (32 bytes) at specified data rate
1893 bits_per_char
= info
->params
.data_bits
+
1894 info
->params
.stop_bits
+ 1;
1896 /* if port data rate is set to 460800 or less then
1897 * allow tty settings to override, otherwise keep the
1898 * current data rate.
1900 if (info
->params
.data_rate
<= 460800)
1901 info
->params
.data_rate
= tty_get_baud_rate(info
->tty
);
1903 if ( info
->params
.data_rate
) {
1904 info
->timeout
= (32*HZ
*bits_per_char
) /
1905 info
->params
.data_rate
;
1907 info
->timeout
+= HZ
/50; /* Add .02 seconds of slop */
1909 if (cflag
& CRTSCTS
)
1910 info
->flags
|= ASYNC_CTS_FLOW
;
1912 info
->flags
&= ~ASYNC_CTS_FLOW
;
1915 info
->flags
&= ~ASYNC_CHECK_CD
;
1917 info
->flags
|= ASYNC_CHECK_CD
;
1919 /* process tty input control flags */
1921 info
->read_status_mask
= RXSTATUS_OVERRUN
;
1922 if (I_INPCK(info
->tty
))
1923 info
->read_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1924 if (I_BRKINT(info
->tty
) || I_PARMRK(info
->tty
))
1925 info
->read_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1927 if (I_IGNPAR(info
->tty
))
1928 info
->ignore_status_mask
|= RXSTATUS_PARITY_ERROR
| RXSTATUS_FRAMING_ERROR
;
1929 if (I_IGNBRK(info
->tty
)) {
1930 info
->ignore_status_mask
|= RXSTATUS_BREAK_RECEIVED
;
1931 /* If ignoring parity and break indicators, ignore
1932 * overruns too. (For real raw support).
1934 if (I_IGNPAR(info
->tty
))
1935 info
->ignore_status_mask
|= RXSTATUS_OVERRUN
;
1938 mgsl_program_hw(info
);
1940 } /* end of mgsl_change_params() */
1944 * Add a character to the transmit buffer.
1946 * Arguments: tty pointer to tty information structure
1947 * ch character to add to transmit buffer
1949 * Return Value: None
1951 static void mgsl_put_char(struct tty_struct
*tty
, unsigned char ch
)
1953 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1954 unsigned long flags
;
1956 if ( debug_level
>= DEBUG_LEVEL_INFO
) {
1957 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
1958 __FILE__
,__LINE__
,ch
,info
->device_name
);
1961 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_put_char"))
1964 if (!tty
|| !info
->xmit_buf
)
1967 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
1969 if ( (info
->params
.mode
!= MGSL_MODE_HDLC
) ||
1970 !info
->tx_active
) {
1972 if (info
->xmit_cnt
< SERIAL_XMIT_SIZE
- 1) {
1973 info
->xmit_buf
[info
->xmit_head
++] = ch
;
1974 info
->xmit_head
&= SERIAL_XMIT_SIZE
-1;
1979 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
1981 } /* end of mgsl_put_char() */
1983 /* mgsl_flush_chars()
1985 * Enable transmitter so remaining characters in the
1986 * transmit buffer are sent.
1988 * Arguments: tty pointer to tty information structure
1989 * Return Value: None
1991 static void mgsl_flush_chars(struct tty_struct
*tty
)
1993 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
1994 unsigned long flags
;
1996 if ( debug_level
>= DEBUG_LEVEL_INFO
)
1997 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
1998 __FILE__
,__LINE__
,info
->device_name
,info
->xmit_cnt
);
2000 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_flush_chars"))
2003 if (info
->xmit_cnt
<= 0 || tty
->stopped
|| tty
->hw_stopped
||
2007 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2008 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2009 __FILE__
,__LINE__
,info
->device_name
);
2011 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2013 if (!info
->tx_active
) {
2014 if ( (info
->params
.mode
== MGSL_MODE_HDLC
) &&
2016 /* operating in synchronous (frame oriented) mode */
2017 /* copy data from circular xmit_buf to */
2018 /* transmit DMA buffer. */
2019 mgsl_load_tx_dma_buffer(info
,
2020 info
->xmit_buf
,info
->xmit_cnt
);
2022 usc_start_transmitter(info
);
2025 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2027 } /* end of mgsl_flush_chars() */
2031 * Send a block of data
2035 * tty pointer to tty information structure
2036 * from_user flag: 1 = from user process
2037 * buf pointer to buffer containing send data
2038 * count size of send data in bytes
2040 * Return Value: number of characters written
2042 static int mgsl_write(struct tty_struct
* tty
, int from_user
,
2043 const unsigned char *buf
, int count
)
2045 int c
, ret
= 0, err
;
2046 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2047 unsigned long flags
;
2049 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2050 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2051 __FILE__
,__LINE__
,info
->device_name
,count
);
2053 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_write"))
2056 if (!tty
|| !info
->xmit_buf
|| !tmp_buf
)
2059 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2060 /* operating in synchronous (frame oriented) mode */
2062 if (info
->tx_active
) {
2063 ret
= 0; goto cleanup
;
2066 /* if operating in HDLC LoopMode and the adapter */
2067 /* has yet to be inserted into the loop, we can't */
2070 if ( (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) &&
2071 !usc_loopmode_active(info
) )
2077 if ( info
->xmit_cnt
) {
2078 /* Send accumulated from send_char() calls */
2079 /* as frame and wait before accepting more data. */
2082 /* copy data from circular xmit_buf to */
2083 /* transmit DMA buffer. */
2084 mgsl_load_tx_dma_buffer(info
,
2085 info
->xmit_buf
,info
->xmit_cnt
);
2086 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2087 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2088 __FILE__
,__LINE__
,info
->device_name
);
2090 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2091 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2092 __FILE__
,__LINE__
,info
->device_name
);
2094 info
->xmit_cnt
= count
;
2097 COPY_FROM_USER(err
,tmp_buf
, buf
, count
);
2099 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2100 printk( "%s(%d):mgsl_write(%s) sync user buf copy failed\n",
2101 __FILE__
,__LINE__
,info
->device_name
);
2104 mgsl_load_tx_dma_buffer(info
,tmp_buf
,count
);
2108 mgsl_load_tx_dma_buffer(info
,buf
,count
);
2115 MIN(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2116 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2120 COPY_FROM_USER(err
,tmp_buf
, buf
, c
);
2127 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2128 c
= MIN(c
, MIN(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2129 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2130 memcpy(info
->xmit_buf
+ info
->xmit_head
, tmp_buf
, c
);
2131 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2132 (SERIAL_XMIT_SIZE
-1));
2133 info
->xmit_cnt
+= c
;
2134 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2142 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2144 MIN(SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1,
2145 SERIAL_XMIT_SIZE
- info
->xmit_head
));
2147 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2150 memcpy(info
->xmit_buf
+ info
->xmit_head
, buf
, c
);
2151 info
->xmit_head
= ((info
->xmit_head
+ c
) &
2152 (SERIAL_XMIT_SIZE
-1));
2153 info
->xmit_cnt
+= c
;
2154 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2162 if (info
->xmit_cnt
&& !tty
->stopped
&& !tty
->hw_stopped
) {
2163 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2164 if (!info
->tx_active
)
2165 usc_start_transmitter(info
);
2166 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2169 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2170 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2171 __FILE__
,__LINE__
,info
->device_name
,ret
);
2175 } /* end of mgsl_write() */
2177 /* mgsl_write_room()
2179 * Return the count of free bytes in transmit buffer
2181 * Arguments: tty pointer to tty info structure
2182 * Return Value: None
2184 static int mgsl_write_room(struct tty_struct
*tty
)
2186 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2189 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_write_room"))
2191 ret
= SERIAL_XMIT_SIZE
- info
->xmit_cnt
- 1;
2195 if (debug_level
>= DEBUG_LEVEL_INFO
)
2196 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2197 __FILE__
,__LINE__
, info
->device_name
,ret
);
2199 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2200 /* operating in synchronous (frame oriented) mode */
2201 if ( info
->tx_active
)
2204 return HDLC_MAX_FRAME_SIZE
;
2209 } /* end of mgsl_write_room() */
2211 /* mgsl_chars_in_buffer()
2213 * Return the count of bytes in transmit buffer
2215 * Arguments: tty pointer to tty info structure
2216 * Return Value: None
2218 static int mgsl_chars_in_buffer(struct tty_struct
*tty
)
2220 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2222 if (debug_level
>= DEBUG_LEVEL_INFO
)
2223 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2224 __FILE__
,__LINE__
, info
->device_name
);
2226 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_chars_in_buffer"))
2229 if (debug_level
>= DEBUG_LEVEL_INFO
)
2230 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2231 __FILE__
,__LINE__
, info
->device_name
,info
->xmit_cnt
);
2233 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
2234 /* operating in synchronous (frame oriented) mode */
2235 if ( info
->tx_active
)
2236 return info
->tx_buffer_list
[0].rcc
;
2241 return info
->xmit_cnt
;
2242 } /* end of mgsl_chars_in_buffer() */
2244 /* mgsl_flush_buffer()
2246 * Discard all data in the send buffer
2248 * Arguments: tty pointer to tty info structure
2249 * Return Value: None
2251 static void mgsl_flush_buffer(struct tty_struct
*tty
)
2253 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2254 unsigned long flags
;
2256 if (debug_level
>= DEBUG_LEVEL_INFO
)
2257 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2258 __FILE__
,__LINE__
, info
->device_name
);
2260 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_flush_buffer"))
2263 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2264 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
2265 del_timer(&info
->tx_timer
);
2266 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2268 wake_up_interruptible(&tty
->write_wait
);
2269 if ((tty
->flags
& (1 << TTY_DO_WRITE_WAKEUP
)) &&
2270 tty
->ldisc
.write_wakeup
)
2271 (tty
->ldisc
.write_wakeup
)(tty
);
2273 } /* end of mgsl_flush_buffer() */
2275 /* mgsl_send_xchar()
2277 * Send a high-priority XON/XOFF character
2279 * Arguments: tty pointer to tty info structure
2280 * ch character to send
2281 * Return Value: None
2283 static void mgsl_send_xchar(struct tty_struct
*tty
, char ch
)
2285 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2286 unsigned long flags
;
2288 if (debug_level
>= DEBUG_LEVEL_INFO
)
2289 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2290 __FILE__
,__LINE__
, info
->device_name
, ch
);
2292 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_send_xchar"))
2297 /* Make sure transmit interrupts are on */
2298 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2299 if (!info
->tx_enabled
)
2300 usc_start_transmitter(info
);
2301 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2303 } /* end of mgsl_send_xchar() */
2307 * Signal remote device to throttle send data (our receive data)
2309 * Arguments: tty pointer to tty info structure
2310 * Return Value: None
2312 static void mgsl_throttle(struct tty_struct
* tty
)
2314 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2315 unsigned long flags
;
2317 if (debug_level
>= DEBUG_LEVEL_INFO
)
2318 printk("%s(%d):mgsl_throttle(%s) entry\n",
2319 __FILE__
,__LINE__
, info
->device_name
);
2321 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_throttle"))
2325 mgsl_send_xchar(tty
, STOP_CHAR(tty
));
2327 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2328 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2329 info
->serial_signals
&= ~SerialSignal_RTS
;
2330 usc_set_serial_signals(info
);
2331 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2333 } /* end of mgsl_throttle() */
2335 /* mgsl_unthrottle()
2337 * Signal remote device to stop throttling send data (our receive data)
2339 * Arguments: tty pointer to tty info structure
2340 * Return Value: None
2342 static void mgsl_unthrottle(struct tty_struct
* tty
)
2344 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
2345 unsigned long flags
;
2347 if (debug_level
>= DEBUG_LEVEL_INFO
)
2348 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2349 __FILE__
,__LINE__
, info
->device_name
);
2351 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_unthrottle"))
2358 mgsl_send_xchar(tty
, START_CHAR(tty
));
2361 if (tty
->termios
->c_cflag
& CRTSCTS
) {
2362 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2363 info
->serial_signals
|= SerialSignal_RTS
;
2364 usc_set_serial_signals(info
);
2365 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2368 } /* end of mgsl_unthrottle() */
2372 * get the current serial parameters information
2374 * Arguments: info pointer to device instance data
2375 * user_icount pointer to buffer to hold returned stats
2377 * Return Value: 0 if success, otherwise error code
2379 static int mgsl_get_stats(struct mgsl_struct
* info
, struct mgsl_icount
*user_icount
)
2383 if (debug_level
>= DEBUG_LEVEL_INFO
)
2384 printk("%s(%d):mgsl_get_params(%s)\n",
2385 __FILE__
,__LINE__
, info
->device_name
);
2387 COPY_TO_USER(err
,user_icount
, &info
->icount
, sizeof(struct mgsl_icount
));
2389 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2390 printk( "%s(%d):mgsl_get_stats(%s) user buffer copy failed\n",
2391 __FILE__
,__LINE__
,info
->device_name
);
2397 } /* end of mgsl_get_stats() */
2399 /* mgsl_get_params()
2401 * get the current serial parameters information
2403 * Arguments: info pointer to device instance data
2404 * user_params pointer to buffer to hold returned params
2406 * Return Value: 0 if success, otherwise error code
2408 static int mgsl_get_params(struct mgsl_struct
* info
, MGSL_PARAMS
*user_params
)
2411 if (debug_level
>= DEBUG_LEVEL_INFO
)
2412 printk("%s(%d):mgsl_get_params(%s)\n",
2413 __FILE__
,__LINE__
, info
->device_name
);
2415 COPY_TO_USER(err
,user_params
, &info
->params
, sizeof(MGSL_PARAMS
));
2417 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2418 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2419 __FILE__
,__LINE__
,info
->device_name
);
2425 } /* end of mgsl_get_params() */
2427 /* mgsl_set_params()
2429 * set the serial parameters
2433 * info pointer to device instance data
2434 * new_params user buffer containing new serial params
2436 * Return Value: 0 if success, otherwise error code
2438 static int mgsl_set_params(struct mgsl_struct
* info
, MGSL_PARAMS
*new_params
)
2440 unsigned long flags
;
2441 MGSL_PARAMS tmp_params
;
2444 if (debug_level
>= DEBUG_LEVEL_INFO
)
2445 printk("%s(%d):mgsl_set_params %s\n", __FILE__
,__LINE__
,
2446 info
->device_name
);
2447 COPY_FROM_USER(err
,&tmp_params
, new_params
, sizeof(MGSL_PARAMS
));
2449 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2450 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2451 __FILE__
,__LINE__
,info
->device_name
);
2455 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2456 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
2457 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2459 mgsl_change_params(info
);
2463 } /* end of mgsl_set_params() */
2465 /* mgsl_get_txidle()
2467 * get the current transmit idle mode
2469 * Arguments: info pointer to device instance data
2470 * idle_mode pointer to buffer to hold returned idle mode
2472 * Return Value: 0 if success, otherwise error code
2474 static int mgsl_get_txidle(struct mgsl_struct
* info
, int*idle_mode
)
2478 if (debug_level
>= DEBUG_LEVEL_INFO
)
2479 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2480 __FILE__
,__LINE__
, info
->device_name
, info
->idle_mode
);
2482 COPY_TO_USER(err
,idle_mode
, &info
->idle_mode
, sizeof(int));
2484 if ( debug_level
>= DEBUG_LEVEL_INFO
)
2485 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2486 __FILE__
,__LINE__
,info
->device_name
);
2492 } /* end of mgsl_get_txidle() */
2494 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2496 * Arguments: info pointer to device instance data
2497 * idle_mode new idle mode
2499 * Return Value: 0 if success, otherwise error code
2501 static int mgsl_set_txidle(struct mgsl_struct
* info
, int idle_mode
)
2503 unsigned long flags
;
2505 if (debug_level
>= DEBUG_LEVEL_INFO
)
2506 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__
,__LINE__
,
2507 info
->device_name
, idle_mode
);
2509 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2510 info
->idle_mode
= idle_mode
;
2511 usc_set_txidle( info
);
2512 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2515 } /* end of mgsl_set_txidle() */
2519 * enable or disable the transmitter
2523 * info pointer to device instance data
2524 * enable 1 = enable, 0 = disable
2526 * Return Value: 0 if success, otherwise error code
2528 static int mgsl_txenable(struct mgsl_struct
* info
, int enable
)
2530 unsigned long flags
;
2532 if (debug_level
>= DEBUG_LEVEL_INFO
)
2533 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__
,__LINE__
,
2534 info
->device_name
, enable
);
2536 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2538 if ( !info
->tx_enabled
) {
2540 usc_start_transmitter(info
);
2541 /*--------------------------------------------------
2542 * if HDLC/SDLC Loop mode, attempt to insert the
2543 * station in the 'loop' by setting CMR:13. Upon
2544 * receipt of the next GoAhead (RxAbort) sequence,
2545 * the OnLoop indicator (CCSR:7) should go active
2546 * to indicate that we are on the loop
2547 *--------------------------------------------------*/
2548 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2549 usc_loopmode_insert_request( info
);
2552 if ( info
->tx_enabled
)
2553 usc_stop_transmitter(info
);
2555 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2558 } /* end of mgsl_txenable() */
2560 /* mgsl_txabort() abort send HDLC frame
2562 * Arguments: info pointer to device instance data
2563 * Return Value: 0 if success, otherwise error code
2565 static int mgsl_txabort(struct mgsl_struct
* info
)
2567 unsigned long flags
;
2569 if (debug_level
>= DEBUG_LEVEL_INFO
)
2570 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__
,__LINE__
,
2573 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2574 if ( info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
)
2576 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
2577 usc_loopmode_cancel_transmit( info
);
2579 usc_TCmd(info
,TCmd_SendAbort
);
2581 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2584 } /* end of mgsl_txabort() */
2586 /* mgsl_rxenable() enable or disable the receiver
2588 * Arguments: info pointer to device instance data
2589 * enable 1 = enable, 0 = disable
2590 * Return Value: 0 if success, otherwise error code
2592 static int mgsl_rxenable(struct mgsl_struct
* info
, int enable
)
2594 unsigned long flags
;
2596 if (debug_level
>= DEBUG_LEVEL_INFO
)
2597 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__
,__LINE__
,
2598 info
->device_name
, enable
);
2600 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2602 if ( !info
->rx_enabled
)
2603 usc_start_receiver(info
);
2605 if ( info
->rx_enabled
)
2606 usc_stop_receiver(info
);
2608 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2611 } /* end of mgsl_rxenable() */
2613 /* mgsl_wait_event() wait for specified event to occur
2615 * Arguments: info pointer to device instance data
2616 * mask pointer to bitmask of events to wait for
2617 * Return Value: 0 if successful and bit mask updated with
2618 * of events triggerred,
2619 * otherwise error code
2621 static int mgsl_wait_event(struct mgsl_struct
* info
, int * mask_ptr
)
2623 unsigned long flags
;
2627 struct mgsl_icount cprev
, cnow
;
2630 struct _input_signal_events signal_events_prev
, signal_events_now
;
2632 COPY_FROM_USER(rc
,&mask
, mask_ptr
, sizeof(int));
2637 if (debug_level
>= DEBUG_LEVEL_INFO
)
2638 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__
,__LINE__
,
2639 info
->device_name
, mask
);
2641 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2643 usc_get_serial_signals(info
);
2644 s
= info
->serial_signals
;
2646 /* note the counters on entry */
2647 cprev
= info
->icount
;
2648 signal_events_prev
= info
->input_signal_events
;
2650 if (mask
& MgslEvent_ExitHuntMode
) {
2651 /* enable exit hunt mode IRQ */
2652 regval
= usc_InReg(info
,RICR
);
2653 if (!(regval
& RXSTATUS_EXITED_HUNT
))
2654 usc_OutReg(info
, RICR
, regval
| RXSTATUS_EXITED_HUNT
);
2657 if (mask
& MgslEvent_IdleReceived
) {
2658 /* enable idle mode received IRQ */
2659 regval
= usc_InReg(info
,RICR
);
2660 if (!(regval
& RXSTATUS_IDLE_RECEIVED
))
2661 usc_OutReg(info
, RICR
, regval
| RXSTATUS_IDLE_RECEIVED
);
2664 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2666 /* Determine if any user requested events for input signals is currently TRUE */
2668 events
|= (mask
& ((s
& SerialSignal_DSR
) ?
2669 MgslEvent_DsrActive
:MgslEvent_DsrInactive
));
2671 events
|= (mask
& ((s
& SerialSignal_DCD
) ?
2672 MgslEvent_DcdActive
:MgslEvent_DcdInactive
));
2674 events
|= (mask
& ((s
& SerialSignal_CTS
) ?
2675 MgslEvent_CtsActive
:MgslEvent_CtsInactive
));
2677 events
|= (mask
& ((s
& SerialSignal_RI
) ?
2678 MgslEvent_RiActive
:MgslEvent_RiInactive
));
2682 /* sleep until event occurs */
2683 interruptible_sleep_on(&info
->event_wait_q
);
2685 /* see if a signal woke us */
2686 if (signal_pending(current
)) {
2691 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2693 /* get icount and serial signal states */
2694 cnow
= info
->icount
;
2695 signal_events_now
= info
->input_signal_events
;
2696 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2698 if (signal_events_now
.dsr_up
!= signal_events_prev
.dsr_up
&&
2699 mask
& MgslEvent_DsrActive
)
2700 events
|= MgslEvent_DsrActive
;
2702 if (signal_events_now
.dsr_down
!= signal_events_prev
.dsr_down
&&
2703 mask
& MgslEvent_DsrInactive
)
2704 events
|= MgslEvent_DsrInactive
;
2706 if (signal_events_now
.dcd_up
!= signal_events_prev
.dcd_up
&&
2707 mask
& MgslEvent_DcdActive
)
2708 events
|= MgslEvent_DcdActive
;
2710 if (signal_events_now
.dcd_down
!= signal_events_prev
.dcd_down
&&
2711 mask
& MgslEvent_DcdInactive
)
2712 events
|= MgslEvent_DcdInactive
;
2714 if (signal_events_now
.cts_up
!= signal_events_prev
.cts_up
&&
2715 mask
& MgslEvent_CtsActive
)
2716 events
|= MgslEvent_CtsActive
;
2718 if (signal_events_now
.cts_down
!= signal_events_prev
.cts_down
&&
2719 mask
& MgslEvent_CtsInactive
)
2720 events
|= MgslEvent_CtsInactive
;
2722 if (signal_events_now
.ri_up
!= signal_events_prev
.ri_up
&&
2723 mask
& MgslEvent_RiActive
)
2724 events
|= MgslEvent_RiActive
;
2726 if (signal_events_now
.ri_down
!= signal_events_prev
.ri_down
&&
2727 mask
& MgslEvent_RiInactive
)
2728 events
|= MgslEvent_RiInactive
;
2730 if (cnow
.exithunt
!= cprev
.exithunt
)
2731 events
|= (mask
& MgslEvent_ExitHuntMode
);
2733 if (cnow
.rxidle
!= cprev
.rxidle
)
2734 events
|= (mask
& MgslEvent_IdleReceived
);
2737 signal_events_prev
= signal_events_now
;
2740 if (mask
& (MgslEvent_ExitHuntMode
+ MgslEvent_IdleReceived
)) {
2741 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2742 if (!waitqueue_active(&info
->event_wait_q
)) {
2743 /* disable enable exit hunt mode/idle rcvd IRQs */
2744 regval
= usc_InReg(info
,RICR
);
2745 usc_OutReg(info
, RICR
, regval
&
2746 ~(RXSTATUS_EXITED_HUNT
+ RXSTATUS_IDLE_RECEIVED
));
2748 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2752 PUT_USER(rc
, events
, mask_ptr
);
2756 } /* end of mgsl_wait_event() */
2760 * Read the state of the serial control and
2761 * status signals and return to caller.
2763 * Arguments: info pointer to device instance data
2764 * value pointer to int to hold returned info
2766 * Return Value: 0 if success, otherwise error code
2768 static int get_modem_info(struct mgsl_struct
* info
, unsigned int *value
)
2770 unsigned int result
= 0;
2771 unsigned long flags
;
2774 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2775 usc_get_serial_signals(info
);
2776 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2778 if (info
->serial_signals
& SerialSignal_RTS
)
2779 result
|= TIOCM_RTS
;
2780 if (info
->serial_signals
& SerialSignal_DTR
)
2781 result
|= TIOCM_DTR
;
2782 if (info
->serial_signals
& SerialSignal_DCD
)
2783 result
|= TIOCM_CAR
;
2784 if (info
->serial_signals
& SerialSignal_RI
)
2785 result
|= TIOCM_RNG
;
2786 if (info
->serial_signals
& SerialSignal_DSR
)
2787 result
|= TIOCM_DSR
;
2788 if (info
->serial_signals
& SerialSignal_CTS
)
2789 result
|= TIOCM_CTS
;
2791 if (debug_level
>= DEBUG_LEVEL_INFO
)
2792 printk("%s(%d):mgsl_get_modem_info %s value=%08X\n",
2793 __FILE__
,__LINE__
, info
->device_name
, result
);
2795 PUT_USER(err
,result
,value
);
2797 } /* end of get_modem_info() */
2801 * Set the state of the modem control signals (DTR/RTS)
2805 * info pointer to device instance data
2806 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
2807 * TIOCMSET = set/clear signal values
2808 * value bit mask for command
2810 * Return Value: 0 if success, otherwise error code
2812 static int set_modem_info(struct mgsl_struct
* info
, unsigned int cmd
,
2813 unsigned int *value
)
2817 unsigned long flags
;
2819 if (debug_level
>= DEBUG_LEVEL_INFO
)
2820 printk("%s(%d):mgsl_set_modem_info %s\n", __FILE__
,__LINE__
,
2821 info
->device_name
);
2823 GET_USER(error
,arg
,value
);
2829 if (arg
& TIOCM_RTS
)
2830 info
->serial_signals
|= SerialSignal_RTS
;
2831 if (arg
& TIOCM_DTR
)
2832 info
->serial_signals
|= SerialSignal_DTR
;
2835 if (arg
& TIOCM_RTS
)
2836 info
->serial_signals
&= ~SerialSignal_RTS
;
2837 if (arg
& TIOCM_DTR
)
2838 info
->serial_signals
&= ~SerialSignal_DTR
;
2841 if (arg
& TIOCM_RTS
)
2842 info
->serial_signals
|= SerialSignal_RTS
;
2844 info
->serial_signals
&= ~SerialSignal_RTS
;
2846 if (arg
& TIOCM_DTR
)
2847 info
->serial_signals
|= SerialSignal_DTR
;
2849 info
->serial_signals
&= ~SerialSignal_DTR
;
2855 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2856 usc_set_serial_signals(info
);
2857 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2861 } /* end of set_modem_info() */
2863 /* mgsl_break() Set or clear transmit break condition
2865 * Arguments: tty pointer to tty instance data
2866 * break_state -1=set break condition, 0=clear
2867 * Return Value: None
2869 static void mgsl_break(struct tty_struct
*tty
, int break_state
)
2871 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2872 unsigned long flags
;
2874 if (debug_level
>= DEBUG_LEVEL_INFO
)
2875 printk("%s(%d):mgsl_break(%s,%d)\n",
2876 __FILE__
,__LINE__
, info
->device_name
, break_state
);
2878 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_break"))
2881 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2882 if (break_state
== -1)
2883 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) | BIT7
));
2885 usc_OutReg(info
,IOCR
,(u16
)(usc_InReg(info
,IOCR
) & ~BIT7
));
2886 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2888 } /* end of mgsl_break() */
2890 /* mgsl_ioctl() Service an IOCTL request
2894 * tty pointer to tty instance data
2895 * file pointer to associated file object for device
2896 * cmd IOCTL command code
2897 * arg command argument/context
2899 * Return Value: 0 if success, otherwise error code
2901 static int mgsl_ioctl(struct tty_struct
*tty
, struct file
* file
,
2902 unsigned int cmd
, unsigned long arg
)
2904 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
2906 if (debug_level
>= DEBUG_LEVEL_INFO
)
2907 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
2908 info
->device_name
, cmd
);
2910 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_ioctl"))
2913 if ((cmd
!= TIOCGSERIAL
) && (cmd
!= TIOCSSERIAL
) &&
2914 (cmd
!= TIOCMIWAIT
) && (cmd
!= TIOCGICOUNT
)) {
2915 if (tty
->flags
& (1 << TTY_IO_ERROR
))
2919 return mgsl_ioctl_common(info
, cmd
, arg
);
2922 int mgsl_ioctl_common(struct mgsl_struct
*info
, unsigned int cmd
, unsigned long arg
)
2925 struct mgsl_icount cprev
, cnow
; /* kernel counter temps */
2926 struct serial_icounter_struct
*p_cuser
; /* user space */
2927 unsigned long flags
;
2931 return get_modem_info(info
, (unsigned int *) arg
);
2935 return set_modem_info(info
, cmd
, (unsigned int *) arg
);
2936 case MGSL_IOCGPARAMS
:
2937 return mgsl_get_params(info
,(MGSL_PARAMS
*)arg
);
2938 case MGSL_IOCSPARAMS
:
2939 return mgsl_set_params(info
,(MGSL_PARAMS
*)arg
);
2940 case MGSL_IOCGTXIDLE
:
2941 return mgsl_get_txidle(info
,(int*)arg
);
2942 case MGSL_IOCSTXIDLE
:
2943 return mgsl_set_txidle(info
,(int)arg
);
2944 case MGSL_IOCTXENABLE
:
2945 return mgsl_txenable(info
,(int)arg
);
2946 case MGSL_IOCRXENABLE
:
2947 return mgsl_rxenable(info
,(int)arg
);
2948 case MGSL_IOCTXABORT
:
2949 return mgsl_txabort(info
);
2950 case MGSL_IOCGSTATS
:
2951 return mgsl_get_stats(info
,(struct mgsl_icount
*)arg
);
2952 case MGSL_IOCWAITEVENT
:
2953 return mgsl_wait_event(info
,(int*)arg
);
2954 case MGSL_IOCLOOPTXDONE
:
2955 return mgsl_loopmode_send_done(info
);
2956 case MGSL_IOCCLRMODCOUNT
:
2961 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
2962 * - mask passed in arg for lines of interest
2963 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
2964 * Caller should use TIOCGICOUNT to see which one it was
2967 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
2968 /* note the counters on entry */
2969 cprev
= info
->icount
;
2970 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
2972 interruptible_sleep_on(&info
->status_event_wait_q
);
2973 /* see if a signal did it */
2974 if (signal_pending(current
))
2975 return -ERESTARTSYS
;
2976 save_flags(flags
); cli();
2977 cnow
= info
->icount
; /* atomic copy */
2978 restore_flags(flags
);
2979 if (cnow
.rng
== cprev
.rng
&& cnow
.dsr
== cprev
.dsr
&&
2980 cnow
.dcd
== cprev
.dcd
&& cnow
.cts
== cprev
.cts
)
2981 return -EIO
; /* no change => error */
2982 if ( ((arg
& TIOCM_RNG
) && (cnow
.rng
!= cprev
.rng
)) ||
2983 ((arg
& TIOCM_DSR
) && (cnow
.dsr
!= cprev
.dsr
)) ||
2984 ((arg
& TIOCM_CD
) && (cnow
.dcd
!= cprev
.dcd
)) ||
2985 ((arg
& TIOCM_CTS
) && (cnow
.cts
!= cprev
.cts
)) ) {
2993 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
2994 * Return: write counters to the user passed counter struct
2995 * NB: both 1->0 and 0->1 transitions are counted except for
2996 * RI where only 0->1 is counted.
2999 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3000 cnow
= info
->icount
;
3001 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3002 p_cuser
= (struct serial_icounter_struct
*) arg
;
3003 PUT_USER(error
,cnow
.cts
, &p_cuser
->cts
);
3004 if (error
) return error
;
3005 PUT_USER(error
,cnow
.dsr
, &p_cuser
->dsr
);
3006 if (error
) return error
;
3007 PUT_USER(error
,cnow
.rng
, &p_cuser
->rng
);
3008 if (error
) return error
;
3009 PUT_USER(error
,cnow
.dcd
, &p_cuser
->dcd
);
3010 if (error
) return error
;
3011 PUT_USER(error
,cnow
.rx
, &p_cuser
->rx
);
3012 if (error
) return error
;
3013 PUT_USER(error
,cnow
.tx
, &p_cuser
->tx
);
3014 if (error
) return error
;
3015 PUT_USER(error
,cnow
.frame
, &p_cuser
->frame
);
3016 if (error
) return error
;
3017 PUT_USER(error
,cnow
.overrun
, &p_cuser
->overrun
);
3018 if (error
) return error
;
3019 PUT_USER(error
,cnow
.parity
, &p_cuser
->parity
);
3020 if (error
) return error
;
3021 PUT_USER(error
,cnow
.brk
, &p_cuser
->brk
);
3022 if (error
) return error
;
3023 PUT_USER(error
,cnow
.buf_overrun
, &p_cuser
->buf_overrun
);
3024 if (error
) return error
;
3027 return -ENOIOCTLCMD
;
3032 /* mgsl_set_termios()
3034 * Set new termios settings
3038 * tty pointer to tty structure
3039 * termios pointer to buffer to hold returned old termios
3041 * Return Value: None
3043 static void mgsl_set_termios(struct tty_struct
*tty
, struct termios
*old_termios
)
3045 struct mgsl_struct
*info
= (struct mgsl_struct
*)tty
->driver_data
;
3046 unsigned long flags
;
3048 if (debug_level
>= DEBUG_LEVEL_INFO
)
3049 printk("%s(%d):mgsl_set_termios %s\n", __FILE__
,__LINE__
,
3052 /* just return if nothing has changed */
3053 if ((tty
->termios
->c_cflag
== old_termios
->c_cflag
)
3054 && (RELEVANT_IFLAG(tty
->termios
->c_iflag
)
3055 == RELEVANT_IFLAG(old_termios
->c_iflag
)))
3058 mgsl_change_params(info
);
3060 /* Handle transition to B0 status */
3061 if (old_termios
->c_cflag
& CBAUD
&&
3062 !(tty
->termios
->c_cflag
& CBAUD
)) {
3063 info
->serial_signals
&= ~(SerialSignal_RTS
+ SerialSignal_DTR
);
3064 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3065 usc_set_serial_signals(info
);
3066 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3069 /* Handle transition away from B0 status */
3070 if (!(old_termios
->c_cflag
& CBAUD
) &&
3071 tty
->termios
->c_cflag
& CBAUD
) {
3072 info
->serial_signals
|= SerialSignal_DTR
;
3073 if (!(tty
->termios
->c_cflag
& CRTSCTS
) ||
3074 !test_bit(TTY_THROTTLED
, &tty
->flags
)) {
3075 info
->serial_signals
|= SerialSignal_RTS
;
3077 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3078 usc_set_serial_signals(info
);
3079 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3082 /* Handle turning off CRTSCTS */
3083 if (old_termios
->c_cflag
& CRTSCTS
&&
3084 !(tty
->termios
->c_cflag
& CRTSCTS
)) {
3085 tty
->hw_stopped
= 0;
3089 } /* end of mgsl_set_termios() */
3093 * Called when port is closed. Wait for remaining data to be
3094 * sent. Disable port and free resources.
3098 * tty pointer to open tty structure
3099 * filp pointer to open file object
3101 * Return Value: None
3103 static void mgsl_close(struct tty_struct
*tty
, struct file
* filp
)
3105 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3107 if (!info
|| mgsl_paranoia_check(info
, tty
->device
, "mgsl_close"))
3110 if (debug_level
>= DEBUG_LEVEL_INFO
)
3111 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3112 __FILE__
,__LINE__
, info
->device_name
, info
->count
);
3114 if (!info
->count
|| tty_hung_up_p(filp
))
3117 if ((tty
->count
== 1) && (info
->count
!= 1)) {
3119 * tty->count is 1 and the tty structure will be freed.
3120 * info->count should be one in this case.
3121 * if it's not, correct it so that the port is shutdown.
3123 printk("mgsl_close: bad refcount; tty->count is 1, "
3124 "info->count is %d\n", info
->count
);
3130 /* if at least one open remaining, leave hardware active */
3134 info
->flags
|= ASYNC_CLOSING
;
3136 /* Save the termios structure, since this port may have
3137 * separate termios for callout and dialin.
3139 if (info
->flags
& ASYNC_NORMAL_ACTIVE
)
3140 info
->normal_termios
= *tty
->termios
;
3141 if (info
->flags
& ASYNC_CALLOUT_ACTIVE
)
3142 info
->callout_termios
= *tty
->termios
;
3144 /* set tty->closing to notify line discipline to
3145 * only process XON/XOFF characters. Only the N_TTY
3146 * discipline appears to use this (ppp does not).
3150 /* wait for transmit data to clear all layers */
3152 if (info
->closing_wait
!= ASYNC_CLOSING_WAIT_NONE
) {
3153 if (debug_level
>= DEBUG_LEVEL_INFO
)
3154 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3155 __FILE__
,__LINE__
, info
->device_name
);
3156 tty_wait_until_sent(tty
, info
->closing_wait
);
3159 if (info
->flags
& ASYNC_INITIALIZED
)
3160 mgsl_wait_until_sent(tty
, info
->timeout
);
3162 if (tty
->driver
.flush_buffer
)
3163 tty
->driver
.flush_buffer(tty
);
3165 if (tty
->ldisc
.flush_buffer
)
3166 tty
->ldisc
.flush_buffer(tty
);
3173 if (info
->blocked_open
) {
3174 if (info
->close_delay
) {
3175 set_current_state(TASK_INTERRUPTIBLE
);
3176 schedule_timeout(info
->close_delay
);
3178 wake_up_interruptible(&info
->open_wait
);
3181 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CALLOUT_ACTIVE
|
3184 wake_up_interruptible(&info
->close_wait
);
3187 if (debug_level
>= DEBUG_LEVEL_INFO
)
3188 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__
,__LINE__
,
3189 tty
->driver
.name
, info
->count
);
3193 } /* end of mgsl_close() */
3195 /* mgsl_wait_until_sent()
3197 * Wait until the transmitter is empty.
3201 * tty pointer to tty info structure
3202 * timeout time to wait for send completion
3204 * Return Value: None
3206 static void mgsl_wait_until_sent(struct tty_struct
*tty
, int timeout
)
3208 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3209 unsigned long orig_jiffies
, char_time
;
3214 if (debug_level
>= DEBUG_LEVEL_INFO
)
3215 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3216 __FILE__
,__LINE__
, info
->device_name
);
3218 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_wait_until_sent"))
3221 if (!(info
->flags
& ASYNC_INITIALIZED
))
3224 orig_jiffies
= jiffies
;
3226 /* Set check interval to 1/5 of estimated time to
3227 * send a character, and make it at least 1. The check
3228 * interval should also be less than the timeout.
3229 * Note: use tight timings here to satisfy the NIST-PCTS.
3232 if ( info
->params
.data_rate
) {
3233 char_time
= info
->timeout
/(32 * 5);
3240 char_time
= MIN(char_time
, timeout
);
3242 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
3243 while (info
->tx_active
) {
3244 set_current_state(TASK_INTERRUPTIBLE
);
3245 schedule_timeout(char_time
);
3246 if (signal_pending(current
))
3248 if (timeout
&& ((orig_jiffies
+ timeout
) < jiffies
))
3252 while (!(usc_InReg(info
,TCSR
) & TXSTATUS_ALL_SENT
) &&
3254 set_current_state(TASK_INTERRUPTIBLE
);
3255 schedule_timeout(char_time
);
3256 if (signal_pending(current
))
3258 if (timeout
&& ((orig_jiffies
+ timeout
) < jiffies
))
3264 if (debug_level
>= DEBUG_LEVEL_INFO
)
3265 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3266 __FILE__
,__LINE__
, info
->device_name
);
3268 } /* end of mgsl_wait_until_sent() */
3272 * Called by tty_hangup() when a hangup is signaled.
3273 * This is the same as to closing all open files for the port.
3275 * Arguments: tty pointer to associated tty object
3276 * Return Value: None
3278 static void mgsl_hangup(struct tty_struct
*tty
)
3280 struct mgsl_struct
* info
= (struct mgsl_struct
*)tty
->driver_data
;
3282 if (debug_level
>= DEBUG_LEVEL_INFO
)
3283 printk("%s(%d):mgsl_hangup(%s)\n",
3284 __FILE__
,__LINE__
, info
->device_name
);
3286 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_hangup"))
3289 mgsl_flush_buffer(tty
);
3293 info
->flags
&= ~(ASYNC_NORMAL_ACTIVE
|ASYNC_CALLOUT_ACTIVE
);
3296 wake_up_interruptible(&info
->open_wait
);
3298 } /* end of mgsl_hangup() */
3300 /* block_til_ready()
3302 * Block the current process until the specified port
3303 * is ready to be opened.
3307 * tty pointer to tty info structure
3308 * filp pointer to open file object
3309 * info pointer to device instance data
3311 * Return Value: 0 if success, otherwise error code
3313 static int block_til_ready(struct tty_struct
*tty
, struct file
* filp
,
3314 struct mgsl_struct
*info
)
3316 DECLARE_WAITQUEUE(wait
, current
);
3318 int do_clocal
= 0, extra_count
= 0;
3319 unsigned long flags
;
3321 if (debug_level
>= DEBUG_LEVEL_INFO
)
3322 printk("%s(%d):block_til_ready on %s\n",
3323 __FILE__
,__LINE__
, tty
->driver
.name
);
3325 if (tty
->driver
.subtype
== SERIAL_TYPE_CALLOUT
) {
3326 /* this is a callout device */
3327 /* just verify that normal device is not in use */
3328 if (info
->flags
& ASYNC_NORMAL_ACTIVE
)
3330 if ((info
->flags
& ASYNC_CALLOUT_ACTIVE
) &&
3331 (info
->flags
& ASYNC_SESSION_LOCKOUT
) &&
3332 (info
->session
!= current
->session
))
3334 if ((info
->flags
& ASYNC_CALLOUT_ACTIVE
) &&
3335 (info
->flags
& ASYNC_PGRP_LOCKOUT
) &&
3336 (info
->pgrp
!= current
->pgrp
))
3338 info
->flags
|= ASYNC_CALLOUT_ACTIVE
;
3342 if (filp
->f_flags
& O_NONBLOCK
|| tty
->flags
& (1 << TTY_IO_ERROR
)){
3343 /* nonblock mode is set or port is not enabled */
3344 /* just verify that callout device is not active */
3345 if (info
->flags
& ASYNC_CALLOUT_ACTIVE
)
3347 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3351 if (info
->flags
& ASYNC_CALLOUT_ACTIVE
) {
3352 if (info
->normal_termios
.c_cflag
& CLOCAL
)
3355 if (tty
->termios
->c_cflag
& CLOCAL
)
3359 /* Wait for carrier detect and the line to become
3360 * free (i.e., not in use by the callout). While we are in
3361 * this loop, info->count is dropped by one, so that
3362 * mgsl_close() knows when to free things. We restore it upon
3363 * exit, either normal or abnormal.
3367 add_wait_queue(&info
->open_wait
, &wait
);
3369 if (debug_level
>= DEBUG_LEVEL_INFO
)
3370 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3371 __FILE__
,__LINE__
, tty
->driver
.name
, info
->count
);
3373 save_flags(flags
); cli();
3374 if (!tty_hung_up_p(filp
)) {
3378 restore_flags(flags
);
3379 info
->blocked_open
++;
3382 if (!(info
->flags
& ASYNC_CALLOUT_ACTIVE
) &&
3383 (tty
->termios
->c_cflag
& CBAUD
)) {
3384 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3385 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
3386 usc_set_serial_signals(info
);
3387 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3390 set_current_state(TASK_INTERRUPTIBLE
);
3392 if (tty_hung_up_p(filp
) || !(info
->flags
& ASYNC_INITIALIZED
)){
3393 retval
= (info
->flags
& ASYNC_HUP_NOTIFY
) ?
3394 -EAGAIN
: -ERESTARTSYS
;
3398 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3399 usc_get_serial_signals(info
);
3400 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3402 if (!(info
->flags
& ASYNC_CALLOUT_ACTIVE
) &&
3403 !(info
->flags
& ASYNC_CLOSING
) &&
3404 (do_clocal
|| (info
->serial_signals
& SerialSignal_DCD
)) ) {
3408 if (signal_pending(current
)) {
3409 retval
= -ERESTARTSYS
;
3413 if (debug_level
>= DEBUG_LEVEL_INFO
)
3414 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3415 __FILE__
,__LINE__
, tty
->driver
.name
, info
->count
);
3420 set_current_state(TASK_RUNNING
);
3421 remove_wait_queue(&info
->open_wait
, &wait
);
3425 info
->blocked_open
--;
3427 if (debug_level
>= DEBUG_LEVEL_INFO
)
3428 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3429 __FILE__
,__LINE__
, tty
->driver
.name
, info
->count
);
3432 info
->flags
|= ASYNC_NORMAL_ACTIVE
;
3436 } /* end of block_til_ready() */
3440 * Called when a port is opened. Init and enable port.
3441 * Perform serial-specific initialization for the tty structure.
3443 * Arguments: tty pointer to tty info structure
3444 * filp associated file pointer
3446 * Return Value: 0 if success, otherwise error code
3448 static int mgsl_open(struct tty_struct
*tty
, struct file
* filp
)
3450 struct mgsl_struct
*info
;
3453 unsigned long flags
;
3455 /* verify range of specified line number */
3456 line
= MINOR(tty
->device
) - tty
->driver
.minor_start
;
3457 if ((line
< 0) || (line
>= mgsl_device_count
)) {
3458 printk("%s(%d):mgsl_open with illegal line #%d.\n",
3459 __FILE__
,__LINE__
,line
);
3463 /* find the info structure for the specified line */
3464 info
= mgsl_device_list
;
3465 while(info
&& info
->line
!= line
)
3466 info
= info
->next_device
;
3468 printk("%s(%d):Can't find specified device on open (line=%d)\n",
3469 __FILE__
,__LINE__
,line
);
3473 tty
->driver_data
= info
;
3475 if (mgsl_paranoia_check(info
, tty
->device
, "mgsl_open"))
3478 if (debug_level
>= DEBUG_LEVEL_INFO
)
3479 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3480 __FILE__
,__LINE__
,tty
->driver
.name
, info
->count
);
3484 /* If port is closing, signal caller to try again */
3485 if (tty_hung_up_p(filp
) || info
->flags
& ASYNC_CLOSING
){
3486 if (info
->flags
& ASYNC_CLOSING
)
3487 interruptible_sleep_on(&info
->close_wait
);
3488 retval
= ((info
->flags
& ASYNC_HUP_NOTIFY
) ?
3489 -EAGAIN
: -ERESTARTSYS
);
3494 page
= get_free_page(GFP_KERNEL
);
3502 tmp_buf
= (unsigned char *) page
;
3505 info
->tty
->low_latency
= (info
->flags
& ASYNC_LOW_LATENCY
) ? 1 : 0;
3507 spin_lock_irqsave(&info
->netlock
, flags
);
3508 if (info
->netcount
) {
3510 spin_unlock_irqrestore(&info
->netlock
, flags
);
3514 spin_unlock_irqrestore(&info
->netlock
, flags
);
3516 if (info
->count
== 1) {
3517 /* 1st open on this device, init hardware */
3518 retval
= startup(info
);
3523 retval
= block_til_ready(tty
, filp
, info
);
3525 if (debug_level
>= DEBUG_LEVEL_INFO
)
3526 printk("%s(%d):block_til_ready(%s) returned %d\n",
3527 __FILE__
,__LINE__
, info
->device_name
, retval
);
3531 if ((info
->count
== 1) &&
3532 info
->flags
& ASYNC_SPLIT_TERMIOS
) {
3533 if (tty
->driver
.subtype
== SERIAL_TYPE_NORMAL
)
3534 *tty
->termios
= info
->normal_termios
;
3536 *tty
->termios
= info
->callout_termios
;
3537 mgsl_change_params(info
);
3540 info
->session
= current
->session
;
3541 info
->pgrp
= current
->pgrp
;
3543 if (debug_level
>= DEBUG_LEVEL_INFO
)
3544 printk("%s(%d):mgsl_open(%s) success\n",
3545 __FILE__
,__LINE__
, info
->device_name
);
3558 } /* end of mgsl_open() */
3561 * /proc fs routines....
3564 static inline int line_info(char *buf
, struct mgsl_struct
*info
)
3568 unsigned long flags
;
3570 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3571 ret
= sprintf(buf
, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3572 info
->device_name
, info
->io_base
, info
->irq_level
,
3573 info
->phys_memory_base
, info
->phys_lcr_base
);
3575 ret
= sprintf(buf
, "%s:(E)ISA io:%04X irq:%d dma:%d",
3576 info
->device_name
, info
->io_base
,
3577 info
->irq_level
, info
->dma_level
);
3580 /* output current serial signal states */
3581 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3582 usc_get_serial_signals(info
);
3583 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3587 if (info
->serial_signals
& SerialSignal_RTS
)
3588 strcat(stat_buf
, "|RTS");
3589 if (info
->serial_signals
& SerialSignal_CTS
)
3590 strcat(stat_buf
, "|CTS");
3591 if (info
->serial_signals
& SerialSignal_DTR
)
3592 strcat(stat_buf
, "|DTR");
3593 if (info
->serial_signals
& SerialSignal_DSR
)
3594 strcat(stat_buf
, "|DSR");
3595 if (info
->serial_signals
& SerialSignal_DCD
)
3596 strcat(stat_buf
, "|CD");
3597 if (info
->serial_signals
& SerialSignal_RI
)
3598 strcat(stat_buf
, "|RI");
3600 if (info
->params
.mode
== MGSL_MODE_HDLC
) {
3601 ret
+= sprintf(buf
+ret
, " HDLC txok:%d rxok:%d",
3602 info
->icount
.txok
, info
->icount
.rxok
);
3603 if (info
->icount
.txunder
)
3604 ret
+= sprintf(buf
+ret
, " txunder:%d", info
->icount
.txunder
);
3605 if (info
->icount
.txabort
)
3606 ret
+= sprintf(buf
+ret
, " txabort:%d", info
->icount
.txabort
);
3607 if (info
->icount
.rxshort
)
3608 ret
+= sprintf(buf
+ret
, " rxshort:%d", info
->icount
.rxshort
);
3609 if (info
->icount
.rxlong
)
3610 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxlong
);
3611 if (info
->icount
.rxover
)
3612 ret
+= sprintf(buf
+ret
, " rxover:%d", info
->icount
.rxover
);
3613 if (info
->icount
.rxcrc
)
3614 ret
+= sprintf(buf
+ret
, " rxlong:%d", info
->icount
.rxcrc
);
3616 ret
+= sprintf(buf
+ret
, " ASYNC tx:%d rx:%d",
3617 info
->icount
.tx
, info
->icount
.rx
);
3618 if (info
->icount
.frame
)
3619 ret
+= sprintf(buf
+ret
, " fe:%d", info
->icount
.frame
);
3620 if (info
->icount
.parity
)
3621 ret
+= sprintf(buf
+ret
, " pe:%d", info
->icount
.parity
);
3622 if (info
->icount
.brk
)
3623 ret
+= sprintf(buf
+ret
, " brk:%d", info
->icount
.brk
);
3624 if (info
->icount
.overrun
)
3625 ret
+= sprintf(buf
+ret
, " oe:%d", info
->icount
.overrun
);
3628 /* Append serial signal status to end */
3629 ret
+= sprintf(buf
+ret
, " %s\n", stat_buf
+1);
3631 ret
+= sprintf(buf
+ret
, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3632 info
->tx_active
,info
->bh_requested
,info
->bh_running
,
3635 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
3637 u16 Tcsr
= usc_InReg( info
, TCSR
);
3638 u16 Tdmr
= usc_InDmaReg( info
, TDMR
);
3639 u16 Ticr
= usc_InReg( info
, TICR
);
3640 u16 Rscr
= usc_InReg( info
, RCSR
);
3641 u16 Rdmr
= usc_InDmaReg( info
, RDMR
);
3642 u16 Ricr
= usc_InReg( info
, RICR
);
3643 u16 Icr
= usc_InReg( info
, ICR
);
3644 u16 Dccr
= usc_InReg( info
, DCCR
);
3645 u16 Tmr
= usc_InReg( info
, TMR
);
3646 u16 Tccr
= usc_InReg( info
, TCCR
);
3647 u16 Ccar
= inw( info
->io_base
+ CCAR
);
3648 ret
+= sprintf(buf
+ret
, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3649 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3650 Tcsr
,Tdmr
,Ticr
,Rscr
,Rdmr
,Ricr
,Icr
,Dccr
,Tmr
,Tccr
,Ccar
);
3652 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
3656 } /* end of line_info() */
3660 * Called to print information about devices
3663 * page page of memory to hold returned info
3672 int mgsl_read_proc(char *page
, char **start
, off_t off
, int count
,
3673 int *eof
, void *data
)
3677 struct mgsl_struct
*info
;
3679 len
+= sprintf(page
, "synclink driver:%s\n", driver_version
);
3681 info
= mgsl_device_list
;
3683 l
= line_info(page
+ len
, info
);
3685 if (len
+begin
> off
+count
)
3687 if (len
+begin
< off
) {
3691 info
= info
->next_device
;
3696 if (off
>= len
+begin
)
3698 *start
= page
+ (off
-begin
);
3699 return ((count
< begin
+len
-off
) ? count
: begin
+len
-off
);
3701 } /* end of mgsl_read_proc() */
3703 /* mgsl_allocate_dma_buffers()
3705 * Allocate and format DMA buffers (ISA adapter)
3706 * or format shared memory buffers (PCI adapter).
3708 * Arguments: info pointer to device instance data
3709 * Return Value: 0 if success, otherwise error
3711 int mgsl_allocate_dma_buffers(struct mgsl_struct
*info
)
3713 unsigned short BuffersPerFrame
;
3715 info
->last_mem_alloc
= 0;
3717 /* Calculate the number of DMA buffers necessary to hold the */
3718 /* largest allowable frame size. Note: If the max frame size is */
3719 /* not an even multiple of the DMA buffer size then we need to */
3720 /* round the buffer count per frame up one. */
3722 BuffersPerFrame
= (unsigned short)(info
->max_frame_size
/DMABUFFERSIZE
);
3723 if ( info
->max_frame_size
% DMABUFFERSIZE
)
3726 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3728 * The PCI adapter has 256KBytes of shared memory to use.
3729 * This is 64 PAGE_SIZE buffers.
3731 * The first page is used for padding at this time so the
3732 * buffer list does not begin at offset 0 of the PCI
3733 * adapter's shared memory.
3735 * The 2nd page is used for the buffer list. A 4K buffer
3736 * list can hold 128 DMA_BUFFER structures at 32 bytes
3739 * This leaves 62 4K pages.
3741 * The next N pages are used for a transmit frame. We
3742 * reserve enough 4K page blocks to hold the configured
3745 * Of the remaining pages (62-N), determine how many can
3746 * be used to receive full MaxFrameSize inbound frames
3749 info
->tx_buffer_count
= BuffersPerFrame
;
3750 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3752 /* Calculate the number of PAGE_SIZE buffers needed for */
3753 /* receive and transmit DMA buffers. */
3756 /* Calculate the number of DMA buffers necessary to */
3757 /* hold 7 max size receive frames and one max size transmit frame. */
3758 /* The receive buffer count is bumped by one so we avoid an */
3759 /* End of List condition if all receive buffers are used when */
3760 /* using linked list DMA buffers. */
3762 info
->tx_buffer_count
= BuffersPerFrame
;
3763 info
->rx_buffer_count
= (BuffersPerFrame
* MAXRXFRAMES
) + 6;
3766 * limit total TxBuffers & RxBuffers to 62 4K total
3767 * (ala PCI Allocation)
3770 if ( (info
->tx_buffer_count
+ info
->rx_buffer_count
) > 62 )
3771 info
->rx_buffer_count
= 62 - info
->tx_buffer_count
;
3775 if ( debug_level
>= DEBUG_LEVEL_INFO
)
3776 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3777 __FILE__
,__LINE__
, info
->tx_buffer_count
,info
->rx_buffer_count
);
3779 if ( mgsl_alloc_buffer_list_memory( info
) < 0 ||
3780 mgsl_alloc_frame_memory(info
, info
->rx_buffer_list
, info
->rx_buffer_count
) < 0 ||
3781 mgsl_alloc_frame_memory(info
, info
->tx_buffer_list
, info
->tx_buffer_count
) < 0 ||
3782 mgsl_alloc_intermediate_rxbuffer_memory(info
) < 0 ) {
3783 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__
,__LINE__
);
3787 mgsl_reset_rx_dma_buffers( info
);
3791 } /* end of mgsl_allocate_dma_buffers() */
3794 * mgsl_alloc_buffer_list_memory()
3796 * Allocate a common DMA buffer for use as the
3797 * receive and transmit buffer lists.
3799 * A buffer list is a set of buffer entries where each entry contains
3800 * a pointer to an actual buffer and a pointer to the next buffer entry
3801 * (plus some other info about the buffer).
3803 * The buffer entries for a list are built to form a circular list so
3804 * that when the entire list has been traversed you start back at the
3807 * This function allocates memory for just the buffer entries.
3808 * The links (pointer to next entry) are filled in with the physical
3809 * address of the next entry so the adapter can navigate the list
3810 * using bus master DMA. The pointers to the actual buffers are filled
3811 * out later when the actual buffers are allocated.
3813 * Arguments: info pointer to device instance data
3814 * Return Value: 0 if success, otherwise error
3816 int mgsl_alloc_buffer_list_memory( struct mgsl_struct
*info
)
3820 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3821 /* PCI adapter uses shared memory. */
3822 info
->buffer_list
= info
->memory_base
+ info
->last_mem_alloc
;
3823 info
->buffer_list_phys
= info
->last_mem_alloc
;
3824 info
->last_mem_alloc
+= BUFFERLISTSIZE
;
3826 /* ISA adapter uses system memory. */
3827 /* The buffer lists are allocated as a common buffer that both */
3828 /* the processor and adapter can access. This allows the driver to */
3829 /* inspect portions of the buffer while other portions are being */
3830 /* updated by the adapter using Bus Master DMA. */
3832 info
->buffer_list
= kmalloc(BUFFERLISTSIZE
, GFP_KERNEL
| GFP_DMA
);
3833 if ( info
->buffer_list
== NULL
)
3836 info
->buffer_list_phys
= virt_to_bus(info
->buffer_list
);
3839 /* We got the memory for the buffer entry lists. */
3840 /* Initialize the memory block to all zeros. */
3841 memset( info
->buffer_list
, 0, BUFFERLISTSIZE
);
3843 /* Save virtual address pointers to the receive and */
3844 /* transmit buffer lists. (Receive 1st). These pointers will */
3845 /* be used by the processor to access the lists. */
3846 info
->rx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3847 info
->tx_buffer_list
= (DMABUFFERENTRY
*)info
->buffer_list
;
3848 info
->tx_buffer_list
+= info
->rx_buffer_count
;
3851 * Build the links for the buffer entry lists such that
3852 * two circular lists are built. (Transmit and Receive).
3854 * Note: the links are physical addresses
3855 * which are read by the adapter to determine the next
3856 * buffer entry to use.
3859 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
3860 /* calculate and store physical address of this buffer entry */
3861 info
->rx_buffer_list
[i
].phys_entry
=
3862 info
->buffer_list_phys
+ (i
* sizeof(DMABUFFERENTRY
));
3864 /* calculate and store physical address of */
3865 /* next entry in cirular list of entries */
3867 info
->rx_buffer_list
[i
].link
= info
->buffer_list_phys
;
3869 if ( i
< info
->rx_buffer_count
- 1 )
3870 info
->rx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3873 for ( i
= 0; i
< info
->tx_buffer_count
; i
++ ) {
3874 /* calculate and store physical address of this buffer entry */
3875 info
->tx_buffer_list
[i
].phys_entry
= info
->buffer_list_phys
+
3876 ((info
->rx_buffer_count
+ i
) * sizeof(DMABUFFERENTRY
));
3878 /* calculate and store physical address of */
3879 /* next entry in cirular list of entries */
3881 info
->tx_buffer_list
[i
].link
= info
->buffer_list_phys
+
3882 info
->rx_buffer_count
* sizeof(DMABUFFERENTRY
);
3884 if ( i
< info
->tx_buffer_count
- 1 )
3885 info
->tx_buffer_list
[i
].link
+= (i
+ 1) * sizeof(DMABUFFERENTRY
);
3890 } /* end of mgsl_alloc_buffer_list_memory() */
3892 /* Free DMA buffers allocated for use as the
3893 * receive and transmit buffer lists.
3896 * The data transfer buffers associated with the buffer list
3897 * MUST be freed before freeing the buffer list itself because
3898 * the buffer list contains the information necessary to free
3899 * the individual buffers!
3901 void mgsl_free_buffer_list_memory( struct mgsl_struct
*info
)
3903 if ( info
->buffer_list
&& info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3904 kfree(info
->buffer_list
);
3906 info
->buffer_list
= NULL
;
3907 info
->rx_buffer_list
= NULL
;
3908 info
->tx_buffer_list
= NULL
;
3910 } /* end of mgsl_free_buffer_list_memory() */
3913 * mgsl_alloc_frame_memory()
3915 * Allocate the frame DMA buffers used by the specified buffer list.
3916 * Each DMA buffer will be one memory page in size. This is necessary
3917 * because memory can fragment enough that it may be impossible
3922 * info pointer to device instance data
3923 * BufferList pointer to list of buffer entries
3924 * Buffercount count of buffer entries in buffer list
3926 * Return Value: 0 if success, otherwise -ENOMEM
3928 int mgsl_alloc_frame_memory(struct mgsl_struct
*info
,DMABUFFERENTRY
*BufferList
,int Buffercount
)
3931 unsigned long phys_addr
;
3933 /* Allocate page sized buffers for the receive buffer list */
3935 for ( i
= 0; i
< Buffercount
; i
++ ) {
3936 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
3937 /* PCI adapter uses shared memory buffers. */
3938 BufferList
[i
].virt_addr
= info
->memory_base
+ info
->last_mem_alloc
;
3939 phys_addr
= info
->last_mem_alloc
;
3940 info
->last_mem_alloc
+= DMABUFFERSIZE
;
3942 /* ISA adapter uses system memory. */
3943 BufferList
[i
].virt_addr
=
3944 kmalloc(DMABUFFERSIZE
, GFP_KERNEL
| GFP_DMA
);
3945 if ( BufferList
[i
].virt_addr
== NULL
)
3947 phys_addr
= virt_to_bus(BufferList
[i
].virt_addr
);
3949 BufferList
[i
].phys_addr
= phys_addr
;
3954 } /* end of mgsl_alloc_frame_memory() */
3957 * mgsl_free_frame_memory()
3959 * Free the buffers associated with
3960 * each buffer entry of a buffer list.
3964 * info pointer to device instance data
3965 * BufferList pointer to list of buffer entries
3966 * Buffercount count of buffer entries in buffer list
3968 * Return Value: None
3970 void mgsl_free_frame_memory(struct mgsl_struct
*info
, DMABUFFERENTRY
*BufferList
, int Buffercount
)
3975 for ( i
= 0 ; i
< Buffercount
; i
++ ) {
3976 if ( BufferList
[i
].virt_addr
) {
3977 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
3978 kfree(BufferList
[i
].virt_addr
);
3979 BufferList
[i
].virt_addr
= NULL
;
3984 } /* end of mgsl_free_frame_memory() */
3986 /* mgsl_free_dma_buffers()
3990 * Arguments: info pointer to device instance data
3991 * Return Value: None
3993 void mgsl_free_dma_buffers( struct mgsl_struct
*info
)
3995 mgsl_free_frame_memory( info
, info
->rx_buffer_list
, info
->rx_buffer_count
);
3996 mgsl_free_frame_memory( info
, info
->tx_buffer_list
, info
->tx_buffer_count
);
3997 mgsl_free_buffer_list_memory( info
);
3999 } /* end of mgsl_free_dma_buffers() */
4003 * mgsl_alloc_intermediate_rxbuffer_memory()
4005 * Allocate a buffer large enough to hold max_frame_size. This buffer
4006 * is used to pass an assembled frame to the line discipline.
4010 * info pointer to device instance data
4012 * Return Value: 0 if success, otherwise -ENOMEM
4014 int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
4016 info
->intermediate_rxbuffer
= kmalloc(info
->max_frame_size
, GFP_KERNEL
| GFP_DMA
);
4017 if ( info
->intermediate_rxbuffer
== NULL
)
4022 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4025 * mgsl_free_intermediate_rxbuffer_memory()
4030 * info pointer to device instance data
4032 * Return Value: None
4034 void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct
*info
)
4036 if ( info
->intermediate_rxbuffer
)
4037 kfree(info
->intermediate_rxbuffer
);
4039 info
->intermediate_rxbuffer
= NULL
;
4041 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4043 int mgsl_claim_resources(struct mgsl_struct
*info
)
4045 if (request_region(info
->io_base
,info
->io_addr_size
,"synclink") == NULL
) {
4046 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4047 __FILE__
,__LINE__
,info
->device_name
, info
->io_base
);
4050 info
->io_addr_requested
= 1;
4052 if ( request_irq(info
->irq_level
,mgsl_interrupt
,info
->irq_flags
,
4053 info
->device_name
, info
) < 0 ) {
4054 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4055 __FILE__
,__LINE__
,info
->device_name
, info
->irq_level
);
4058 info
->irq_requested
= 1;
4060 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4061 if (request_mem_region(info
->phys_memory_base
,0x40000,"synclink") == NULL
) {
4062 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4063 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4066 info
->shared_mem_requested
= 1;
4067 if (request_mem_region(info
->phys_lcr_base
,128,"synclink") == NULL
) {
4068 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4069 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4072 info
->lcr_mem_requested
= 1;
4074 info
->memory_base
= ioremap(info
->phys_memory_base
,0x40000);
4075 if (!info
->memory_base
) {
4076 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4077 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4081 if ( !mgsl_memory_test(info
) ) {
4082 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4083 __FILE__
,__LINE__
,info
->device_name
, info
->phys_memory_base
);
4087 info
->lcr_base
= ioremap(info
->phys_lcr_base
,PAGE_SIZE
) + info
->lcr_offset
;
4088 if (!info
->lcr_base
) {
4089 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4090 __FILE__
,__LINE__
,info
->device_name
, info
->phys_lcr_base
);
4095 /* claim DMA channel */
4097 if (request_dma(info
->dma_level
,info
->device_name
) < 0){
4098 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4099 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4100 mgsl_release_resources( info
);
4103 info
->dma_requested
= 1;
4105 /* ISA adapter uses bus master DMA */
4106 set_dma_mode(info
->dma_level
,DMA_MODE_CASCADE
);
4107 enable_dma(info
->dma_level
);
4110 if ( mgsl_allocate_dma_buffers(info
) < 0 ) {
4111 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4112 __FILE__
,__LINE__
,info
->device_name
, info
->dma_level
);
4118 mgsl_release_resources(info
);
4121 } /* end of mgsl_claim_resources() */
4123 void mgsl_release_resources(struct mgsl_struct
*info
)
4125 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4126 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4127 __FILE__
,__LINE__
,info
->device_name
);
4129 if ( info
->irq_requested
) {
4130 free_irq(info
->irq_level
, info
);
4131 info
->irq_requested
= 0;
4133 if ( info
->dma_requested
) {
4134 disable_dma(info
->dma_level
);
4135 free_dma(info
->dma_level
);
4136 info
->dma_requested
= 0;
4138 mgsl_free_dma_buffers(info
);
4139 mgsl_free_intermediate_rxbuffer_memory(info
);
4141 if ( info
->io_addr_requested
) {
4142 release_region(info
->io_base
,info
->io_addr_size
);
4143 info
->io_addr_requested
= 0;
4145 if ( info
->shared_mem_requested
) {
4146 release_mem_region(info
->phys_memory_base
,0x40000);
4147 info
->shared_mem_requested
= 0;
4149 if ( info
->lcr_mem_requested
) {
4150 release_mem_region(info
->phys_lcr_base
,128);
4151 info
->lcr_mem_requested
= 0;
4153 if (info
->memory_base
){
4154 iounmap(info
->memory_base
);
4155 info
->memory_base
= 0;
4157 if (info
->lcr_base
){
4158 iounmap(info
->lcr_base
- info
->lcr_offset
);
4162 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4163 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4164 __FILE__
,__LINE__
,info
->device_name
);
4166 } /* end of mgsl_release_resources() */
4168 /* mgsl_add_device()
4170 * Add the specified device instance data structure to the
4171 * global linked list of devices and increment the device count.
4173 * Arguments: info pointer to device instance data
4174 * Return Value: None
4176 void mgsl_add_device( struct mgsl_struct
*info
)
4178 info
->next_device
= NULL
;
4179 info
->line
= mgsl_device_count
;
4180 sprintf(info
->device_name
,"ttySL%d",info
->line
);
4182 if (info
->line
< MAX_TOTAL_DEVICES
) {
4183 if (maxframe
[info
->line
])
4184 info
->max_frame_size
= maxframe
[info
->line
];
4185 info
->dosyncppp
= dosyncppp
[info
->line
];
4188 mgsl_device_count
++;
4190 if ( !mgsl_device_list
)
4191 mgsl_device_list
= info
;
4193 struct mgsl_struct
*current_dev
= mgsl_device_list
;
4194 while( current_dev
->next_device
)
4195 current_dev
= current_dev
->next_device
;
4196 current_dev
->next_device
= info
;
4199 if ( info
->max_frame_size
< 4096 )
4200 info
->max_frame_size
= 4096;
4201 else if ( info
->max_frame_size
> 65535 )
4202 info
->max_frame_size
= 65535;
4204 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
4205 printk( "SyncLink device %s added:PCI bus IO=%04X IRQ=%d Mem=%08X LCR=%08X MaxFrameSize=%u\n",
4206 info
->device_name
, info
->io_base
, info
->irq_level
,
4207 info
->phys_memory_base
, info
->phys_lcr_base
,
4208 info
->max_frame_size
);
4210 printk( "SyncLink device %s added:ISA bus IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4211 info
->device_name
, info
->io_base
, info
->irq_level
, info
->dma_level
,
4212 info
->max_frame_size
);
4215 #ifdef CONFIG_SYNCLINK_SYNCPPP
4216 if (info
->dosyncppp
)
4217 mgsl_sppp_init(info
);
4219 } /* end of mgsl_add_device() */
4221 /* mgsl_allocate_device()
4223 * Allocate and initialize a device instance structure
4226 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4228 struct mgsl_struct
* mgsl_allocate_device()
4230 struct mgsl_struct
*info
;
4232 info
= (struct mgsl_struct
*)kmalloc(sizeof(struct mgsl_struct
),
4236 printk("Error can't allocate device instance data\n");
4238 memset(info
, 0, sizeof(struct mgsl_struct
));
4239 info
->magic
= MGSL_MAGIC
;
4240 info
->task
.sync
= 0;
4241 info
->task
.routine
= mgsl_bh_handler
;
4242 info
->task
.data
= info
;
4243 info
->max_frame_size
= 4096;
4244 info
->close_delay
= 5*HZ
/10;
4245 info
->closing_wait
= 30*HZ
;
4246 init_waitqueue_head(&info
->open_wait
);
4247 init_waitqueue_head(&info
->close_wait
);
4248 init_waitqueue_head(&info
->status_event_wait_q
);
4249 init_waitqueue_head(&info
->event_wait_q
);
4250 spin_lock_init(&info
->irq_spinlock
);
4251 spin_lock_init(&info
->netlock
);
4252 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
4253 info
->idle_mode
= HDLC_TXIDLE_FLAGS
;
4258 } /* end of mgsl_allocate_device()*/
4261 * perform tty device initialization
4263 int mgsl_init_tty(void);
4266 struct mgsl_struct
*info
;
4268 memset(serial_table
,0,sizeof(struct tty_struct
*)*MAX_TOTAL_DEVICES
);
4269 memset(serial_termios
,0,sizeof(struct termios
*)*MAX_TOTAL_DEVICES
);
4270 memset(serial_termios_locked
,0,sizeof(struct termios
*)*MAX_TOTAL_DEVICES
);
4272 /* Initialize the tty_driver structure */
4274 memset(&serial_driver
, 0, sizeof(struct tty_driver
));
4275 serial_driver
.magic
= TTY_DRIVER_MAGIC
;
4276 serial_driver
.driver_name
= "synclink";
4277 serial_driver
.name
= "ttySL";
4278 serial_driver
.major
= ttymajor
;
4279 serial_driver
.minor_start
= 64;
4280 serial_driver
.num
= mgsl_device_count
;
4281 serial_driver
.type
= TTY_DRIVER_TYPE_SERIAL
;
4282 serial_driver
.subtype
= SERIAL_TYPE_NORMAL
;
4283 serial_driver
.init_termios
= tty_std_termios
;
4284 serial_driver
.init_termios
.c_cflag
=
4285 B9600
| CS8
| CREAD
| HUPCL
| CLOCAL
;
4286 serial_driver
.flags
= TTY_DRIVER_REAL_RAW
;
4287 serial_driver
.refcount
= &serial_refcount
;
4288 serial_driver
.table
= serial_table
;
4289 serial_driver
.termios
= serial_termios
;
4290 serial_driver
.termios_locked
= serial_termios_locked
;
4292 serial_driver
.open
= mgsl_open
;
4293 serial_driver
.close
= mgsl_close
;
4294 serial_driver
.write
= mgsl_write
;
4295 serial_driver
.put_char
= mgsl_put_char
;
4296 serial_driver
.flush_chars
= mgsl_flush_chars
;
4297 serial_driver
.write_room
= mgsl_write_room
;
4298 serial_driver
.chars_in_buffer
= mgsl_chars_in_buffer
;
4299 serial_driver
.flush_buffer
= mgsl_flush_buffer
;
4300 serial_driver
.ioctl
= mgsl_ioctl
;
4301 serial_driver
.throttle
= mgsl_throttle
;
4302 serial_driver
.unthrottle
= mgsl_unthrottle
;
4303 serial_driver
.send_xchar
= mgsl_send_xchar
;
4304 serial_driver
.break_ctl
= mgsl_break
;
4305 serial_driver
.wait_until_sent
= mgsl_wait_until_sent
;
4306 serial_driver
.read_proc
= mgsl_read_proc
;
4307 serial_driver
.set_termios
= mgsl_set_termios
;
4308 serial_driver
.stop
= mgsl_stop
;
4309 serial_driver
.start
= mgsl_start
;
4310 serial_driver
.hangup
= mgsl_hangup
;
4313 * The callout device is just like normal device except for
4314 * major number and the subtype code.
4316 callout_driver
= serial_driver
;
4317 callout_driver
.name
= "cuaSL";
4318 callout_driver
.major
= cuamajor
;
4319 callout_driver
.subtype
= SERIAL_TYPE_CALLOUT
;
4320 callout_driver
.read_proc
= 0;
4321 callout_driver
.proc_entry
= 0;
4323 if (tty_register_driver(&serial_driver
) < 0)
4324 printk("%s(%d):Couldn't register serial driver\n",
4327 if (tty_register_driver(&callout_driver
) < 0)
4328 printk("%s(%d):Couldn't register callout driver\n",
4331 printk("%s version %s, tty major#%d callout major#%d\n",
4332 driver_name
, driver_version
,
4333 serial_driver
.major
, callout_driver
.major
);
4335 /* Propagate these values to all device instances */
4337 info
= mgsl_device_list
;
4339 info
->callout_termios
= callout_driver
.init_termios
;
4340 info
->normal_termios
= serial_driver
.init_termios
;
4341 info
= info
->next_device
;
4347 /* enumerate user specified ISA adapters
4349 int mgsl_enum_isa_devices()
4351 struct mgsl_struct
*info
;
4354 /* Check for user specified ISA devices */
4356 for (i
=0 ;(i
< MAX_ISA_DEVICES
) && io
[i
] && irq
[i
]; i
++){
4357 if ( debug_level
>= DEBUG_LEVEL_INFO
)
4358 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4359 io
[i
], irq
[i
], dma
[i
] );
4361 info
= mgsl_allocate_device();
4363 /* error allocating device instance data */
4364 if ( debug_level
>= DEBUG_LEVEL_ERROR
)
4365 printk( "can't allocate device instance data.\n");
4369 /* Copy user configuration info to device instance data */
4370 info
->io_base
= (unsigned int)io
[i
];
4371 info
->irq_level
= (unsigned int)irq
[i
];
4372 info
->irq_level
= irq_cannonicalize(info
->irq_level
);
4373 info
->dma_level
= (unsigned int)dma
[i
];
4374 info
->bus_type
= MGSL_BUS_TYPE_ISA
;
4375 info
->io_addr_size
= 16;
4376 info
->irq_flags
= 0;
4378 mgsl_add_device( info
);
4386 * Driver initialization entry point.
4389 * Return Value: 0 if success, otherwise error code
4391 int __init
mgsl_init(void)
4397 printk("%s version %s\n", driver_name
, driver_version
);
4399 mgsl_enum_isa_devices();
4400 pci_register_driver(&synclink_pci_driver
);
4402 if ( !mgsl_device_list
) {
4403 printk("%s(%d):No SyncLink devices found.\n",__FILE__
,__LINE__
);
4406 if ((rc
= mgsl_init_tty()))
4412 static int __init
synclink_init(void)
4414 /* Uncomment this to kernel debug module.
4415 * mgsl_get_text_ptr() leaves the .text address in eax
4416 * which can be used with add-symbol-file with gdb.
4418 if (break_on_load
) {
4419 mgsl_get_text_ptr();
4426 static void __exit
synclink_exit(void)
4428 unsigned long flags
;
4430 struct mgsl_struct
*info
;
4432 printk("Unloading %s: version %s\n", driver_name
, driver_version
);
4435 if ((rc
= tty_unregister_driver(&serial_driver
)))
4436 printk("%s(%d) failed to unregister tty driver err=%d\n",
4437 __FILE__
,__LINE__
,rc
);
4438 if ((rc
= tty_unregister_driver(&callout_driver
)))
4439 printk("%s(%d) failed to unregister callout driver err=%d\n",
4440 __FILE__
,__LINE__
,rc
);
4441 restore_flags(flags
);
4443 info
= mgsl_device_list
;
4445 #ifdef CONFIG_SYNCLINK_SYNCPPP
4446 if (info
->dosyncppp
)
4447 mgsl_sppp_delete(info
);
4449 mgsl_release_resources(info
);
4450 info
= info
->next_device
;
4454 free_page((unsigned long) tmp_buf
);
4458 pci_unregister_driver(&synclink_pci_driver
);
4461 module_init(synclink_init
);
4462 module_exit(synclink_exit
);
4467 * Issue a USC Receive/Transmit command to the
4468 * Channel Command/Address Register (CCAR).
4472 * The command is encoded in the most significant 5 bits <15..11>
4473 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4474 * and Bits <6..0> must be written as zeros.
4478 * info pointer to device information structure
4479 * Cmd command mask (use symbolic macros)
4485 void usc_RTCmd( struct mgsl_struct
*info
, u16 Cmd
)
4487 /* output command to CCAR in bits <15..11> */
4488 /* preserve bits <10..7>, bits <6..0> must be zero */
4490 outw( Cmd
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4492 /* Read to flush write to CCAR */
4493 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4494 inw( info
->io_base
+ CCAR
);
4496 } /* end of usc_RTCmd() */
4501 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4505 * info pointer to device information structure
4506 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4512 void usc_DmaCmd( struct mgsl_struct
*info
, u16 Cmd
)
4514 /* write command mask to DCAR */
4515 outw( Cmd
+ info
->mbre_bit
, info
->io_base
);
4517 /* Read to flush write to DCAR */
4518 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4519 inw( info
->io_base
);
4521 } /* end of usc_DmaCmd() */
4526 * Write a 16-bit value to a USC DMA register
4530 * info pointer to device info structure
4531 * RegAddr register address (number) for write
4532 * RegValue 16-bit value to write to register
4539 void usc_OutDmaReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4541 /* Note: The DCAR is located at the adapter base address */
4542 /* Note: must preserve state of BIT8 in DCAR */
4544 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4545 outw( RegValue
, info
->io_base
);
4547 /* Read to flush write to DCAR */
4548 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4549 inw( info
->io_base
);
4551 } /* end of usc_OutDmaReg() */
4556 * Read a 16-bit value from a DMA register
4560 * info pointer to device info structure
4561 * RegAddr register address (number) to read from
4565 * The 16-bit value read from register
4568 u16
usc_InDmaReg( struct mgsl_struct
*info
, u16 RegAddr
)
4570 /* Note: The DCAR is located at the adapter base address */
4571 /* Note: must preserve state of BIT8 in DCAR */
4573 outw( RegAddr
+ info
->mbre_bit
, info
->io_base
);
4574 return inw( info
->io_base
);
4576 } /* end of usc_InDmaReg() */
4582 * Write a 16-bit value to a USC serial channel register
4586 * info pointer to device info structure
4587 * RegAddr register address (number) to write to
4588 * RegValue 16-bit value to write to register
4595 void usc_OutReg( struct mgsl_struct
*info
, u16 RegAddr
, u16 RegValue
)
4597 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4598 outw( RegValue
, info
->io_base
+ CCAR
);
4600 /* Read to flush write to CCAR */
4601 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4602 inw( info
->io_base
+ CCAR
);
4604 } /* end of usc_OutReg() */
4609 * Reads a 16-bit value from a USC serial channel register
4613 * info pointer to device extension
4614 * RegAddr register address (number) to read from
4618 * 16-bit value read from register
4620 u16
usc_InReg( struct mgsl_struct
*info
, u16 RegAddr
)
4622 outw( RegAddr
+ info
->loopback_bits
, info
->io_base
+ CCAR
);
4623 return inw( info
->io_base
+ CCAR
);
4625 } /* end of usc_InReg() */
4627 /* usc_set_sdlc_mode()
4629 * Set up the adapter for SDLC DMA communications.
4631 * Arguments: info pointer to device instance data
4632 * Return Value: NONE
4634 void usc_set_sdlc_mode( struct mgsl_struct
*info
)
4640 * determine if the IUSC on the adapter is pre-SL1660. If
4641 * not, take advantage of the UnderWait feature of more
4642 * modern chips. If an underrun occurs and this bit is set,
4643 * the transmitter will idle the programmed idle pattern
4644 * until the driver has time to service the underrun. Otherwise,
4645 * the dma controller may get the cycles previously requested
4646 * and begin transmitting queued tx data.
4648 usc_OutReg(info
,TMCR
,0x1f);
4649 RegValue
=usc_InReg(info
,TMDR
);
4650 if ( RegValue
== IUSC_PRE_SL1660
)
4656 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
4659 ** Channel Mode Register (CMR)
4661 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4662 ** <13> 0 0 = Transmit Disabled (initially)
4663 ** <12> 0 1 = Consecutive Idles share common 0
4664 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4665 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4666 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4668 ** 1000 1110 0000 0110 = 0x8e06
4672 /*--------------------------------------------------
4673 * ignore user options for UnderRun Actions and
4675 *--------------------------------------------------*/
4679 /* Channel mode Register (CMR)
4681 * <15..14> 00 Tx Sub modes, Underrun Action
4682 * <13> 0 1 = Send Preamble before opening flag
4683 * <12> 0 1 = Consecutive Idles share common 0
4684 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4685 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4686 * <3..0> 0110 Receiver mode = HDLC/SDLC
4688 * 0000 0110 0000 0110 = 0x0606
4693 if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_ABORT15
)
4695 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_FLAG
)
4697 else if ( info
->params
.flags
& HDLC_FLAG_UNDERRUN_CRC
)
4698 RegValue
|= BIT15
+ BIT14
;
4700 if ( info
->params
.preamble
!= HDLC_PREAMBLE_PATTERN_NONE
)
4704 if ( info
->params
.flags
& HDLC_FLAG_SHARE_ZERO
)
4707 if ( info
->params
.addr_filter
!= 0xff )
4709 /* set up receive address filtering */
4710 usc_OutReg( info
, RSR
, info
->params
.addr_filter
);
4714 usc_OutReg( info
, CMR
, RegValue
);
4715 info
->cmr_value
= RegValue
;
4717 /* Receiver mode Register (RMR)
4719 * <15..13> 000 encoding
4720 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4721 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4722 * <9> 0 1 = Include Receive chars in CRC
4723 * <8> 1 1 = Use Abort/PE bit as abort indicator
4724 * <7..6> 00 Even parity
4725 * <5> 0 parity disabled
4726 * <4..2> 000 Receive Char Length = 8 bits
4727 * <1..0> 00 Disable Receiver
4729 * 0000 0101 0000 0000 = 0x0500
4734 switch ( info
->params
.encoding
) {
4735 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4736 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4737 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4738 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4739 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4740 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4741 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4744 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4746 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
4747 RegValue
|= ( BIT12
| BIT10
| BIT9
);
4749 usc_OutReg( info
, RMR
, RegValue
);
4753 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4754 /* When an opening flag of an SDLC frame is recognized the */
4755 /* Receive Character count (RCC) is loaded with the value in */
4756 /* RCLR. The RCC is decremented for each received byte. The */
4757 /* value of RCC is stored after the closing flag of the frame */
4758 /* allowing the frame size to be computed. */
4760 usc_OutReg( info
, RCLR
, RCLRVALUE
);
4762 usc_RCmd( info
, RCmd_SelectRicrdma_level
);
4764 /* Receive Interrupt Control Register (RICR)
4766 * <15..8> ? RxFIFO DMA Request Level
4767 * <7> 0 Exited Hunt IA (Interrupt Arm)
4768 * <6> 0 Idle Received IA
4769 * <5> 0 Break/Abort IA
4771 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4773 * <1> 1 Rx Overrun IA
4774 * <0> 0 Select TC0 value for readback
4776 * 0000 0000 0000 1000 = 0x000a
4779 /* Carry over the Exit Hunt and Idle Received bits */
4780 /* in case they have been armed by usc_ArmEvents. */
4782 RegValue
= usc_InReg( info
, RICR
) & 0xc0;
4784 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4785 usc_OutReg( info
, RICR
, (u16
)(0x030a | RegValue
) );
4787 usc_OutReg( info
, RICR
, (u16
)(0x140a | RegValue
) );
4789 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4791 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
4792 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
4794 /* Transmit mode Register (TMR)
4796 * <15..13> 000 encoding
4797 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4798 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4799 * <9> 0 1 = Tx CRC Enabled
4800 * <8> 0 1 = Append CRC to end of transmit frame
4801 * <7..6> 00 Transmit parity Even
4802 * <5> 0 Transmit parity Disabled
4803 * <4..2> 000 Tx Char Length = 8 bits
4804 * <1..0> 00 Disable Transmitter
4806 * 0000 0100 0000 0000 = 0x0400
4811 switch ( info
->params
.encoding
) {
4812 case HDLC_ENCODING_NRZB
: RegValue
|= BIT13
; break;
4813 case HDLC_ENCODING_NRZI_MARK
: RegValue
|= BIT14
; break;
4814 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT14
+ BIT13
; break;
4815 case HDLC_ENCODING_BIPHASE_MARK
: RegValue
|= BIT15
; break;
4816 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT15
+ BIT13
; break;
4817 case HDLC_ENCODING_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
; break;
4818 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT15
+ BIT14
+ BIT13
; break;
4821 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
4822 RegValue
|= BIT9
+ BIT8
;
4823 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
4824 RegValue
|= ( BIT12
| BIT10
| BIT9
| BIT8
);
4826 usc_OutReg( info
, TMR
, RegValue
);
4828 usc_set_txidle( info
);
4831 usc_TCmd( info
, TCmd_SelectTicrdma_level
);
4833 /* Transmit Interrupt Control Register (TICR)
4835 * <15..8> ? Transmit FIFO DMA Level
4836 * <7> 0 Present IA (Interrupt Arm)
4837 * <6> 0 Idle Sent IA
4838 * <5> 1 Abort Sent IA
4839 * <4> 1 EOF/EOM Sent IA
4841 * <2> 1 1 = Wait for SW Trigger to Start Frame
4842 * <1> 1 Tx Underrun IA
4843 * <0> 0 TC0 constant on read back
4845 * 0000 0000 0011 0110 = 0x0036
4848 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4849 usc_OutReg( info
, TICR
, 0x0736 );
4851 usc_OutReg( info
, TICR
, 0x1436 );
4853 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
4854 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
4857 ** Transmit Command/Status Register (TCSR)
4859 ** <15..12> 0000 TCmd
4860 ** <11> 0/1 UnderWait
4861 ** <10..08> 000 TxIdle
4865 ** <4> x EOF/EOM Sent
4871 ** 0000 0000 0000 0000 = 0x0000
4873 info
->tcsr_value
= 0;
4876 info
->tcsr_value
|= TCSR_UNDERWAIT
;
4878 usc_OutReg( info
, TCSR
, info
->tcsr_value
);
4880 /* Clock mode Control Register (CMCR)
4882 * <15..14> 00 counter 1 Source = Disabled
4883 * <13..12> 00 counter 0 Source = Disabled
4884 * <11..10> 11 BRG1 Input is TxC Pin
4885 * <9..8> 11 BRG0 Input is TxC Pin
4886 * <7..6> 01 DPLL Input is BRG1 Output
4887 * <5..3> XXX TxCLK comes from Port 0
4888 * <2..0> XXX RxCLK comes from Port 1
4890 * 0000 1111 0111 0111 = 0x0f77
4895 if ( info
->params
.flags
& HDLC_FLAG_RXC_DPLL
)
4896 RegValue
|= 0x0003; /* RxCLK from DPLL */
4897 else if ( info
->params
.flags
& HDLC_FLAG_RXC_BRG
)
4898 RegValue
|= 0x0004; /* RxCLK from BRG0 */
4899 else if ( info
->params
.flags
& HDLC_FLAG_RXC_TXCPIN
)
4900 RegValue
|= 0x0006; /* RxCLK from TXC Input */
4902 RegValue
|= 0x0007; /* RxCLK from Port1 */
4904 if ( info
->params
.flags
& HDLC_FLAG_TXC_DPLL
)
4905 RegValue
|= 0x0018; /* TxCLK from DPLL */
4906 else if ( info
->params
.flags
& HDLC_FLAG_TXC_BRG
)
4907 RegValue
|= 0x0020; /* TxCLK from BRG0 */
4908 else if ( info
->params
.flags
& HDLC_FLAG_TXC_RXCPIN
)
4909 RegValue
|= 0x0038; /* RxCLK from TXC Input */
4911 RegValue
|= 0x0030; /* TxCLK from Port0 */
4913 usc_OutReg( info
, CMCR
, RegValue
);
4916 /* Hardware Configuration Register (HCR)
4918 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
4919 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
4920 * <12> 0 CVOK:0=report code violation in biphase
4921 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
4922 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
4923 * <7..6> 00 reserved
4924 * <5> 0 BRG1 mode:0=continuous,1=single cycle
4926 * <3..2> 00 reserved
4927 * <1> 0 BRG0 mode:0=continuous,1=single cycle
4933 if ( info
->params
.flags
& (HDLC_FLAG_RXC_DPLL
+ HDLC_FLAG_TXC_DPLL
) ) {
4938 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
4939 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
4941 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
4942 XtalSpeed
= 11059200;
4944 XtalSpeed
= 14745600;
4946 if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV16
) {
4950 else if ( info
->params
.flags
& HDLC_FLAG_DPLL_DIV8
) {
4957 /* Tc = (Xtal/Speed) - 1 */
4958 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
4959 /* then rounding up gives a more precise time constant. Instead */
4960 /* of rounding up and then subtracting 1 we just don't subtract */
4961 /* the one in this case. */
4963 /*--------------------------------------------------
4964 * ejz: for DPLL mode, application should use the
4965 * same clock speed as the partner system, even
4966 * though clocking is derived from the input RxData.
4967 * In case the user uses a 0 for the clock speed,
4968 * default to 0xffffffff and don't try to divide by
4970 *--------------------------------------------------*/
4971 if ( info
->params
.clock_speed
)
4973 Tc
= (u16
)((XtalSpeed
/DpllDivisor
)/info
->params
.clock_speed
);
4974 if ( !((((XtalSpeed
/DpllDivisor
) % info
->params
.clock_speed
) * 2)
4975 / info
->params
.clock_speed
) )
4982 /* Write 16-bit Time Constant for BRG1 */
4983 usc_OutReg( info
, TC1R
, Tc
);
4985 RegValue
|= BIT4
; /* enable BRG1 */
4987 switch ( info
->params
.encoding
) {
4988 case HDLC_ENCODING_NRZ
:
4989 case HDLC_ENCODING_NRZB
:
4990 case HDLC_ENCODING_NRZI_MARK
:
4991 case HDLC_ENCODING_NRZI_SPACE
: RegValue
|= BIT8
; break;
4992 case HDLC_ENCODING_BIPHASE_MARK
:
4993 case HDLC_ENCODING_BIPHASE_SPACE
: RegValue
|= BIT9
; break;
4994 case HDLC_ENCODING_BIPHASE_LEVEL
:
4995 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL
: RegValue
|= BIT9
+ BIT8
; break;
4999 usc_OutReg( info
, HCR
, RegValue
);
5002 /* Channel Control/status Register (CCSR)
5004 * <15> X RCC FIFO Overflow status (RO)
5005 * <14> X RCC FIFO Not Empty status (RO)
5006 * <13> 0 1 = Clear RCC FIFO (WO)
5007 * <12> X DPLL Sync (RW)
5008 * <11> X DPLL 2 Missed Clocks status (RO)
5009 * <10> X DPLL 1 Missed Clock status (RO)
5010 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5011 * <7> X SDLC Loop On status (RO)
5012 * <6> X SDLC Loop Send status (RO)
5013 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5014 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5015 * <1..0> 00 reserved
5017 * 0000 0000 0010 0000 = 0x0020
5020 usc_OutReg( info
, CCSR
, 0x1020 );
5023 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
) {
5024 usc_OutReg( info
, SICR
,
5025 (u16
)(usc_InReg(info
,SICR
) | SICR_CTS_INACTIVE
) );
5029 /* enable Master Interrupt Enable bit (MIE) */
5030 usc_EnableMasterIrqBit( info
);
5032 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
+ RECEIVE_DATA
+
5033 TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5036 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5037 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5038 info
->mbre_bit
= BIT8
;
5039 outw( BIT8
, info
->io_base
); /* set Master Bus Enable (DCAR) */
5041 /* Enable DMAEN (Port 7, Bit 14) */
5042 /* This connects the DMA request signal to the ISA bus */
5043 /* on the ISA adapter. This has no effect for the PCI adapter */
5044 usc_OutReg( info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT15
) & ~BIT14
) );
5046 /* DMA Control Register (DCR)
5048 * <15..14> 10 Priority mode = Alternating Tx/Rx
5049 * 01 Rx has priority
5050 * 00 Tx has priority
5052 * <13> 1 Enable Priority Preempt per DCR<15..14>
5053 * (WARNING DCR<11..10> must be 00 when this is 1)
5054 * 0 Choose activate channel per DCR<11..10>
5056 * <12> 0 Little Endian for Array/List
5057 * <11..10> 00 Both Channels can use each bus grant
5058 * <9..6> 0000 reserved
5059 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5060 * <4> 0 1 = drive D/C and S/D pins
5061 * <3> 1 1 = Add one wait state to all DMA cycles.
5062 * <2> 0 1 = Strobe /UAS on every transfer.
5063 * <1..0> 11 Addr incrementing only affects LS24 bits
5065 * 0110 0000 0000 1011 = 0x600b
5068 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5069 /* PCI adapter does not need DMA wait state */
5070 usc_OutDmaReg( info
, DCR
, 0xa00b );
5073 usc_OutDmaReg( info
, DCR
, 0x800b );
5076 /* Receive DMA mode Register (RDMR)
5078 * <15..14> 11 DMA mode = Linked List Buffer mode
5079 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5080 * <12> 1 Clear count of List Entry after fetching
5081 * <11..10> 00 Address mode = Increment
5082 * <9> 1 Terminate Buffer on RxBound
5083 * <8> 0 Bus Width = 16bits
5084 * <7..0> ? status Bits (write as 0s)
5086 * 1111 0010 0000 0000 = 0xf200
5089 usc_OutDmaReg( info
, RDMR
, 0xf200 );
5092 /* Transmit DMA mode Register (TDMR)
5094 * <15..14> 11 DMA mode = Linked List Buffer mode
5095 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5096 * <12> 1 Clear count of List Entry after fetching
5097 * <11..10> 00 Address mode = Increment
5098 * <9> 1 Terminate Buffer on end of frame
5099 * <8> 0 Bus Width = 16bits
5100 * <7..0> ? status Bits (Read Only so write as 0)
5102 * 1111 0010 0000 0000 = 0xf200
5105 usc_OutDmaReg( info
, TDMR
, 0xf200 );
5108 /* DMA Interrupt Control Register (DICR)
5110 * <15> 1 DMA Interrupt Enable
5111 * <14> 0 1 = Disable IEO from USC
5112 * <13> 0 1 = Don't provide vector during IntAck
5113 * <12> 1 1 = Include status in Vector
5114 * <10..2> 0 reserved, Must be 0s
5115 * <1> 0 1 = Rx DMA Interrupt Enabled
5116 * <0> 0 1 = Tx DMA Interrupt Enabled
5118 * 1001 0000 0000 0000 = 0x9000
5121 usc_OutDmaReg( info
, DICR
, 0x9000 );
5123 usc_InDmaReg( info
, RDMR
); /* clear pending receive DMA IRQ bits */
5124 usc_InDmaReg( info
, TDMR
); /* clear pending transmit DMA IRQ bits */
5125 usc_OutDmaReg( info
, CDIR
, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5127 /* Channel Control Register (CCR)
5129 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5130 * <13> 0 Trigger Tx on SW Command Disabled
5131 * <12> 0 Flag Preamble Disabled
5132 * <11..10> 00 Preamble Length
5133 * <9..8> 00 Preamble Pattern
5134 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5135 * <5> 0 Trigger Rx on SW Command Disabled
5138 * 1000 0000 1000 0000 = 0x8080
5143 switch ( info
->params
.preamble_length
) {
5144 case HDLC_PREAMBLE_LENGTH_16BITS
: RegValue
|= BIT10
; break;
5145 case HDLC_PREAMBLE_LENGTH_32BITS
: RegValue
|= BIT11
; break;
5146 case HDLC_PREAMBLE_LENGTH_64BITS
: RegValue
|= BIT11
+ BIT10
; break;
5149 switch ( info
->params
.preamble
) {
5150 case HDLC_PREAMBLE_PATTERN_FLAGS
: RegValue
|= BIT8
+ BIT12
; break;
5151 case HDLC_PREAMBLE_PATTERN_ONES
: RegValue
|= BIT8
; break;
5152 case HDLC_PREAMBLE_PATTERN_10
: RegValue
|= BIT9
; break;
5153 case HDLC_PREAMBLE_PATTERN_01
: RegValue
|= BIT9
+ BIT8
; break;
5156 usc_OutReg( info
, CCR
, RegValue
);
5160 * Burst/Dwell Control Register
5162 * <15..8> 0x20 Maximum number of transfers per bus grant
5163 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5166 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5167 /* don't limit bus occupancy on PCI adapter */
5168 usc_OutDmaReg( info
, BDCR
, 0x0000 );
5171 usc_OutDmaReg( info
, BDCR
, 0x2000 );
5173 usc_stop_transmitter(info
);
5174 usc_stop_receiver(info
);
5176 } /* end of usc_set_sdlc_mode() */
5178 /* usc_enable_loopback()
5180 * Set the 16C32 for internal loopback mode.
5181 * The TxCLK and RxCLK signals are generated from the BRG0 and
5182 * the TxD is looped back to the RxD internally.
5184 * Arguments: info pointer to device instance data
5185 * enable 1 = enable loopback, 0 = disable
5186 * Return Value: None
5188 void usc_enable_loopback(struct mgsl_struct
*info
, int enable
)
5191 /* blank external TXD output */
5192 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) | (BIT7
+BIT6
));
5194 /* Clock mode Control Register (CMCR)
5196 * <15..14> 00 counter 1 Disabled
5197 * <13..12> 00 counter 0 Disabled
5198 * <11..10> 11 BRG1 Input is TxC Pin
5199 * <9..8> 11 BRG0 Input is TxC Pin
5200 * <7..6> 01 DPLL Input is BRG1 Output
5201 * <5..3> 100 TxCLK comes from BRG0
5202 * <2..0> 100 RxCLK comes from BRG0
5204 * 0000 1111 0110 0100 = 0x0f64
5207 usc_OutReg( info
, CMCR
, 0x0f64 );
5209 /* Write 16-bit Time Constant for BRG0 */
5210 /* use clock speed if available, otherwise use 8 for diagnostics */
5211 if (info
->params
.clock_speed
) {
5212 if (info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5213 usc_OutReg(info
, TC0R
, (u16
)((11059200/info
->params
.clock_speed
)-1));
5215 usc_OutReg(info
, TC0R
, (u16
)((14745600/info
->params
.clock_speed
)-1));
5217 usc_OutReg(info
, TC0R
, (u16
)8);
5219 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5220 mode = Continuous Set Bit 0 to enable BRG0. */
5221 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5223 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5224 usc_OutReg(info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004));
5226 /* set Internal Data loopback mode */
5227 info
->loopback_bits
= 0x300;
5228 outw( 0x0300, info
->io_base
+ CCAR
);
5230 /* enable external TXD output */
5231 usc_OutReg(info
,IOCR
,usc_InReg(info
,IOCR
) & ~(BIT7
+BIT6
));
5233 /* clear Internal Data loopback mode */
5234 info
->loopback_bits
= 0;
5235 outw( 0,info
->io_base
+ CCAR
);
5238 } /* end of usc_enable_loopback() */
5240 /* usc_enable_aux_clock()
5242 * Enabled the AUX clock output at the specified frequency.
5246 * info pointer to device extension
5247 * data_rate data rate of clock in bits per second
5248 * A data rate of 0 disables the AUX clock.
5250 * Return Value: None
5252 void usc_enable_aux_clock( struct mgsl_struct
*info
, u32 data_rate
)
5258 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
5259 XtalSpeed
= 11059200;
5261 XtalSpeed
= 14745600;
5264 /* Tc = (Xtal/Speed) - 1 */
5265 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5266 /* then rounding up gives a more precise time constant. Instead */
5267 /* of rounding up and then subtracting 1 we just don't subtract */
5268 /* the one in this case. */
5271 Tc
= (u16
)(XtalSpeed
/data_rate
);
5272 if ( !(((XtalSpeed
% data_rate
) * 2) / data_rate
) )
5275 /* Write 16-bit Time Constant for BRG0 */
5276 usc_OutReg( info
, TC0R
, Tc
);
5279 * Hardware Configuration Register (HCR)
5280 * Clear Bit 1, BRG0 mode = Continuous
5281 * Set Bit 0 to enable BRG0.
5284 usc_OutReg( info
, HCR
, (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
5286 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5287 usc_OutReg( info
, IOCR
, (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
5289 /* data rate == 0 so turn off BRG0 */
5290 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
5293 } /* end of usc_enable_aux_clock() */
5297 * usc_process_rxoverrun_sync()
5299 * This function processes a receive overrun by resetting the
5300 * receive DMA buffers and issuing a Purge Rx FIFO command
5301 * to allow the receiver to continue receiving.
5305 * info pointer to device extension
5307 * Return Value: None
5309 void usc_process_rxoverrun_sync( struct mgsl_struct
*info
)
5313 int frame_start_index
;
5314 int start_of_frame_found
= FALSE
;
5315 int end_of_frame_found
= FALSE
;
5316 int reprogram_dma
= FALSE
;
5318 DMABUFFERENTRY
*buffer_list
= info
->rx_buffer_list
;
5321 usc_DmaCmd( info
, DmaCmd_PauseRxChannel
);
5322 usc_RCmd( info
, RCmd_EnterHuntmode
);
5323 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5325 /* CurrentRxBuffer points to the 1st buffer of the next */
5326 /* possibly available receive frame. */
5328 frame_start_index
= start_index
= end_index
= info
->current_rx_buffer
;
5330 /* Search for an unfinished string of buffers. This means */
5331 /* that a receive frame started (at least one buffer with */
5332 /* count set to zero) but there is no terminiting buffer */
5333 /* (status set to non-zero). */
5335 while( !buffer_list
[end_index
].count
)
5337 /* Count field has been reset to zero by 16C32. */
5338 /* This buffer is currently in use. */
5340 if ( !start_of_frame_found
)
5342 start_of_frame_found
= TRUE
;
5343 frame_start_index
= end_index
;
5344 end_of_frame_found
= FALSE
;
5347 if ( buffer_list
[end_index
].status
)
5349 /* Status field has been set by 16C32. */
5350 /* This is the last buffer of a received frame. */
5352 /* We want to leave the buffers for this frame intact. */
5353 /* Move on to next possible frame. */
5355 start_of_frame_found
= FALSE
;
5356 end_of_frame_found
= TRUE
;
5359 /* advance to next buffer entry in linked list */
5361 if ( end_index
== info
->rx_buffer_count
)
5364 if ( start_index
== end_index
)
5366 /* The entire list has been searched with all Counts == 0 and */
5367 /* all Status == 0. The receive buffers are */
5368 /* completely screwed, reset all receive buffers! */
5369 mgsl_reset_rx_dma_buffers( info
);
5370 frame_start_index
= 0;
5371 start_of_frame_found
= FALSE
;
5372 reprogram_dma
= TRUE
;
5377 if ( start_of_frame_found
&& !end_of_frame_found
)
5379 /* There is an unfinished string of receive DMA buffers */
5380 /* as a result of the receiver overrun. */
5382 /* Reset the buffers for the unfinished frame */
5383 /* and reprogram the receive DMA controller to start */
5384 /* at the 1st buffer of unfinished frame. */
5386 start_index
= frame_start_index
;
5390 *((unsigned long *)&(info
->rx_buffer_list
[start_index
++].count
)) = DMABUFFERSIZE
;
5392 /* Adjust index for wrap around. */
5393 if ( start_index
== info
->rx_buffer_count
)
5396 } while( start_index
!= end_index
);
5398 reprogram_dma
= TRUE
;
5401 if ( reprogram_dma
)
5403 usc_UnlatchRxstatusBits(info
,RXSTATUS_ALL
);
5404 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5405 usc_UnlatchRxstatusBits(info
, RECEIVE_DATA
|RECEIVE_STATUS
);
5407 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5409 /* This empties the receive FIFO and loads the RCC with RCLR */
5410 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5412 /* program 16C32 with physical address of 1st DMA buffer entry */
5413 phys_addr
= info
->rx_buffer_list
[frame_start_index
].phys_entry
;
5414 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5415 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5417 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5418 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5419 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5421 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5422 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5424 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5425 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5426 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5427 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5428 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5430 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5434 /* This empties the receive FIFO and loads the RCC with RCLR */
5435 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5436 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5439 } /* end of usc_process_rxoverrun_sync() */
5441 /* usc_stop_receiver()
5443 * Disable USC receiver
5445 * Arguments: info pointer to device instance data
5446 * Return Value: None
5448 void usc_stop_receiver( struct mgsl_struct
*info
)
5450 if (debug_level
>= DEBUG_LEVEL_ISR
)
5451 printk("%s(%d):usc_stop_receiver(%s)\n",
5452 __FILE__
,__LINE__
, info
->device_name
);
5454 /* Disable receive DMA channel. */
5455 /* This also disables receive DMA channel interrupts */
5456 usc_DmaCmd( info
, DmaCmd_ResetRxChannel
);
5458 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5459 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5460 usc_DisableInterrupts( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5462 usc_EnableReceiver(info
,DISABLE_UNCONDITIONAL
);
5464 /* This empties the receive FIFO and loads the RCC with RCLR */
5465 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5466 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5468 info
->rx_enabled
= 0;
5469 info
->rx_overflow
= 0;
5471 } /* end of stop_receiver() */
5473 /* usc_start_receiver()
5475 * Enable the USC receiver
5477 * Arguments: info pointer to device instance data
5478 * Return Value: None
5480 void usc_start_receiver( struct mgsl_struct
*info
)
5484 if (debug_level
>= DEBUG_LEVEL_ISR
)
5485 printk("%s(%d):usc_start_receiver(%s)\n",
5486 __FILE__
,__LINE__
, info
->device_name
);
5488 mgsl_reset_rx_dma_buffers( info
);
5489 usc_stop_receiver( info
);
5491 usc_OutReg( info
, CCSR
, (u16
)(usc_InReg(info
,CCSR
) | BIT13
) );
5492 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5494 if ( info
->params
.mode
== MGSL_MODE_HDLC
) {
5495 /* DMA mode Transfers */
5496 /* Program the DMA controller. */
5497 /* Enable the DMA controller end of buffer interrupt. */
5499 /* program 16C32 with physical address of 1st DMA buffer entry */
5500 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
5501 usc_OutDmaReg( info
, NRARL
, (u16
)phys_addr
);
5502 usc_OutDmaReg( info
, NRARU
, (u16
)(phys_addr
>> 16) );
5504 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5505 usc_ClearIrqPendingBits( info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5506 usc_EnableInterrupts( info
, RECEIVE_STATUS
);
5508 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5509 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5511 usc_OutDmaReg( info
, RDIAR
, BIT3
+ BIT2
);
5512 usc_OutDmaReg( info
, DICR
, (u16
)(usc_InDmaReg(info
,DICR
) | BIT1
) );
5513 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
5514 if ( info
->params
.flags
& HDLC_FLAG_AUTO_DCD
)
5515 usc_EnableReceiver(info
,ENABLE_AUTO_DCD
);
5517 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5519 usc_UnlatchRxstatusBits(info
, RXSTATUS_ALL
);
5520 usc_ClearIrqPendingBits(info
, RECEIVE_DATA
+ RECEIVE_STATUS
);
5521 usc_EnableInterrupts(info
, RECEIVE_DATA
);
5523 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
5524 usc_RCmd( info
, RCmd_EnterHuntmode
);
5526 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
5529 usc_OutReg( info
, CCSR
, 0x1020 );
5531 info
->rx_enabled
= 1;
5533 } /* end of usc_start_receiver() */
5535 /* usc_start_transmitter()
5537 * Enable the USC transmitter and send a transmit frame if
5538 * one is loaded in the DMA buffers.
5540 * Arguments: info pointer to device instance data
5541 * Return Value: None
5543 void usc_start_transmitter( struct mgsl_struct
*info
)
5546 unsigned int FrameSize
;
5548 if (debug_level
>= DEBUG_LEVEL_ISR
)
5549 printk("%s(%d):usc_start_transmitter(%s)\n",
5550 __FILE__
,__LINE__
, info
->device_name
);
5552 if ( info
->xmit_cnt
) {
5554 /* If auto RTS enabled and RTS is inactive, then assert */
5555 /* RTS and set a flag indicating that the driver should */
5556 /* negate RTS when the transmission completes. */
5558 info
->drop_rts_on_tx_done
= 0;
5560 if ( info
->params
.flags
& HDLC_FLAG_AUTO_RTS
) {
5561 usc_get_serial_signals( info
);
5562 if ( !(info
->serial_signals
& SerialSignal_RTS
) ) {
5563 info
->serial_signals
|= SerialSignal_RTS
;
5564 usc_set_serial_signals( info
);
5565 info
->drop_rts_on_tx_done
= 1;
5570 if ( info
->params
.mode
== MGSL_MODE_ASYNC
) {
5571 if ( !info
->tx_active
) {
5572 usc_UnlatchTxstatusBits(info
, TXSTATUS_ALL
);
5573 usc_ClearIrqPendingBits(info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5574 usc_EnableInterrupts(info
, TRANSMIT_DATA
);
5575 usc_load_txfifo(info
);
5578 /* Disable transmit DMA controller while programming. */
5579 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5581 /* Transmit DMA buffer is loaded, so program USC */
5582 /* to send the frame contained in the buffers. */
5585 FrameSize
= info
->tx_buffer_list
[0].rcc
;
5587 /* Program the Transmit Character Length Register (TCLR) */
5588 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5589 usc_OutReg( info
, TCLR
, (u16
)FrameSize
);
5591 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5593 /* Program the address of the 1st DMA Buffer Entry in linked list */
5594 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
5595 usc_OutDmaReg( info
, NTARL
, (u16
)phys_addr
);
5596 usc_OutDmaReg( info
, NTARU
, (u16
)(phys_addr
>> 16) );
5598 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5599 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5600 usc_EnableInterrupts( info
, TRANSMIT_STATUS
);
5602 /* Initialize Transmit DMA Channel */
5603 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
5605 usc_TCmd( info
, TCmd_SendFrame
);
5607 info
->tx_timer
.expires
= jiffies
+ jiffies_from_ms(5000);
5608 add_timer(&info
->tx_timer
);
5610 info
->tx_active
= 1;
5613 if ( !info
->tx_enabled
) {
5614 info
->tx_enabled
= 1;
5615 if ( info
->params
.flags
& HDLC_FLAG_AUTO_CTS
)
5616 usc_EnableTransmitter(info
,ENABLE_AUTO_CTS
);
5618 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
5621 } /* end of usc_start_transmitter() */
5623 /* usc_stop_transmitter()
5625 * Stops the transmitter and DMA
5627 * Arguments: info pointer to device isntance data
5628 * Return Value: None
5630 void usc_stop_transmitter( struct mgsl_struct
*info
)
5632 if (debug_level
>= DEBUG_LEVEL_ISR
)
5633 printk("%s(%d):usc_stop_transmitter(%s)\n",
5634 __FILE__
,__LINE__
, info
->device_name
);
5636 del_timer(&info
->tx_timer
);
5638 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5639 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5640 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
);
5642 usc_EnableTransmitter(info
,DISABLE_UNCONDITIONAL
);
5643 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
5644 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
5646 info
->tx_enabled
= 0;
5647 info
->tx_active
= 0;
5649 } /* end of usc_stop_transmitter() */
5651 /* usc_load_txfifo()
5653 * Fill the transmit FIFO until the FIFO is full or
5654 * there is no more data to load.
5656 * Arguments: info pointer to device extension (instance data)
5657 * Return Value: None
5659 void usc_load_txfifo( struct mgsl_struct
*info
)
5664 if ( !info
->xmit_cnt
&& !info
->x_char
)
5667 /* Select transmit FIFO status readback in TICR */
5668 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
5670 /* load the Transmit FIFO until FIFOs full or all data sent */
5672 while( (Fifocount
= usc_InReg(info
, TICR
) >> 8) && info
->xmit_cnt
) {
5673 /* there is more space in the transmit FIFO and */
5674 /* there is more data in transmit buffer */
5676 if ( (info
->xmit_cnt
> 1) && (Fifocount
> 1) && !info
->x_char
) {
5677 /* write a 16-bit word from transmit buffer to 16C32 */
5679 TwoBytes
[0] = info
->xmit_buf
[info
->xmit_tail
++];
5680 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5681 TwoBytes
[1] = info
->xmit_buf
[info
->xmit_tail
++];
5682 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5684 outw( *((u16
*)TwoBytes
), info
->io_base
+ DATAREG
);
5686 info
->xmit_cnt
-= 2;
5687 info
->icount
.tx
+= 2;
5689 /* only 1 byte left to transmit or 1 FIFO slot left */
5691 outw( (inw( info
->io_base
+ CCAR
) & 0x0780) | (TDR
+LSBONLY
),
5692 info
->io_base
+ CCAR
);
5695 /* transmit pending high priority char */
5696 outw( info
->x_char
,info
->io_base
+ CCAR
);
5699 outw( info
->xmit_buf
[info
->xmit_tail
++],info
->io_base
+ CCAR
);
5700 info
->xmit_tail
= info
->xmit_tail
& (SERIAL_XMIT_SIZE
-1);
5707 } /* end of usc_load_txfifo() */
5711 * Reset the adapter to a known state and prepare it for further use.
5713 * Arguments: info pointer to device instance data
5714 * Return Value: None
5716 void usc_reset( struct mgsl_struct
*info
)
5718 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
) {
5722 /* Set BIT30 of Misc Control Register */
5723 /* (Local Control Register 0x50) to force reset of USC. */
5725 volatile u32
*MiscCtrl
= (u32
*)(info
->lcr_base
+ 0x50);
5726 u32
*LCR0BRDR
= (u32
*)(info
->lcr_base
+ 0x28);
5728 info
->misc_ctrl_value
|= BIT30
;
5729 *MiscCtrl
= info
->misc_ctrl_value
;
5732 * Force at least 170ns delay before clearing
5733 * reset bit. Each read from LCR takes at least
5734 * 30ns so 10 times for 300ns to be safe.
5737 readval
= *MiscCtrl
;
5739 info
->misc_ctrl_value
&= ~BIT30
;
5740 *MiscCtrl
= info
->misc_ctrl_value
;
5742 *LCR0BRDR
= BUS_DESCRIPTOR(
5743 1, // Write Strobe Hold (0-3)
5744 2, // Write Strobe Delay (0-3)
5745 2, // Read Strobe Delay (0-3)
5746 0, // NWDD (Write data-data) (0-3)
5747 4, // NWAD (Write Addr-data) (0-31)
5748 0, // NXDA (Read/Write Data-Addr) (0-3)
5749 0, // NRDD (Read Data-Data) (0-3)
5750 5 // NRAD (Read Addr-Data) (0-31)
5754 outb( 0,info
->io_base
+ 8 );
5758 info
->loopback_bits
= 0;
5759 info
->usc_idle_mode
= 0;
5762 * Program the Bus Configuration Register (BCR)
5764 * <15> 0 Don't use seperate address
5765 * <14..6> 0 reserved
5766 * <5..4> 00 IAckmode = Default, don't care
5767 * <3> 1 Bus Request Totem Pole output
5768 * <2> 1 Use 16 Bit data bus
5769 * <1> 0 IRQ Totem Pole output
5770 * <0> 0 Don't Shift Right Addr
5772 * 0000 0000 0000 1100 = 0x000c
5774 * By writing to io_base + SDPIN the Wait/Ack pin is
5775 * programmed to work as a Wait pin.
5778 outw( 0x000c,info
->io_base
+ SDPIN
);
5781 outw( 0,info
->io_base
);
5782 outw( 0,info
->io_base
+ CCAR
);
5784 /* select little endian byte ordering */
5785 usc_RTCmd( info
, RTCmd_SelectLittleEndian
);
5788 /* Port Control Register (PCR)
5790 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5791 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5792 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5793 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5794 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5795 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5796 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5797 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5799 * 1111 0000 1111 0101 = 0xf0f5
5802 usc_OutReg( info
, PCR
, 0xf0f5 );
5806 * Input/Output Control Register
5808 * <15..14> 00 CTS is active low input
5809 * <13..12> 00 DCD is active low input
5810 * <11..10> 00 TxREQ pin is input (DSR)
5811 * <9..8> 00 RxREQ pin is input (RI)
5812 * <7..6> 00 TxD is output (Transmit Data)
5813 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5814 * <2..0> 100 RxC is Output (drive with BRG0)
5816 * 0000 0000 0000 0100 = 0x0004
5819 usc_OutReg( info
, IOCR
, 0x0004 );
5821 } /* end of usc_reset() */
5823 /* usc_set_async_mode()
5825 * Program adapter for asynchronous communications.
5827 * Arguments: info pointer to device instance data
5828 * Return Value: None
5830 void usc_set_async_mode( struct mgsl_struct
*info
)
5834 /* disable interrupts while programming USC */
5835 usc_DisableMasterIrqBit( info
);
5837 outw( 0, info
->io_base
); /* clear Master Bus Enable (DCAR) */
5838 usc_DmaCmd( info
, DmaCmd_ResetAllChannels
); /* disable both DMA channels */
5840 usc_loopback_frame( info
);
5842 /* Channel mode Register (CMR)
5844 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5845 * <13..12> 00 00 = 16X Clock
5846 * <11..8> 0000 Transmitter mode = Asynchronous
5847 * <7..6> 00 reserved?
5848 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5849 * <3..0> 0000 Receiver mode = Asynchronous
5851 * 0000 0000 0000 0000 = 0x0
5855 if ( info
->params
.stop_bits
!= 1 )
5857 usc_OutReg( info
, CMR
, RegValue
);
5860 /* Receiver mode Register (RMR)
5862 * <15..13> 000 encoding = None
5863 * <12..08> 00000 reserved (Sync Only)
5864 * <7..6> 00 Even parity
5865 * <5> 0 parity disabled
5866 * <4..2> 000 Receive Char Length = 8 bits
5867 * <1..0> 00 Disable Receiver
5869 * 0000 0000 0000 0000 = 0x0
5874 if ( info
->params
.data_bits
!= 8 )
5875 RegValue
|= BIT4
+BIT3
+BIT2
;
5877 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5879 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5883 usc_OutReg( info
, RMR
, RegValue
);
5886 /* Set IRQ trigger level */
5888 usc_RCmd( info
, RCmd_SelectRicrIntLevel
);
5891 /* Receive Interrupt Control Register (RICR)
5893 * <15..8> ? RxFIFO IRQ Request Level
5895 * Note: For async mode the receive FIFO level must be set
5896 * to 0 to aviod the situation where the FIFO contains fewer bytes
5897 * than the trigger level and no more data is expected.
5899 * <7> 0 Exited Hunt IA (Interrupt Arm)
5900 * <6> 0 Idle Received IA
5901 * <5> 0 Break/Abort IA
5903 * <3> 0 Queued status reflects oldest byte in FIFO
5905 * <1> 0 Rx Overrun IA
5906 * <0> 0 Select TC0 value for readback
5908 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
5911 usc_OutReg( info
, RICR
, 0x0000 );
5913 usc_UnlatchRxstatusBits( info
, RXSTATUS_ALL
);
5914 usc_ClearIrqPendingBits( info
, RECEIVE_STATUS
);
5917 /* Transmit mode Register (TMR)
5919 * <15..13> 000 encoding = None
5920 * <12..08> 00000 reserved (Sync Only)
5921 * <7..6> 00 Transmit parity Even
5922 * <5> 0 Transmit parity Disabled
5923 * <4..2> 000 Tx Char Length = 8 bits
5924 * <1..0> 00 Disable Transmitter
5926 * 0000 0000 0000 0000 = 0x0
5931 if ( info
->params
.data_bits
!= 8 )
5932 RegValue
|= BIT4
+BIT3
+BIT2
;
5934 if ( info
->params
.parity
!= ASYNC_PARITY_NONE
) {
5936 if ( info
->params
.parity
!= ASYNC_PARITY_ODD
)
5940 usc_OutReg( info
, TMR
, RegValue
);
5942 usc_set_txidle( info
);
5945 /* Set IRQ trigger level */
5947 usc_TCmd( info
, TCmd_SelectTicrIntLevel
);
5950 /* Transmit Interrupt Control Register (TICR)
5952 * <15..8> ? Transmit FIFO IRQ Level
5953 * <7> 0 Present IA (Interrupt Arm)
5954 * <6> 1 Idle Sent IA
5955 * <5> 0 Abort Sent IA
5956 * <4> 0 EOF/EOM Sent IA
5958 * <2> 0 1 = Wait for SW Trigger to Start Frame
5959 * <1> 0 Tx Underrun IA
5960 * <0> 0 TC0 constant on read back
5962 * 0000 0000 0100 0000 = 0x0040
5965 usc_OutReg( info
, TICR
, 0x1f40 );
5967 usc_UnlatchTxstatusBits( info
, TXSTATUS_ALL
);
5968 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
);
5970 usc_enable_async_clock( info
, info
->params
.data_rate
);
5973 /* Channel Control/status Register (CCSR)
5975 * <15> X RCC FIFO Overflow status (RO)
5976 * <14> X RCC FIFO Not Empty status (RO)
5977 * <13> 0 1 = Clear RCC FIFO (WO)
5978 * <12> X DPLL in Sync status (RO)
5979 * <11> X DPLL 2 Missed Clocks status (RO)
5980 * <10> X DPLL 1 Missed Clock status (RO)
5981 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5982 * <7> X SDLC Loop On status (RO)
5983 * <6> X SDLC Loop Send status (RO)
5984 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5985 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5986 * <1..0> 00 reserved
5988 * 0000 0000 0010 0000 = 0x0020
5991 usc_OutReg( info
, CCSR
, 0x0020 );
5993 usc_DisableInterrupts( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
5994 RECEIVE_DATA
+ RECEIVE_STATUS
);
5996 usc_ClearIrqPendingBits( info
, TRANSMIT_STATUS
+ TRANSMIT_DATA
+
5997 RECEIVE_DATA
+ RECEIVE_STATUS
);
5999 usc_EnableMasterIrqBit( info
);
6001 /* Enable INTEN (Port 6, Bit12) */
6002 /* This connects the IRQ request signal to the ISA bus */
6003 /* on the ISA adapter. This has no effect for the PCI adapter */
6004 usc_OutReg( info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
6006 } /* end of usc_set_async_mode() */
6008 /* usc_loopback_frame()
6010 * Loop back a small (2 byte) dummy SDLC frame.
6011 * Interrupts and DMA are NOT used. The purpose of this is to
6012 * clear any 'stale' status info left over from running in async mode.
6014 * The 16C32 shows the strange behaviour of marking the 1st
6015 * received SDLC frame with a CRC error even when there is no
6016 * CRC error. To get around this a small dummy from of 2 bytes
6017 * is looped back when switching from async to sync mode.
6019 * Arguments: info pointer to device instance data
6020 * Return Value: None
6022 void usc_loopback_frame( struct mgsl_struct
*info
)
6026 usc_DisableMasterIrqBit( info
);
6028 usc_set_sdlc_mode( info
);
6029 usc_enable_loopback( info
, 1 );
6031 /* Write 16-bit Time Constant for BRG0 */
6032 usc_OutReg( info
, TC0R
, 0 );
6034 /* Channel Control Register (CCR)
6036 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6037 * <13> 0 Trigger Tx on SW Command Disabled
6038 * <12> 0 Flag Preamble Disabled
6039 * <11..10> 00 Preamble Length = 8-Bits
6040 * <9..8> 01 Preamble Pattern = flags
6041 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6042 * <5> 0 Trigger Rx on SW Command Disabled
6045 * 0000 0001 0000 0000 = 0x0100
6048 usc_OutReg( info
, CCR
, 0x0100 );
6050 /* SETUP RECEIVER */
6051 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6052 usc_EnableReceiver(info
,ENABLE_UNCONDITIONAL
);
6054 /* SETUP TRANSMITTER */
6055 /* Program the Transmit Character Length Register (TCLR) */
6056 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6057 usc_OutReg( info
, TCLR
, 2 );
6058 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6060 /* unlatch Tx status bits, and start transmit channel. */
6061 usc_UnlatchTxstatusBits(info
,TXSTATUS_ALL
);
6062 outw(0,info
->io_base
+ DATAREG
);
6064 /* ENABLE TRANSMITTER */
6065 usc_TCmd( info
, TCmd_SendFrame
);
6066 usc_EnableTransmitter(info
,ENABLE_UNCONDITIONAL
);
6068 /* WAIT FOR RECEIVE COMPLETE */
6069 for (i
=0 ; i
<1000 ; i
++)
6070 if (usc_InReg( info
, RCSR
) & (BIT8
+ BIT4
+ BIT3
+ BIT1
))
6073 /* clear Internal Data loopback mode */
6074 usc_enable_loopback(info
, 0);
6076 usc_EnableMasterIrqBit(info
);
6078 } /* end of usc_loopback_frame() */
6080 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6082 * Arguments: info pointer to adapter info structure
6083 * Return Value: None
6085 void usc_set_sync_mode( struct mgsl_struct
*info
)
6087 usc_loopback_frame( info
);
6088 usc_set_sdlc_mode( info
);
6090 /* Enable INTEN (Port 6, Bit12) */
6091 /* This connects the IRQ request signal to the ISA bus */
6092 /* on the ISA adapter. This has no effect for the PCI adapter */
6093 usc_OutReg(info
, PCR
, (u16
)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
));
6095 usc_enable_aux_clock(info
, info
->params
.clock_speed
);
6097 if (info
->params
.loopback
)
6098 usc_enable_loopback(info
,1);
6100 } /* end of mgsl_set_sync_mode() */
6102 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6104 * Arguments: info pointer to device instance data
6105 * Return Value: None
6107 void usc_set_txidle( struct mgsl_struct
*info
)
6109 u16 usc_idle_mode
= IDLEMODE_FLAGS
;
6111 /* Map API idle mode to USC register bits */
6113 switch( info
->idle_mode
){
6114 case HDLC_TXIDLE_FLAGS
: usc_idle_mode
= IDLEMODE_FLAGS
; break;
6115 case HDLC_TXIDLE_ALT_ZEROS_ONES
: usc_idle_mode
= IDLEMODE_ALT_ONE_ZERO
; break;
6116 case HDLC_TXIDLE_ZEROS
: usc_idle_mode
= IDLEMODE_ZERO
; break;
6117 case HDLC_TXIDLE_ONES
: usc_idle_mode
= IDLEMODE_ONE
; break;
6118 case HDLC_TXIDLE_ALT_MARK_SPACE
: usc_idle_mode
= IDLEMODE_ALT_MARK_SPACE
; break;
6119 case HDLC_TXIDLE_SPACE
: usc_idle_mode
= IDLEMODE_SPACE
; break;
6120 case HDLC_TXIDLE_MARK
: usc_idle_mode
= IDLEMODE_MARK
; break;
6123 info
->usc_idle_mode
= usc_idle_mode
;
6124 //usc_OutReg(info, TCSR, usc_idle_mode);
6125 info
->tcsr_value
&= ~IDLEMODE_MASK
; /* clear idle mode bits */
6126 info
->tcsr_value
+= usc_idle_mode
;
6127 usc_OutReg(info
, TCSR
, info
->tcsr_value
);
6129 } /* end of usc_set_txidle() */
6131 /* usc_get_serial_signals()
6133 * Query the adapter for the state of the V24 status (input) signals.
6135 * Arguments: info pointer to device instance data
6136 * Return Value: None
6138 void usc_get_serial_signals( struct mgsl_struct
*info
)
6142 /* clear all serial signals except DTR and RTS */
6143 info
->serial_signals
&= SerialSignal_DTR
+ SerialSignal_RTS
;
6145 /* Read the Misc Interrupt status Register (MISR) to get */
6146 /* the V24 status signals. */
6148 status
= usc_InReg( info
, MISR
);
6150 /* set serial signal bits to reflect MISR */
6152 if ( status
& MISCSTATUS_CTS
)
6153 info
->serial_signals
|= SerialSignal_CTS
;
6155 if ( status
& MISCSTATUS_DCD
)
6156 info
->serial_signals
|= SerialSignal_DCD
;
6158 if ( status
& MISCSTATUS_RI
)
6159 info
->serial_signals
|= SerialSignal_RI
;
6161 if ( status
& MISCSTATUS_DSR
)
6162 info
->serial_signals
|= SerialSignal_DSR
;
6164 } /* end of usc_get_serial_signals() */
6166 /* usc_set_serial_signals()
6168 * Set the state of DTR and RTS based on contents of
6169 * serial_signals member of device extension.
6171 * Arguments: info pointer to device instance data
6172 * Return Value: None
6174 void usc_set_serial_signals( struct mgsl_struct
*info
)
6177 unsigned char V24Out
= info
->serial_signals
;
6179 /* get the current value of the Port Control Register (PCR) */
6181 Control
= usc_InReg( info
, PCR
);
6183 if ( V24Out
& SerialSignal_RTS
)
6188 if ( V24Out
& SerialSignal_DTR
)
6193 usc_OutReg( info
, PCR
, Control
);
6195 } /* end of usc_set_serial_signals() */
6197 /* usc_enable_async_clock()
6199 * Enable the async clock at the specified frequency.
6201 * Arguments: info pointer to device instance data
6202 * data_rate data rate of clock in bps
6203 * 0 disables the AUX clock.
6204 * Return Value: None
6206 void usc_enable_async_clock( struct mgsl_struct
*info
, u32 data_rate
)
6210 * Clock mode Control Register (CMCR)
6212 * <15..14> 00 counter 1 Disabled
6213 * <13..12> 00 counter 0 Disabled
6214 * <11..10> 11 BRG1 Input is TxC Pin
6215 * <9..8> 11 BRG0 Input is TxC Pin
6216 * <7..6> 01 DPLL Input is BRG1 Output
6217 * <5..3> 100 TxCLK comes from BRG0
6218 * <2..0> 100 RxCLK comes from BRG0
6220 * 0000 1111 0110 0100 = 0x0f64
6223 usc_OutReg( info
, CMCR
, 0x0f64 );
6227 * Write 16-bit Time Constant for BRG0
6228 * Time Constant = (ClkSpeed / data_rate) - 1
6229 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6232 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6233 usc_OutReg( info
, TC0R
, (u16
)((691200/data_rate
) - 1) );
6235 usc_OutReg( info
, TC0R
, (u16
)((921600/data_rate
) - 1) );
6239 * Hardware Configuration Register (HCR)
6240 * Clear Bit 1, BRG0 mode = Continuous
6241 * Set Bit 0 to enable BRG0.
6244 usc_OutReg( info
, HCR
,
6245 (u16
)((usc_InReg( info
, HCR
) & ~BIT1
) | BIT0
) );
6248 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6250 usc_OutReg( info
, IOCR
,
6251 (u16
)((usc_InReg(info
, IOCR
) & 0xfff8) | 0x0004) );
6253 /* data rate == 0 so turn off BRG0 */
6254 usc_OutReg( info
, HCR
, (u16
)(usc_InReg( info
, HCR
) & ~BIT0
) );
6257 } /* end of usc_enable_async_clock() */
6260 * Buffer Structures:
6262 * Normal memory access uses virtual addresses that can make discontiguous
6263 * physical memory pages appear to be contiguous in the virtual address
6264 * space (the processors memory mapping handles the conversions).
6266 * DMA transfers require physically contiguous memory. This is because
6267 * the DMA system controller and DMA bus masters deal with memory using
6268 * only physical addresses.
6270 * This causes a problem under Windows NT when large DMA buffers are
6271 * needed. Fragmentation of the nonpaged pool prevents allocations of
6272 * physically contiguous buffers larger than the PAGE_SIZE.
6274 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6275 * allows DMA transfers to physically discontiguous buffers. Information
6276 * about each data transfer buffer is contained in a memory structure
6277 * called a 'buffer entry'. A list of buffer entries is maintained
6278 * to track and control the use of the data transfer buffers.
6280 * To support this strategy we will allocate sufficient PAGE_SIZE
6281 * contiguous memory buffers to allow for the total required buffer
6284 * The 16C32 accesses the list of buffer entries using Bus Master
6285 * DMA. Control information is read from the buffer entries by the
6286 * 16C32 to control data transfers. status information is written to
6287 * the buffer entries by the 16C32 to indicate the status of completed
6290 * The CPU writes control information to the buffer entries to control
6291 * the 16C32 and reads status information from the buffer entries to
6292 * determine information about received and transmitted frames.
6294 * Because the CPU and 16C32 (adapter) both need simultaneous access
6295 * to the buffer entries, the buffer entry memory is allocated with
6296 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6297 * entry list to PAGE_SIZE.
6299 * The actual data buffers on the other hand will only be accessed
6300 * by the CPU or the adapter but not by both simultaneously. This allows
6301 * Scatter/Gather packet based DMA procedures for using physically
6302 * discontiguous pages.
6306 * mgsl_reset_rx_dma_buffers()
6308 * Set the count for all receive buffers to DMABUFFERSIZE
6309 * and set the current buffer to the first buffer. This effectively
6310 * makes all buffers free and discards any data in buffers.
6312 * Arguments: info pointer to device instance data
6313 * Return Value: None
6315 void mgsl_reset_rx_dma_buffers( struct mgsl_struct
*info
)
6319 for ( i
= 0; i
< info
->rx_buffer_count
; i
++ ) {
6320 *((unsigned long *)&(info
->rx_buffer_list
[i
].count
)) = DMABUFFERSIZE
;
6321 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6322 // info->rx_buffer_list[i].status = 0;
6325 info
->current_rx_buffer
= 0;
6327 } /* end of mgsl_reset_rx_dma_buffers() */
6330 * mgsl_free_rx_frame_buffers()
6332 * Free the receive buffers used by a received SDLC
6333 * frame such that the buffers can be reused.
6337 * info pointer to device instance data
6338 * StartIndex index of 1st receive buffer of frame
6339 * EndIndex index of last receive buffer of frame
6341 * Return Value: None
6343 void mgsl_free_rx_frame_buffers( struct mgsl_struct
*info
, unsigned int StartIndex
, unsigned int EndIndex
)
6346 DMABUFFERENTRY
*pBufEntry
;
6349 /* Starting with 1st buffer entry of the frame clear the status */
6350 /* field and set the count field to DMA Buffer Size. */
6355 pBufEntry
= &(info
->rx_buffer_list
[Index
]);
6357 if ( Index
== EndIndex
) {
6358 /* This is the last buffer of the frame! */
6362 /* reset current buffer for reuse */
6363 // pBufEntry->status = 0;
6364 // pBufEntry->count = DMABUFFERSIZE;
6365 *((unsigned long *)&(pBufEntry
->count
)) = DMABUFFERSIZE
;
6367 /* advance to next buffer entry in linked list */
6369 if ( Index
== info
->rx_buffer_count
)
6373 /* set current buffer to next buffer after last buffer of frame */
6374 info
->current_rx_buffer
= Index
;
6376 } /* end of free_rx_frame_buffers() */
6378 /* mgsl_get_rx_frame()
6380 * This function attempts to return a received SDLC frame from the
6381 * receive DMA buffers. Only frames received without errors are returned.
6383 * Arguments: info pointer to device extension
6384 * Return Value: 1 if frame returned, otherwise 0
6386 int mgsl_get_rx_frame(struct mgsl_struct
*info
)
6388 unsigned int StartIndex
, EndIndex
; /* index of 1st and last buffers of Rx frame */
6389 unsigned short status
;
6390 DMABUFFERENTRY
*pBufEntry
;
6391 unsigned int framesize
;
6393 unsigned long flags
;
6394 struct tty_struct
*tty
= info
->tty
;
6397 * current_rx_buffer points to the 1st buffer of the next available
6398 * receive frame. To find the last buffer of the frame look for
6399 * a non-zero status field in the buffer entries. (The status
6400 * field is set by the 16C32 after completing a receive frame.
6403 StartIndex
= EndIndex
= info
->current_rx_buffer
;
6405 while( !info
->rx_buffer_list
[EndIndex
].status
) {
6407 * If the count field of the buffer entry is non-zero then
6408 * this buffer has not been used. (The 16C32 clears the count
6409 * field when it starts using the buffer.) If an unused buffer
6410 * is encountered then there are no frames available.
6413 if ( info
->rx_buffer_list
[EndIndex
].count
)
6416 /* advance to next buffer entry in linked list */
6418 if ( EndIndex
== info
->rx_buffer_count
)
6421 /* if entire list searched then no frame available */
6422 if ( EndIndex
== StartIndex
) {
6423 /* If this occurs then something bad happened,
6424 * all buffers have been 'used' but none mark
6425 * the end of a frame. Reset buffers and receiver.
6428 if ( info
->rx_enabled
){
6429 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6430 usc_start_receiver(info
);
6431 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6438 /* check status of receive frame */
6440 status
= info
->rx_buffer_list
[EndIndex
].status
;
6442 if ( status
& (RXSTATUS_SHORT_FRAME
+ RXSTATUS_OVERRUN
+
6443 RXSTATUS_CRC_ERROR
+ RXSTATUS_ABORT
) ) {
6444 if ( status
& RXSTATUS_SHORT_FRAME
)
6445 info
->icount
.rxshort
++;
6446 else if ( status
& RXSTATUS_ABORT
)
6447 info
->icount
.rxabort
++;
6448 else if ( status
& RXSTATUS_OVERRUN
)
6449 info
->icount
.rxover
++;
6451 info
->icount
.rxcrc
++;
6453 #ifdef CONFIG_SYNCLINK_SYNCPPP
6454 info
->netstats
.rx_errors
++;
6455 info
->netstats
.rx_frame_errors
++;
6458 /* receive frame has no errors, get frame size.
6459 * The frame size is the starting value of the RCC (which was
6460 * set to 0xffff) minus the ending value of the RCC (decremented
6461 * once for each receive character) minus 2 for the 16-bit CRC.
6464 framesize
= RCLRVALUE
- info
->rx_buffer_list
[EndIndex
].rcc
;
6466 /* adjust frame size for CRC if any */
6467 if ( info
->params
.crc_type
== HDLC_CRC_16_CCITT
)
6469 else if ( info
->params
.crc_type
== HDLC_CRC_32_CCITT
)
6473 if ( debug_level
>= DEBUG_LEVEL_BH
)
6474 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6475 __FILE__
,__LINE__
,info
->device_name
,status
,framesize
);
6477 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6478 mgsl_trace_block(info
,info
->rx_buffer_list
[StartIndex
].virt_addr
,
6479 MIN(framesize
,DMABUFFERSIZE
),0);
6482 if (framesize
> info
->max_frame_size
)
6483 info
->icount
.rxlong
++;
6485 /* copy dma buffer(s) to contiguous intermediate buffer */
6486 int copy_count
= framesize
;
6487 int index
= StartIndex
;
6488 unsigned char *ptmp
= info
->intermediate_rxbuffer
;
6490 info
->icount
.rxok
++;
6494 if ( copy_count
> DMABUFFERSIZE
)
6495 partial_count
= DMABUFFERSIZE
;
6497 partial_count
= copy_count
;
6499 pBufEntry
= &(info
->rx_buffer_list
[index
]);
6500 memcpy( ptmp
, pBufEntry
->virt_addr
, partial_count
);
6501 ptmp
+= partial_count
;
6502 copy_count
-= partial_count
;
6504 if ( ++index
== info
->rx_buffer_count
)
6508 #ifdef CONFIG_SYNCLINK_SYNCPPP
6509 if (info
->netcount
) {
6510 /* pass frame to syncppp device */
6511 mgsl_sppp_rx_done(info
,info
->intermediate_rxbuffer
,framesize
);
6516 /* Call the line discipline receive callback directly. */
6517 tty
->ldisc
.receive_buf(tty
, info
->intermediate_rxbuffer
, info
->flag_buf
, framesize
);
6521 /* Free the buffers used by this frame. */
6522 mgsl_free_rx_frame_buffers( info
, StartIndex
, EndIndex
);
6528 if ( info
->rx_enabled
&& info
->rx_overflow
) {
6529 /* The receiver needs to restarted because of
6530 * a receive overflow (buffer or FIFO). If the
6531 * receive buffers are now empty, then restart receiver.
6534 if ( !info
->rx_buffer_list
[EndIndex
].status
&&
6535 info
->rx_buffer_list
[EndIndex
].count
) {
6536 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6537 usc_start_receiver(info
);
6538 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6544 } /* end of mgsl_get_rx_frame() */
6546 /* mgsl_load_tx_dma_buffer()
6548 * Load the transmit DMA buffer with the specified data.
6552 * info pointer to device extension
6553 * Buffer pointer to buffer containing frame to load
6554 * BufferSize size in bytes of frame in Buffer
6556 * Return Value: None
6558 void mgsl_load_tx_dma_buffer(struct mgsl_struct
*info
, const char *Buffer
,
6559 unsigned int BufferSize
)
6561 unsigned short Copycount
;
6563 DMABUFFERENTRY
*pBufEntry
;
6565 if ( debug_level
>= DEBUG_LEVEL_DATA
)
6566 mgsl_trace_block(info
,Buffer
, MIN(BufferSize
,DMABUFFERSIZE
), 1);
6568 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
6569 /* set CMR:13 to start transmit when
6570 * next GoAhead (abort) is received
6572 info
->cmr_value
|= BIT13
;
6575 /* Setup the status and RCC (Frame Size) fields of the 1st */
6576 /* buffer entry in the transmit DMA buffer list. */
6578 info
->tx_buffer_list
[0].status
= info
->cmr_value
& 0xf000;
6579 info
->tx_buffer_list
[0].rcc
= BufferSize
;
6580 info
->tx_buffer_list
[0].count
= BufferSize
;
6582 /* Copy frame data from 1st source buffer to the DMA buffers. */
6583 /* The frame data may span multiple DMA buffers. */
6585 while( BufferSize
){
6586 /* Get a pointer to next DMA buffer entry. */
6587 pBufEntry
= &info
->tx_buffer_list
[i
++];
6589 /* Calculate the number of bytes that can be copied from */
6590 /* the source buffer to this DMA buffer. */
6591 if ( BufferSize
> DMABUFFERSIZE
)
6592 Copycount
= DMABUFFERSIZE
;
6594 Copycount
= BufferSize
;
6596 /* Actually copy data from source buffer to DMA buffer. */
6597 /* Also set the data count for this individual DMA buffer. */
6598 if ( info
->bus_type
== MGSL_BUS_TYPE_PCI
)
6599 mgsl_load_pci_memory(pBufEntry
->virt_addr
, Buffer
,Copycount
);
6601 memcpy(pBufEntry
->virt_addr
, Buffer
, Copycount
);
6603 pBufEntry
->count
= Copycount
;
6605 /* Advance source pointer and reduce remaining data count. */
6606 Buffer
+= Copycount
;
6607 BufferSize
-= Copycount
;
6610 } /* end of mgsl_load_tx_dma_buffer() */
6613 * mgsl_register_test()
6615 * Performs a register test of the 16C32.
6617 * Arguments: info pointer to device instance data
6618 * Return Value: TRUE if test passed, otherwise FALSE
6620 BOOLEAN
mgsl_register_test( struct mgsl_struct
*info
)
6622 static unsigned short BitPatterns
[] =
6623 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
6624 static unsigned int Patterncount
= sizeof(BitPatterns
)/sizeof(unsigned short);
6627 unsigned long flags
;
6629 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6632 /* Verify the reset state of some registers. */
6634 if ( (usc_InReg( info
, SICR
) != 0) ||
6635 (usc_InReg( info
, IVR
) != 0) ||
6636 (usc_InDmaReg( info
, DIVR
) != 0) ){
6641 /* Write bit patterns to various registers but do it out of */
6642 /* sync, then read back and verify values. */
6644 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
6645 usc_OutReg( info
, TC0R
, BitPatterns
[i
] );
6646 usc_OutReg( info
, TC1R
, BitPatterns
[(i
+1)%Patterncount
] );
6647 usc_OutReg( info
, TCLR
, BitPatterns
[(i
+2)%Patterncount
] );
6648 usc_OutReg( info
, RCLR
, BitPatterns
[(i
+3)%Patterncount
] );
6649 usc_OutReg( info
, RSR
, BitPatterns
[(i
+4)%Patterncount
] );
6650 usc_OutDmaReg( info
, TBCR
, BitPatterns
[(i
+5)%Patterncount
] );
6652 if ( (usc_InReg( info
, TC0R
) != BitPatterns
[i
]) ||
6653 (usc_InReg( info
, TC1R
) != BitPatterns
[(i
+1)%Patterncount
]) ||
6654 (usc_InReg( info
, TCLR
) != BitPatterns
[(i
+2)%Patterncount
]) ||
6655 (usc_InReg( info
, RCLR
) != BitPatterns
[(i
+3)%Patterncount
]) ||
6656 (usc_InReg( info
, RSR
) != BitPatterns
[(i
+4)%Patterncount
]) ||
6657 (usc_InDmaReg( info
, TBCR
) != BitPatterns
[(i
+5)%Patterncount
]) ){
6665 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6669 } /* end of mgsl_register_test() */
6671 /* mgsl_irq_test() Perform interrupt test of the 16C32.
6673 * Arguments: info pointer to device instance data
6674 * Return Value: TRUE if test passed, otherwise FALSE
6676 BOOLEAN
mgsl_irq_test( struct mgsl_struct
*info
)
6678 unsigned long EndTime
;
6679 unsigned long flags
;
6681 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6685 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
6686 * The ISR sets irq_occurred to 1.
6689 info
->irq_occurred
= FALSE
;
6691 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
6692 /* Enable INTEN (Port 6, Bit12) */
6693 /* This connects the IRQ request signal to the ISA bus */
6694 /* on the ISA adapter. This has no effect for the PCI adapter */
6695 usc_OutReg( info
, PCR
, (unsigned short)((usc_InReg(info
, PCR
) | BIT13
) & ~BIT12
) );
6697 usc_EnableMasterIrqBit(info
);
6698 usc_EnableInterrupts(info
, IO_PIN
);
6699 usc_ClearIrqPendingBits(info
, IO_PIN
);
6701 usc_UnlatchIostatusBits(info
, MISCSTATUS_TXC_LATCHED
);
6702 usc_EnableStatusIrqs(info
, SICR_TXC_ACTIVE
+ SICR_TXC_INACTIVE
);
6704 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6707 while( EndTime
-- && !info
->irq_occurred
) {
6708 set_current_state(TASK_INTERRUPTIBLE
);
6709 schedule_timeout(jiffies_from_ms(10));
6712 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6714 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6716 if ( !info
->irq_occurred
)
6721 } /* end of mgsl_irq_test() */
6725 * Perform a DMA test of the 16C32. A small frame is
6726 * transmitted via DMA from a transmit buffer to a receive buffer
6727 * using single buffer DMA mode.
6729 * Arguments: info pointer to device instance data
6730 * Return Value: TRUE if test passed, otherwise FALSE
6732 BOOLEAN
mgsl_dma_test( struct mgsl_struct
*info
)
6734 unsigned short FifoLevel
;
6735 unsigned long phys_addr
;
6736 unsigned int FrameSize
;
6740 unsigned short status
;
6741 unsigned long EndTime
;
6742 unsigned long flags
;
6743 MGSL_PARAMS tmp_params
;
6745 /* save current port options */
6746 memcpy(&tmp_params
,&info
->params
,sizeof(MGSL_PARAMS
));
6747 /* load default port options */
6748 memcpy(&info
->params
,&default_params
,sizeof(MGSL_PARAMS
));
6750 #define TESTFRAMESIZE 40
6752 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6754 /* setup 16C32 for SDLC DMA transfer mode */
6757 usc_set_sdlc_mode(info
);
6758 usc_enable_loopback(info
,1);
6760 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
6761 * field of the buffer entry after fetching buffer address. This
6762 * way we can detect a DMA failure for a DMA read (which should be
6763 * non-destructive to system memory) before we try and write to
6764 * memory (where a failure could corrupt system memory).
6767 /* Receive DMA mode Register (RDMR)
6769 * <15..14> 11 DMA mode = Linked List Buffer mode
6770 * <13> 1 RSBinA/L = store Rx status Block in List entry
6771 * <12> 0 1 = Clear count of List Entry after fetching
6772 * <11..10> 00 Address mode = Increment
6773 * <9> 1 Terminate Buffer on RxBound
6774 * <8> 0 Bus Width = 16bits
6775 * <7..0> ? status Bits (write as 0s)
6777 * 1110 0010 0000 0000 = 0xe200
6780 usc_OutDmaReg( info
, RDMR
, 0xe200 );
6782 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6785 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
6787 FrameSize
= TESTFRAMESIZE
;
6789 /* setup 1st transmit buffer entry: */
6790 /* with frame size and transmit control word */
6792 info
->tx_buffer_list
[0].count
= FrameSize
;
6793 info
->tx_buffer_list
[0].rcc
= FrameSize
;
6794 info
->tx_buffer_list
[0].status
= 0x4000;
6796 /* build a transmit frame in 1st transmit DMA buffer */
6798 TmpPtr
= info
->tx_buffer_list
[0].virt_addr
;
6799 for (i
= 0; i
< FrameSize
; i
++ )
6802 /* setup 1st receive buffer entry: */
6803 /* clear status, set max receive buffer size */
6805 info
->rx_buffer_list
[0].status
= 0;
6806 info
->rx_buffer_list
[0].count
= FrameSize
+ 4;
6808 /* zero out the 1st receive buffer */
6810 memset( info
->rx_buffer_list
[0].virt_addr
, 0, FrameSize
+ 4 );
6812 /* Set count field of next buffer entries to prevent */
6813 /* 16C32 from using buffers after the 1st one. */
6815 info
->tx_buffer_list
[1].count
= 0;
6816 info
->rx_buffer_list
[1].count
= 0;
6819 /***************************/
6820 /* Program 16C32 receiver. */
6821 /***************************/
6823 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6825 /* setup DMA transfers */
6826 usc_RTCmd( info
, RTCmd_PurgeRxFifo
);
6828 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
6829 phys_addr
= info
->rx_buffer_list
[0].phys_entry
;
6830 usc_OutDmaReg( info
, NRARL
, (unsigned short)phys_addr
);
6831 usc_OutDmaReg( info
, NRARU
, (unsigned short)(phys_addr
>> 16) );
6833 /* Clear the Rx DMA status bits (read RDMR) and start channel */
6834 usc_InDmaReg( info
, RDMR
);
6835 usc_DmaCmd( info
, DmaCmd_InitRxChannel
);
6837 /* Enable Receiver (RMR <1..0> = 10) */
6838 usc_OutReg( info
, RMR
, (unsigned short)((usc_InReg(info
, RMR
) & 0xfffc) | 0x0002) );
6840 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6843 /*************************************************************/
6844 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
6845 /*************************************************************/
6847 /* Wait 100ms for interrupt. */
6848 EndTime
= jiffies
+ jiffies_from_ms(100);
6851 if ( jiffies
> EndTime
) {
6856 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6857 status
= usc_InDmaReg( info
, RDMR
);
6858 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6860 if ( !(status
& BIT4
) && (status
& BIT5
) ) {
6861 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
6862 /* BUSY (BIT 5) is active (channel still active). */
6863 /* This means the buffer entry read has completed. */
6869 /******************************/
6870 /* Program 16C32 transmitter. */
6871 /******************************/
6873 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6875 /* Program the Transmit Character Length Register (TCLR) */
6876 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6878 usc_OutReg( info
, TCLR
, (unsigned short)info
->tx_buffer_list
[0].count
);
6879 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
6881 /* Program the address of the 1st DMA Buffer Entry in linked list */
6883 phys_addr
= info
->tx_buffer_list
[0].phys_entry
;
6884 usc_OutDmaReg( info
, NTARL
, (unsigned short)phys_addr
);
6885 usc_OutDmaReg( info
, NTARU
, (unsigned short)(phys_addr
>> 16) );
6887 /* unlatch Tx status bits, and start transmit channel. */
6889 usc_OutReg( info
, TCSR
, (unsigned short)(( usc_InReg(info
, TCSR
) & 0x0f00) | 0xfa) );
6890 usc_DmaCmd( info
, DmaCmd_InitTxChannel
);
6892 /* wait for DMA controller to fill transmit FIFO */
6894 usc_TCmd( info
, TCmd_SelectTicrTxFifostatus
);
6896 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6899 /**********************************/
6900 /* WAIT FOR TRANSMIT FIFO TO FILL */
6901 /**********************************/
6904 EndTime
= jiffies
+ jiffies_from_ms(100);
6907 if ( jiffies
> EndTime
) {
6912 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6913 FifoLevel
= usc_InReg(info
, TICR
) >> 8;
6914 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6916 if ( FifoLevel
< 16 )
6919 if ( FrameSize
< 32 ) {
6920 /* This frame is smaller than the entire transmit FIFO */
6921 /* so wait for the entire frame to be loaded. */
6922 if ( FifoLevel
<= (32 - FrameSize
) )
6930 /* Enable 16C32 transmitter. */
6932 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6934 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
6935 usc_TCmd( info
, TCmd_SendFrame
);
6936 usc_OutReg( info
, TMR
, (unsigned short)((usc_InReg(info
, TMR
) & 0xfffc) | 0x0002) );
6938 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6941 /******************************/
6942 /* WAIT FOR TRANSMIT COMPLETE */
6943 /******************************/
6946 EndTime
= jiffies
+ jiffies_from_ms(100);
6948 /* While timer not expired wait for transmit complete */
6950 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6951 status
= usc_InReg( info
, TCSR
);
6952 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6954 while ( !(status
& (BIT6
+BIT5
+BIT4
+BIT2
+BIT1
)) ) {
6955 if ( jiffies
> EndTime
) {
6960 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
6961 status
= usc_InReg( info
, TCSR
);
6962 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
6968 /* CHECK FOR TRANSMIT ERRORS */
6969 if ( status
& (BIT5
+ BIT1
) )
6974 /* WAIT FOR RECEIVE COMPLETE */
6977 EndTime
= jiffies
+ jiffies_from_ms(100);
6979 /* Wait for 16C32 to write receive status to buffer entry. */
6980 status
=info
->rx_buffer_list
[0].status
;
6981 while ( status
== 0 ) {
6982 if ( jiffies
> EndTime
) {
6983 printk(KERN_ERR
"mark 4\n");
6987 status
=info
->rx_buffer_list
[0].status
;
6993 /* CHECK FOR RECEIVE ERRORS */
6994 status
= info
->rx_buffer_list
[0].status
;
6996 if ( status
& (BIT8
+ BIT3
+ BIT1
) ) {
6997 /* receive error has occured */
7000 if ( memcmp( info
->tx_buffer_list
[0].virt_addr
,
7001 info
->rx_buffer_list
[0].virt_addr
, FrameSize
) ){
7007 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7009 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7011 /* restore current port options */
7012 memcpy(&info
->params
,&tmp_params
,sizeof(MGSL_PARAMS
));
7016 } /* end of mgsl_dma_test() */
7018 /* mgsl_adapter_test()
7020 * Perform the register, IRQ, and DMA tests for the 16C32.
7022 * Arguments: info pointer to device instance data
7023 * Return Value: 0 if success, otherwise -ENODEV
7025 int mgsl_adapter_test( struct mgsl_struct
*info
)
7027 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7028 printk( "%s(%d):Testing device %s\n",
7029 __FILE__
,__LINE__
,info
->device_name
);
7031 if ( !mgsl_register_test( info
) ) {
7032 info
->init_error
= DiagStatus_AddressFailure
;
7033 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7034 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->io_base
) );
7038 if ( !mgsl_irq_test( info
) ) {
7039 info
->init_error
= DiagStatus_IrqFailure
;
7040 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7041 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->irq_level
) );
7045 if ( !mgsl_dma_test( info
) ) {
7046 info
->init_error
= DiagStatus_DmaFailure
;
7047 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7048 __FILE__
,__LINE__
,info
->device_name
, (unsigned short)(info
->dma_level
) );
7052 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7053 printk( "%s(%d):device %s passed diagnostics\n",
7054 __FILE__
,__LINE__
,info
->device_name
);
7058 } /* end of mgsl_adapter_test() */
7060 /* mgsl_memory_test()
7062 * Test the shared memory on a PCI adapter.
7064 * Arguments: info pointer to device instance data
7065 * Return Value: TRUE if test passed, otherwise FALSE
7067 BOOLEAN
mgsl_memory_test( struct mgsl_struct
*info
)
7069 static unsigned long BitPatterns
[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7070 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7071 unsigned long Patterncount
= sizeof(BitPatterns
)/sizeof(unsigned long);
7073 unsigned long TestLimit
= SHARED_MEM_ADDRESS_SIZE
/sizeof(unsigned long);
7074 unsigned long * TestAddr
;
7076 if ( info
->bus_type
!= MGSL_BUS_TYPE_PCI
)
7079 TestAddr
= (unsigned long *)info
->memory_base
;
7081 /* Test data lines with test pattern at one location. */
7083 for ( i
= 0 ; i
< Patterncount
; i
++ ) {
7084 *TestAddr
= BitPatterns
[i
];
7085 if ( *TestAddr
!= BitPatterns
[i
] )
7089 /* Test address lines with incrementing pattern over */
7090 /* entire address range. */
7092 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7097 TestAddr
= (unsigned long *)info
->memory_base
;
7099 for ( i
= 0 ; i
< TestLimit
; i
++ ) {
7100 if ( *TestAddr
!= i
* 4 )
7105 memset( info
->memory_base
, 0, SHARED_MEM_ADDRESS_SIZE
);
7109 } /* End Of mgsl_memory_test() */
7112 /* mgsl_load_pci_memory()
7114 * Load a large block of data into the PCI shared memory.
7115 * Use this instead of memcpy() or memmove() to move data
7116 * into the PCI shared memory.
7120 * This function prevents the PCI9050 interface chip from hogging
7121 * the adapter local bus, which can starve the 16C32 by preventing
7122 * 16C32 bus master cycles.
7124 * The PCI9050 documentation says that the 9050 will always release
7125 * control of the local bus after completing the current read
7126 * or write operation.
7128 * It appears that as long as the PCI9050 write FIFO is full, the
7129 * PCI9050 treats all of the writes as a single burst transaction
7130 * and will not release the bus. This causes DMA latency problems
7131 * at high speeds when copying large data blocks to the shared
7134 * This function in effect, breaks the a large shared memory write
7135 * into multiple transations by interleaving a shared memory read
7136 * which will flush the write FIFO and 'complete' the write
7137 * transation. This allows any pending DMA request to gain control
7138 * of the local bus in a timely fasion.
7142 * TargetPtr pointer to target address in PCI shared memory
7143 * SourcePtr pointer to source buffer for data
7144 * count count in bytes of data to copy
7146 * Return Value: None
7148 void mgsl_load_pci_memory( char* TargetPtr
, const char* SourcePtr
,
7149 unsigned short count
)
7151 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7152 #define PCI_LOAD_INTERVAL 64
7154 unsigned short Intervalcount
= count
/ PCI_LOAD_INTERVAL
;
7155 unsigned short Index
;
7156 unsigned long Dummy
;
7158 for ( Index
= 0 ; Index
< Intervalcount
; Index
++ )
7160 memcpy(TargetPtr
, SourcePtr
, PCI_LOAD_INTERVAL
);
7161 Dummy
= *((volatile unsigned long *)TargetPtr
);
7162 TargetPtr
+= PCI_LOAD_INTERVAL
;
7163 SourcePtr
+= PCI_LOAD_INTERVAL
;
7166 memcpy( TargetPtr
, SourcePtr
, count
% PCI_LOAD_INTERVAL
);
7168 } /* End Of mgsl_load_pci_memory() */
7170 void mgsl_trace_block(struct mgsl_struct
*info
,const char* data
, int count
, int xmit
)
7175 printk("%s tx data:\n",info
->device_name
);
7177 printk("%s rx data:\n",info
->device_name
);
7185 for(i
=0;i
<linecount
;i
++)
7186 printk("%02X ",(unsigned char)data
[i
]);
7189 for(i
=0;i
<linecount
;i
++) {
7190 if (data
[i
]>=040 && data
[i
]<=0176)
7191 printk("%c",data
[i
]);
7200 } /* end of mgsl_trace_block() */
7202 /* mgsl_tx_timeout()
7204 * called when HDLC frame times out
7205 * update stats and do tx completion processing
7207 * Arguments: context pointer to device instance data
7208 * Return Value: None
7210 void mgsl_tx_timeout(unsigned long context
)
7212 struct mgsl_struct
*info
= (struct mgsl_struct
*)context
;
7213 unsigned long flags
;
7215 if ( debug_level
>= DEBUG_LEVEL_INFO
)
7216 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7217 __FILE__
,__LINE__
,info
->device_name
);
7218 if(info
->tx_active
&& info
->params
.mode
== MGSL_MODE_HDLC
) {
7219 info
->icount
.txtimeout
++;
7221 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7222 info
->tx_active
= 0;
7223 info
->xmit_cnt
= info
->xmit_head
= info
->xmit_tail
= 0;
7225 if ( info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
)
7226 usc_loopmode_cancel_transmit( info
);
7228 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7230 #ifdef CONFIG_SYNCLINK_SYNCPPP
7232 mgsl_sppp_tx_done(info
);
7235 mgsl_bh_transmit(info
);
7237 } /* end of mgsl_tx_timeout() */
7239 /* signal that there are no more frames to send, so that
7240 * line is 'released' by echoing RxD to TxD when current
7241 * transmission is complete (or immediately if no tx in progress).
7243 static int mgsl_loopmode_send_done( struct mgsl_struct
* info
)
7245 unsigned long flags
;
7247 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7248 if (info
->params
.flags
& HDLC_FLAG_HDLC_LOOPMODE
) {
7249 if (info
->tx_active
)
7250 info
->loopmode_send_done_requested
= TRUE
;
7252 usc_loopmode_send_done(info
);
7254 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7259 /* release the line by echoing RxD to TxD
7260 * upon completion of a transmit frame
7262 void usc_loopmode_send_done( struct mgsl_struct
* info
)
7264 info
->loopmode_send_done_requested
= FALSE
;
7265 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7266 info
->cmr_value
&= ~BIT13
;
7267 usc_OutReg(info
, CMR
, info
->cmr_value
);
7270 /* abort a transmit in progress while in HDLC LoopMode
7272 void usc_loopmode_cancel_transmit( struct mgsl_struct
* info
)
7274 /* reset tx dma channel and purge TxFifo */
7275 usc_RTCmd( info
, RTCmd_PurgeTxFifo
);
7276 usc_DmaCmd( info
, DmaCmd_ResetTxChannel
);
7277 usc_loopmode_send_done( info
);
7280 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7281 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7282 * we must clear CMR:13 to begin repeating TxData to RxData
7284 void usc_loopmode_insert_request( struct mgsl_struct
* info
)
7286 info
->loopmode_insert_requested
= TRUE
;
7288 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7289 * begin repeating TxData on RxData (complete insertion)
7291 usc_OutReg( info
, RICR
,
7292 (usc_InReg( info
, RICR
) | RXSTATUS_ABORT_RECEIVED
) );
7294 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7295 info
->cmr_value
|= BIT13
;
7296 usc_OutReg(info
, CMR
, info
->cmr_value
);
7299 /* return 1 if station is inserted into the loop, otherwise 0
7301 int usc_loopmode_active( struct mgsl_struct
* info
)
7303 return usc_InReg( info
, CCSR
) & BIT7
? 1 : 0 ;
7306 /* return 1 if USC is in loop send mode, otherwise 0
7308 int usc_loopmode_send_active( struct mgsl_struct
* info
)
7310 return usc_InReg( info
, CCSR
) & BIT6
? 1 : 0 ;
7313 #ifdef CONFIG_SYNCLINK_SYNCPPP
7314 /* syncppp net device routines
7317 void mgsl_sppp_init(struct mgsl_struct
*info
)
7319 struct net_device
*d
;
7321 sprintf(info
->netname
,"mgsl%d",info
->line
);
7323 info
->if_ptr
= &info
->pppdev
;
7324 info
->netdev
= info
->pppdev
.dev
= &info
->netdevice
;
7326 sppp_attach(&info
->pppdev
);
7329 strcpy(d
->name
,info
->netname
);
7330 d
->base_addr
= info
->io_base
;
7331 d
->irq
= info
->irq_level
;
7332 d
->dma
= info
->dma_level
;
7335 d
->open
= mgsl_sppp_open
;
7336 d
->stop
= mgsl_sppp_close
;
7337 d
->hard_start_xmit
= mgsl_sppp_tx
;
7338 d
->do_ioctl
= mgsl_sppp_ioctl
;
7339 d
->get_stats
= mgsl_net_stats
;
7340 d
->tx_timeout
= mgsl_sppp_tx_timeout
;
7341 d
->watchdog_timeo
= 10*HZ
;
7343 dev_init_buffers(d
);
7345 if (register_netdev(d
) == -1) {
7346 printk(KERN_WARNING
"%s: register_netdev failed.\n", d
->name
);
7347 sppp_detach(info
->netdev
);
7351 if (debug_level
>= DEBUG_LEVEL_INFO
)
7352 printk("mgsl_sppp_init()\n");
7355 void mgsl_sppp_delete(struct mgsl_struct
*info
)
7357 if (debug_level
>= DEBUG_LEVEL_INFO
)
7358 printk("mgsl_sppp_delete(%s)\n",info
->netname
);
7359 sppp_detach(info
->netdev
);
7360 unregister_netdev(info
->netdev
);
7363 int mgsl_sppp_open(struct net_device
*d
)
7365 struct mgsl_struct
*info
= d
->priv
;
7368 if (debug_level
>= DEBUG_LEVEL_INFO
)
7369 printk("mgsl_sppp_open(%s)\n",info
->netname
);
7371 spin_lock_irqsave(&info
->netlock
, flags
);
7372 if (info
->count
!= 0 || info
->netcount
!= 0) {
7373 printk(KERN_WARNING
"%s: sppp_open returning busy\n", info
->netname
);
7374 spin_unlock_irqrestore(&info
->netlock
, flags
);
7379 spin_unlock_irqrestore(&info
->netlock
, flags
);
7381 /* claim resources and init adapter */
7382 if ((err
= startup(info
)) != 0)
7385 /* allow syncppp module to do open processing */
7386 if ((err
= sppp_open(d
)) != 0) {
7391 info
->serial_signals
|= SerialSignal_RTS
+ SerialSignal_DTR
;
7392 mgsl_program_hw(info
);
7394 d
->trans_start
= jiffies
;
7395 netif_start_queue(d
);
7399 spin_lock_irqsave(&info
->netlock
, flags
);
7402 spin_unlock_irqrestore(&info
->netlock
, flags
);
7406 void mgsl_sppp_tx_timeout(struct net_device
*dev
)
7408 struct mgsl_struct
*info
= dev
->priv
;
7411 if (debug_level
>= DEBUG_LEVEL_INFO
)
7412 printk("mgsl_sppp_tx_timeout(%s)\n",info
->netname
);
7414 info
->netstats
.tx_errors
++;
7415 info
->netstats
.tx_aborted_errors
++;
7417 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7418 usc_stop_transmitter(info
);
7419 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7421 netif_wake_queue(dev
);
7424 int mgsl_sppp_tx(struct sk_buff
*skb
, struct net_device
*dev
)
7426 struct mgsl_struct
*info
= dev
->priv
;
7427 unsigned long flags
;
7429 if (debug_level
>= DEBUG_LEVEL_INFO
)
7430 printk("mgsl_sppp_tx(%s)\n",info
->netname
);
7432 netif_stop_queue(dev
);
7434 info
->xmit_cnt
= skb
->len
;
7435 mgsl_load_tx_dma_buffer(info
, skb
->data
, skb
->len
);
7436 info
->netstats
.tx_packets
++;
7437 info
->netstats
.tx_bytes
+= skb
->len
;
7440 dev
->trans_start
= jiffies
;
7442 spin_lock_irqsave(&info
->irq_spinlock
,flags
);
7443 if (!info
->tx_active
)
7444 usc_start_transmitter(info
);
7445 spin_unlock_irqrestore(&info
->irq_spinlock
,flags
);
7450 int mgsl_sppp_close(struct net_device
*d
)
7452 struct mgsl_struct
*info
= d
->priv
;
7453 unsigned long flags
;
7455 if (debug_level
>= DEBUG_LEVEL_INFO
)
7456 printk("mgsl_sppp_close(%s)\n",info
->netname
);
7458 /* shutdown adapter and release resources */
7461 /* allow syncppp to do close processing */
7463 netif_stop_queue(d
);
7465 spin_lock_irqsave(&info
->netlock
, flags
);
7468 spin_unlock_irqrestore(&info
->netlock
, flags
);
7472 void mgsl_sppp_rx_done(struct mgsl_struct
*info
, char *buf
, int size
)
7474 struct sk_buff
*skb
= dev_alloc_skb(size
);
7475 if (debug_level
>= DEBUG_LEVEL_INFO
)
7476 printk("mgsl_sppp_rx_done(%s)\n",info
->netname
);
7478 printk(KERN_NOTICE
"%s: cant alloc skb, dropping packet\n",
7480 info
->netstats
.rx_dropped
++;
7484 memcpy(skb_put(skb
, size
),buf
,size
);
7486 skb
->protocol
= htons(ETH_P_WAN_PPP
);
7487 skb
->dev
= info
->netdev
;
7488 skb
->mac
.raw
= skb
->data
;
7489 info
->netstats
.rx_packets
++;
7490 info
->netstats
.rx_bytes
+= size
;
7492 info
->netdev
->trans_start
= jiffies
;
7495 void mgsl_sppp_tx_done(struct mgsl_struct
*info
)
7497 if (netif_queue_stopped(info
->netdev
))
7498 netif_wake_queue(info
->netdev
);
7501 struct net_device_stats
*mgsl_net_stats(struct net_device
*dev
)
7503 struct mgsl_struct
*info
= dev
->priv
;
7504 if (debug_level
>= DEBUG_LEVEL_INFO
)
7505 printk("mgsl_net_stats(%s)\n",info
->netname
);
7506 return &info
->netstats
;
7509 int mgsl_sppp_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
7511 struct mgsl_struct
*info
= (struct mgsl_struct
*)dev
->priv
;
7512 if (debug_level
>= DEBUG_LEVEL_INFO
)
7513 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__
,__LINE__
,
7514 info
->netname
, cmd
);
7515 return sppp_do_ioctl(dev
, ifr
, cmd
);
7518 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
7520 static int __init
synclink_init_one (struct pci_dev
*dev
,
7521 const struct pci_device_id
*ent
)
7523 struct mgsl_struct
*info
;
7525 if (pci_enable_device(dev
)) {
7526 printk("error enabling pci device %p\n", dev
);
7530 if (!(info
= mgsl_allocate_device())) {
7531 printk("can't allocate device instance data.\n");
7535 /* Copy user configuration info to device instance data */
7537 info
->io_base
= pci_resource_start(dev
, 2);
7538 info
->irq_level
= dev
->irq
;
7539 info
->phys_memory_base
= pci_resource_start(dev
, 3);
7541 /* Because veremap only works on page boundaries we must map
7542 * a larger area than is actually implemented for the LCR
7543 * memory range. We map a full page starting at the page boundary.
7545 info
->phys_lcr_base
= pci_resource_start(dev
, 0);
7546 info
->lcr_offset
= info
->phys_lcr_base
& (PAGE_SIZE
-1);
7547 info
->phys_lcr_base
&= ~(PAGE_SIZE
-1);
7549 info
->bus_type
= MGSL_BUS_TYPE_PCI
;
7550 info
->io_addr_size
= 8;
7551 info
->irq_flags
= SA_SHIRQ
;
7553 /* Store the PCI9050 misc control register value because a flaw
7554 * in the PCI9050 prevents LCR registers from being read if
7555 * BIOS assigns an LCR base address with bit 7 set.
7557 * Only the misc control register is accessed for which only
7558 * write access is needed, so set an initial value and change
7559 * bits to the device instance data as we write the value
7560 * to the actual misc control register.
7562 info
->misc_ctrl_value
= 0x087e4546;
7564 mgsl_add_device(info
);
7569 static void __exit
synclink_remove_one (struct pci_dev
*dev
)