soc/intel/braswell: Correct configuration of interrupts
[coreboot.git] / Documentation / arch / 
tree2bf5bd4cdf4e9b4c2487877355ea3411b860badd
drwxr-xr-x   ..
-rw-r--r-- 218 index.md
drwxr-xr-x - riscv
drwxr-xr-x - x86