| blob | dfe10769d8565ae8d1bb7e57c8c2bcca2c6c20a1 |
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2009 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
16 /* DefinitionBlock Statement */
17 DefinitionBlock (
18 "DSDT.AML", /* Output filename */
19 "DSDT", /* Signature */
20 0x02, /* DSDT Revision, needs to be 2 for 64bit */
21 "AMD ", /* OEMID */
22 "COREBOOT", /* TABLE ID */
23 0x00010001 /* OEM Revision */
24 )
25 { /* Start of ASL file */
26 /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
28 /* Data to be patched by the BIOS during POST */
29 /* FIXME the patching is not done yet! */
30 /* Memory related values */
31 Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
32 Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
33 Name(PBLN, 0x0) /* Length of BIOS area */
35 Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
36 Name(HPBA, 0xFED00000) /* Base address of HPET table */
38 Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
40 /* USB overcurrent mapping pins. */
41 Name(UOM0, 0)
42 Name(UOM1, 2)
43 Name(UOM2, 0)
44 Name(UOM3, 7)
45 Name(UOM4, 2)
46 Name(UOM5, 2)
47 Name(UOM6, 6)
48 Name(UOM7, 2)
49 Name(UOM8, 6)
50 Name(UOM9, 6)
52 /* Some global data */
53 Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
54 Name(OSV, Ones) /* Assume nothing */
55 Name(PMOD, One) /* Assume APIC */
57 /*
58 * Processor Object
59 *
60 */
61 Scope (\_PR) { /* define processor scope */
62 Processor(
63 CPU0, /* name space name */
64 0, /* Unique number for this processor */
65 0x808, /* PBLK system I/O address !hardcoded! */
66 0x06 /* PBLKLEN for boot processor */
67 ) {
68 #include "acpi/cpstate.asl"
69 }
71 Processor(
72 CPU1, /* name space name */
73 1, /* Unique number for this processor */
74 0x0000, /* PBLK system I/O address !hardcoded! */
75 0x00 /* PBLKLEN for boot processor */
76 ) {
77 #include "acpi/cpstate.asl"
78 }
80 Processor(
81 CPU2, /* name space name */
82 2, /* Unique number for this processor */
83 0x0000, /* PBLK system I/O address !hardcoded! */
84 0x00 /* PBLKLEN for boot processor */
85 ) {
86 #include "acpi/cpstate.asl"
87 }
89 Processor(
90 CPU3, /* name space name */
91 3, /* Unique number for this processor */
92 0x0000, /* PBLK system I/O address !hardcoded! */
93 0x00 /* PBLKLEN for boot processor */
94 ) {
95 #include "acpi/cpstate.asl"
96 }
98 Processor(
99 CPU4, /* name space name */
100 4, /* Unique number for this processor */
101 0x0000, /* PBLK system I/O address !hardcoded! */
102 0x00 /* PBLKLEN for boot processor */
103 ) {
104 #include "acpi/cpstate.asl"
105 }
107 Processor(
108 CPU5, /* name space name */
109 5, /* Unique number for this processor */
110 0x0000, /* PBLK system I/O address !hardcoded! */
111 0x00 /* PBLKLEN for boot processor */
112 ) {
113 #include "acpi/cpstate.asl"
114 }
115 } /* End _PR scope */
117 /* PIC IRQ mapping registers, C00h-C01h */
118 OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
119 Field(PRQM, ByteAcc, NoLock, Preserve) {
120 PRQI, 0x00000008,
121 PRQD, 0x00000008, /* Offset: 1h */
122 }
123 IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
124 PINA, 0x00000008, /* Index 0 */
125 PINB, 0x00000008, /* Index 1 */
126 PINC, 0x00000008, /* Index 2 */
127 PIND, 0x00000008, /* Index 3 */
128 AINT, 0x00000008, /* Index 4 */
129 SINT, 0x00000008, /* Index 5 */
130 , 0x00000008, /* Index 6 */
131 AAUD, 0x00000008, /* Index 7 */
132 AMOD, 0x00000008, /* Index 8 */
133 PINE, 0x00000008, /* Index 9 */
134 PINF, 0x00000008, /* Index A */
135 PING, 0x00000008, /* Index B */
136 PINH, 0x00000008, /* Index C */
137 }
139 /* PCI Error control register */
140 OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
141 Field(PERC, ByteAcc, NoLock, Preserve) {
142 SENS, 0x00000001,
143 PENS, 0x00000001,
144 SENE, 0x00000001,
145 PENE, 0x00000001,
146 }
148 /* Client Management index/data registers */
149 OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002)
150 Field(CMT, ByteAcc, NoLock, Preserve) {
151 CMTI, 8,
152 /* Client Management Data register */
153 G64E, 1,
154 G64O, 1,
155 G32O, 2,
156 , 2,
157 GPSL, 2,
158 }
160 /* GPM Port register */
161 OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001)
162 Field(GPT, ByteAcc, NoLock, Preserve) {
163 GPB0,1,
164 GPB1,1,
165 GPB2,1,
166 GPB3,1,
167 GPB4,1,
168 GPB5,1,
169 GPB6,1,
170 GPB7,1,
171 }
173 /* Flash ROM program enable register */
174 OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001)
175 Field(FRE, ByteAcc, NoLock, Preserve) {
176 , 0x00000006,
177 FLRE, 0x00000001,
178 }
180 /* PM2 index/data registers */
181 OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002)
182 Field(PM2R, ByteAcc, NoLock, Preserve) {
183 PM2I, 0x00000008,
184 PM2D, 0x00000008,
185 }
187 /* Power Management I/O registers */
188 OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002)
189 Field(PIOR, ByteAcc, NoLock, Preserve) {
190 PIOI, 0x00000008,
191 PIOD, 0x00000008,
192 }
193 IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) {
194 Offset(0x00), /* MiscControl */
195 , 1,
196 T1EE, 1,
197 T2EE, 1,
198 Offset(0x01), /* MiscStatus */
199 , 1,
200 T1E, 1,
201 T2E, 1,
202 Offset(0x04), /* SmiWakeUpEventEnable3 */
203 , 7,
204 SSEN, 1,
205 Offset(0x07), /* SmiWakeUpEventStatus3 */
206 , 7,
207 CSSM, 1,
208 Offset(0x10), /* AcpiEnable */
209 , 6,
210 PWDE, 1,
211 Offset(0x1C), /* ProgramIoEnable */
212 , 3,
213 MKME, 1,
214 IO3E, 1,
215 IO2E, 1,
216 IO1E, 1,
217 IO0E, 1,
218 Offset(0x1D), /* IOMonitorStatus */
219 , 3,
220 MKMS, 1,
221 IO3S, 1,
222 IO2S, 1,
223 IO1S, 1,
224 IO0S,1,
225 Offset(0x20), /* AcpiPmEvtBlk */
226 APEB, 16,
227 Offset(0x36), /* GEvtLevelConfig */
228 , 6,
229 ELC6, 1,
230 ELC7, 1,
231 Offset(0x37), /* GPMLevelConfig0 */
232 , 3,
233 PLC0, 1,
234 PLC1, 1,
235 PLC2, 1,
236 PLC3, 1,
237 PLC8, 1,
238 Offset(0x38), /* GPMLevelConfig1 */
239 , 1,
240 PLC4, 1,
241 PLC5, 1,
242 , 1,
243 PLC6, 1,
244 PLC7, 1,
245 Offset(0x3B), /* PMEStatus1 */
246 GP0S, 1,
247 GM4S, 1,
248 GM5S, 1,
249 APS, 1,
250 GM6S, 1,
251 GM7S, 1,
252 GP2S, 1,
253 STSS, 1,
254 Offset(0x55), /* SoftPciRst */
255 SPRE, 1,
256 , 1,
257 , 1,
258 PNAT, 1,
259 PWMK, 1,
260 PWNS, 1,
262 /* Offset(0x61), */ /* Options_1 */
263 /* ,7, */
264 /* R617,1, */
266 Offset(0x65), /* UsbPMControl */
267 , 4,
268 URRE, 1,
269 Offset(0x68), /* MiscEnable68 */
270 , 3,
271 TMTE, 1,
272 , 1,
273 Offset(0x92), /* GEVENTIN */
274 , 7,
275 E7IS, 1,
276 Offset(0x96), /* GPM98IN */
277 G8IS, 1,
278 G9IS, 1,
279 Offset(0x9A), /* EnhanceControl */
280 ,7,
281 HPDE, 1,
282 Offset(0xA8), /* PIO7654Enable */
283 IO4E, 1,
284 IO5E, 1,
285 IO6E, 1,
286 IO7E, 1,
287 Offset(0xA9), /* PIO7654Status */
288 IO4S, 1,
289 IO5S, 1,
290 IO6S, 1,
291 IO7S, 1,
292 }
294 /* PM1 Event Block
295 * First word is PM1_Status, Second word is PM1_Enable
296 */
297 OperationRegion(P1EB, SystemIO, APEB, 0x04)
298 Field(P1EB, ByteAcc, NoLock, Preserve) {
299 TMST, 1,
300 , 3,
301 BMST, 1,
302 GBST, 1,
303 Offset(0x01),
304 PBST, 1,
305 , 1,
306 RTST, 1,
307 , 3,
308 PWST, 1,
309 SPWS, 1,
310 Offset(0x02),
311 TMEN, 1,
312 , 4,
313 GBEN, 1,
314 Offset(0x03),
315 PBEN, 1,
316 , 1,
317 RTEN, 1,
318 , 3,
319 PWDA, 1,
320 }
322 Scope(\_SB) {
323 /* PCIe Configuration Space for 16 busses */
324 OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
325 Field(PCFG, ByteAcc, NoLock, Preserve) {
326 /* Byte offsets are computed using the following technique:
327 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
328 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
329 */
330 Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
331 STB5, 32,
332 Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
333 PT0D, 1,
334 PT1D, 1,
335 PT2D, 1,
336 PT3D, 1,
337 PT4D, 1,
338 PT5D, 1,
339 PT6D, 1,
340 PT7D, 1,
341 PT8D, 1,
342 PT9D, 1,
343 Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
344 SBIE, 1,
345 SBME, 1,
346 Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
347 SBRI, 8,
348 Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
349 SBB1, 32,
350 Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
351 ,14,
352 P92E, 1, /* Port92 decode enable */
353 }
355 OperationRegion(SB5, SystemMemory, STB5, 0x1000)
356 Field(SB5, AnyAcc, NoLock, Preserve){
357 /* Port 0 */
358 Offset(0x120), /* Port 0 Task file status */
359 P0ER, 1,
360 , 2,
361 P0DQ, 1,
362 , 3,
363 P0BY, 1,
364 Offset(0x128), /* Port 0 Serial ATA status */
365 P0DD, 4,
366 , 4,
367 P0IS, 4,
368 Offset(0x12C), /* Port 0 Serial ATA control */
369 P0DI, 4,
370 Offset(0x130), /* Port 0 Serial ATA error */
371 , 16,
372 P0PR, 1,
374 /* Port 1 */
375 offset(0x1A0), /* Port 1 Task file status */
376 P1ER, 1,
377 , 2,
378 P1DQ, 1,
379 , 3,
380 P1BY, 1,
381 Offset(0x1A8), /* Port 1 Serial ATA status */
382 P1DD, 4,
383 , 4,
384 P1IS, 4,
385 Offset(0x1AC), /* Port 1 Serial ATA control */
386 P1DI, 4,
387 Offset(0x1B0), /* Port 1 Serial ATA error */
388 , 16,
389 P1PR, 1,
391 /* Port 2 */
392 Offset(0x220), /* Port 2 Task file status */
393 P2ER, 1,
394 , 2,
395 P2DQ, 1,
396 , 3,
397 P2BY, 1,
398 Offset(0x228), /* Port 2 Serial ATA status */
399 P2DD, 4,
400 , 4,
401 P2IS, 4,
402 Offset(0x22C), /* Port 2 Serial ATA control */
403 P2DI, 4,
404 Offset(0x230), /* Port 2 Serial ATA error */
405 , 16,
406 P2PR, 1,
408 /* Port 3 */
409 Offset(0x2A0), /* Port 3 Task file status */
410 P3ER, 1,
411 , 2,
412 P3DQ, 1,
413 , 3,
414 P3BY, 1,
415 Offset(0x2A8), /* Port 3 Serial ATA status */
416 P3DD, 4,
417 , 4,
418 P3IS, 4,
419 Offset(0x2AC), /* Port 3 Serial ATA control */
420 P3DI, 4,
421 Offset(0x2B0), /* Port 3 Serial ATA error */
422 , 16,
423 P3PR, 1,
424 }
425 }
428 #include "acpi/routing.asl"
430 Scope(\_SB) {
432 Method(OSFL, 0){
434 if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
436 if(CondRefOf(\_OSI))
437 {
438 Store(1, OSVR) /* Assume some form of XP */
439 if (\_OSI("Windows 2006")) /* Vista */
440 {
441 Store(2, OSVR)
442 }
443 } else {
444 If(WCMP(\_OS,"Linux")) {
445 Store(3, OSVR) /* Linux */
446 } Else {
447 Store(4, OSVR) /* Gotta be WinCE */
448 }
449 }
450 Return(OSVR)
451 }
453 Method(_PIC, 0x01, NotSerialized)
454 {
455 If (Arg0)
456 {
457 \_SB.CIRQ()
458 }
459 Store(Arg0, PMOD)
460 }
461 Method(CIRQ, 0x00, NotSerialized){
462 Store(0, PINA)
463 Store(0, PINB)
464 Store(0, PINC)
465 Store(0, PIND)
466 Store(0, PINE)
467 Store(0, PINF)
468 Store(0, PING)
469 Store(0, PINH)
470 }
472 Name(IRQB, ResourceTemplate(){
473 IRQ(Level,ActiveLow,Shared){15}
474 })
476 Name(IRQP, ResourceTemplate(){
477 IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15}
478 })
480 Name(PITF, ResourceTemplate(){
481 IRQ(Level,ActiveLow,Exclusive){9}
482 })
484 Device(INTA) {
485 Name(_HID, EISAID("PNP0C0F"))
486 Name(_UID, 1)
488 Method(_STA, 0) {
489 if (PINA) {
490 Return(0x0B) /* sata is invisible */
491 } else {
492 Return(0x09) /* sata is disabled */
493 }
494 } /* End Method(_SB.INTA._STA) */
496 Method(_DIS ,0) {
497 /* DBGO("\\_SB\\LNKA\\_DIS\n") */
498 Store(0, PINA)
499 } /* End Method(_SB.INTA._DIS) */
501 Method(_PRS ,0) {
502 /* DBGO("\\_SB\\LNKA\\_PRS\n") */
503 Return(IRQP)
504 } /* Method(_SB.INTA._PRS) */
506 Method(_CRS ,0) {
507 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
508 CreateWordField(IRQB, 0x1, IRQN)
509 ShiftLeft(1, PINA, IRQN)
510 Return(IRQB)
511 } /* Method(_SB.INTA._CRS) */
513 Method(_SRS, 1) {
514 /* DBGO("\\_SB\\LNKA\\_CRS\n") */
515 CreateWordField(ARG0, 1, IRQM)
517 /* Use lowest available IRQ */
518 FindSetRightBit(IRQM, Local0)
519 if (Local0) {
520 Decrement(Local0)
521 }
522 Store(Local0, PINA)
523 } /* End Method(_SB.INTA._SRS) */
524 } /* End Device(INTA) */
526 Device(INTB) {
527 Name(_HID, EISAID("PNP0C0F"))
528 Name(_UID, 2)
530 Method(_STA, 0) {
531 if (PINB) {
532 Return(0x0B) /* sata is invisible */
533 } else {
534 Return(0x09) /* sata is disabled */
535 }
536 } /* End Method(_SB.INTB._STA) */
538 Method(_DIS ,0) {
539 /* DBGO("\\_SB\\LNKB\\_DIS\n") */
540 Store(0, PINB)
541 } /* End Method(_SB.INTB._DIS) */
543 Method(_PRS ,0) {
544 /* DBGO("\\_SB\\LNKB\\_PRS\n") */
545 Return(IRQP)
546 } /* Method(_SB.INTB._PRS) */
548 Method(_CRS ,0) {
549 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
550 CreateWordField(IRQB, 0x1, IRQN)
551 ShiftLeft(1, PINB, IRQN)
552 Return(IRQB)
553 } /* Method(_SB.INTB._CRS) */
555 Method(_SRS, 1) {
556 /* DBGO("\\_SB\\LNKB\\_CRS\n") */
557 CreateWordField(ARG0, 1, IRQM)
559 /* Use lowest available IRQ */
560 FindSetRightBit(IRQM, Local0)
561 if (Local0) {
562 Decrement(Local0)
563 }
564 Store(Local0, PINB)
565 } /* End Method(_SB.INTB._SRS) */
566 } /* End Device(INTB) */
568 Device(INTC) {
569 Name(_HID, EISAID("PNP0C0F"))
570 Name(_UID, 3)
572 Method(_STA, 0) {
573 if (PINC) {
574 Return(0x0B) /* sata is invisible */
575 } else {
576 Return(0x09) /* sata is disabled */
577 }
578 } /* End Method(_SB.INTC._STA) */
580 Method(_DIS ,0) {
581 /* DBGO("\\_SB\\LNKC\\_DIS\n") */
582 Store(0, PINC)
583 } /* End Method(_SB.INTC._DIS) */
585 Method(_PRS ,0) {
586 /* DBGO("\\_SB\\LNKC\\_PRS\n") */
587 Return(IRQP)
588 } /* Method(_SB.INTC._PRS) */
590 Method(_CRS ,0) {
591 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
592 CreateWordField(IRQB, 0x1, IRQN)
593 ShiftLeft(1, PINC, IRQN)
594 Return(IRQB)
595 } /* Method(_SB.INTC._CRS) */
597 Method(_SRS, 1) {
598 /* DBGO("\\_SB\\LNKC\\_CRS\n") */
599 CreateWordField(ARG0, 1, IRQM)
601 /* Use lowest available IRQ */
602 FindSetRightBit(IRQM, Local0)
603 if (Local0) {
604 Decrement(Local0)
605 }
606 Store(Local0, PINC)
607 } /* End Method(_SB.INTC._SRS) */
608 } /* End Device(INTC) */
610 Device(INTD) {
611 Name(_HID, EISAID("PNP0C0F"))
612 Name(_UID, 4)
614 Method(_STA, 0) {
615 if (PIND) {
616 Return(0x0B) /* sata is invisible */
617 } else {
618 Return(0x09) /* sata is disabled */
619 }
620 } /* End Method(_SB.INTD._STA) */
622 Method(_DIS ,0) {
623 /* DBGO("\\_SB\\LNKD\\_DIS\n") */
624 Store(0, PIND)
625 } /* End Method(_SB.INTD._DIS) */
627 Method(_PRS ,0) {
628 /* DBGO("\\_SB\\LNKD\\_PRS\n") */
629 Return(IRQP)
630 } /* Method(_SB.INTD._PRS) */
632 Method(_CRS ,0) {
633 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
634 CreateWordField(IRQB, 0x1, IRQN)
635 ShiftLeft(1, PIND, IRQN)
636 Return(IRQB)
637 } /* Method(_SB.INTD._CRS) */
639 Method(_SRS, 1) {
640 /* DBGO("\\_SB\\LNKD\\_CRS\n") */
641 CreateWordField(ARG0, 1, IRQM)
643 /* Use lowest available IRQ */
644 FindSetRightBit(IRQM, Local0)
645 if (Local0) {
646 Decrement(Local0)
647 }
648 Store(Local0, PIND)
649 } /* End Method(_SB.INTD._SRS) */
650 } /* End Device(INTD) */
652 Device(INTE) {
653 Name(_HID, EISAID("PNP0C0F"))
654 Name(_UID, 5)
656 Method(_STA, 0) {
657 if (PINE) {
658 Return(0x0B) /* sata is invisible */
659 } else {
660 Return(0x09) /* sata is disabled */
661 }
662 } /* End Method(_SB.INTE._STA) */
664 Method(_DIS ,0) {
665 /* DBGO("\\_SB\\LNKE\\_DIS\n") */
666 Store(0, PINE)
667 } /* End Method(_SB.INTE._DIS) */
669 Method(_PRS ,0) {
670 /* DBGO("\\_SB\\LNKE\\_PRS\n") */
671 Return(IRQP)
672 } /* Method(_SB.INTE._PRS) */
674 Method(_CRS ,0) {
675 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
676 CreateWordField(IRQB, 0x1, IRQN)
677 ShiftLeft(1, PINE, IRQN)
678 Return(IRQB)
679 } /* Method(_SB.INTE._CRS) */
681 Method(_SRS, 1) {
682 /* DBGO("\\_SB\\LNKE\\_CRS\n") */
683 CreateWordField(ARG0, 1, IRQM)
685 /* Use lowest available IRQ */
686 FindSetRightBit(IRQM, Local0)
687 if (Local0) {
688 Decrement(Local0)
689 }
690 Store(Local0, PINE)
691 } /* End Method(_SB.INTE._SRS) */
692 } /* End Device(INTE) */
694 Device(INTF) {
695 Name(_HID, EISAID("PNP0C0F"))
696 Name(_UID, 6)
698 Method(_STA, 0) {
699 if (PINF) {
700 Return(0x0B) /* sata is invisible */
701 } else {
702 Return(0x09) /* sata is disabled */
703 }
704 } /* End Method(_SB.INTF._STA) */
706 Method(_DIS ,0) {
707 /* DBGO("\\_SB\\LNKF\\_DIS\n") */
708 Store(0, PINF)
709 } /* End Method(_SB.INTF._DIS) */
711 Method(_PRS ,0) {
712 /* DBGO("\\_SB\\LNKF\\_PRS\n") */
713 Return(PITF)
714 } /* Method(_SB.INTF._PRS) */
716 Method(_CRS ,0) {
717 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
718 CreateWordField(IRQB, 0x1, IRQN)
719 ShiftLeft(1, PINF, IRQN)
720 Return(IRQB)
721 } /* Method(_SB.INTF._CRS) */
723 Method(_SRS, 1) {
724 /* DBGO("\\_SB\\LNKF\\_CRS\n") */
725 CreateWordField(ARG0, 1, IRQM)
727 /* Use lowest available IRQ */
728 FindSetRightBit(IRQM, Local0)
729 if (Local0) {
730 Decrement(Local0)
731 }
732 Store(Local0, PINF)
733 } /* End Method(_SB.INTF._SRS) */
734 } /* End Device(INTF) */
736 Device(INTG) {
737 Name(_HID, EISAID("PNP0C0F"))
738 Name(_UID, 7)
740 Method(_STA, 0) {
741 if (PING) {
742 Return(0x0B) /* sata is invisible */
743 } else {
744 Return(0x09) /* sata is disabled */
745 }
746 } /* End Method(_SB.INTG._STA) */
748 Method(_DIS ,0) {
749 /* DBGO("\\_SB\\LNKG\\_DIS\n") */
750 Store(0, PING)
751 } /* End Method(_SB.INTG._DIS) */
753 Method(_PRS ,0) {
754 /* DBGO("\\_SB\\LNKG\\_PRS\n") */
755 Return(IRQP)
756 } /* Method(_SB.INTG._CRS) */
758 Method(_CRS ,0) {
759 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
760 CreateWordField(IRQB, 0x1, IRQN)
761 ShiftLeft(1, PING, IRQN)
762 Return(IRQB)
763 } /* Method(_SB.INTG._CRS) */
765 Method(_SRS, 1) {
766 /* DBGO("\\_SB\\LNKG\\_CRS\n") */
767 CreateWordField(ARG0, 1, IRQM)
769 /* Use lowest available IRQ */
770 FindSetRightBit(IRQM, Local0)
771 if (Local0) {
772 Decrement(Local0)
773 }
774 Store(Local0, PING)
775 } /* End Method(_SB.INTG._SRS) */
776 } /* End Device(INTG) */
778 Device(INTH) {
779 Name(_HID, EISAID("PNP0C0F"))
780 Name(_UID, 8)
782 Method(_STA, 0) {
783 if (PINH) {
784 Return(0x0B) /* sata is invisible */
785 } else {
786 Return(0x09) /* sata is disabled */
787 }
788 } /* End Method(_SB.INTH._STA) */
790 Method(_DIS ,0) {
791 /* DBGO("\\_SB\\LNKH\\_DIS\n") */
792 Store(0, PINH)
793 } /* End Method(_SB.INTH._DIS) */
795 Method(_PRS ,0) {
796 /* DBGO("\\_SB\\LNKH\\_PRS\n") */
797 Return(IRQP)
798 } /* Method(_SB.INTH._CRS) */
800 Method(_CRS ,0) {
801 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
802 CreateWordField(IRQB, 0x1, IRQN)
803 ShiftLeft(1, PINH, IRQN)
804 Return(IRQB)
805 } /* Method(_SB.INTH._CRS) */
807 Method(_SRS, 1) {
808 /* DBGO("\\_SB\\LNKH\\_CRS\n") */
809 CreateWordField(ARG0, 1, IRQM)
811 /* Use lowest available IRQ */
812 FindSetRightBit(IRQM, Local0)
813 if (Local0) {
814 Decrement(Local0)
815 }
816 Store(Local0, PINH)
817 } /* End Method(_SB.INTH._SRS) */
818 } /* End Device(INTH) */
820 } /* End Scope(_SB) */
823 /* Supported sleep states: */
824 Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */
826 If (LAnd(SSFG, 0x01)) {
827 Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */
828 }
829 If (LAnd(SSFG, 0x02)) {
830 Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */
831 }
832 If (LAnd(SSFG, 0x04)) {
833 Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */
834 }
835 If (LAnd(SSFG, 0x08)) {
836 Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */
837 }
839 Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */
841 Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */
842 Name(CSMS, 0) /* Current System State */
844 /* Wake status package */
845 Name(WKST,Package(){Zero, Zero})
847 /*
848 * \_PTS - Prepare to Sleep method
849 *
850 * Entry:
851 * Arg0=The value of the sleeping state S1=1, S2=2, etc
852 *
853 * Exit:
854 * -none-
855 *
856 * The _PTS control method is executed at the beginning of the sleep process
857 * for S1-S5. The sleeping value is passed to the _PTS control method. This
858 * control method may be executed a relatively long time before entering the
859 * sleep state and the OS may abort the operation without notification to
860 * the ACPI driver. This method cannot modify the configuration or power
861 * state of any device in the system.
862 */
863 Method(\_PTS, 1) {
864 /* DBGO("\\_PTS\n") */
865 /* DBGO("From S0 to S") */
866 /* DBGO(Arg0) */
867 /* DBGO("\n") */
869 /* Don't allow PCIRST# to reset USB */
870 if (LEqual(Arg0,3)){
871 Store(0,URRE)
872 }
874 /* Clear sleep SMI status flag and enable sleep SMI trap. */
875 /*Store(One, CSSM)
876 Store(One, SSEN)*/
878 /* On older chips, clear PciExpWakeDisEn */
879 /*if (LLessEqual(\_SB.SBRI, 0x13)) {
880 * Store(0,\_SB.PWDE)
881 *}
882 */
884 /* Clear wake status structure. */
885 Store(0, Index(WKST,0))
886 Store(0, Index(WKST,1))
887 \_SB.PCI0.SIOS (Arg0)
888 } /* End Method(\_PTS) */
890 /*
891 * The following method results in a "not a valid reserved NameSeg"
892 * warning so I have commented it out for the duration. It isn't
893 * used, so it could be removed.
894 *
895 *
896 * \_GTS OEM Going To Sleep method
897 *
898 * Entry:
899 * Arg0=The value of the sleeping state S1=1, S2=2
900 *
901 * Exit:
902 * -none-
903 *
904 * Method(\_GTS, 1) {
905 * DBGO("\\_GTS\n")
906 * DBGO("From S0 to S")
907 * DBGO(Arg0)
908 * DBGO("\n")
909 * }
910 */
912 /*
913 * \_BFS OEM Back From Sleep method
914 *
915 * Entry:
916 * Arg0=The value of the sleeping state S1=1, S2=2
917 *
918 * Exit:
919 * -none-
920 */
921 Method(\_BFS, 1) {
922 /* DBGO("\\_BFS\n") */
923 /* DBGO("From S") */
924 /* DBGO(Arg0) */
925 /* DBGO(" to S0\n") */
926 }
928 /*
929 * \_WAK System Wake method
930 *
931 * Entry:
932 * Arg0=The value of the sleeping state S1=1, S2=2
933 *
934 * Exit:
935 * Return package of 2 DWords
936 * Dword 1 - Status
937 * 0x00000000 wake succeeded
938 * 0x00000001 Wake was signaled but failed due to lack of power
939 * 0x00000002 Wake was signaled but failed due to thermal condition
940 * Dword 2 - Power Supply state
941 * if non-zero the effective S-state the power supply entered
942 */
943 Method(\_WAK, 1) {
944 /* DBGO("\\_WAK\n") */
945 /* DBGO("From S") */
946 /* DBGO(Arg0) */
947 /* DBGO(" to S0\n") */
949 /* Re-enable HPET */
950 Store(1,HPDE)
952 /* Restore PCIRST# so it resets USB */
953 if (LEqual(Arg0,3)){
954 Store(1,URRE)
955 }
957 /* Arbitrarily clear PciExpWakeStatus */
958 Store(PWST, Local1)
959 Store(Local1, PWST)
961 /* if(DeRefOf(Index(WKST,0))) {
962 * Store(0, Index(WKST,1))
963 * } else {
964 * Store(Arg0, Index(WKST,1))
965 * }
966 */
967 \_SB.PCI0.SIOW (Arg0)
968 Return(WKST)
969 } /* End Method(\_WAK) */
971 Scope(\_GPE) { /* Start Scope GPE */
972 /* General event 0 */
973 /* Method(_L00) {
974 * DBGO("\\_GPE\\_L00\n")
975 * }
976 */
978 /* General event 1 */
979 /* Method(_L01) {
980 * DBGO("\\_GPE\\_L00\n")
981 * }
982 */
984 /* General event 2 */
985 /* Method(_L02) {
986 * DBGO("\\_GPE\\_L00\n")
987 * }
988 */
990 /* General event 3 */
991 Method(_L03) {
992 /* DBGO("\\_GPE\\_L00\n") */
993 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
994 }
996 /* General event 4 */
997 /* Method(_L04) {
998 * DBGO("\\_GPE\\_L00\n")
999 * }
1000 */
1002 /* General event 5 */
1003 /* Method(_L05) {
1004 * DBGO("\\_GPE\\_L00\n")
1005 * }
1006 */
1008 /* General event 6 - Used for GPM6, moved to USB.asl */
1009 /* Method(_L06) {
1010 * DBGO("\\_GPE\\_L00\n")
1011 * }
1012 */
1014 /* General event 7 - Used for GPM7, moved to USB.asl */
1015 /* Method(_L07) {
1016 * DBGO("\\_GPE\\_L07\n")
1017 * }
1018 */
1020 /* Legacy PM event */
1021 Method(_L08) {
1022 /* DBGO("\\_GPE\\_L08\n") */
1023 }
1025 /* Temp warning (TWarn) event */
1026 Method(_L09) {
1027 /* DBGO("\\_GPE\\_L09\n") */
1028 Notify (\_TZ.TZ00, 0x80)
1029 }
1031 /* Reserved */
1032 /* Method(_L0A) {
1033 * DBGO("\\_GPE\\_L0A\n")
1034 * }
1035 */
1037 /* USB controller PME# */
1038 Method(_L0B) {
1039 /* DBGO("\\_GPE\\_L0B\n") */
1040 Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1041 Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
1042 Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
1043 Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
1044 Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
1045 Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
1046 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1047 }
1049 /* AC97 controller PME# */
1050 /* Method(_L0C) {
1051 * DBGO("\\_GPE\\_L0C\n")
1052 * }
1053 */
1055 /* OtherTherm PME# */
1056 /* Method(_L0D) {
1057 * DBGO("\\_GPE\\_L0D\n")
1058 * }
1059 */
1061 /* GPM9 SCI event - Moved to USB.asl */
1062 /* Method(_L0E) {
1063 * DBGO("\\_GPE\\_L0E\n")
1064 * }
1065 */
1067 /* PCIe HotPlug event */
1068 /* Method(_L0F) {
1069 * DBGO("\\_GPE\\_L0F\n")
1070 * }
1071 */
1073 /* ExtEvent0 SCI event */
1074 Method(_L10) {
1075 /* DBGO("\\_GPE\\_L10\n") */
1076 }
1079 /* ExtEvent1 SCI event */
1080 Method(_L11) {
1081 /* DBGO("\\_GPE\\_L11\n") */
1082 }
1084 /* PCIe PME# event */
1085 /* Method(_L12) {
1086 * DBGO("\\_GPE\\_L12\n")
1087 * }
1088 */
1090 /* GPM0 SCI event - Moved to USB.asl */
1091 /* Method(_L13) {
1092 * DBGO("\\_GPE\\_L13\n")
1093 * }
1094 */
1096 /* GPM1 SCI event - Moved to USB.asl */
1097 /* Method(_L14) {
1098 * DBGO("\\_GPE\\_L14\n")
1099 * }
1100 */
1102 /* GPM2 SCI event - Moved to USB.asl */
1103 /* Method(_L15) {
1104 * DBGO("\\_GPE\\_L15\n")
1105 * }
1106 */
1108 /* GPM3 SCI event - Moved to USB.asl */
1109 /* Method(_L16) {
1110 * DBGO("\\_GPE\\_L16\n")
1111 * }
1112 */
1114 /* GPM8 SCI event - Moved to USB.asl */
1115 /* Method(_L17) {
1116 * DBGO("\\_GPE\\_L17\n")
1117 * }
1118 */
1120 /* GPIO0 or GEvent8 event */
1121 Method(_L18) {
1122 /* DBGO("\\_GPE\\_L18\n") */
1123 Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
1124 Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
1125 Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
1126 Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
1127 Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
1128 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1129 }
1131 /* GPM4 SCI event - Moved to USB.asl */
1132 /* Method(_L19) {
1133 * DBGO("\\_GPE\\_L19\n")
1134 * }
1135 */
1137 /* GPM5 SCI event - Moved to USB.asl */
1138 /* Method(_L1A) {
1139 * DBGO("\\_GPE\\_L1A\n")
1140 * }
1141 */
1143 /* Azalia SCI event */
1144 Method(_L1B) {
1145 /* DBGO("\\_GPE\\_L1B\n") */
1146 Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
1147 Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
1148 }
1150 /* GPM6 SCI event - Reassigned to _L06 */
1151 /* Method(_L1C) {
1152 * DBGO("\\_GPE\\_L1C\n")
1153 * }
1154 */
1156 /* GPM7 SCI event - Reassigned to _L07 */
1157 /* Method(_L1D) {
1158 * DBGO("\\_GPE\\_L1D\n")
1159 * }
1160 */
1162 /* GPIO2 or GPIO66 SCI event */
1163 /* Method(_L1E) {
1164 * DBGO("\\_GPE\\_L1E\n")
1165 * }
1166 */
1168 /* SATA SCI event - Moved to sata.asl */
1169 /* Method(_L1F) {
1170 * DBGO("\\_GPE\\_L1F\n")
1171 * }
1172 */
1174 } /* End Scope GPE */
1176 #include "acpi/usb.asl"
1178 /* System Bus */
1179 Scope(\_SB) { /* Start \_SB scope */
1180 #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */
1182 /* _SB.PCI0 */
1183 /* Note: Only need HID on Primary Bus */
1184 Device(PCI0) {
1185 External (TOM1)
1186 External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */
1187 Name(_HID, EISAID("PNP0A03"))
1188 Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
1189 Method(_BBN, 0) { /* Bus number = 0 */
1190 Return(0)
1191 }
1192 Method(_STA, 0) {
1193 /* DBGO("\\_SB\\PCI0\\_STA\n") */
1194 Return(0x0B) /* Status is visible */
1195 }
1197 Method(_PRT,0) {
1198 If(PMOD){ Return(APR0) } /* APIC mode */
1199 Return (PR0) /* PIC Mode */
1200 } /* end _PRT */
1202 /* Describe the Northbridge devices */
1203 Device(AMRT) {
1204 Name(_ADR, 0x00000000)
1205 } /* end AMRT */
1207 /* The internal GFX bridge */
1208 Device(AGPB) {
1209 Name(_ADR, 0x00010000)
1210 Name(_PRW, Package() {0x18, 4})
1211 Method(_PRT,0) {
1212 Return (APR1)
1213 }
1214 } /* end AGPB */
1216 /* The external GFX bridge */
1217 Device(PBR2) {
1218 Name(_ADR, 0x00020000)
1219 Name(_PRW, Package() {0x18, 4})
1220 Method(_PRT,0) {
1221 If(PMOD){ Return(APS2) } /* APIC mode */
1222 Return (PS2) /* PIC Mode */
1223 } /* end _PRT */
1224 } /* end PBR2 */
1226 /* Dev3 is also an external GFX bridge, not used in Herring */
1228 Device(PBR4) {
1229 Name(_ADR, 0x00040000)
1230 Name(_PRW, Package() {0x18, 4})
1231 Method(_PRT,0) {
1232 If(PMOD){ Return(APS4) } /* APIC mode */
1233 Return (PS4) /* PIC Mode */
1234 } /* end _PRT */
1235 } /* end PBR4 */
1237 Device(PBR5) {
1238 Name(_ADR, 0x00050000)
1239 Name(_PRW, Package() {0x18, 4})
1240 Method(_PRT,0) {
1241 If(PMOD){ Return(APS5) } /* APIC mode */
1242 Return (PS5) /* PIC Mode */
1243 } /* end _PRT */
1244 } /* end PBR5 */
1246 Device(PBR6) {
1247 Name(_ADR, 0x00060000)
1248 Name(_PRW, Package() {0x18, 4})
1249 Method(_PRT,0) {
1250 If(PMOD){ Return(APS6) } /* APIC mode */
1251 Return (PS6) /* PIC Mode */
1252 } /* end _PRT */
1253 } /* end PBR6 */
1255 /* The onboard EtherNet chip */
1256 Device(PBR7) {
1257 Name(_ADR, 0x00070000)
1258 Name(_PRW, Package() {0x18, 4})
1259 Method(_PRT,0) {
1260 If(PMOD){ Return(APS7) } /* APIC mode */
1261 Return (PS7) /* PIC Mode */
1262 } /* end _PRT */
1263 } /* end PBR7 */
1265 /* GPP */
1266 Device(PBR9) {
1267 Name(_ADR, 0x00090000)
1268 Name(_PRW, Package() {0x18, 4})
1269 Method(_PRT,0) {
1270 If(PMOD){ Return(APS9) } /* APIC mode */
1271 Return (PS9) /* PIC Mode */
1272 } /* end _PRT */
1273 } /* end PBR9 */
1275 Device(PBRa) {
1276 Name(_ADR, 0x000A0000)
1277 Name(_PRW, Package() {0x18, 4})
1278 Method(_PRT,0) {
1279 If(PMOD){ Return(APSa) } /* APIC mode */
1280 Return (PSa) /* PIC Mode */
1281 } /* end _PRT */
1282 } /* end PBRa */
1284 Device(PBRb) {
1285 Name(_ADR, 0x000b0000)
1286 Name(_PRW, Package() {0x18, 4})
1287 Method(_PRT,0) {
1288 If(PMOD){ Return(APSb) } /* APIC mode */
1289 Return (PSb) /* PIC Mode */
1290 } /* end _PRT */
1291 } /* end PBRb */
1293 Device(PBRc) {
1294 Name(_ADR, 0x000c0000)
1295 Name(_PRW, Package() {0x18, 4})
1296 Method(_PRT,0) {
1297 If(PMOD){ Return(APSc) } /* APIC mode */
1298 Return (PSc) /* PIC Mode */
1299 } /* end _PRT */
1300 } /* end PBRc */
1303 /* PCI slot 1, 2, 3 */
1304 Device(PIBR) {
1305 Name(_ADR, 0x00140004)
1306 Name(_PRW, Package() {0x18, 4})
1308 Method(_PRT, 0) {
1309 Return (PCIB)
1310 }
1311 }
1313 /* Describe the Southbridge devices */
1314 Device(STCR) {
1315 Name(_ADR, 0x00110000)
1316 #include "acpi/sata.asl"
1317 } /* end STCR */
1319 Device(UOH1) {
1320 Name(_ADR, 0x00130000)
1321 Name(_PRW, Package() {0x0B, 3})
1322 } /* end UOH1 */
1324 Device(UOH2) {
1325 Name(_ADR, 0x00130001)
1326 Name(_PRW, Package() {0x0B, 3})
1327 } /* end UOH2 */
1329 Device(UOH3) {
1330 Name(_ADR, 0x00130002)
1331 Name(_PRW, Package() {0x0B, 3})
1332 } /* end UOH3 */
1334 Device(UOH4) {
1335 Name(_ADR, 0x00130003)
1336 Name(_PRW, Package() {0x0B, 3})
1337 } /* end UOH4 */
1339 Device(UOH5) {
1340 Name(_ADR, 0x00130004)
1341 Name(_PRW, Package() {0x0B, 3})
1342 } /* end UOH5 */
1344 Device(UEH1) {
1345 Name(_ADR, 0x00130005)
1346 Name(_PRW, Package() {0x0B, 3})
1347 } /* end UEH1 */
1349 Device(SBUS) {
1350 Name(_ADR, 0x00140000)
1351 } /* end SBUS */
1353 /* Primary (and only) IDE channel */
1354 Device(IDEC) {
1355 Name(_ADR, 0x00140001)
1356 #include "acpi/ide.asl"
1357 } /* end IDEC */
1359 Device(AZHD) {
1360 Name(_ADR, 0x00140002)
1361 OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
1362 Field(AZPD, AnyAcc, NoLock, Preserve) {
1363 offset (0x42),
1364 NSDI, 1,
1365 NSDO, 1,
1366 NSEN, 1,
1367 offset (0x44),
1368 IPCR, 4,
1369 offset (0x54),
1370 PWST, 2,
1371 , 6,
1372 PMEB, 1,
1373 , 6,
1374 PMST, 1,
1375 offset (0x62),
1376 MMCR, 1,
1377 offset (0x64),
1378 MMLA, 32,
1379 offset (0x68),
1380 MMHA, 32,
1381 offset (0x6C),
1382 MMDT, 16,
1383 }
1385 Method(_INI) {
1386 If(LEqual(OSVR,3)){ /* If we are running Linux */
1387 Store(zero, NSEN)
1388 Store(one, NSDO)
1389 Store(one, NSDI)
1390 }
1391 }
1392 } /* end AZHD */
1394 Device(LIBR) {
1395 Name(_ADR, 0x00140003)
1396 /* Method(_INI) {
1397 * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n")
1398 } */ /* End Method(_SB.SBRDG._INI) */
1400 /* Real Time Clock Device */
1401 Device(RTC0) {
1402 Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */
1403 Name(_CRS, ResourceTemplate() {
1404 IRQNoFlags(){8}
1405 IO(Decode16,0x0070, 0x0070, 0, 2)
1406 /* IO(Decode16,0x0070, 0x0070, 0, 4) */
1407 })
1408 } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
1410 Device(TMR) { /* Timer */
1411 Name(_HID,EISAID("PNP0100")) /* System Timer */
1412 Name(_CRS, ResourceTemplate() {
1413 IRQNoFlags(){0}
1414 IO(Decode16, 0x0040, 0x0040, 0, 4)
1415 /* IO(Decode16, 0x0048, 0x0048, 0, 4) */
1416 })
1417 } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
1419 Device(SPKR) { /* Speaker */
1420 Name(_HID,EISAID("PNP0800")) /* AT style speaker */
1421 Name(_CRS, ResourceTemplate() {
1422 IO(Decode16, 0x0061, 0x0061, 0, 1)
1423 })
1424 } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
1426 Device(PIC) {
1427 Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */
1428 Name(_CRS, ResourceTemplate() {
1429 IRQNoFlags(){2}
1430 IO(Decode16,0x0020, 0x0020, 0, 2)
1431 IO(Decode16,0x00A0, 0x00A0, 0, 2)
1432 /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
1433 /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
1434 })
1435 } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
1437 Device(MAD) { /* 8257 DMA */
1438 Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */
1439 Name(_CRS, ResourceTemplate() {
1440 DMA(Compatibility,BusMaster,Transfer8){4}
1441 IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
1442 IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
1443 IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
1444 IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
1445 IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
1446 IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
1447 }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
1448 } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
1450 Device(COPR) {
1451 Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */
1452 Name(_CRS, ResourceTemplate() {
1453 IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
1454 IRQNoFlags(){13}
1455 })
1456 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1458 Device(HPTM) {
1459 Name(_HID,EISAID("PNP0103"))
1460 Name(CRS,ResourceTemplate() {
1461 Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */
1462 })
1463 Method(_STA, 0) {
1464 Return(0x0F) /* sata is visible */
1465 }
1466 Method(_CRS, 0) {
1467 CreateDwordField(CRS, ^HPT._BAS, HPBA)
1468 Store(HPBA, HPBA)
1469 Return(CRS)
1470 }
1471 } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
1472 } /* end LIBR */
1474 Device(HPBR) {
1475 Name(_ADR, 0x00140004)
1476 } /* end HostPciBr */
1478 Device(ACAD) {
1479 Name(_ADR, 0x00140005)
1480 } /* end Ac97audio */
1482 Device(ACMD) {
1483 Name(_ADR, 0x00140006)
1484 } /* end Ac97modem */
1486 /* ITE8718 Support */
1487 OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */
1488 Field (IOID, ByteAcc, NoLock, Preserve)
1489 {
1490 SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */
1491 }
1493 IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve)
1494 {
1495 Offset (0x07),
1496 LDN, 8, /* Logical Device Number */
1497 Offset (0x20),
1498 CID1, 8, /* Chip ID Byte 1, 0x87 */
1499 CID2, 8, /* Chip ID Byte 2, 0x12 */
1500 Offset (0x30),
1501 ACTR, 8, /* Function activate */
1502 Offset (0xF0),
1503 APC0, 8, /* APC/PME Event Enable Register */
1504 APC1, 8, /* APC/PME Status Register */
1505 APC2, 8, /* APC/PME Control Register 1 */
1506 APC3, 8, /* Environment Controller Special Configuration Register */
1507 APC4, 8 /* APC/PME Control Register 2 */
1508 }
1510 /* Enter the 8718 MB PnP Mode */
1511 Method (EPNP)
1512 {
1513 Store(0x87, SIOI)
1514 Store(0x01, SIOI)
1515 Store(0x55, SIOI)
1516 Store(0x55, SIOI) /* 8718 magic number */
1517 }
1518 /* Exit the 8718 MB PnP Mode */
1519 Method (XPNP)
1520 {
1521 Store (0x02, SIOI)
1522 Store (0x02, SIOD)
1523 }
1524 /*
1525 * Keyboard PME is routed to SB700 Gevent3. We can wake
1526 * up the system by pressing the key.
1527 */
1528 Method (SIOS, 1)
1529 {
1530 /* We only enable KBD PME for S5. */
1531 If (LLess (Arg0, 0x05))
1532 {
1533 EPNP()
1534 /* DBGO("8718F\n") */
1536 Store (0x4, LDN)
1537 Store (One, ACTR) /* Enable EC */
1538 /*
1539 Store (0x4, LDN)
1540 Store (0x04, APC4)
1541 */ /* falling edge. which mode? Not sure. */
1543 Store (0x4, LDN)
1544 Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */
1545 Store (0x4, LDN)
1546 Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */
1548 XPNP()
1549 }
1550 }
1551 Method (SIOW, 1)
1552 {
1553 EPNP()
1554 Store (0x4, LDN)
1555 Store (Zero, APC0) /* disable keyboard PME */
1556 Store (0x4, LDN)
1557 Store (0xFF, APC1) /* clear keyboard PME status */
1558 XPNP()
1559 }
1561 Name(CRES, ResourceTemplate() {
1562 IO(Decode16, 0x0CF8, 0x0CF8, 1, 8)
1564 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1565 0x0000, /* address granularity */
1566 0x0000, /* range minimum */
1567 0x0CF7, /* range maximum */
1568 0x0000, /* translation */
1569 0x0CF8 /* length */
1570 )
1572 WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
1573 0x0000, /* address granularity */
1574 0x0D00, /* range minimum */
1575 0xFFFF, /* range maximum */
1576 0x0000, /* translation */
1577 0xF300 /* length */
1578 )
1580 #if 0
1581 Memory32Fixed(READWRITE, 0, 0xA0000, BSMM)
1582 Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */
1583 Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
1584 Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */
1586 /* DRAM Memory from 1MB to TopMem */
1587 Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */
1589 /* BIOS space just below 4GB */
1590 DWORDMemory(
1591 ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1592 0x00, /* Granularity */
1593 0x00000000, /* Min */
1594 0x00000000, /* Max */
1595 0x00000000, /* Translation */
1596 0x00000001, /* Max-Min, RLEN */
1597 ,,
1598 PCBM
1599 )
1601 /* DRAM memory from 4GB to TopMem2 */
1602 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1603 0x00000000, /* Granularity */
1604 0x00000000, /* Min */
1605 0x00000000, /* Max */
1606 0x00000000, /* Translation */
1607 0x00000001, /* Max-Min, RLEN */
1608 ,,
1609 DMHI
1610 )
1612 /* BIOS space just below 16EB */
1613 QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
1614 0x00000000, /* Granularity */
1615 0x00000000, /* Min */
1616 0x00000000, /* Max */
1617 0x00000000, /* Translation */
1618 0x00000001, /* Max-Min, RLEN */
1619 ,,
1620 PEBM
1621 )
1622 #endif
1624 /* memory space for PCI BARs below 4GB */
1625 Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
1626 }) /* End Name(_SB.PCI0.CRES) */
1628 Method(_CRS, 0) {
1629 /* DBGO("\\_SB\\PCI0\\_CRS\n") */
1631 #if 0
1632 CreateDWordField(CRES, ^EMM1._BAS, EM1B)
1633 CreateDWordField(CRES, ^EMM1._LEN, EM1L)
1634 CreateDWordField(CRES, ^DMLO._BAS, DMLB)
1635 CreateDWordField(CRES, ^DMLO._LEN, DMLL)
1636 CreateDWordField(CRES, ^PCBM._MIN, PBMB)
1637 CreateDWordField(CRES, ^PCBM._LEN, PBML)
1639 CreateQWordField(CRES, ^DMHI._MIN, DMHB)
1640 CreateQWordField(CRES, ^DMHI._LEN, DMHL)
1641 CreateQWordField(CRES, ^PEBM._MIN, EBMB)
1642 CreateQWordField(CRES, ^PEBM._LEN, EBML)
1644 If(LGreater(LOMH, 0xC0000)){
1645 Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */
1646 Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */
1647 }
1649 /* Set size of memory from 1MB to TopMem */
1650 Subtract(TOM1, 0x100000, DMLL)
1652 /*
1653 * If(LNotEqual(TOM2, 0x00000000)){
1654 * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2
1655 * Subtract(TOM2, 0x100000000, DMHL)
1656 * }
1657 */
1659 /* If there is no memory above 4GB, put the BIOS just below 4GB */
1660 If(LEqual(TOM2, 0x00000000)){
1661 Store(PBAD,PBMB) /* Reserve the "BIOS" space */
1662 Store(PBLN,PBML)
1663 }
1664 Else { /* Otherwise, put the BIOS just below 16EB */
1665 ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */
1666 Store(PBLN,EBML)
1667 }
1668 #endif
1670 CreateDWordField(CRES, ^MMIO._BAS, MM1B)
1671 CreateDWordField(CRES, ^MMIO._LEN, MM1L)
1672 /*
1673 * Declare memory between TOM1 and 4GB as available
1674 * for PCI MMIO.
1675 * Use ShiftLeft to avoid 64bit constant (for XP).
1676 * This will work even if the OS does 32bit arithmetic, as
1677 * 32bit (0x00000000 - TOM1) will wrap and give the same
1678 * result as 64bit (0x100000000 - TOM1).
1679 */
1680 Store(TOM1, MM1B)
1681 ShiftLeft(0x10000000, 4, Local0)
1682 Subtract(Local0, TOM1, Local0)
1683 Store(Local0, MM1L)
1685 Return(CRES) /* note to change the Name buffer */
1686 } /* end of Method(_SB.PCI0._CRS) */
1688 /*
1689 *
1690 * FIRST METHOD CALLED UPON BOOT
1691 *
1692 * 1. If debugging, print current OS and ACPI interpreter.
1693 * 2. Get PCI Interrupt routing from ACPI VSM, this
1694 * value is based on user choice in BIOS setup.
1695 */
1696 Method(_INI, 0) {
1697 /* DBGO("\\_SB\\_INI\n") */
1698 /* DBGO(" DSDT.ASL code from ") */
1699 /* DBGO(__DATE__) */
1700 /* DBGO(" ") */
1701 /* DBGO(__TIME__) */
1702 /* DBGO("\n Sleep states supported: ") */
1703 /* DBGO("\n") */
1704 /* DBGO(" \\_OS=") */
1705 /* DBGO(\_OS) */
1706 /* DBGO("\n \\_REV=") */
1707 /* DBGO(\_REV) */
1708 /* DBGO("\n") */
1710 /* Determine the OS we're running on */
1711 OSFL()
1713 /* On older chips, clear PciExpWakeDisEn */
1714 /*if (LLessEqual(\SBRI, 0x13)) {
1715 * Store(0,\PWDE)
1716 * }
1717 */
1718 } /* End Method(_SB._INI) */
1719 } /* End Device(PCI0) */
1721 Device(PWRB) { /* Start Power button device */
1722 Name(_HID, EISAID("PNP0C0C"))
1723 Name(_UID, 0xAA)
1724 Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */
1725 Name(_STA, 0x0B) /* sata is invisible */
1726 }
1727 } /* End \_SB scope */
1729 Scope(\_SI) {
1730 Method(_SST, 1) {
1731 /* DBGO("\\_SI\\_SST\n") */
1732 /* DBGO(" New Indicator state: ") */
1733 /* DBGO(Arg0) */
1734 /* DBGO("\n") */
1735 }
1736 } /* End Scope SI */
1738 #include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
1740 /* THERMAL */
1741 Scope(\_TZ) {
1742 Name (KELV, 2732)
1743 Name (THOT, 800)
1744 Name (TCRT, 850)
1746 ThermalZone(TZ00) {
1747 Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */
1748 /* DBGO("\\_TZ\\TZ00\\_AC0\n") */
1749 Return(Add(0, 2730))
1750 }
1751 Method(_AL0,0) { /* Returns package of cooling device to turn on */
1752 /* DBGO("\\_TZ\\TZ00\\_AL0\n") */
1753 Return(Package() {\_TZ.TZ00.FAN0})
1754 }
1755 Device (FAN0) {
1756 Name(_HID, EISAID("PNP0C0B"))
1757 Name(_PR0, Package() {PFN0})
1758 }
1760 PowerResource(PFN0,0,0) {
1761 Method(_STA) {
1762 Store(0xF,Local0)
1763 Return(Local0)
1764 }
1765 Method(_ON) {
1766 /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */
1767 }
1768 Method(_OFF) {
1769 /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */
1770 }
1771 }
1773 Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */
1774 /* DBGO("\\_TZ\\TZ00\\_HOT\n") */
1775 Return (Add (THOT, KELV))
1776 }
1777 Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */
1778 /* DBGO("\\_TZ\\TZ00\\_CRT\n") */
1779 Return (Add (TCRT, KELV))
1780 }
1781 Method(_TMP,0) { /* return current temp of this zone */
1782 Store (SMBR (0x07, 0x4C,, 0x00), Local0)
1783 If (LGreater (Local0, 0x10)) {
1784 Store (Local0, Local1)
1785 }
1786 Else {
1787 Add (Local0, THOT, Local0)
1788 Return (Add (400, KELV))
1789 }
1791 Store (SMBR (0x07, 0x4C, 0x01), Local0)
1792 /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */
1793 /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */
1794 If (LGreater (Local0, 0x10)) {
1795 If (LGreater (Local0, Local1)) {
1796 Store (Local0, Local1)
1797 }
1799 Multiply (Local1, 10, Local1)
1800 Return (Add (Local1, KELV))
1801 }
1802 Else {
1803 Add (Local0, THOT, Local0)
1804 Return (Add (400 , KELV))
1805 }
1806 } /* end of _TMP */
1807 } /* end of TZ00 */
1808 }
1809 }
1810 /* End of ASL file */