src/southbridge/intel/i82801gx/lpc.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/device.h>
   5 #include <device/pci.h>
   6 #include <device/pci_ids.h>
   7 #include <option.h>
   8 #include <pc80/mc146818rtc.h>
   9 #include <pc80/isa-dma.h>
  10 #include <pc80/i8259.h>
  11 #include <arch/io.h>
  12 #include <device/pci_ops.h>
  13 #include <arch/ioapic.h>
  14 #include <acpi/acpi.h>
  15 #include <cpu/x86/smm.h>
  16 #include <acpi/acpigen.h>
  17 #include <arch/smp/mpspec.h>
  18 #include <southbridge/intel/common/acpi_pirq_gen.h>
  19 #include <southbridge/intel/common/rcba_pirq.h>
  20 #include <southbridge/intel/common/hpet.h>
  21 #include <southbridge/intel/common/pmbase.h>
  22 #include <southbridge/intel/common/spi.h>
  23
  24 #include "chip.h"
  25 #include "i82801gx.h"
  26
  27 #define NMI_OFF 0
  28
  29 /**
  30  * Set miscellaneous static southbridge features.
  31  *
  32  * @param dev PCI device with I/O APIC control registers
  33  */
  34 static void i82801gx_enable_ioapic(struct device *dev)
  35 {
  36         set_ioapic_id(VIO_APIC_VADDR, 0x02);
  37
  38         /*
  39          * Select Boot Configuration register (0x03) and
  40          * use Processor System Bus (0x01) to deliver interrupts.
  41          */
  42         io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
  43 }
  44
  45 static void i82801gx_enable_serial_irqs(struct device *dev)
  46 {
  47         /* Set packet length and toggle silent mode bit for one frame. */
  48         pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
  49 }
  50
  51 /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
  52  * 0x00 - 0000 = Reserved
  53  * 0x01 - 0001 = Reserved
  54  * 0x02 - 0010 = Reserved
  55  * 0x03 - 0011 = IRQ3
  56  * 0x04 - 0100 = IRQ4
  57  * 0x05 - 0101 = IRQ5
  58  * 0x06 - 0110 = IRQ6
  59  * 0x07 - 0111 = IRQ7
  60  * 0x08 - 1000 = Reserved
  61  * 0x09 - 1001 = IRQ9
  62  * 0x0A - 1010 = IRQ10
  63  * 0x0B - 1011 = IRQ11
  64  * 0x0C - 1100 = IRQ12
  65  * 0x0D - 1101 = Reserved
  66  * 0x0E - 1110 = IRQ14
  67  * 0x0F - 1111 = IRQ15
  68  * PIRQ[n]_ROUT[7] - PIRQ Routing Control
  69  * 0x80 - The PIRQ is not routed.
  70  */
  71
  72 static void i82801gx_pirq_init(struct device *dev)
  73 {
  74         struct device *irq_dev;
  75         /* Get the chip configuration */
  76         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
  77
  78         pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
  79         pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
  80         pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
  81         pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
  82
  83         pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
  84         pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
  85         pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
  86         pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
  87
  88         /* Eric Biederman once said we should let the OS do this.
  89          * I am not so sure anymore he was right.
  90          */
  91
  92         for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
  93                 u8 int_pin = 0, int_line = 0;
  94
  95                 if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
  96                         continue;
  97
  98                 int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
  99
 100                 switch (int_pin) {
 101                 case 1:
 102                         /* INTA# */ int_line = config->pirqa_routing; break;
 103                 case 2:
 104                         /* INTB# */ int_line = config->pirqb_routing; break;
 105                 case 3:
 106                         /* INTC# */ int_line = config->pirqc_routing; break;
 107                 case 4:
 108                         /* INTD# */ int_line = config->pirqd_routing; break;
 109                 }
 110
 111                 if (!int_line)
 112                         continue;
 113
 114                 pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
 115         }
 116 }
 117
 118 static void i82801gx_gpi_routing(struct device *dev)
 119 {
 120         /* Get the chip configuration */
 121         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 122         u32 reg32 = 0;
 123
 124         /* An array would be much nicer here, or some other method of doing this. */
 125         reg32 |= (config->gpi0_routing & 0x03) << 0;
 126         reg32 |= (config->gpi1_routing & 0x03) << 2;
 127         reg32 |= (config->gpi2_routing & 0x03) << 4;
 128         reg32 |= (config->gpi3_routing & 0x03) << 6;
 129         reg32 |= (config->gpi4_routing & 0x03) << 8;
 130         reg32 |= (config->gpi5_routing & 0x03) << 10;
 131         reg32 |= (config->gpi6_routing & 0x03) << 12;
 132         reg32 |= (config->gpi7_routing & 0x03) << 14;
 133         reg32 |= (config->gpi8_routing & 0x03) << 16;
 134         reg32 |= (config->gpi9_routing & 0x03) << 18;
 135         reg32 |= (config->gpi10_routing & 0x03) << 20;
 136         reg32 |= (config->gpi11_routing & 0x03) << 22;
 137         reg32 |= (config->gpi12_routing & 0x03) << 24;
 138         reg32 |= (config->gpi13_routing & 0x03) << 26;
 139         reg32 |= (config->gpi14_routing & 0x03) << 28;
 140         reg32 |= (config->gpi15_routing & 0x03) << 30;
 141
 142         pci_write_config32(dev, GPIO_ROUT, reg32);
 143 }
 144
 145 static void i82801gx_power_options(struct device *dev)
 146 {
 147         u8 reg8;
 148         u16 reg16;
 149         u32 reg32;
 150         const char *state;
 151         /* Get the chip configuration */
 152         const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
 153
 154         /* Which state do we want to goto after g3 (power restored)?
 155          * 0 == S0 Full On
 156          * 1 == S5 Soft Off
 157          *
 158          * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
 159          */
 160         const int pwr_on = get_int_option("power_on_after_fail", MAINBOARD_POWER_ON);
 161
 162         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 163         reg8 &= 0xfe;
 164         switch (pwr_on) {
 165         case MAINBOARD_POWER_OFF:
 166                 reg8 |= 1;
 167                 state = "off";
 168                 break;
 169         case MAINBOARD_POWER_ON:
 170                 reg8 &= ~1;
 171                 state = "on";
 172                 break;
 173         case MAINBOARD_POWER_KEEP:
 174                 reg8 &= ~1;
 175                 state = "state keep";
 176                 break;
 177         default:
 178                 state = "undefined";
 179         }
 180
 181         reg8 |= (3 << 4);       /* avoid #S4 assertions */
 182         reg8 &= ~(1 << 3);      /* minimum assertion is 1 to 2 RTCCLK */
 183
 184         pci_write_config8(dev, GEN_PMCON_3, reg8);
 185         printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 186
 187         /* Set up NMI on errors. */
 188         reg8 = inb(0x61);
 189         reg8 &= 0x0f;           /* Higher Nibble must be 0 */
 190         reg8 &= ~(1 << 3);      /* IOCHK# NMI Enable */
 191         // reg8 &= ~(1 << 2);   /* PCI SERR# Enable */
 192         reg8 |= (1 << 2); /* PCI SERR# Disable for now */
 193         outb(reg8, 0x61);
 194
 195         reg8 = inb(0x70);
 196         const int nmi_option = get_int_option("nmi", NMI_OFF);
 197         if (nmi_option) {
 198                 printk(BIOS_INFO, "NMI sources enabled.\n");
 199                 reg8 &= ~(1 << 7);      /* Set NMI. */
 200         } else {
 201                 printk(BIOS_INFO, "NMI sources disabled.\n");
 202                 reg8 |= (1 << 7);       /* Can't mask NMI from PCI-E and NMI_NOW */
 203         }
 204         outb(reg8, 0x70);
 205
 206         /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
 207         reg16 = pci_read_config16(dev, GEN_PMCON_1);
 208         reg16 &= ~(3 << 0);     // SMI# rate 1 minute
 209         reg16 |= (1 << 2);      // CLKRUN_EN - Mobile/Ultra only
 210         reg16 |= (1 << 3);      // Speedstep Enable - Mobile/Ultra only
 211         reg16 |= (1 << 5);      // CPUSLP_EN Desktop only
 212
 213         if (config->c4onc3_enable)
 214                 reg16 |= (1 << 7);
 215
 216         // another laptop wants this?
 217         // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only
 218         reg16 |= (1 << 10);     // BIOS_PCI_EXP_EN - Desktop/Mobile only
 219         if (CONFIG(DEBUG_PERIODIC_SMI))
 220                 reg16 |= (3 << 0); // Periodic SMI every 8s
 221         pci_write_config16(dev, GEN_PMCON_1, reg16);
 222
 223         // Set the board's GPI routing.
 224         i82801gx_gpi_routing(dev);
 225
 226         write_pmbase32(GPE0_EN, config->gpe0_en);
 227         write_pmbase16(ALT_GP_SMI_EN, config->alt_gp_smi_en);
 228
 229         /* Set up power management block and determine sleep mode */
 230         reg32 = read_pmbase32(PM1_CNT);
 231
 232         reg32 &= ~(7 << 10);    // SLP_TYP
 233         reg32 |= (1 << 1);      // enable C3->C0 transition on bus master
 234         reg32 |= (1 << 0);      // SCI_EN
 235         write_pmbase32(PM1_CNT, reg32);
 236 }
 237
 238 static void i82801gx_configure_cstates(struct device *dev)
 239 {
 240         // Enable Popup & Popdown
 241         pci_or_config8(dev, 0xa9, (1 << 4) | (1 << 3) | (1 << 2));
 242
 243         // Set Deeper Sleep configuration to recommended values
 244         // Deeper Sleep to Stop CPU: 34-40us
 245         // Deeper Sleep to Sleep: 15us
 246         pci_update_config8(dev, 0xaa, 0xf0, (2 << 2) | (2 << 0));
 247 }
 248
 249 static void i82801gx_rtc_init(struct device *dev)
 250 {
 251         u8 reg8;
 252         int rtc_failed;
 253
 254         reg8 = pci_read_config8(dev, GEN_PMCON_3);
 255         rtc_failed = reg8 & RTC_BATTERY_DEAD;
 256         if (rtc_failed) {
 257                 reg8 &= ~RTC_BATTERY_DEAD;
 258                 pci_write_config8(dev, GEN_PMCON_3, reg8);
 259         }
 260         printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
 261
 262         cmos_init(rtc_failed);
 263 }
 264
 265 static void enable_clock_gating(void)
 266 {
 267         u32 reg32;
 268
 269         /* Enable Clock Gating for most devices */
 270         reg32 = RCBA32(CG);
 271         reg32 |= (1 << 31);     // LPC clock gating
 272         reg32 |= (1 << 30);     // PATA clock gating
 273         // SATA clock gating
 274         reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
 275         reg32 |= (1 << 23);     // AC97 clock gating
 276         reg32 |= (1 << 19);     // USB EHCI clock gating
 277         reg32 |= (1 << 3) | (1 << 1);   // DMI clock gating
 278         reg32 |= (1 << 2);      // PCIe clock gating;
 279         reg32 &= ~(1 << 20); // No static clock gating for USB
 280         reg32 &= ~((1 << 29) | (1 << 28)); // Disable UHCI clock gating
 281         RCBA32(CG) = reg32;
 282 }
 283
 284 static void i82801gx_set_acpi_mode(struct device *dev)
 285 {
 286         if (!acpi_is_wakeup_s3()) {
 287                 apm_control(APM_CNT_ACPI_DISABLE);
 288         } else {
 289                 apm_control(APM_CNT_ACPI_ENABLE);
 290         }
 291 }
 292
 293 #define SPIBASE 0x3020
 294 static void i82801gx_spi_init(void)
 295 {
 296         u16 spicontrol;
 297
 298         spicontrol = RCBA16(SPIBASE + 2);
 299         spicontrol &= ~(1 << 0); // SPI Access Request
 300         RCBA16(SPIBASE + 2) = spicontrol;
 301 }
 302
 303 static void i82801gx_fixups(struct device *dev)
 304 {
 305         /* This needs to happen after PCI enumeration */
 306         RCBA32(0x1d40) |= 1;
 307
 308         /* USB Transient Disconnect Detect:
 309          * Prevent a SE0 condition on the USB ports from being
 310          * interpreted by the UHCI controller as a disconnect
 311          */
 312         pci_write_config8(dev, 0xad, 0x3);
 313 }
 314
 315 static void lpc_init(struct device *dev)
 316 {
 317         printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
 318
 319         /* IO APIC initialization. */
 320         i82801gx_enable_ioapic(dev);
 321
 322         i82801gx_enable_serial_irqs(dev);
 323
 324         /* Setup the PIRQ. */
 325         i82801gx_pirq_init(dev);
 326
 327         /* Setup power options. */
 328         i82801gx_power_options(dev);
 329
 330         /* Configure Cx state registers */
 331         i82801gx_configure_cstates(dev);
 332
 333         /* Initialize the real time clock. */
 334         i82801gx_rtc_init(dev);
 335
 336         /* Initialize ISA DMA. */
 337         isa_dma_init();
 338
 339         /* Initialize the High Precision Event Timers, if present. */
 340         enable_hpet();
 341
 342         /* Initialize Clock Gating */
 343         enable_clock_gating();
 344
 345         setup_i8259();
 346
 347         /* The OS should do this? */
 348         /* Interrupt 9 should be level triggered (SCI) */
 349         i8259_configure_irq_trigger(9, 1);
 350
 351         i82801gx_set_acpi_mode(dev);
 352
 353         i82801gx_spi_init();
 354
 355         i82801gx_fixups(dev);
 356 }
 357
 358 unsigned long acpi_fill_madt(unsigned long current)
 359 {
 360         /* Local APICs */
 361         current = acpi_create_madt_lapics(current);
 362
 363         /* IOAPIC */
 364         current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0);
 365
 366         /* LAPIC_NMI */
 367         current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
 368                                 current, 0,
 369                                 MP_IRQ_POLARITY_HIGH |
 370                                 MP_IRQ_TRIGGER_EDGE, 0x01);
 371         current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
 372                                 current, 1, MP_IRQ_POLARITY_HIGH |
 373                                 MP_IRQ_TRIGGER_EDGE, 0x01);
 374
 375         /* INT_SRC_OVR */
 376         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 377                  current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE);
 378         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
 379                  current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
 380
 381         return current;
 382 }
 383
 384 static void i82801gx_lpc_read_resources(struct device *dev)
 385 {
 386         struct resource *res;
 387         u8 io_index = 0;
 388         int i;
 389
 390         /* Get the normal PCI resources of this device. */
 391         pci_dev_read_resources(dev);
 392
 393         /* Add an extra subtractive resource for both memory and I/O. */
 394         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 395         res->base = 0;
 396         res->size = 0x1000;
 397         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 398                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 399
 400         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 401         res->base = 0xff800000;
 402         res->size = 0x00800000; /* 8 MB for flash */
 403         res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
 404                      IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 405
 406         res = new_resource(dev, 3); /* IOAPIC */
 407         res->base = IO_APIC_ADDR;
 408         res->size = 0x00001000;
 409         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 410
 411         /* Set IO decode ranges if required.*/
 412         for (i = 0; i < 4; i++) {
 413                 u32 gen_dec;
 414                 gen_dec = pci_read_config32(dev, 0x84 + 4 * i);
 415
 416                 if ((gen_dec & 0xFFFC) > 0x1000) {
 417                         res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
 418                         res->base = gen_dec & 0xFFFC;
 419                         res->size = (gen_dec >> 16) & 0xFC;
 420                         res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
 421                                 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 422                 }
 423         }
 424 }
 425
 426 #define SPIBAR16(x) RCBA16(0x3020 + x)
 427 #define SPIBAR32(x) RCBA32(0x3020 + x)
 428
 429 static void lpc_final(struct device *dev)
 430 {
 431         u16 tco1_cnt;
 432
 433         if (!CONFIG(INTEL_CHIPSET_LOCKDOWN))
 434                 return;
 435
 436         if (CONFIG(BOOT_DEVICE_SPI_FLASH))
 437                 spi_finalize_ops();
 438
 439         /* Lock SPIBAR */
 440         SPIBAR16(0) = SPIBAR16(0) | (1 << 15);
 441
 442         /* BIOS Interface Lockdown */
 443         RCBA32(0x3410) |= 1 << 0;
 444
 445         /* Global SMI Lock */
 446         pci_or_config16(dev, GEN_PMCON_1, 1 << 4);
 447
 448         /* TCO_Lock */
 449         tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT);
 450         tco1_cnt |= (1 << 12); /* TCO lock */
 451         outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
 452
 453         /* Indicate finalize step with post code */
 454         outb(POST_OS_BOOT, 0x80);
 455 }
 456
 457 static const char *lpc_acpi_name(const struct device *dev)
 458 {
 459         return "LPCB";
 460 }
 461
 462 static void southbridge_fill_ssdt(const struct device *device)
 463 {
 464         intel_acpi_gen_def_acpi_pirq(device);
 465 }
 466
 467 static struct device_operations device_ops = {
 468         .read_resources         = i82801gx_lpc_read_resources,
 469         .set_resources          = pci_dev_set_resources,
 470         .enable_resources       = pci_dev_enable_resources,
 471         .write_acpi_tables      = acpi_write_hpet,
 472         .acpi_fill_ssdt         = southbridge_fill_ssdt,
 473         .acpi_name              = lpc_acpi_name,
 474         .init                   = lpc_init,
 475         .scan_bus               = scan_static_bus,
 476         .enable                 = i82801gx_enable,
 477         .ops_pci                = &pci_dev_ops_pci,
 478         .final                  = lpc_final,
 479 };
 480
 481 static const unsigned short pci_device_ids[] = {
 482         0x27b0, /* 82801GH (ICH7 DH) */
 483         0x27b8, /* 82801GB/GR (ICH7/ICH7R) */
 484         0x27b9, /* 82801GBM/GU (ICH7-M/ICH7-U) */
 485         0x27bc, /* 82NM10 (NM10) */
 486         0x27bd, /* 82801GHM (ICH7-M DH) */
 487         0
 488 };
 489
 490 static const struct pci_driver ich7_lpc __pci_driver = {
 491         .ops    = &device_ops,
 492         .vendor = PCI_VENDOR_ID_INTEL,
 493         .devices = pci_device_ids,
 494 };