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soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` config
[coreboot.git] / src / mainboard / google / dedede / variants / baseboard / devicetree.cb
blob1349f69dab97c2a844b81f0a15eb6fb6db7e34c3
1 fw_config
2 field DB_PORTS 0 3
3 option DB_PORTS_NONE 0
4 option DB_PORTS_2C_2A 1
5 option DB_PORTS_1C_LTE 2
6 option DB_PORTS_1A_HDMI 3
7 option DB_PORTS_1C_1A 4
8 option DB_PORTS_LTE_HDMI 5
9 option DB_PORTS_1C_1A_LTE 6
10 option DB_PORTS_1C 7
11 option DB_PORTS_1A_HDMI_LTE 8
12 end
13 field STYLUS 4
14 option STYLUS_ABSENT 0
15 option STYLUS_PRESENT 1
16 end
17 field TABLETMODE 10
18 option TABLETMODE_DISABLED 0
19 option TABLETMODE_ENABLED 1
20 end
21 field AUDIO_AMP 14 16
22 option UNPROVISIONED 0
23 option MAX98360 1
24 option RT1015_I2C 2
25 option RT1015P_AUTO 3
26 end
27 field LTE 11
28 option LTE_ABSENT 0
29 option LTE_PRESENT 1
30 end
31 field EXT_VR 18
32 option EXT_VR_PRESENT 0
33 option EXT_VR_ABSENT 1
34 end
35 end
36
37 chip soc/intel/jasperlake
38 device cpu_cluster 0 on end
39
40 # GPE configuration
41 # Note that GPE events called out in ASL code rely on this
42 # route, i.e., if this route changes then the affected GPE
43 # offset bits also need to be changed.
44 # DW0 is used by:
45 # - GPP_B3 - TRACKPAD_INT_ODL
46 # - GPP_B4 - H1_AP_INT_ODL
47 # DW1 is used by:
48 # - GPP_C12 - AP_PEN_DET_ODL
49 # DW2 is used by:
50 # - GPP_D0 - WWAN_HOST_WAKE
51 # - GPP_D3 - WLAN_PCIE_WAKE_ODL
52 # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
53 register "pmc_gpe0_dw0" = "PMC_GPP_B"
54 register "pmc_gpe0_dw1" = "PMC_GPP_C"
55 register "pmc_gpe0_dw2" = "PMC_GPP_D"
56
57 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
58 register "gen1_dec" = "0x00fc0801"
59 register "gen2_dec" = "0x000c0201"
60 # EC memory map range is 0x900-0x9ff
61 register "gen3_dec" = "0x00fc0901"
62
63 # USB Port Configuration
64 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0
65 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
66 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
67 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
68 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
69 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth
70
71 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0
72 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1
73 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0
74 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1
75
76 register "SerialIoI2cMode" = "{
77 [PchSerialIoIndexI2C0] = PchSerialIoPci,
78 [PchSerialIoIndexI2C1] = PchSerialIoPci,
79 [PchSerialIoIndexI2C2] = PchSerialIoPci,
80 [PchSerialIoIndexI2C3] = PchSerialIoPci,
81 [PchSerialIoIndexI2C4] = PchSerialIoPci,
82 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
83 }"
84
85 register "SerialIoGSpiMode" = "{
86 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
87 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
88 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
89 }"
90
91 register "SerialIoGSpiCsMode" = "{
92 [PchSerialIoIndexGSPI0] = 1,
93 [PchSerialIoIndexGSPI1] = 0,
94 [PchSerialIoIndexGSPI2] = 0,
95 }"
96
97 register "SerialIoGSpiCsState" = "{
98 [PchSerialIoIndexGSPI0] = 0,
99 [PchSerialIoIndexGSPI1] = 0,
100 [PchSerialIoIndexGSPI2] = 0,
101 }"
102
103 register "SerialIoUartMode" = "{
104 [PchSerialIoIndexUART0] = PchSerialIoDisabled,
105 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
106 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
107 }"
108
109 # PCIE Root Port Configuration
110 register "PcieRpEnable[0]" = "0"
111 register "PcieRpEnable[1]" = "0"
112 register "PcieRpEnable[2]" = "0"
113 register "PcieRpEnable[3]" = "0"
114 register "PcieRpEnable[4]" = "0"
115 register "PcieRpEnable[5]" = "0"
116 register "PcieRpEnable[6]" = "0"
117 # PCIe Root Port 8 (index 7) hosts M.2 E-key WLAN.
118 register "PcieRpEnable[7]" = "1"
119
120 register "PcieClkSrcUsage[0]" = "0xff"
121 register "PcieClkSrcUsage[1]" = "0xff"
122 register "PcieClkSrcUsage[2]" = "0xff"
123 # PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7)
124 register "PcieClkSrcUsage[3]" = "7"
125 register "PcieClkSrcUsage[4]" = "0xff"
126 register "PcieClkSrcUsage[5]" = "0xff"
127
128 # PCIE Clock Request to Clock Source Mapping
129 register "PcieClkSrcClkReq[0]" = "0"
130 register "PcieClkSrcClkReq[1]" = "1"
131 register "PcieClkSrcClkReq[2]" = "2"
132 register "PcieClkSrcClkReq[3]" = "3"
133 register "PcieClkSrcClkReq[4]" = "4"
134 register "PcieClkSrcClkReq[5]" = "5"
135
136 # Audio related configurations
137 register "PchHdaDspEnable" = "1"
138 register "PchHdaAudioLinkHdaEnable" = "1"
139 register "PchHdaAudioLinkSspEnable[0]" = "1"
140 register "PchHdaAudioLinkSspEnable[1]" = "1"
141 register "PchHdaAudioLinkDmicEnable[0]" = "1"
142 register "PchHdaAudioLinkDmicEnable[1]" = "1"
143
144 # Enable EMMC HS400 mode
145 register "ScsEmmcHs400Enabled" = "1"
146
147 # GPIO for SD card detect
148 register "sdcard_cd_gpio" = "VGPIO_39"
149 # SD card power enable polarity
150 register "SdCardPowerEnableActiveHigh" = "1"
151
152 # Enable S0ix support
153 register "s0ix_enable" = "1"
154
155 # Display related UPDs
156 # Select eDP for port A
157 register "DdiPortAConfig" = "1"
158
159 # Enable HPD for DDI ports B/C
160 register "DdiPortBHpd" = "1"
161 register "DdiPortCHpd" = "1"
162 # Enable DDC for DDI ports B/C
163 register "DdiPortBDdc" = "1"
164 register "DdiPortCDdc" = "1"
165
166 # Enable DPTF
167 register "dptf_enable" = "1"
168
169 register "power_limits_config" = "{
170 .tdp_pl1_override = 6,
171 .tdp_pl2_override = 20,
172 }"
173
174 register "tcc_offset" = "10" # TCC of 90C
175
176 # VR config settings
177 # Imon Slope correction specified in 1/100 increment values. Range is 0-200.
178 # Eg: 125 = 1.25
179 register "ImonSlope" = "100"
180
181 # Imon offset correction. Value is a 2's complement signed integer.
182 # Units 1/1000, Range 0-63999.
183 # For an offset = 12.580, use 12580
184 register "ImonOffset" = "0"
185
186 # Skip the CPU repalcement check
187 register "SkipCpuReplacementCheck" = "1"
188
189 # Sagv Configuration
190 register "SaGv" = "SaGv_Enabled"
191
192 # Set the minimum assertion width
193 register "PchPmSlpS3MinAssert" = "3" # 50ms
194 register "PchPmSlpS4MinAssert" = "1" # 1s
195 register "PchPmSlpSusMinAssert" = "3" # 1s
196 register "PchPmSlpAMinAssert" = "3" # 98ms
197
198 # NOTE: Duration programmed in the below register should never be smaller than the
199 # stretch duration programmed in the following registers -
200 # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
201 # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
202 # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
203 # - PM_CFG.SLP_LAN_MIN_ASST_WDTH
204 register "PchPmPwrCycDur" = "1" # 1s
205
206 # Set xHCI LFPS period sampling off time, the default is 9ms.
207 register "xhci_lfps_sampling_offtime_ms" = "9"
208
209 device domain 0 on
210 device pci 00.0 on end # Host Bridge
211 device pci 02.0 on end # Integrated Graphics Device
212 device pci 04.0 on
213 # Default DPTF Policy for all Dedede boards if not overridden
214 chip drivers/intel/dptf
215 ## Passive Policy
216 register "policies.passive" = "{
217 [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
218 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
219 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000),
220 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000)
221 }"
222
223 ## Critical Policy
224 register "policies.critical" = "{
225 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
226 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
227 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
228 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN)
229 }"
230
231 ## Power Limits Control
232 register "controls.power_limits" = "{
233 .pl1 = {
234 .min_power = 3000,
235 .max_power = 6000,
236 .time_window_min = 1 * MSECS_PER_SEC,
237 .time_window_max = 1 * MSECS_PER_SEC,
238 .granularity = 200,
239 },
240 .pl2 = {
241 .min_power = 20000,
242 .max_power = 20000,
243 .time_window_min = 1 * MSECS_PER_SEC,
244 .time_window_max = 1 * MSECS_PER_SEC,
245 .granularity = 1000,
246 }
247 }"
248
249 register "options.tsr[0].desc" = ""Memory""
250 register "options.tsr[1].desc" = ""Ambient""
251 register "options.tsr[2].desc" = ""Charger""
252
253 ## Charger Performance Control (Control, mA)
254 register "controls.charger_perf" = "{
255 [0] = { 255, 3000 },
256 [1] = { 24, 1500 },
257 [2] = { 16, 1000 },
258 [3] = { 8, 500 }
259 }"
260
261 device generic 0 on end
262 end
263 end # SA Thermal device
264 device pci 05.0 off end # IPU
265 device pci 09.0 off end # Intel Trace Hub
266 device pci 12.6 off end # GSPI 2
267 device pci 14.0 on
268 chip drivers/usb/acpi
269 register "desc" = ""Root Hub""
270 register "type" = "UPC_TYPE_HUB"
271 device usb 0.0 on
272 chip drivers/usb/acpi
273 register "desc" = ""Left Type-C Port""
274 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
275 register "group" = "ACPI_PLD_GROUP(1, 1)"
276 device usb 2.0 on end
277 end
278 chip drivers/usb/acpi
279 register "desc" = ""Right Type-C Port""
280 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
281 register "group" = "ACPI_PLD_GROUP(2, 1)"
282 device usb 2.1 on end
283 end
284 chip drivers/usb/acpi
285 register "desc" = ""Left Type-A Port""
286 register "type" = "UPC_TYPE_A"
287 register "group" = "ACPI_PLD_GROUP(1, 2)"
288 device usb 2.2 on end
289 end
290 chip drivers/usb/acpi
291 register "desc" = ""Right Type-A Port""
292 register "type" = "UPC_TYPE_A"
293 register "group" = "ACPI_PLD_GROUP(2, 2)"
294 device usb 2.3 on end
295 end
296 chip drivers/usb/acpi
297 device usb 2.4 off end
298 end
299 chip drivers/usb/acpi
300 device usb 2.5 off end
301 end
302 chip drivers/usb/acpi
303 device usb 2.6 off end
304 end
305 chip drivers/usb/acpi
306 register "desc" = ""Bluetooth""
307 register "type" = "UPC_TYPE_INTERNAL"
308 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
309 device usb 2.7 on end
310 end
311 chip drivers/usb/acpi
312 register "desc" = ""Left Type-C Port""
313 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
314 register "group" = "ACPI_PLD_GROUP(1, 1)"
315 device usb 3.0 on end
316 end
317 chip drivers/usb/acpi
318 register "desc" = ""Right Type-C Port""
319 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
320 register "group" = "ACPI_PLD_GROUP(2, 1)"
321 device usb 3.1 on end
322 end
323 chip drivers/usb/acpi
324 register "desc" = ""Left Type-A Port""
325 register "type" = "UPC_TYPE_USB3_A"
326 register "group" = "ACPI_PLD_GROUP(1, 2)"
327 device usb 3.2 on end
328 end
329 chip drivers/usb/acpi
330 register "desc" = ""Right Type-A Port""
331 register "type" = "UPC_TYPE_USB3_A"
332 register "group" = "ACPI_PLD_GROUP(2, 2)"
333 device usb 3.3 on end
334 end
335 end
336 end
337 end # USB xHCI
338 device pci 14.1 off end # USB xDCI (OTG)
339 device pci 14.2 off end # PMC SRAM
340 device pci 14.3 on
341 chip drivers/wifi/generic
342 register "wake" = "GPE0_PME_B0"
343 device generic 0 on end
344 end
345 end # CNVi wifi
346 device pci 14.5 on end # SDCard
347 device pci 15.0 on end # I2C 0
348 device pci 15.1 on end # I2C 1
349 device pci 15.2 on end # I2C 2
350 device pci 15.3 on end # I2C 3
351 device pci 16.0 on end # HECI 1
352 device pci 16.1 off end # HECI 2
353 device pci 16.4 off end # HECI 3
354 device pci 16.5 off end # HECI 4
355 device pci 17.0 off end # SATA
356 device pci 19.0 on end # I2C 4
357 device pci 19.1 off end # I2C 5
358 device pci 19.2 on end # UART 2
359 device pci 1a.0 on end # eMMC
360 device pci 1c.0 off end # PCI Express Root Port 1
361 device pci 1c.1 off end # PCI Express Root Port 2
362 device pci 1c.2 off end # PCI Express Root Port 3
363 device pci 1c.3 off end # PCI Express Root Port 4
364 device pci 1c.4 off end # PCI Express Root Port 5
365 device pci 1c.5 off end # PCI Express Root Port 6
366 device pci 1c.6 off end # PCI Express Root Port 7
367 # External PCIe port 4 is mapped to PCIe Root port 8
368 device pci 1c.7 on end # PCI Express Root Port 8 - WLAN
369 device pci 1e.0 off end # UART 0
370 device pci 1e.1 off end # UART 1
371 device pci 1e.2 on
372 chip drivers/spi/acpi
373 register "hid" = "ACPI_DT_NAMESPACE_HID"
374 register "compat_string" = ""google,cr50""
375 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
376 device spi 0 on end
377 end
378 end # GSPI 0
379 device pci 1e.3 off end # GSPI 1
380 device pci 1f.0 on
381 chip ec/google/chromeec
382 device pnp 0c09.0 on end
383 end
384 end # eSPI Interface
385 device pci 1f.1 on end # P2SB
386 device pci 1f.2 hidden end # Power Management Controller
387 device pci 1f.3 off end # Intel HDA/cAVS
388 device pci 1f.4 off end # SMBus
389 device pci 1f.5 on end # PCH SPI
390 device pci 1f.7 off end # Intel Trace Hub
391 end
392 end
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