| commit | f04e83abbf98d1d55ec2c4fea3fb74bf2f459139 | |
| author | Subrata Banik <subratabanik@google.com> | |
| Mon, 3 Jan 2022 19:00:00 +0000 (3 19:00 +0000) | ||
| committer | Paul Fagerburg <pfagerburg@chromium.org> | |
| Fri, 14 Jan 2022 00:33:23 +0000 (14 00:33 +0000) | ||
| tree | 913e22a7f68ea646b686ea151282a9fc07048078 | treesnapshot (tar.gz zip) |
| parent | ad50b40eed3f7f235e848a2382ffbee6a51d1755 | commitdiff |
soc/intel/jsl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib9fb554c8f3cfd1e91bbcd1977905e1321db0802
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>