2 ## This file is part of the coreboot project.
5 ## SPDX-License-Identifier: GPL-2.0-only
7 if BOARD_INTEL_HARCUVAR
9 config BOARD_SPECIFIC_OPTIONS
11 select SOC_INTEL_DENVERTON_NS
12 select BOARD_ROMSIZE_KB_16384
13 select HAVE_ACPI_TABLES
17 default "intel/harcuvar"
19 config MAINBOARD_PART_NUMBER
21 default "Harcuvar CRB"
23 config ENABLE_FSP_MEMORY_DOWN
24 bool "Enable Memory Down"
27 Select this option to enable Memory Down function.
30 depends on ENABLE_FSP_MEMORY_DOWN
31 hex "SPD binary location in cbfs"
34 Location of SPD binary for memory down function.
36 endif # BOARD_INTEL_HARCUVAR