src/soc/amd/picasso/southbridge.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <device/mmio.h>
   5 #include <bootstate.h>
   6 #include <cpu/amd/msr.h>
   7 #include <cpu/x86/smm.h>
   8 #include <cpu/x86/msr.h>
   9 #include <device/device.h>
  10 #include <device/pci.h>
  11 #include <device/pci_ops.h>
  12 #include <cbmem.h>
  13 #include <acpi/acpi_gnvs.h>
  14 #include <amdblocks/amd_pci_util.h>
  15 #include <amdblocks/reset.h>
  16 #include <amdblocks/acpimmio.h>
  17 #include <amdblocks/espi.h>
  18 #include <amdblocks/lpc.h>
  19 #include <amdblocks/acpi.h>
  20 #include <amdblocks/spi.h>
  21 #include <soc/cpu.h>
  22 #include <soc/i2c.h>
  23 #include <soc/southbridge.h>
  24 #include <soc/smi.h>
  25 #include <soc/uart.h>
  26 #include <soc/amd_pci_int_defs.h>
  27 #include <delay.h>
  28 #include <soc/pci_devs.h>
  29 #include <soc/nvs.h>
  30 #include <types.h>
  31 #include "chip.h"
  32
  33 /*
  34  * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
  35  * provides a visible association with the index, therefore helping
  36  * maintainability of table. If a new index/name is defined in
  37  * amd_pci_int_defs.h, just add the pair at the end of this table.
  38  * Order is not important.
  39  */
  40 const static struct irq_idx_name irq_association[] = {
  41         { PIRQ_A,       "INTA#" },
  42         { PIRQ_B,       "INTB#" },
  43         { PIRQ_C,       "INTC#" },
  44         { PIRQ_D,       "INTD#" },
  45         { PIRQ_E,       "INTE#" },
  46         { PIRQ_F,       "INTF#/GENINT2" },
  47         { PIRQ_G,       "INTG#" },
  48         { PIRQ_H,       "INTH#" },
  49         { PIRQ_MISC,    "Misc" },
  50         { PIRQ_MISC0,   "Misc0" },
  51         { PIRQ_MISC1,   "Misc1" },
  52         { PIRQ_MISC2,   "Misc2" },
  53         { PIRQ_SIRQA,   "Ser IRQ INTA" },
  54         { PIRQ_SIRQB,   "Ser IRQ INTB" },
  55         { PIRQ_SIRQC,   "Ser IRQ INTC" },
  56         { PIRQ_SIRQD,   "Ser IRQ INTD" },
  57         { PIRQ_SCI,     "SCI" },
  58         { PIRQ_SMBUS,   "SMBUS" },
  59         { PIRQ_ASF,     "ASF" },
  60         { PIRQ_PMON,    "PerMon" },
  61         { PIRQ_SD,      "SD" },
  62         { PIRQ_SDIO,    "SDIO" },
  63         { PIRQ_CIR,     "CIR" },
  64         { PIRQ_GPIOA,   "GPIOa" },
  65         { PIRQ_GPIOB,   "GPIOb" },
  66         { PIRQ_GPIOC,   "GPIOc" },
  67         { PIRQ_SATA,    "SATA" },
  68         { PIRQ_EMMC,    "eMMC" },
  69         { PIRQ_GPP0,    "GPP0" },
  70         { PIRQ_GPP1,    "GPP1" },
  71         { PIRQ_GPP2,    "GPP2" },
  72         { PIRQ_GPP3,    "GPP3" },
  73         { PIRQ_GPIO,    "GPIO" },
  74         { PIRQ_I2C0,    "I2C0" },
  75         { PIRQ_I2C1,    "I2C1" },
  76         { PIRQ_I2C2,    "I2C2" },
  77         { PIRQ_I2C3,    "I2C3" },
  78         { PIRQ_UART0,   "UART0" },
  79         { PIRQ_UART1,   "UART1" },
  80         { PIRQ_I2C4,    "I2C4" },
  81         { PIRQ_I2C5,    "I2C5" },
  82         { PIRQ_UART2,   "UART2" },
  83         { PIRQ_UART3,   "UART3" },
  84 };
  85
  86 const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
  87 {
  88         *size = ARRAY_SIZE(irq_association);
  89         return irq_association;
  90 }
  91
  92 static void sb_enable_cf9_io(void)
  93 {
  94         uint32_t reg = pm_read32(PM_DECODE_EN);
  95
  96         pm_write32(PM_DECODE_EN, reg | CF9_IO_EN);
  97 }
  98
  99 static void sb_enable_legacy_io(void)
 100 {
 101         uint32_t reg = pm_read32(PM_DECODE_EN);
 102
 103         pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
 104 }
 105
 106 void sb_clk_output_48Mhz(void)
 107 {
 108         u32 ctrl;
 109
 110         ctrl = misc_read32(MISC_CLK_CNTL1);
 111         ctrl |= BP_X48M0_OUTPUT_EN;
 112         misc_write32(MISC_CLK_CNTL1, ctrl);
 113 }
 114
 115 static void fch_smbus_init(void)
 116 {
 117         /* 400 kHz smbus speed. */
 118         const uint8_t smbus_speed = (66000000 / (400000 * 4));
 119
 120         pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8);
 121         smbus_write8(SMBTIMING, smbus_speed);
 122         /* Clear all SMBUS status bits */
 123         smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
 124         smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
 125         asf_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR);
 126         asf_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR);
 127 }
 128
 129 static void lpc_configure_decodes(void)
 130 {
 131         if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
 132                 lpc_enable_port80();
 133 }
 134
 135 /* Before console init */
 136 void fch_pre_init(void)
 137 {
 138         lpc_early_init();
 139
 140         if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
 141                 lpc_configure_decodes();
 142
 143         fch_spi_early_init();
 144         enable_acpimmio_decode_pm04();
 145         fch_smbus_init();
 146         sb_enable_cf9_io();
 147         sb_enable_legacy_io();
 148         enable_aoac_devices();
 149         sb_reset_i2c_slaves();
 150
 151         /*
 152          * On reset Range_0 defaults to enabled. We want to start with a clean
 153          * slate to not have things unexpectedly enabled.
 154          */
 155         clear_uart_legacy_config();
 156
 157         if (CONFIG(PICASSO_CONSOLE_UART))
 158                 set_uart_config(CONFIG_UART_FOR_CONSOLE);
 159 }
 160
 161 static void print_num_status_bits(int num_bits, uint32_t status,
 162                                   const char *const bit_names[])
 163 {
 164         int i;
 165
 166         if (!status)
 167                 return;
 168
 169         for (i = num_bits - 1; i >= 0; i--) {
 170                 if (status & (1 << i)) {
 171                         if (bit_names[i])
 172                                 printk(BIOS_DEBUG, "%s ", bit_names[i]);
 173                         else
 174                                 printk(BIOS_DEBUG, "BIT%d ", i);
 175                 }
 176         }
 177 }
 178
 179 static void sb_print_pmxc0_status(void)
 180 {
 181         /* PMxC0 S5/Reset Status shows the source of previous reset. */
 182         uint32_t pmxc0_status = pm_read32(PM_RST_STATUS);
 183
 184         static const char *const pmxc0_status_bits[32] = {
 185                 [0] = "ThermalTrip",
 186                 [1] = "FourSecondPwrBtn",
 187                 [2] = "Shutdown",
 188                 [3] = "ThermalTripFromTemp",
 189                 [4] = "RemotePowerDownFromASF",
 190                 [5] = "ShutDownFan0",
 191                 [16] = "UserRst",
 192                 [17] = "SoftPciRst",
 193                 [18] = "DoInit",
 194                 [19] = "DoReset",
 195                 [20] = "DoFullReset",
 196                 [21] = "SleepReset",
 197                 [22] = "KbReset",
 198                 [23] = "LtReset",
 199                 [24] = "FailBootRst",
 200                 [25] = "WatchdogIssueReset",
 201                 [26] = "RemoteResetFromASF",
 202                 [27] = "SyncFlood",
 203                 [28] = "HangReset",
 204                 [29] = "EcWatchdogRst",
 205         };
 206
 207         printk(BIOS_DEBUG, "PMxC0 STATUS: 0x%x ", pmxc0_status);
 208         print_num_status_bits(ARRAY_SIZE(pmxc0_status_bits), pmxc0_status,
 209                               pmxc0_status_bits);
 210         printk(BIOS_DEBUG, "\n");
 211 }
 212
 213 /* After console init */
 214 void fch_early_init(void)
 215 {
 216         sb_print_pmxc0_status();
 217         i2c_soc_early_init();
 218
 219         if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
 220                 lpc_disable_spi_rom_sharing();
 221
 222         if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI)) {
 223                 espi_setup();
 224                 espi_configure_decodes();
 225         }
 226 }
 227
 228 void sb_enable(struct device *dev)
 229 {
 230         printk(BIOS_DEBUG, "%s\n", __func__);
 231 }
 232
 233 static void sb_init_acpi_ports(void)
 234 {
 235         u32 reg;
 236
 237         /* We use some of these ports in SMM regardless of whether or not
 238          * ACPI tables are generated. Enable these ports indiscriminately.
 239          */
 240
 241         pm_write16(PM_EVT_BLK, ACPI_PM_EVT_BLK);
 242         pm_write16(PM1_CNT_BLK, ACPI_PM1_CNT_BLK);
 243         pm_write16(PM_TMR_BLK, ACPI_PM_TMR_BLK);
 244         pm_write16(PM_GPE0_BLK, ACPI_GPE0_BLK);
 245
 246         if (CONFIG(HAVE_SMI_HANDLER)) {
 247                 /* APMC - SMI Command Port */
 248                 pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
 249                 configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
 250
 251                 /* SMI on SlpTyp requires sending SMI before completion
 252                  * response of the I/O write.  The BKDG also specifies
 253                  * clearing ForceStpClkRetry for SMI trapping.
 254                  */
 255                 reg = pm_read32(PM_PCI_CTRL);
 256                 reg |= FORCE_SLPSTATE_RETRY;
 257                 pm_write32(PM_PCI_CTRL, reg);
 258
 259                 /* Disable SlpTyp feature */
 260                 reg = pm_read8(PM_RST_CTRL1);
 261                 reg &= ~SLPTYPE_CONTROL_EN;
 262                 pm_write8(PM_RST_CTRL1, reg);
 263
 264                 configure_smi(SMITYPE_SLP_TYP, SMI_MODE_SMI);
 265         } else {
 266                 pm_write16(PM_ACPI_SMI_CMD, 0);
 267         }
 268
 269         /* Decode ACPI registers and enable standard features */
 270         pm_write8(PM_ACPI_CONF, PM_ACPI_DECODE_STD |
 271                                 PM_ACPI_GLOBAL_EN |
 272                                 PM_ACPI_RTC_EN_EN |
 273                                 PM_ACPI_TIMER_EN_EN);
 274 }
 275
 276 static void set_nvs_sws(void *unused)
 277 {
 278         struct acpi_pm_gpe_state *state;
 279         struct global_nvs *gnvs;
 280
 281         state = cbmem_find(CBMEM_ID_POWER_STATE);
 282         if (state == NULL)
 283                 return;
 284         gnvs = acpi_get_gnvs();
 285         if (gnvs == NULL)
 286                 return;
 287
 288         acpi_fill_gnvs(gnvs, state);
 289 }
 290
 291 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);
 292
 293 /*
 294  * A-Link to AHB bridge, part of the AMBA fabric. These are internal clocks
 295  * and unneeded for Raven/Picasso so gate them to save power.
 296  */
 297 static void al2ahb_clock_gate(void)
 298 {
 299         uint8_t al2ahb_val;
 300         uintptr_t al2ahb_base = ALINK_AHB_ADDRESS;
 301
 302         al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET));
 303         al2ahb_val |= AL2AHB_CLK_GATE_EN;
 304         write8((void *)(al2ahb_base + AL2AHB_CONTROL_CLK_OFFSET), al2ahb_val);
 305         al2ahb_val = read8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET));
 306         al2ahb_val |= AL2AHB_HCLK_GATE_EN;
 307         write8((void *)(al2ahb_base + AL2AHB_CONTROL_HCLK_OFFSET), al2ahb_val);
 308 }
 309
 310 void southbridge_init(void *chip_info)
 311 {
 312         struct acpi_pm_gpe_state *state;
 313
 314         i2c_soc_init();
 315         sb_init_acpi_ports();
 316
 317         state = cbmem_find(CBMEM_ID_POWER_STATE);
 318         if (state)
 319                 acpi_pm_gpe_add_events_print_events(state);
 320         acpi_clear_pm_gpe_status();
 321
 322         al2ahb_clock_gate();
 323 }
 324
 325 void southbridge_final(void *chip_info)
 326 {
 327         uint8_t restored_power = PM_S5_AT_POWER_RECOVERY;
 328
 329         if (CONFIG(MAINBOARD_POWER_RESTORE))
 330                 restored_power = PM_RESTORE_S0_IF_PREV_S0;
 331         pm_write8(PM_RTC_SHADOW, restored_power);
 332 }
 333
 334 /*
 335  * Update the PCI devices with a valid IRQ number
 336  * that is set in the mainboard PCI_IRQ structures.
 337  */
 338 static void set_pci_irqs(void *unused)
 339 {
 340         /* Write PCI_INTR regs 0xC00/0xC01 */
 341         write_pci_int_table();
 342
 343         /* Write IRQs for all devicetree enabled devices */
 344         write_pci_cfg_irqs();
 345 }
 346
 347 /*
 348  * Hook this function into the PCI state machine
 349  * on entry into BS_DEV_ENABLE.
 350  */
 351 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL);