| commit | c30981c952ba35f20c280b651f5a61616993af26 | |
| author | Aaron Durbin <adurbin@chromium.org> | |
| Fri, 14 Aug 2020 22:54:44 +0000 (14 16:54 -0600) | ||
| committer | Aaron Durbin <adurbin@chromium.org> | |
| Mon, 17 Aug 2020 17:41:01 +0000 (17 17:41 +0000) | ||
| tree | 35ced87157c43853a2a13984d24ac78a7c148013 | treesnapshot (tar.gz zip) |
| parent | d24e5f15f2c28ba2519603a09cbe5a80a0ebbc48 | commitdiff |
soc/amd/picasso: snapshot chipset state early in boot sequence
Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
| src/soc/amd/picasso/romstage.c | diffblobblamehistory | |
| src/soc/amd/picasso/southbridge.c | diffblobblamehistory |