util/inteltool/inteltool.h

   1 /*
   2  * inteltool - dump all registers on an Intel CPU + chipset based system.
   3  *
   4  * Copyright (C) 2008-2010 by coresystems GmbH
   5  * Copyright (C) 2009 Carl-Daniel Hailfinger
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <commonlib/helpers.h>
  18
  19 #include <stdint.h>
  20
  21 #if defined(__GLIBC__)
  22 #include <sys/io.h>
  23 #endif
  24 #if (defined(__MACH__) && defined(__APPLE__))
  25 /* DirectHW is available here: https://www.coreboot.org/DirectHW */
  26 #define __DARWIN__
  27 #include <DirectHW/DirectHW.h>
  28 #endif
  29 #ifdef __NetBSD__
  30 #include <pciutils/pci.h>
  31 #else
  32 #include <pci/pci.h>
  33 #endif
  34
  35 /* This #include is needed for freebsd_{rd,wr}msr. */
  36 #if defined(__FreeBSD__)
  37 #include <machine/cpufunc.h>
  38 #endif
  39
  40 #ifdef __NetBSD__
  41 static inline uint8_t inb(unsigned port)
  42 {
  43         uint8_t data;
  44         __asm volatile("inb %w1,%0" : "=a" (data) : "d" (port));
  45         return data;
  46 }
  47 static inline uint16_t inw(unsigned port)
  48 {
  49         uint16_t data;
  50         __asm volatile("inw %w1,%0": "=a" (data) : "d" (port));
  51         return data;
  52 }
  53 static inline uint32_t inl(unsigned port)
  54 {
  55         uint32_t data;
  56         __asm volatile("inl %w1,%0": "=a" (data) : "d" (port));
  57         return data;
  58 }
  59 #endif
  60
  61 #define INTELTOOL_VERSION "1.0"
  62
  63 /* Tested chipsets: */
  64 #define PCI_VENDOR_ID_INTEL                     0x8086
  65 #define PCI_DEVICE_ID_INTEL_ICH                 0x2410
  66 #define PCI_DEVICE_ID_INTEL_ICH0                0x2420
  67 #define PCI_DEVICE_ID_INTEL_ICH2                0x2440
  68 #define PCI_DEVICE_ID_INTEL_ICH4                0x24c0
  69 #define PCI_DEVICE_ID_INTEL_ICH4M               0x24cc
  70 #define PCI_DEVICE_ID_INTEL_ICH5                0x24d0
  71 #define PCI_DEVICE_ID_INTEL_ICH6                0x2640
  72 #define PCI_DEVICE_ID_INTEL_ICH7DH              0x27b0
  73 #define PCI_DEVICE_ID_INTEL_ICH7                0x27b8
  74 #define PCI_DEVICE_ID_INTEL_ICH7M               0x27b9
  75 #define PCI_DEVICE_ID_INTEL_ICH7MDH             0x27bd
  76 #define PCI_DEVICE_ID_INTEL_NM10                0x27bc
  77 #define PCI_DEVICE_ID_INTEL_ICH8                0x2810
  78 #define PCI_DEVICE_ID_INTEL_ICH8M               0x2815
  79 #define PCI_DEVICE_ID_INTEL_ICH8ME              0x2811
  80 #define PCI_DEVICE_ID_INTEL_ICH9DH              0x2912
  81 #define PCI_DEVICE_ID_INTEL_ICH9DO              0x2914
  82 #define PCI_DEVICE_ID_INTEL_ICH9R               0x2916
  83 #define PCI_DEVICE_ID_INTEL_ICH9                0x2918
  84 #define PCI_DEVICE_ID_INTEL_ICH9M               0x2919
  85 #define PCI_DEVICE_ID_INTEL_ICH9ME              0x2917
  86 #define PCI_DEVICE_ID_INTEL_ICH10R              0x3a16
  87 #define PCI_DEVICE_ID_INTEL_ICH10               0x3a18
  88 #define PCI_DEVICE_ID_INTEL_3400_DESKTOP        0x3b00
  89 #define PCI_DEVICE_ID_INTEL_3400_MOBILE         0x3b01
  90 #define PCI_DEVICE_ID_INTEL_P55                 0x3b02
  91 #define PCI_DEVICE_ID_INTEL_PM55                0x3b03
  92 #define PCI_DEVICE_ID_INTEL_H55                 0x3b06
  93 #define PCI_DEVICE_ID_INTEL_QM57                0x3b07
  94 #define PCI_DEVICE_ID_INTEL_H57                 0x3b08
  95 #define PCI_DEVICE_ID_INTEL_HM55                0x3b09
  96 #define PCI_DEVICE_ID_INTEL_Q57                 0x3b0a
  97 #define PCI_DEVICE_ID_INTEL_HM57                0x3b0b
  98 #define PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF     0x3b0d
  99 #define PCI_DEVICE_ID_INTEL_B55_A               0x3b0e
 100 #define PCI_DEVICE_ID_INTEL_QS57                0x3b0f
 101 #define PCI_DEVICE_ID_INTEL_3400                0x3b12
 102 #define PCI_DEVICE_ID_INTEL_3420                0x3b14
 103 #define PCI_DEVICE_ID_INTEL_3450                0x3b16
 104 #define PCI_DEVICE_ID_INTEL_B55_B               0x3b1e
 105 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC     0x8119
 106 #define PCI_DEVICE_ID_INTEL_Z68                 0x1c44
 107 #define PCI_DEVICE_ID_INTEL_P67                 0x1c46
 108 #define PCI_DEVICE_ID_INTEL_UM67                0x1c47
 109 #define PCI_DEVICE_ID_INTEL_HM65                0x1c49
 110 #define PCI_DEVICE_ID_INTEL_H67                 0x1c4a
 111 #define PCI_DEVICE_ID_INTEL_HM67                0x1c4b
 112 #define PCI_DEVICE_ID_INTEL_Q65                 0x1c4c
 113 #define PCI_DEVICE_ID_INTEL_QS67                0x1c4d
 114 #define PCI_DEVICE_ID_INTEL_Q67                 0x1c4e
 115 #define PCI_DEVICE_ID_INTEL_QM67                0x1c4f
 116 #define PCI_DEVICE_ID_INTEL_B65                 0x1c50
 117 #define PCI_DEVICE_ID_INTEL_C202                0x1c52
 118 #define PCI_DEVICE_ID_INTEL_C204                0x1c54
 119 #define PCI_DEVICE_ID_INTEL_C206                0x1c56
 120 #define PCI_DEVICE_ID_INTEL_H61                 0x1c5c
 121 #define PCI_DEVICE_ID_INTEL_Z77                 0x1e44
 122 #define PCI_DEVICE_ID_INTEL_Z75                 0x1e46
 123 #define PCI_DEVICE_ID_INTEL_Q77                 0x1e47
 124 #define PCI_DEVICE_ID_INTEL_Q75                 0x1e48
 125 #define PCI_DEVICE_ID_INTEL_B75                 0x1e49
 126 #define PCI_DEVICE_ID_INTEL_H77                 0x1e4a
 127 #define PCI_DEVICE_ID_INTEL_C216                0x1e53
 128 #define PCI_DEVICE_ID_INTEL_QM77                0x1e55
 129 #define PCI_DEVICE_ID_INTEL_QS77                0x1e56
 130 #define PCI_DEVICE_ID_INTEL_HM77                0x1e57
 131 #define PCI_DEVICE_ID_INTEL_UM77                0x1e58
 132 #define PCI_DEVICE_ID_INTEL_HM76                0x1e59
 133 #define PCI_DEVICE_ID_INTEL_HM75                0x1e5d
 134 #define PCI_DEVICE_ID_INTEL_HM70                0x1e5e
 135 #define PCI_DEVICE_ID_INTEL_NM70                0x1e5f
 136 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL   0x9c41
 137 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM   0x9c43
 138 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE   0x9c45
 139 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM        0x9cc3
 140 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP     0x9cc5
 141 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA   0xa102
 142 #define PCI_DEVICE_ID_INTEL_CM236               0xa150
 143 #define PCI_DEVICE_ID_INTEL_82810               0x7120
 144 #define PCI_DEVICE_ID_INTEL_82810_DC    0x7122
 145 #define PCI_DEVICE_ID_INTEL_82810E_DC   0x7124
 146 #define PCI_DEVICE_ID_INTEL_82830M              0x3575
 147 #define PCI_DEVICE_ID_INTEL_82845               0x1a30
 148 #define PCI_DEVICE_ID_INTEL_82865               0x2570
 149 #define PCI_DEVICE_ID_INTEL_82915               0x2580
 150 #define PCI_DEVICE_ID_INTEL_82945P              0x2770
 151 #define PCI_DEVICE_ID_INTEL_82945GM             0x27a0
 152 #define PCI_DEVICE_ID_INTEL_82945GSE    0x27ac
 153 #define PCI_DEVICE_ID_INTEL_82946               0x2970
 154 #define PCI_DEVICE_ID_INTEL_82965PM             0x2a00
 155 #define PCI_DEVICE_ID_INTEL_82Q965              0x2990
 156 #define PCI_DEVICE_ID_INTEL_82975X              0x277c
 157 #define PCI_DEVICE_ID_INTEL_82Q35               0x29b0
 158 #define PCI_DEVICE_ID_INTEL_82G33               0x29c0
 159 #define PCI_DEVICE_ID_INTEL_82Q33               0x29d0
 160 #define PCI_DEVICE_ID_INTEL_82X38               0x29e0
 161 #define PCI_DEVICE_ID_INTEL_32X0                0x29f0
 162 #define PCI_DEVICE_ID_INTEL_82XX4X              0x2a40
 163 #define PCI_DEVICE_ID_INTEL_82Q45               0x2e10
 164 #define PCI_DEVICE_ID_INTEL_82G45               0x2e20
 165 #define PCI_DEVICE_ID_INTEL_82G41               0x2e30
 166 #define PCI_DEVICE_ID_INTEL_82B43               0x2e40
 167 #define PCI_DEVICE_ID_INTEL_82B43_2             0x2e90
 168
 169 #define PCI_DEVICE_ID_INTEL_82X58               0x3405
 170 #define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
 171 #define PCI_DEVICE_ID_INTEL_ATOM_DXXX   0xa000
 172 #define PCI_DEVICE_ID_INTEL_I63XX               0x2670
 173
 174 #define PCI_DEVICE_ID_INTEL_I5000X              0x25c0
 175 #define PCI_DEVICE_ID_INTEL_I5000Z              0x25d0
 176 #define PCI_DEVICE_ID_INTEL_I5000V              0x25d4
 177 #define PCI_DEVICE_ID_INTEL_I5000P              0x25d8
 178
 179 /* untested, but almost identical to D-series */
 180 #define PCI_DEVICE_ID_INTEL_ATOM_NXXX   0xa010
 181
 182 #define PCI_DEVICE_ID_INTEL_82443LX             0x7180
 183 /* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
 184 #define PCI_DEVICE_ID_INTEL_82443BX             0x7190
 185 #define PCI_DEVICE_ID_INTEL_82443BX_NO_AGP      0x7192
 186
 187 /* 82371AB/EB/MB use the same device ID value. */
 188 #define PCI_DEVICE_ID_INTEL_82371XX             0x7110
 189
 190 /* Bay Trail */
 191 #define PCI_DEVICE_ID_INTEL_BAYTRAIL            0x0f00 /* SOC Transaction Router */
 192 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC        0x0f1c
 193 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_GFX        0x0f31
 194 #define CPUID_BAYTRAIL                                          0x30670
 195
 196 /* Intel starts counting these generations with the integration of the DRAM controller */
 197 #define PCI_DEVICE_ID_INTEL_CORE_0TH_GEN        0xd132 /* Nehalem */
 198 #define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN        0x0044 /* Westmere */
 199 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D      0x0100 /* Sandy Bridge (Desktop) */
 200 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M      0x0104 /* Sandy Bridge (Mobile) */
 201 #define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_E3     0x0108 /* Sandy Bridge (Xeon E3) */
 202 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_D      0x0150 /* Ivy Bridge (Desktop) */
 203 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_M      0x0154 /* Ivy Bridge (Mobile) */
 204 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_E3     0x0158 /* Ivy Bridge (Xeon E3 v2) */
 205 #define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c   0x015c /* Ivy Bridge (?) */
 206 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_D      0x0c00 /* Haswell (Desktop) */
 207 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_M      0x0c04 /* Haswell (Mobile) */
 208 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3     0x0c08 /* Haswell (Xeon E3 v3) */
 209 #define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U      0x0a04 /* Haswell-ULT */
 210 #define PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U      0x1604 /* Broadwell-ULT */
 211 #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST    0x1918
 212
 213 #if !defined(__DARWIN__) && !defined(__FreeBSD__)
 214 typedef struct { uint32_t hi, lo; } msr_t;
 215 #endif
 216 #if defined (__FreeBSD__)
 217 /* FreeBSD already has conflicting definitions for wrmsr/rdmsr. */
 218 #undef rdmsr
 219 #undef wrmsr
 220 #define rdmsr freebsd_rdmsr
 221 #define wrmsr freebsd_wrmsr
 222 typedef struct { uint32_t hi, lo; } msr_t;
 223 msr_t freebsd_rdmsr(int addr);
 224 int freebsd_wrmsr(int addr, msr_t msr);
 225 #endif
 226 typedef struct { uint16_t addr; int size; char *name; } io_register_t;
 227
 228 void *map_physical(uint64_t phys_addr, size_t len);
 229 void unmap_physical(void *virt_addr, size_t len);
 230
 231 unsigned int cpuid(unsigned int op);
 232 int print_intel_core_msrs(void);
 233 int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_spd_file);
 234 int print_pmbase(struct pci_dev *sb, struct pci_access *pacc);
 235 int print_rcba(struct pci_dev *sb);
 236 int print_gpios(struct pci_dev *sb, int show_all, int show_diffs);
 237 int print_epbar(struct pci_dev *nb);
 238 int print_dmibar(struct pci_dev *nb);
 239 int print_pciexbar(struct pci_dev *nb);
 240 int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
 241 int print_spi(struct pci_dev *sb);
 242 int print_gfx(struct pci_dev *gfx);
 243 int print_ahci(struct pci_dev *ahci);
 244 void ivybridge_dump_timings(const char *dump_spd_file);