4 <title>Development
</title>
8 <h1>Intel
® x86 coreboot/FSP Development Process
</h1>
10 The x86 development process for coreboot is broken into the following components:
13 <li>coreboot
<a target=
"_blank" href=
"SoC/soc.html">SoC
</a> development
</li>
14 <li>coreboot
<a target=
"_blank" href=
"Board/board.html">mainboard
</a> development
</li>
15 <li><a target=
"_blank" href=
"fsp1_1.html">FSP
1.1</a> integration
</li>
18 The development process has two main phases:
21 <li>Minimal coreboot; This phase is single threaded
</li>
22 <li>Adding coreboot features
</li>
25 <h2>Minimal coreboot
</h2>
27 The combined steps below describe how to bring up a minimal coreboot for a
28 system-on-a-chip (SoC) and a development board:
31 <tr bgcolor=
"#ffffc0">
32 <td>The initial coreboot steps are single threaded!
33 The initial minimal FSP development is also single threaded.
34 Progress can speed up by adding more developers after the minimal coreboot/FSP
35 implementation reaches the payload.
40 <li>Get the necessary tools:
42 <li>Linux: Use your package manager to install m4 bison flex and the libcurses development
45 <li>Ubuntu or other Linux distribution that use apt, run:
46 <pre><code>sudo apt-get install m4 bison flex libncurses5-dev
53 <li>Build the cross tools for i386:
56 <pre><code>make crossgcc-i386
</code></pre>
57 To use multiple processors for the toolchain build (which takes a long time), use:
58 <pre><code>make crossgcc-i386 CPUS=N
</code></pre>
59 where N is the number of cores to use for the build.
63 <li>Get something to build:
65 <li><a target=
"_blank" href=
"fsp1_1.html#RequiredFiles">FSP
1.1</a> required files
</li>
66 <li><a target=
"_blank" href=
"SoC/soc.html#RequiredFiles">SoC
</a> required files
</li>
67 <li><a target=
"_blank" href=
"Board/board.html#RequiredFiles">Board
</a> required files
</li>
70 <li>Get result to start
<a target=
"_blank" href=
"SoC/soc.html#Descriptor">booting
</a></li>
71 <li><a target=
"_blank" href=
"SoC/soc.html#EarlyDebug">Early Debug
</a></li>
72 <li>Implement and debug the
<a target=
"_blank" href=
"SoC/soc.html#Bootblock">bootblock
</a> code
</li>
73 <li>Implement and debug the call to
<a target=
"_blank" href=
"SoC/soc.html#TempRamInit">TempRamInit
</a></li>
74 <li>Enable the serial port
76 <li>Power on, enable and configure GPIOs for the
77 <a target=
"_blank" href=
"Board/board.html#SerialOutput">debug serial UART
</a>
79 <li>Add the
<a target=
"_blank" href=
"SoC/soc.html#SerialOutput">serial outupt
</a>
84 <li>Enable
<a target=
"_blank" href=
"fsp1_1.html#corebootFspDebugging">coreboot/FSP
</a> debugging
</li>
85 <li>Determine the
<a target=
"_blank" href=
"SoC/soc.html#PreviousSleepState">Previous Sleep State
</a></li>
89 <a target=
"_blank" href=
"SoC/soc.html#MemoryInit">MemoryInit
</a>
92 <li>Implement the board support to read the
93 <a target=
"_blank" href=
"Board/board.html#SpdData">Memory Timing Data
</a>
98 <a target=
"_blank" href=
"SoC/soc.html#DisableShadowRom">Shadow ROM
</a>
100 <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration
</li>
102 Implement the .init routine for the
103 <a target=
"_blank" href=
"SoC/soc.html#ChipOperations">chip operations
</a>
104 structure which calls FSP SiliconInit
108 <a target=
"_blank" href=
"SoC/soc.html#DeviceTree">device tree processing
</a>
109 to display the PCI vendor and device IDs
113 <a target=
"_blank" href=
"Board/board.html#DisablePciDevices">PCI devices
</a>
117 <a target=
"_blank" href=
"SoC/soc.html#MemoryMap">memory map
</a>
119 <li>coreboot should now attempt to load the payload
</li>
124 <h2>Add coreboot Features
</h2>
126 Most of the coreboot development gets done in this phase. Implementation tasks in this
127 phase are easily done in parallel.
130 <li>Payload and OS Features:
132 <li><a target=
"_blank" href=
"SoC/soc.html#AcpiTables">ACPI Tables
</a></li>
133 <li><a target=
"_blank" href=
"SoC/soc.html#LegacyHardware">Legacy hardware
</a> support
</li>
142 <tr bgcolor=
"#c0ffc0">
143 <th colspan=
3><h1>Features
</h1></th>
145 <tr bgcolor=
"#c0ffc0">
151 <td>8254 Programmable Interval Timer
</td>
152 <td><a target=
"_blank" href=
"SoC/soc.html#LegacyHardware">Legacy hardware
</a> support
</td>
153 <td><a target=
"_blank" href=
"SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg
</a> gets to shell prompt
</td>
156 <td>8259 Programmable Interrupt Controller
</td>
157 <td><a target=
"_blank" href=
"SoC/soc.html#LegacyHardware">Legacy hardware
</a> support
</td>
158 <td><a target=
"_blank" href=
"SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg
</a> gets to shell prompt
</td>
161 <td>Cache-as-RAM
</td>
163 <a target=
"_blank" href=
"SoC/soc.html#TempRamInit">Find
</a>
165 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc
</a><br>
166 Enable: FSP
1.1 <a target=
"_blank" href=
"SoC/soc.html#TempRamInit">TempRamInit
</a>
168 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc
</a><br>
169 Disable: FSP
1.1 TempRamExit called from
170 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S
</a><br>
172 <td>FindFSP: POST code
0x90
173 (
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT
</a>)
176 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
178 Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
184 Implement a device driver for the
185 <a target=
"_blank" href=
"SoC/soc.html#MemoryMap">north cluster
</a>
187 <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state
</td>
192 Set values: src/drivers/intel/fsp1_1/stack.c/
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs
</a><br>
193 Load values: src/drivers/intel/fsp1_1/
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S
</a>
195 <td>Set: Post code
0x91
196 (
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT
</a>)
198 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S
</a><br>
199 Load: Post code
0x3C is displayed by
200 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S
</a><br>
201 and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions
</td>
204 <td>PCI Device Support
</td>
205 <td>Implement a PCI
<a target=
"_blank" href=
"SoC/soc.html#DeviceDrivers">device driver
</a></td>
206 <td>The device is detected by coreboot and usable by the payload
</td>
209 <td>Ramstage state machine
</td>
211 Implement the chip and domain operations to start the
212 <a target=
"_blank" href=
"SoC/soc.html#DeviceTree">device tree
</a>
216 During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
217 for the PCI devices on the bus.
221 <td>ROM Shadow
<br>0x000E0000 -
0x000FFFFF</td>
223 Disable: src/soc/
<Vendor
>/
<Chip Family
>/romstage/romstage.c/
<a target=
"_blank" href=
"SoC/soc.html#DisableShadowRom">soc_after_ram_init routine
</a>
225 <td>Operates as RAM: Writes followed by a read to the
0x000E0000 -
0x000FFFFF region returns the value written
</td>
229 <tr bgcolor=
"#c0ffc0">
237 <a target=
"_blank" href=
"SoC/soc.html#DeviceTree">List
</a> PCI vendor and device IDs by starting
238 the device tree processing
<br>
239 <a target=
"_blank" href=
"Board/board.html#DisablePciDevices">Disable
</a> PCI devices
<br>
240 Enable: Implement a PCI
<a target=
"_blank" href=
"SoC/soc.html#DeviceDrivers">device driver
</a>
242 List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs
<br>
243 Disable: BS_DEV_ENUMERATE state shows the devices as disabled
<br>
244 Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
250 Load SPD data: src/soc/mainboard/
<Vendor
>/
<Board
>/spd/
<a target=
"_blank" href=
"Board/board.html#SpdData">spd.c
</a><br>
253 <li>src/soc
<Vendor
>//
<Chip Family
>/romstage/
<a target=
"_blank" href=
"SoC/soc.html#MemoryInit">romstage.c
</a></li>
254 <li>src/mainboard/
<Vendor
>/
<Board
>/
<a target=
"_blank" href=
"Board/board.html#SpdData">romstage.c
</a></li>
256 FSP
1.1 MemoryInit called from src/drivers/intel/fsp1_1/
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c
</a>
258 <td>Select the following Kconfig values
260 <li>DISPLAY_HOBS
</li>
261 <li>DISPLAY_UPD_DATA
</li>
263 Testing successful if:
265 <li>MemoryInit UPD values are correct
</li>
266 <li>MemoryInit returns
0 (success) and
</li>
267 <li>The the message
"ERROR - coreboot's requirements not met by FSP binary!"
276 SoC
<a target=
"_blank" href=
"SoC/soc.html#SerialOutput">Support
</a><br>
277 Enable: src/soc/mainboard/
<Board
>/com_init.c/
<a target=
"_blank" href=
"Board/board.html#SerialOutput">car_mainboard_pre_console_init
</a>
279 <td>Debug serial output works
</td>
283 <tr bgcolor=
"#c0ffc0">
291 SoC
<a target=
"_blank" href=
"SoC/soc.html#AcpiTables">Support
</a><br>
293 <td>Verified by payload or OS
</td>
297 <tr bgcolor=
"#c0ffc0">
304 <td>FSP
<a target=
"_blank" href=
"SoC/soc.html#TempRamInit">TempRamInit
</a></td>
305 <td>FSP binary found: POST code
0x90
306 (
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT
</a>)
308 TempRamInit successful: POST code
309 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
315 <td><a target=
"_blank" href=
"SoC/soc.html#MemoryInit">SoC
</a> support
<br>
316 <a target=
"_blank" href=
"Board/board.html#SpdData">Board
</a> support
<br>
318 <td>Select the following Kconfig values
320 <li>DISPLAY_HOBS
</li>
321 <li>DISPLAY_UPD_DATA
</li>
323 Testing successful if:
325 <li>MemoryInit UPD values are correct
</li>
326 <li>MemoryInit returns
0 (success) and
</li>
327 <li>The the message
"ERROR - coreboot's requirements not met by FSP binary!"
335 <td>src/drivers/intel/fsp1_1/
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S
</a></td>
337 (
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT
</a>)
338 is displayed before calling TempRamExit by
339 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S
</a>,
340 CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
341 Post code
0x39 is displayed by
342 <a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S
</a><br>
348 Implement the .init routine for the
349 <a target=
"_blank" href=
"SoC/soc.html#ChipOperations">chip operations
</a> structure
351 <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns
0x00000000</td>
356 The code which calls FspNotify is located in
357 src/drivers/intel/fsp1_1/
<a target=
"_blank" href=
"https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c
</a>.
358 The fsp_notify_boot_state_callback routine is called three times as specified
359 by the BOOT_STATE_INIT_ENTRY macros below the routine.
362 The FspNotify routines are called during:
364 <li>BS_DEV_RESOURCES - on exit
</li>
365 <li>BS_PAYLOAD_LOAD - on exit
</li>
366 <li>BS_OS_RESUME - on entry (S3 resume)
</li>
375 <p>Modified:
4 March
2016</p>