src/superio/ite/common/early_serial.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2013 Damien Zammit <damien@zamaudio.com>
   5  * Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <arch/io.h>
  19 #include <device/pnp.h>
  20 #include <stdint.h>
  21 #include "ite.h"
  22
  23 /* Global configuration registers. */
  24 #define ITE_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
  25 #define ITE_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
  26 #define ITE_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
  27 #define ITE_CONFIG_REG_SWSUSP    0x24 /* Software Suspend, Flash I/F. */
  28 #define ITE_CONFIG_REG_MFC       0x2a /* multi function pin */
  29 #define ITE_CONFIG_REG_WATCHDOG  0x72 /* watchdog config */
  30
  31 /* Helper procedure */
  32 static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
  33 {
  34         pnp_set_logical_device(dev);
  35         pnp_write_config(dev, reg, value);
  36 }
  37
  38 /* Enable configuration */
  39 static void pnp_enter_conf_state(pnp_devfn_t dev)
  40 {
  41         u16 port = dev >> 8;
  42
  43         outb(0x87, port);
  44         outb(0x01, port);
  45         outb(0x55, port);
  46         outb((port == 0x4e) ? 0xaa : 0x55, port);
  47 }
  48
  49 /* Disable configuration */
  50 static void pnp_exit_conf_state(pnp_devfn_t dev)
  51 {
  52         ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
  53 }
  54
  55 void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value)
  56 {
  57         pnp_enter_conf_state(dev);
  58         ite_sio_write(dev, reg, value);
  59         pnp_exit_conf_state(dev);
  60 }
  61
  62
  63 /*
  64  * in romstage.c
  65  * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO)
  66  * and pass: CLKIN_DEV
  67  * ITE_UART_CLK_PREDIVIDE_24
  68  * ITE_UART_CLK_PREDIVIDE_48 (default)
  69  */
  70 void ite_conf_clkin(pnp_devfn_t dev, u8 predivide)
  71 {
  72         ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
  73 }
  74
  75 /* Bring up early serial debugging output before the RAM is initialized. */
  76 void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
  77 {
  78         pnp_enter_conf_state(dev);
  79         pnp_set_logical_device(dev);
  80         pnp_set_enable(dev, 0);
  81         pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
  82         pnp_set_enable(dev, 1);
  83         pnp_exit_conf_state(dev);
  84 }
  85
  86 /*
  87  *
  88  * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off
  89  * this was documented only in IT8712F_V0.9.2!
  90  *
  91  * Enable 3VSBSW#. (For System Suspend-to-RAM)
  92  * 0: 3VSBSW# will be always inactive.
  93  * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
  94  *
  95  * in romstage.c
  96  * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
  97  * and pass: GPIO_DEV
  98  */
  99
 100 void ite_enable_3vsbsw(pnp_devfn_t dev)
 101 {
 102         u8 tmp;
 103         pnp_enter_conf_state(dev);
 104         pnp_set_logical_device(dev);
 105         tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
 106         tmp |= 0x80;
 107         pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
 108         pnp_exit_conf_state(dev);
 109 }
 110
 111 /*
 112  * in romstage.c
 113  * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
 114  * and pass: GPIO_DEV
 115 */
 116
 117 void ite_kill_watchdog(pnp_devfn_t dev)
 118 {
 119         pnp_enter_conf_state(dev);
 120         ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00);
 121         pnp_exit_conf_state(dev);
 122 }