src/superio/ite/common/early_serial.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <arch/io.h>
   4 #include <device/pnp_ops.h>
   5 #include <device/pnp.h>
   6 #include <stdint.h>
   7 #include "ite.h"
   8
   9 /* Global configuration registers. */
  10 #define ITE_CONFIG_REG_CC               0x02 /* Configure Control (write-only). */
  11 #define ITE_CONFIG_REG_LDN              0x07 /* Logical Device Number. */
  12 #define ITE_CONFIG_REG_CLOCKSEL         0x23 /* Clock Selection. */
  13 #define ITE_CONFIG_REG_SWSUSP           0x24 /* Software Suspend, Flash I/F. */
  14 #define ITE_CONFIG_REG_MFC              0x2a /* multi function pin */
  15 #define ITE_CONFIG_REG_WATCHDOG         0x72 /* watchdog config */
  16 #define ITE_CONFIG_REG_WDT_TIMEOUT_LSB  0x73 /* watchdog timeout (LSB) */
  17 #define ITE_CONFIG_REG_WDT_TIMEOUT_MSB  0x74 /* watchdog timeout (MSB) */
  18 #define ITE_CONFIG_REG_APC_PME_CTL1     0xf2 /* APC_PME Control 1 */
  19 #define ITE_CONFIG_REG_APC_PME_CTL2     0xf4 /* APC_PME Control 2 */
  20
  21 /* Helper procedure */
  22 static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value)
  23 {
  24         pnp_set_logical_device(dev);
  25         pnp_write_config(dev, reg, value);
  26 }
  27
  28 /* Enable configuration */
  29 void pnp_enter_conf_state(pnp_devfn_t dev)
  30 {
  31         u16 port = dev >> 8;
  32
  33         outb(0x87, port);
  34         outb(0x01, port);
  35         outb(0x55, port);
  36         outb((port == 0x4e) ? 0xaa : 0x55, port);
  37 }
  38
  39 /* Disable configuration */
  40 void pnp_exit_conf_state(pnp_devfn_t dev)
  41 {
  42         ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02);
  43 }
  44
  45 void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value)
  46 {
  47         pnp_enter_conf_state(dev);
  48         ite_sio_write(dev, reg, value);
  49         pnp_exit_conf_state(dev);
  50 }
  51
  52 /*
  53  * in romstage.c
  54  * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO)
  55  * and pass: CLKIN_DEV
  56  * ITE_UART_CLK_PREDIVIDE_24
  57  * ITE_UART_CLK_PREDIVIDE_48 (default)
  58  */
  59 void ite_conf_clkin(pnp_devfn_t dev, u8 predivide)
  60 {
  61         ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide));
  62 }
  63
  64 /* Bring up early serial debugging output before the RAM is initialized. */
  65 void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
  66 {
  67         pnp_enter_conf_state(dev);
  68         pnp_set_logical_device(dev);
  69         pnp_set_enable(dev, 0);
  70         pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
  71         pnp_set_enable(dev, 1);
  72         pnp_exit_conf_state(dev);
  73 }
  74
  75 /*
  76  *
  77  * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off
  78  * this was documented only in IT8712F_V0.9.2!
  79  * Also documented in IT8728F_V0.4.2 and IT8772E_V0.4
  80  *
  81  * Enable 3VSBSW#. (For System Suspend-to-RAM)
  82  * 0: 3VSBSW# will be always inactive.
  83  * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
  84  *
  85  * in romstage.c
  86  * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
  87  * and pass: GPIO_DEV
  88  */
  89
  90 void ite_set_3vsbsw(pnp_devfn_t dev, bool enable)
  91 {
  92         u8 tmp;
  93         pnp_enter_conf_state(dev);
  94         pnp_set_logical_device(dev);
  95         tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
  96         if (enable)
  97                 tmp |= 0x80;
  98         else
  99                 tmp &= ~0x80;
 100         pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
 101         pnp_exit_conf_state(dev);
 102 }
 103
 104 /*
 105  *
 106  * LDN 7, reg 0x2a, bit 0 - delay PWRGD3 rising edge after 3VSBSW# rising edge
 107  * This can be needed for S3 resume.
 108  * Documented in IT8728F V0.4.2 but also applies to IT8720F where it is marked
 109  * as reserved.
 110  *
 111  * Delay PWRGD3 assertion after setting 3VSBSW#.
 112  * 0: There will be no extra delay before PWRGD3 is set.
 113  * 1: The delay after 3VSBSW# rising edge before PWRGD3 is set is increased.
 114  *
 115  * in romstage.c
 116  * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
 117  * and pass: GPIO_DEV
 118  */
 119
 120 void ite_delay_pwrgd3(pnp_devfn_t dev)
 121 {
 122         u8 tmp;
 123         pnp_enter_conf_state(dev);
 124         pnp_set_logical_device(dev);
 125         tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
 126         tmp |= 0x01;
 127         pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
 128         pnp_exit_conf_state(dev);
 129 }
 130
 131 /*
 132  * in romstage.c
 133  * #define GPIO_DEV PNP_DEV(0x2e, ITE_GPIO)
 134  * and pass: GPIO_DEV
 135 */
 136
 137 void ite_kill_watchdog(pnp_devfn_t dev)
 138 {
 139         pnp_enter_conf_state(dev);
 140         ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00);
 141         ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_LSB, 0x00);
 142         ite_sio_write(dev, ITE_CONFIG_REG_WDT_TIMEOUT_MSB, 0x00);
 143         pnp_exit_conf_state(dev);
 144 }
 145
 146 /*
 147  * Disable PME# Output
 148  * pass EC_DEV
 149  */
 150 void ite_disable_pme_out(pnp_devfn_t dev)
 151 {
 152         u8 tmp;
 153         pnp_enter_conf_state(dev);
 154         pnp_set_logical_device(dev);
 155         tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL1);
 156         tmp |= 0x40;
 157         pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL1, tmp);
 158         pnp_exit_conf_state(dev);
 159 }
 160
 161 /*
 162  * Set AC resume to be up to the Southbridge
 163  * pass EC_DEV
 164  */
 165 void ite_ac_resume_southbridge(pnp_devfn_t dev)
 166 {
 167         u8 tmp;
 168         pnp_enter_conf_state(dev);
 169         pnp_set_logical_device(dev);
 170         tmp = pnp_read_config(dev, ITE_CONFIG_REG_APC_PME_CTL2);
 171         /*
 172          * Set both
 173          * 6: Gate Extra PWRON# Pulse
 174          * 5: PSON# state when 3VSB switched to on
 175          */
 176         tmp |= 0x60;
 177         pnp_write_config(dev, ITE_CONFIG_REG_APC_PME_CTL2, tmp);
 178         pnp_exit_conf_state(dev);
 179 }