src/southbridge/intel/i82801gx/i82801gx.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
  17 #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
  18 /*
  19  * It does not matter where we put the SMBus I/O base, as long as we
  20  * keep it consistent and don't interfere with other devices.  Stage2
  21  * will relocate this anyways.
  22  * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
  23  * again. But handling static BARs is a generic problem that should be
  24  * solved in the device allocator.
  25  */
  26 #define SMBUS_IO_BASE           0x0400
  27 /* TODO Make sure these don't get changed by stage2 */
  28 #define DEFAULT_GPIOBASE        0x0480
  29 #define DEFAULT_PMBASE          0x0500
  30
  31 #ifndef __ACPI__
  32 #define DEFAULT_RCBA            ((u8 *)0xfed1c000)
  33 #else
  34 #define DEFAULT_RCBA            0xfed1c000
  35 #endif
  36
  37 #ifndef __ACPI__
  38 #define DEBUG_PERIODIC_SMIS 0
  39
  40 #if !defined(__ASSEMBLER__)
  41 #if !defined(__PRE_RAM__)
  42 #include "chip.h"
  43 extern void i82801gx_enable(device_t dev);
  44 void gpi_route_interrupt(u8 gpi, u8 mode);
  45 #else
  46 void enable_smbus(void);
  47 int smbus_read_byte(unsigned device, unsigned address);
  48 int southbridge_detect_s3_resume(void);
  49 #endif
  50 #endif
  51
  52 #define MAINBOARD_POWER_OFF     0
  53 #define MAINBOARD_POWER_ON      1
  54 #define MAINBOARD_POWER_KEEP    2
  55
  56 #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
  57 #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
  58 #endif
  59
  60 /* PCI Configuration Space (D30:F0): PCI2PCI */
  61 #define PSTS    0x06
  62 #define SMLT    0x1b
  63 #define SECSTS  0x1e
  64 #define INTR    0x3c
  65 #define BCTRL   0x3e
  66 #define   SBR   (1 << 6)
  67 #define   SEE   (1 << 1)
  68 #define   PERE  (1 << 0)
  69
  70 /* PCI Configuration Space (D31:F0): LPC */
  71
  72 #define SERIRQ_CNTL             0x64
  73
  74 #define GEN_PMCON_1             0xa0
  75 #define GEN_PMCON_2             0xa2
  76 #define GEN_PMCON_3             0xa4
  77
  78 #define GPIO_ROUT               0xb8
  79 #define   GPI_DISABLE           0x00
  80 #define   GPI_IS_SMI            0x01
  81 #define   GPI_IS_SCI            0x02
  82 #define   GPI_IS_NMI            0x03
  83
  84 /* GEN_PMCON_3 bits */
  85 #define RTC_BATTERY_DEAD        (1 << 2)
  86 #define RTC_POWER_FAILED        (1 << 1)
  87 #define SLEEP_AFTER_POWER_FAIL  (1 << 0)
  88
  89 #define PMBASE                  0x40
  90 #define ACPI_CNTL               0x44
  91 #define   ACPI_EN               (1 << 7)
  92 #define BIOS_CNTL               0xDC
  93 #define GPIO_BASE               0x48 /* LPC GPIO Base Address Register */
  94 #define GPIO_CNTL               0x4C /* LPC GPIO Control Register */
  95
  96 #define PIRQA_ROUT              0x60
  97 #define PIRQB_ROUT              0x61
  98 #define PIRQC_ROUT              0x62
  99 #define PIRQD_ROUT              0x63
 100 #define PIRQE_ROUT              0x68
 101 #define PIRQF_ROUT              0x69
 102 #define PIRQG_ROUT              0x6A
 103 #define PIRQH_ROUT              0x6B
 104
 105 #define LPC_IO_DEC              0x80 /* IO Decode Ranges Register */
 106 #define LPC_EN                  0x82 /* LPC IF Enables Register */
 107 #define   CNF2_LPC_EN           (1 << 13) /* 0x4e/0x4f */
 108 #define   CNF1_LPC_EN           (1 << 12) /* 0x2e/0x2f */
 109 #define   MC_LPC_EN             (1 << 11) /* 0x62/0x66 */
 110 #define   KBC_LPC_EN            (1 << 10) /* 0x60/0x64 */
 111 #define   GAMEH_LPC_EN          (1 << 9)  /* 0x208/0x20f */
 112 #define   GAMEL_LPC_EN          (1 << 8)  /* 0x200/0x207 */
 113 #define   FDD_LPC_EN            (1 << 3)  /* LPC_IO_DEC[12] */
 114 #define   LPT_LPC_EN            (1 << 2)  /* LPC_IO_DEC[9:8] */
 115 #define   COMB_LPC_EN           (1 << 1)  /* LPC_IO_DEC[6:4] */
 116 #define   COMA_LPC_EN           (1 << 0)  /* LPC_IO_DEC[2:0] */
 117
 118 /* PCI Configuration Space (D31:F1): IDE */
 119 #define INTR_LN                 0x3c
 120 #define IDE_TIM_PRI             0x40    /* IDE timings, primary */
 121 #define   IDE_DECODE_ENABLE     (1 << 15)
 122 #define   IDE_SITRE             (1 << 14)
 123 #define   IDE_ISP_5_CLOCKS      (0 << 12)
 124 #define   IDE_ISP_4_CLOCKS      (1 << 12)
 125 #define   IDE_ISP_3_CLOCKS      (2 << 12)
 126 #define   IDE_RCT_4_CLOCKS      (0 <<  8)
 127 #define   IDE_RCT_3_CLOCKS      (1 <<  8)
 128 #define   IDE_RCT_2_CLOCKS      (2 <<  8)
 129 #define   IDE_RCT_1_CLOCKS      (3 <<  8)
 130 #define   IDE_DTE1              (1 <<  7)
 131 #define   IDE_PPE1              (1 <<  6)
 132 #define   IDE_IE1               (1 <<  5)
 133 #define   IDE_TIME1             (1 <<  4)
 134 #define   IDE_DTE0              (1 <<  3)
 135 #define   IDE_PPE0              (1 <<  2)
 136 #define   IDE_IE0               (1 <<  1)
 137 #define   IDE_TIME0             (1 <<  0)
 138 #define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
 139
 140 #define IDE_SDMA_CNT            0x48    /* Synchronous DMA control */
 141 #define   IDE_SSDE1             (1 <<  3)
 142 #define   IDE_SSDE0             (1 <<  2)
 143 #define   IDE_PSDE1             (1 <<  1)
 144 #define   IDE_PSDE0             (1 <<  0)
 145
 146 #define IDE_SDMA_TIM            0x4a
 147
 148 #define IDE_CONFIG              0x54    /* IDE I/O Configuration Register */
 149 #define   SIG_MODE_SEC_NORMAL   (0 << 18)
 150 #define   SIG_MODE_SEC_TRISTATE (1 << 18)
 151 #define   SIG_MODE_SEC_DRIVELOW (2 << 18)
 152 #define   SIG_MODE_PRI_NORMAL   (0 << 16)
 153 #define   SIG_MODE_PRI_TRISTATE (1 << 16)
 154 #define   SIG_MODE_PRI_DRIVELOW (2 << 16)
 155 #define   FAST_SCB1             (1 << 15)
 156 #define   FAST_SCB0             (1 << 14)
 157 #define   FAST_PCB1             (1 << 13)
 158 #define   FAST_PCB0             (1 << 12)
 159 #define   SCB1                  (1 <<  3)
 160 #define   SCB0                  (1 <<  2)
 161 #define   PCB1                  (1 <<  1)
 162 #define   PCB0                  (1 <<  0)
 163
 164 /* PCI Configuration Space (D31:F3): SMBus */
 165 #define SMB_BASE                0x20
 166 #define HOSTC                   0x40
 167
 168 /* HOSTC bits */
 169 #define I2C_EN                  (1 << 2)
 170 #define SMB_SMI_EN              (1 << 1)
 171 #define HST_EN                  (1 << 0)
 172
 173 /* SMBus I/O bits. */
 174 #define SMBHSTSTAT              0x0
 175 #define SMBHSTCTL               0x2
 176 #define SMBHSTCMD               0x3
 177 #define SMBXMITADD              0x4
 178 #define SMBHSTDAT0              0x5
 179 #define SMBHSTDAT1              0x6
 180 #define SMBBLKDAT               0x7
 181 #define SMBTRNSADD              0x9
 182 #define SMBSLVDATA              0xa
 183 #define SMLINK_PIN_CTL          0xe
 184 #define SMBUS_PIN_CTL           0xf
 185
 186 #define SMBUS_TIMEOUT           (10 * 1000 * 100)
 187
 188
 189 /* Southbridge IO BARs */
 190
 191 #define GPIOBASE                0x48
 192
 193 #define PMBASE          0x40
 194
 195 /* Root Complex Register Block */
 196 #define RCBA            0xf0
 197
 198 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
 199 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
 200 #define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
 201
 202 #define VCH             0x0000  /* 32bit */
 203 #define VCAP1           0x0004  /* 32bit */
 204 #define VCAP2           0x0008  /* 32bit */
 205 #define PVC             0x000c  /* 16bit */
 206 #define PVS             0x000e  /* 16bit */
 207
 208 #define V0CAP           0x0010  /* 32bit */
 209 #define V0CTL           0x0014  /* 32bit */
 210 #define V0STS           0x001a  /* 16bit */
 211
 212 #define V1CAP           0x001c  /* 32bit */
 213 #define V1CTL           0x0020  /* 32bit */
 214 #define V1STS           0x0026  /* 16bit */
 215
 216 #define RCTCL           0x0100  /* 32bit */
 217 #define ESD             0x0104  /* 32bit */
 218 #define ULD             0x0110  /* 32bit */
 219 #define ULBA            0x0118  /* 64bit */
 220
 221 #define RP1D            0x0120  /* 32bit */
 222 #define RP1BA           0x0128  /* 64bit */
 223 #define RP2D            0x0130  /* 32bit */
 224 #define RP2BA           0x0138  /* 64bit */
 225 #define RP3D            0x0140  /* 32bit */
 226 #define RP3BA           0x0148  /* 64bit */
 227 #define RP4D            0x0150  /* 32bit */
 228 #define RP4BA           0x0158  /* 64bit */
 229 #define HDD             0x0160  /* 32bit */
 230 #define HDBA            0x0168  /* 64bit */
 231 #define RP5D            0x0170  /* 32bit */
 232 #define RP5BA           0x0178  /* 64bit */
 233 #define RP6D            0x0180  /* 32bit */
 234 #define RP6BA           0x0188  /* 64bit */
 235
 236 #define ILCL            0x01a0  /* 32bit */
 237 #define LCAP            0x01a4  /* 32bit */
 238 #define LCTL            0x01a8  /* 16bit */
 239 #define LSTS            0x01aa  /* 16bit */
 240
 241 #define RPC             0x0224  /* 32bit */
 242 #define RPFN            0x0238  /* 32bit */
 243
 244 #define TRSR            0x1e00  /*  8bit */
 245 #define TRCR            0x1e10  /* 64bit */
 246 #define TWDR            0x1e18  /* 64bit */
 247
 248 #define IOTR0           0x1e80  /* 64bit */
 249 #define IOTR1           0x1e88  /* 64bit */
 250 #define IOTR2           0x1e90  /* 64bit */
 251 #define IOTR3           0x1e98  /* 64bit */
 252
 253 #define TCTL            0x3000  /*  8bit */
 254
 255 #define D31IP           0x3100  /* 32bit */
 256 #define D30IP           0x3104  /* 32bit */
 257 #define D29IP           0x3108  /* 32bit */
 258 #define D28IP           0x310c  /* 32bit */
 259 #define D27IP           0x3110  /* 32bit */
 260 #define D31IR           0x3140  /* 16bit */
 261 #define D30IR           0x3142  /* 16bit */
 262 #define D29IR           0x3144  /* 16bit */
 263 #define D28IR           0x3146  /* 16bit */
 264 #define D27IR           0x3148  /* 16bit */
 265 #define OIC             0x31ff  /*  8bit */
 266
 267 #define RC              0x3400  /* 32bit */
 268 #define HPTC            0x3404  /* 32bit */
 269 #define GCS             0x3410  /* 32bit */
 270 #define BUC             0x3414  /* 32bit */
 271 #define FD              0x3418  /* 32bit */
 272 #define CG              0x341c  /* 32bit */
 273
 274 /* Function Disable (FD) register values.
 275  * Setting a bit disables the corresponding
 276  * feature.
 277  * Not all features might be disabled on
 278  * all chipsets. Esp. ICH-7U is picky.
 279  */
 280 #define FD_PCIE6        (1 << 21)
 281 #define FD_PCIE5        (1 << 20)
 282 #define FD_PCIE4        (1 << 19)
 283 #define FD_PCIE3        (1 << 18)
 284 #define FD_PCIE2        (1 << 17)
 285 #define FD_PCIE1        (1 << 16)
 286 #define FD_EHCI         (1 << 15)
 287 #define FD_LPCB         (1 << 14)
 288
 289 /* UHCI must be disabled from 4 downwards.
 290  * If UHCI controllers get disabled, EHCI
 291  * must know about it, too! */
 292 #define FD_UHCI4        (1 << 11)
 293 #define FD_UHCI34       (1 << 10) | FD_UHCI4
 294 #define FD_UHCI234      (1 <<  9) | FD_UHCI3
 295 #define FD_UHCI1234     (1 <<  8) | FD_UHCI2
 296
 297 #define FD_INTLAN       (1 <<  7)
 298 #define FD_ACMOD        (1 <<  6)
 299 #define FD_ACAUD        (1 <<  5)
 300 #define FD_HDAUD        (1 <<  4)
 301 #define FD_SMBUS        (1 <<  3)
 302 #define FD_SATA         (1 <<  2)
 303 #define FD_PATA         (1 <<  1)
 304
 305 /* ICH7 GPIOBASE */
 306 #define GPIO_USE_SEL    0x00
 307 #define GP_IO_SEL       0x04
 308 #define GP_LVL          0x0c
 309 #define GPO_BLINK       0x18
 310 #define GPI_INV         0x2c
 311 #define GPIO_USE_SEL2   0x30
 312 #define GP_IO_SEL2      0x34
 313 #define GP_LVL2         0x38
 314
 315 /* ICH7 PMBASE */
 316 #define PM1_STS         0x00
 317 #define   WAK_STS       (1 << 15)
 318 #define   PCIEXPWAK_STS (1 << 14)
 319 #define   PRBTNOR_STS   (1 << 11)
 320 #define   RTC_STS       (1 << 10)
 321 #define   PWRBTN_STS    (1 << 8)
 322 #define   GBL_STS       (1 << 5)
 323 #define   BM_STS        (1 << 4)
 324 #define   TMROF_STS     (1 << 0)
 325 #define PM1_EN          0x02
 326 #define   PCIEXPWAK_DIS (1 << 14)
 327 #define   RTC_EN        (1 << 10)
 328 #define   PWRBTN_EN     (1 << 8)
 329 #define   GBL_EN        (1 << 5)
 330 #define   TMROF_EN      (1 << 0)
 331 #define PM1_CNT         0x04
 332 #define   SLP_EN        (1 << 13)
 333 #define   SLP_TYP       (7 << 10)
 334 #define   GBL_RLS       (1 << 2)
 335 #define   BM_RLD        (1 << 1)
 336 #define   SCI_EN        (1 << 0)
 337 #define PM1_TMR         0x08
 338 #define PROC_CNT        0x10
 339 #define LV2             0x14
 340 #define LV3             0x15
 341 #define LV4             0x16
 342 #define PM2_CNT         0x20 // mobile only
 343 #define GPE0_STS        0x28
 344 #define   USB4_STS      (1 << 14)
 345 #define   PME_B0_STS    (1 << 13)
 346 #define   USB3_STS      (1 << 12)
 347 #define   PME_STS       (1 << 11)
 348 #define   BATLOW_STS    (1 << 10)
 349 #define   PCI_EXP_STS   (1 << 9)
 350 #define   RI_STS        (1 << 8)
 351 #define   SMB_WAK_STS   (1 << 7)
 352 #define   TCOSCI_STS    (1 << 6)
 353 #define   AC97_STS      (1 << 5)
 354 #define   USB2_STS      (1 << 4)
 355 #define   USB1_STS      (1 << 3)
 356 #define   SWGPE_STS     (1 << 2)
 357 #define   HOT_PLUG_STS  (1 << 1)
 358 #define   THRM_STS      (1 << 0)
 359 #define GPE0_EN         0x2c
 360 #define   PME_B0_EN     (1 << 13)
 361 #define   PME_EN        (1 << 11)
 362 #define SMI_EN          0x30
 363 #define   EL_SMI_EN      (1 << 25) // Intel Quick Resume Technology
 364 #define   INTEL_USB2_EN  (1 << 18) // Intel-Specific USB2 SMI logic
 365 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
 366 #define   PERIODIC_EN    (1 << 14) // SMI on PERIODIC_STS in SMI_STS
 367 #define   TCO_EN         (1 << 13) // Enable TCO Logic (BIOSWE et al)
 368 #define   MCSMI_EN       (1 << 11) // Trap microcontroller range access
 369 #define   BIOS_RLS       (1 <<  7) // asserts SCI on bit set
 370 #define   SWSMI_TMR_EN   (1 <<  6) // start software smi timer on bit set
 371 #define   APMC_EN        (1 <<  5) // Writes to APM_CNT cause SMI#
 372 #define   SLP_SMI_EN     (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
 373 #define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
 374 #define   BIOS_EN        (1 <<  2) // Assert SMI# on setting GBL_RLS bit
 375 #define   EOS            (1 <<  1) // End of SMI (deassert SMI#)
 376 #define   GBL_SMI_EN     (1 <<  0) // SMI# generation at all?
 377 #define SMI_STS         0x34
 378 #define ALT_GP_SMI_EN   0x38
 379 #define ALT_GP_SMI_STS  0x3a
 380 #define GPE_CNTL        0x42
 381 #define DEVACT_STS      0x44
 382 #define SS_CNT          0x50
 383 #define C3_RES          0x54
 384
 385 #define SKPAD_ACPI_S3_MAGIC     0xcafed00d
 386 #define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe
 387 #endif /* __ACPI__ */
 388 #endif                          /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */