src/southbridge/intel/i82801gx/i82801gx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
   4 #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
   5
   6 /* TODO Make sure these don't get changed by stage2 */
   7 #define DEFAULT_GPIOBASE        0x0480
   8 #define DEFAULT_PMBASE          0x0500
   9
  10 #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */
  11
  12 #define SPIBASE 0x3020
  13 #define SPIBAR16(x) RCBA16(SPIBASE + x)
  14 #define SPIBAR32(x) RCBA32(SPIBASE + x)
  15
  16 #ifndef __ACPI__
  17 #include <device/device.h>
  18
  19 void i82801gx_enable(struct device *dev);
  20
  21 void i82801gx_lpc_setup(void);
  22 void i82801gx_setup_bars(void);
  23 void i82801gx_early_init(void);
  24
  25 void ich7_setup_cir(void);
  26
  27 #define MAINBOARD_POWER_OFF     0
  28 #define MAINBOARD_POWER_ON      1
  29 #define MAINBOARD_POWER_KEEP    2
  30
  31 /* PCI Configuration Space (D30:F0): PCI2PCI */
  32 #define PSTS    0x06
  33 #define SMLT    0x1b
  34 #define SECSTS  0x1e
  35 #define INTR    0x3c
  36
  37 #define ICH_PCIE_DEV_SLOT       28
  38
  39 /* PCI Configuration Space (D31:F0): LPC */
  40
  41 #define SERIRQ_CNTL             0x64
  42
  43 #define GEN_PMCON_1             0xa0
  44 #define GEN_PMCON_2             0xa2
  45 #define GEN_PMCON_3             0xa4
  46
  47 #define GPIO_ROUT               0xb8
  48 #define   GPI_DISABLE           0x00
  49 #define   GPI_IS_SMI            0x01
  50 #define   GPI_IS_SCI            0x02
  51 #define   GPI_IS_NMI            0x03
  52
  53 #define FDVCT                   0xe4
  54 #define   PCIE_4_PORTS_MAX      (1 << 7)
  55 #define   AHCI_UNSUPPORTED      (1 << 3)
  56
  57 /* GEN_PMCON_3 bits */
  58 #define RTC_BATTERY_DEAD        (1 << 2)
  59 #define RTC_POWER_FAILED        (1 << 1)
  60 #define SLEEP_AFTER_POWER_FAIL  (1 << 0)
  61
  62 #define ACPI_CNTL               0x44
  63 #define   ACPI_EN               (1 << 7)
  64 #define BIOS_CNTL               0xDC
  65 #define GPIO_BASE               0x48 /* LPC GPIO Base Address Register */
  66 #define GPIO_CNTL               0x4C /* LPC GPIO Control Register */
  67 #define   GPIO_EN               (1 << 4)
  68
  69 #define PIRQA_ROUT              0x60
  70 #define PIRQB_ROUT              0x61
  71 #define PIRQC_ROUT              0x62
  72 #define PIRQD_ROUT              0x63
  73 #define PIRQE_ROUT              0x68
  74 #define PIRQF_ROUT              0x69
  75 #define PIRQG_ROUT              0x6A
  76 #define PIRQH_ROUT              0x6B
  77
  78 #define LPC_IO_DEC              0x80 /* IO Decode Ranges Register */
  79 #define LPC_EN                  0x82 /* LPC IF Enables Register */
  80 #define   CNF2_LPC_EN           (1 << 13) /* 0x4e/0x4f */
  81 #define   CNF1_LPC_EN           (1 << 12) /* 0x2e/0x2f */
  82 #define   MC_LPC_EN             (1 << 11) /* 0x62/0x66 */
  83 #define   KBC_LPC_EN            (1 << 10) /* 0x60/0x64 */
  84 #define   GAMEH_LPC_EN          (1 << 9)  /* 0x208/0x20f */
  85 #define   GAMEL_LPC_EN          (1 << 8)  /* 0x200/0x207 */
  86 #define   FDD_LPC_EN            (1 << 3)  /* LPC_IO_DEC[12] */
  87 #define   LPT_LPC_EN            (1 << 2)  /* LPC_IO_DEC[9:8] */
  88 #define   COMB_LPC_EN           (1 << 1)  /* LPC_IO_DEC[6:4] */
  89 #define   COMA_LPC_EN           (1 << 0)  /* LPC_IO_DEC[2:0] */
  90
  91 #define GEN1_DEC                0x84
  92 #define GEN2_DEC                0x88
  93 #define GEN3_DEC                0x8c
  94 #define GEN4_DEC                0x90
  95
  96 /* PCI Configuration Space (D31:F1): IDE */
  97 #define INTR_LN                 0x3c
  98 #define IDE_TIM_PRI             0x40    /* IDE timings, primary */
  99 #define   IDE_DECODE_ENABLE     (1 << 15)
 100 #define   IDE_SITRE             (1 << 14)
 101 #define   IDE_ISP_5_CLOCKS      (0 << 12)
 102 #define   IDE_ISP_4_CLOCKS      (1 << 12)
 103 #define   IDE_ISP_3_CLOCKS      (2 << 12)
 104 #define   IDE_RCT_4_CLOCKS      (0 <<  8)
 105 #define   IDE_RCT_3_CLOCKS      (1 <<  8)
 106 #define   IDE_RCT_2_CLOCKS      (2 <<  8)
 107 #define   IDE_RCT_1_CLOCKS      (3 <<  8)
 108 #define   IDE_DTE1              (1 <<  7)
 109 #define   IDE_PPE1              (1 <<  6)
 110 #define   IDE_IE1               (1 <<  5)
 111 #define   IDE_TIME1             (1 <<  4)
 112 #define   IDE_DTE0              (1 <<  3)
 113 #define   IDE_PPE0              (1 <<  2)
 114 #define   IDE_IE0               (1 <<  1)
 115 #define   IDE_TIME0             (1 <<  0)
 116 #define IDE_TIM_SEC             0x42    /* IDE timings, secondary */
 117
 118 #define IDE_SDMA_CNT            0x48    /* Synchronous DMA control */
 119 #define   IDE_SSDE1             (1 <<  3)
 120 #define   IDE_SSDE0             (1 <<  2)
 121 #define   IDE_PSDE1             (1 <<  1)
 122 #define   IDE_PSDE0             (1 <<  0)
 123
 124 #define IDE_SDMA_TIM            0x4a
 125
 126 #define IDE_CONFIG              0x54    /* IDE I/O Configuration Register */
 127 #define   SIG_MODE_SEC_NORMAL   (0 << 18)
 128 #define   SIG_MODE_SEC_TRISTATE (1 << 18)
 129 #define   SIG_MODE_SEC_DRIVELOW (2 << 18)
 130 #define   SIG_MODE_PRI_NORMAL   (0 << 16)
 131 #define   SIG_MODE_PRI_TRISTATE (1 << 16)
 132 #define   SIG_MODE_PRI_DRIVELOW (2 << 16)
 133 #define   FAST_SCB1             (1 << 15)
 134 #define   FAST_SCB0             (1 << 14)
 135 #define   FAST_PCB1             (1 << 13)
 136 #define   FAST_PCB0             (1 << 12)
 137 #define   SCB1                  (1 <<  3)
 138 #define   SCB0                  (1 <<  2)
 139 #define   PCB1                  (1 <<  1)
 140 #define   PCB0                  (1 <<  0)
 141
 142 /* PCI Configuration Space (D31:F3): SMBus */
 143 #define SMB_BASE                0x20
 144 #define HOSTC                   0x40
 145
 146 /* HOSTC bits */
 147 #define I2C_EN                  (1 << 2)
 148 #define SMB_SMI_EN              (1 << 1)
 149 #define HST_EN                  (1 << 0)
 150
 151 /* Southbridge IO BARs */
 152
 153 #define GPIOBASE                0x48
 154
 155 #define PMBASE          0x40
 156
 157 #define VCH             0x0000  /* 32bit */
 158 #define VCAP1           0x0004  /* 32bit */
 159 #define VCAP2           0x0008  /* 32bit */
 160 #define PVC             0x000c  /* 16bit */
 161 #define PVS             0x000e  /* 16bit */
 162
 163 #define V0CAP           0x0010  /* 32bit */
 164 #define V0CTL           0x0014  /* 32bit */
 165 #define V0STS           0x001a  /* 16bit */
 166
 167 #define V1CAP           0x001c  /* 32bit */
 168 #define V1CTL           0x0020  /* 32bit */
 169 #define V1STS           0x0026  /* 16bit */
 170
 171 #define RCTCL           0x0100  /* 32bit */
 172 #define ESD             0x0104  /* 32bit */
 173 #define ULD             0x0110  /* 32bit */
 174 #define ULBA            0x0118  /* 64bit */
 175
 176 #define RP1D            0x0120  /* 32bit */
 177 #define RP1BA           0x0128  /* 64bit */
 178 #define RP2D            0x0130  /* 32bit */
 179 #define RP2BA           0x0138  /* 64bit */
 180 #define RP3D            0x0140  /* 32bit */
 181 #define RP3BA           0x0148  /* 64bit */
 182 #define RP4D            0x0150  /* 32bit */
 183 #define RP4BA           0x0158  /* 64bit */
 184 #define HDD             0x0160  /* 32bit */
 185 #define HDBA            0x0168  /* 64bit */
 186 #define RP5D            0x0170  /* 32bit */
 187 #define RP5BA           0x0178  /* 64bit */
 188 #define RP6D            0x0180  /* 32bit */
 189 #define RP6BA           0x0188  /* 64bit */
 190
 191 #define ILCL            0x01a0  /* 32bit */
 192 #define LCAP            0x01a4  /* 32bit */
 193 #define LCTL            0x01a8  /* 16bit */
 194 #define LSTS            0x01aa  /* 16bit */
 195
 196 #define RPC             0x0224  /* 32bit */
 197 #define RPFN            0x0238  /* 32bit */
 198
 199 /* Get the function number assigned to a Root Port */
 200 #define RPFN_FNGET(reg, port)   (((reg) >> ((port) * 4)) & 7)
 201 /* Set the function number for a Root Port */
 202 #define RPFN_FNSET(port, func)  (((func) & 7) << ((port) * 4))
 203 /* Root Port function number mask */
 204 #define RPFN_FNMASK(port)       (7 << ((port) * 4))
 205
 206 #define TRSR            0x1e00  /*  8bit */
 207 #define TRCR            0x1e10  /* 64bit */
 208 #define TWDR            0x1e18  /* 64bit */
 209
 210 #define IOTR0           0x1e80  /* 64bit */
 211 #define IOTR1           0x1e88  /* 64bit */
 212 #define IOTR2           0x1e90  /* 64bit */
 213 #define IOTR3           0x1e98  /* 64bit */
 214
 215 #define TCTL            0x3000  /*  8bit */
 216
 217 #define D31IP           0x3100  /* 32bit */
 218 #define D30IP           0x3104  /* 32bit */
 219 #define D29IP           0x3108  /* 32bit */
 220 #define D28IP           0x310c  /* 32bit */
 221 #define D27IP           0x3110  /* 32bit */
 222 #define D31IR           0x3140  /* 16bit */
 223 #define D30IR           0x3142  /* 16bit */
 224 #define D29IR           0x3144  /* 16bit */
 225 #define D28IR           0x3146  /* 16bit */
 226 #define D27IR           0x3148  /* 16bit */
 227 #define OIC             0x31ff  /*  8bit */
 228
 229 #define RC              0x3400  /* 32bit */
 230 #define HPTC            0x3404  /* 32bit */
 231 #define GCS             0x3410  /* 32bit */
 232 #define BUC             0x3414  /* 32bit */
 233 #define FD              0x3418  /* 32bit */
 234 #define CG              0x341c  /* 32bit */
 235
 236 /* Function Disable (FD) register values.
 237  * Setting a bit disables the corresponding
 238  * feature.
 239  * Not all features might be disabled on
 240  * all chipsets. Esp. ICH-7U is picky.
 241  */
 242 #define ICH_DISABLE_PCIE(x)     (1 << (16 + (x)))
 243 #define FD_EHCI         (1 << 15)
 244 #define FD_LPCB         (1 << 14)
 245
 246 /* UHCI must be disabled from 4 downwards.
 247  * If UHCI controllers get disabled, EHCI
 248  * must know about it, too! */
 249 #define ICH_DISABLE_UHCI(x)     (1 << (8 + (x)))
 250
 251 #define FD_INTLAN       (1 <<  7)
 252 #define FD_ACMOD        (1 <<  6)
 253 #define FD_ACAUD        (1 <<  5)
 254 #define FD_HDAUD        (1 <<  4)
 255 #define FD_SMBUS        (1 <<  3)
 256 #define FD_SATA         (1 <<  2)
 257 #define FD_PATA         (1 <<  1)
 258
 259 /* ICH7 PMBASE */
 260 #define PM1_STS         0x00
 261 #define   WAK_STS       (1 << 15)
 262 #define   PCIEXPWAK_STS (1 << 14)
 263 #define   PRBTNOR_STS   (1 << 11)
 264 #define   RTC_STS       (1 << 10)
 265 #define   PWRBTN_STS    (1 << 8)
 266 #define   GBL_STS       (1 << 5)
 267 #define   BM_STS        (1 << 4)
 268 #define   TMROF_STS     (1 << 0)
 269 #define PM1_EN          0x02
 270 #define   PCIEXPWAK_DIS (1 << 14)
 271 #define   RTC_EN        (1 << 10)
 272 #define   PWRBTN_EN     (1 << 8)
 273 #define   GBL_EN        (1 << 5)
 274 #define   TMROF_EN      (1 << 0)
 275 #define PM1_CNT         0x04
 276 #define   GBL_RLS       (1 << 2)
 277 #define   BM_RLD        (1 << 1)
 278 #define   SCI_EN        (1 << 0)
 279 #define PM1_TMR         0x08
 280 #define PROC_CNT        0x10
 281 #define LV2             0x14
 282 #define LV3             0x15
 283 #define LV4             0x16
 284 #define PM2_CNT         0x20 // mobile only
 285 #define GPE0_STS        0x28
 286 #define   USB4_STS      (1 << 14)
 287 #define   PME_B0_STS    (1 << 13)
 288 #define   USB3_STS      (1 << 12)
 289 #define   PME_STS       (1 << 11)
 290 #define   BATLOW_STS    (1 << 10)
 291 #define   PCI_EXP_STS   (1 << 9)
 292 #define   RI_STS        (1 << 8)
 293 #define   SMB_WAK_STS   (1 << 7)
 294 #define   TCOSCI_STS    (1 << 6)
 295 #define   AC97_STS      (1 << 5)
 296 #define   USB2_STS      (1 << 4)
 297 #define   USB1_STS      (1 << 3)
 298 #define   SWGPE_STS     (1 << 2)
 299 #define   HOT_PLUG_STS  (1 << 1)
 300 #define   THRM_STS      (1 << 0)
 301 #define GPE0_EN         0x2c
 302 #define   PME_B0_EN     (1 << 13)
 303 #define   PME_EN        (1 << 11)
 304 #define SMI_EN          0x30
 305 #define   EL_SMI_EN      (1 << 25) // Intel Quick Resume Technology
 306 #define   INTEL_USB2_EN  (1 << 18) // Intel-Specific USB2 SMI logic
 307 #define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
 308 #define   PERIODIC_EN    (1 << 14) // SMI on PERIODIC_STS in SMI_STS
 309 #define   TCO_EN         (1 << 13) // Enable TCO Logic (BIOSWE et al)
 310 #define   MCSMI_EN       (1 << 11) // Trap microcontroller range access
 311 #define   BIOS_RLS       (1 <<  7) // asserts SCI on bit set
 312 #define   SWSMI_TMR_EN   (1 <<  6) // start software smi timer on bit set
 313 #define   APMC_EN        (1 <<  5) // Writes to APM_CNT cause SMI#
 314 #define   SLP_SMI_EN     (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
 315 #define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
 316 #define   BIOS_EN        (1 <<  2) // Assert SMI# on setting GBL_RLS bit
 317 #define   EOS            (1 <<  1) // End of SMI (deassert SMI#)
 318 #define   GBL_SMI_EN     (1 <<  0) // SMI# generation at all?
 319 #define SMI_STS         0x34
 320 #define ALT_GP_SMI_EN   0x38
 321 #define ALT_GP_SMI_STS  0x3a
 322 #define GPE_CNTL        0x42
 323 #define DEVACT_STS      0x44
 324 #define SS_CNT          0x50
 325 #define C3_RES          0x54
 326
 327 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT)
 328 #define TCO1_CNT        0x68
 329 #endif
 330
 331 #endif /* __ACPI__ */
 332 #endif                          /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */