cpu/intel/model_2065x: Put stage cache in TSEG
[coreboot.git] / src / cpu / intel / model_2065x / Makefile.inc
blob39246c070827f7593a63b3c92548a12bad126954
1 ramstage-y += model_2065x_init.c
2 subdirs-y += ../../x86/name
3 subdirs-y += ../../x86/cache
4 subdirs-y += ../../x86/mtrr
5 subdirs-y += ../../x86/lapic
6 subdirs-y += ../../x86/tsc
7 subdirs-y += ../../intel/turbo
8 subdirs-y += ../../intel/microcode
9 subdirs-y += ../../x86/smm
10 subdirs-y += ../smm/gen1
11 subdirs-y += ../common
13 ramstage-y += tsc_freq.c
14 romstage-y += tsc_freq.c
15 postcar-y += tsc_freq.c
16 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
18 ramstage-y += acpi.c
20 smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
22 romstage-y += stage_cache.c
23 ramstage-y += stage_cache.c
24 postcar-y += stage_cache.c
26 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
28 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
29 postcar-y += ../car/non-evict/exit_car.S
31 romstage-y += ../car/romstage.c