| commit | 97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f | |
| author | Arthur Heymans <arthur@aheymans.xyz> | |
| Tue, 15 May 2018 14:45:21 +0000 (15 16:45 +0200) | ||
| committer | Arthur Heymans <arthur@aheymans.xyz> | |
| Mon, 27 May 2019 17:25:57 +0000 (27 17:25 +0000) | ||
| tree | 30a67e32ce77415b5b4f8734029a2037e4a7a6d5 | treesnapshot (tar.gz zip) |
| parent | b66ee5507c4c2395868a5cd350dc8a7eb46542fd | commitdiff |
cpu/intel/model_2065x: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>