src/southbridge/nvidia/mcp55/early_smbus.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #include <arch/io.h>
  21 #include <console/console.h>
  22 #include <device/pci.h>
  23 #include "smbus.h"
  24 #include "mcp55.h"
  25
  26 #define SMBUS0_IO_BASE  0x1000
  27 #define SMBUS1_IO_BASE  (0x1000 + (1 << 8))
  28 /* Size: 0x40 */
  29
  30 void enable_smbus(void)
  31 {
  32         pci_devfn_t dev;
  33         dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
  34
  35         if (dev == PCI_DEV_INVALID)
  36                 die("SMBus controller not found\n");
  37
  38         /* Set SMBus I/O base. */
  39         pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
  40         pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1);
  41
  42         /* Set SMBus I/O space enable. */
  43         pci_write_config16(dev, 0x4, 0x01);
  44
  45         /* Clear any lingering errors, so the transaction will run. */
  46         outb(inb(SMBUS0_IO_BASE + SMBHSTSTAT), SMBUS0_IO_BASE + SMBHSTSTAT);
  47         outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT);
  48 }
  49
  50 int smbus_recv_byte(unsigned device)
  51 {
  52         return do_smbus_recv_byte(SMBUS0_IO_BASE, device);
  53 }
  54
  55 int smbus_send_byte(unsigned device, unsigned char val)
  56 {
  57         return do_smbus_send_byte(SMBUS0_IO_BASE, device, val);
  58 }
  59
  60 int smbus_read_byte(unsigned device, unsigned address)
  61 {
  62         return do_smbus_read_byte(SMBUS0_IO_BASE, device, address);
  63 }
  64
  65 int smbus_write_byte(unsigned device, unsigned address,
  66                                    unsigned char val)
  67 {
  68         return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val);
  69 }
  70
  71 int smbusx_recv_byte(unsigned smb_index, unsigned device)
  72 {
  73         return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index << 8), device);
  74 }
  75
  76 int smbusx_send_byte(unsigned smb_index, unsigned device,
  77                                    unsigned char val)
  78 {
  79         return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index << 8),
  80                                   device, val);
  81 }
  82
  83 int smbusx_read_byte(unsigned smb_index, unsigned device,
  84                                    unsigned address)
  85 {
  86         return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index << 8),
  87                                   device, address);
  88 }
  89
  90 int smbusx_write_byte(unsigned smb_index, unsigned device,
  91                                     unsigned address, unsigned char val)
  92 {
  93         return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index << 8),
  94                                    device, address, val);
  95 }