1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <commonlib/helpers.h>
4 #include <baseboard/variants.h>
7 * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
8 * table found in EDS vol 1, but some pins aren't grouped functionally in
9 * the table so those were moved for more logical grouping.
11 static const struct pad_config gpio_table
[] = {
13 /* Southwest Community */
15 /* PCIE_WAKE[0:3]_N */
16 PAD_CFG_NF(GPIO_205
, NONE
, DEEP
, NF1
), /* PCIE_WAKE0_N */
17 PAD_CFG_NF(GPIO_206
, NONE
, DEEP
, NF1
), /* PCIE_WAKE1_N */
18 PAD_CFG_NF(GPIO_207
, NONE
, DEEP
, NF1
), /* PCIE_WAKE2_N */
19 PAD_CFG_NF(GPIO_208
, NONE
, DEEP
, NF1
), /* PCIE_WAKE3_N */
22 PAD_CFG_NF(GPIO_156
, DN_20K
, DEEP
, NF1
), /* EMMC_CLK */
23 PAD_CFG_NF(GPIO_157
, UP_20K
, DEEP
, NF1
), /* EMMC_D0 */
24 PAD_CFG_NF(GPIO_158
, UP_20K
, DEEP
, NF1
), /* EMMC_D1 */
25 PAD_CFG_NF(GPIO_159
, UP_20K
, DEEP
, NF1
), /* EMMC_D2 */
26 PAD_CFG_NF(GPIO_160
, UP_20K
, DEEP
, NF1
), /* EMMC_D3 */
27 PAD_CFG_NF(GPIO_161
, UP_20K
, DEEP
, NF1
), /* EMMC_D4 */
28 PAD_CFG_NF(GPIO_162
, UP_20K
, DEEP
, NF1
), /* EMMC_D5 */
29 PAD_CFG_NF(GPIO_163
, UP_20K
, DEEP
, NF1
), /* EMMC_D6 */
30 PAD_CFG_NF(GPIO_164
, UP_20K
, DEEP
, NF1
), /* EMMC_D7 */
31 PAD_CFG_NF(GPIO_165
, UP_20K
, DEEP
, NF1
), /* EMMC_CMD */
32 PAD_CFG_NF(GPIO_182
, DN_20K
, DEEP
, NF1
), /* EMMC_RCLK */
35 PAD_CFG_GPI(GPIO_166
, DN_20K
, DEEP
), /* SDIO_CLK */
36 PAD_CFG_GPI(GPIO_167
, UP_20K
, DEEP
), /* SDIO_D0 */
37 /* Configure SDIO to enable power gating. */
38 PAD_CFG_NF(GPIO_168
, UP_20K
, DEEP
, NF1
), /* SDIO_D1 */
39 PAD_CFG_GPI(GPIO_169
, UP_20K
, DEEP
), /* SDIO_D2 */
40 PAD_CFG_GPI(GPIO_170
, UP_20K
, DEEP
), /* SDIO_D3 */
41 PAD_CFG_GPI(GPIO_171
, UP_20K
, DEEP
), /* SDIO_CMD */
44 /* Pull down clock by 20K. */
45 PAD_CFG_NF(GPIO_172
, DN_20K
, DEEP
, NF1
), /* SDCARD_CLK */
46 PAD_CFG_NF(GPIO_173
, UP_20K
, DEEP
, NF1
), /* SDCARD_D0 */
47 PAD_CFG_NF(GPIO_174
, UP_20K
, DEEP
, NF1
), /* SDCARD_D1 */
48 PAD_CFG_NF(GPIO_175
, UP_20K
, DEEP
, NF1
), /* SDCARD_D2 */
49 PAD_CFG_NF(GPIO_176
, UP_20K
, DEEP
, NF1
), /* SDCARD_D3 */
50 /* Card detect is active LOW with external pull up. */
51 PAD_CFG_NF(GPIO_177
, UP_20K
, DEEP
, NF1
), /* SDCARD_CD_N */
52 PAD_CFG_NF(GPIO_178
, UP_20K
, DEEP
, NF1
), /* SDCARD_CMD */
53 /* CLK feedback, internal signal, needs 20K pull down. */
54 PAD_CFG_NF(GPIO_179
, DN_20K
, DEEP
, NF1
), /* SDCARD_CLK_FB */
55 PAD_CFG_GPI(GPIO_186
, UP_20K
, DEEP
), /* SDCARD_LVL_WP */
56 /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */
57 PAD_CFG_TERM_GPO(GPIO_183
, 1, DN_20K
, DEEP
), /* SDIO_PWR_DOWN_N */
60 PAD_CFG_GPI(SMB_ALERTB
, UP_20K
, DEEP
), /* SMB_ALERT _N */
61 PAD_CFG_NF(SMB_CLK
, NONE
, DEEP
, NF1
), /* SMB_CLK */
62 PAD_CFG_NF(SMB_DATA
, NONE
, DEEP
, NF1
), /* SMB_DATA */
65 PAD_CFG_NF(LPC_ILB_SERIRQ
, NONE
, DEEP
, NF1
), /* LPC_SERIRQ */
66 PAD_CFG_NF(LPC_CLKOUT0
, DN_20K
, DEEP
, NF1
), /* LPC_CLKOUT0 */
67 PAD_CFG_GPI(LPC_CLKOUT1
, UP_20K
, DEEP
), /* LPC_CLKOUT1 */
68 PAD_CFG_NF(LPC_AD0
, NONE
, DEEP
, NF1
), /* LPC_AD0 */
69 PAD_CFG_NF(LPC_AD1
, NONE
, DEEP
, NF1
), /* LPC_AD1 */
70 PAD_CFG_NF(LPC_AD2
, NONE
, DEEP
, NF1
), /* LPC_AD2 */
71 PAD_CFG_NF(LPC_AD3
, NONE
, DEEP
, NF1
), /* LPC_AD3 */
72 PAD_CFG_NF(LPC_CLKRUNB
, NONE
, DEEP
, NF1
), /* LPC_CLKRUN_N */
73 PAD_CFG_NF(LPC_FRAMEB
, NONE
, DEEP
, NF1
), /* LPC_FRAME_N */
77 /* I2C0 - I2C Level Shifter */
78 PAD_CFG_NF(GPIO_124
, NONE
, DEEP
, NF1
), /* LPSS_I2C0_SDA */
79 PAD_CFG_NF(GPIO_125
, NONE
, DEEP
, NF1
), /* LPSS_I2C0_SCL */
81 /* I2C[1:7] -- unused */
82 PAD_CFG_GPI(GPIO_126
, UP_20K
, DEEP
), /* LPSS_I2C1_SDA */
83 PAD_CFG_GPI(GPIO_127
, UP_20K
, DEEP
), /* LPSS_I2C1_SCL */
84 PAD_CFG_GPI(GPIO_128
, UP_20K
, DEEP
), /* LPSS_I2C2_SDA */
85 PAD_CFG_GPI(GPIO_129
, UP_20K
, DEEP
), /* LPSS_I2C2_SCL */
86 PAD_CFG_GPI(GPIO_130
, UP_20K
, DEEP
), /* LPSS_I2C3_SDA */
87 PAD_CFG_GPI(GPIO_131
, UP_20K
, DEEP
), /* LPSS_I2C3_SCL */
88 PAD_CFG_GPI(GPIO_132
, UP_20K
, DEEP
), /* LPSS_I2C4_SDA */
89 PAD_CFG_GPI(GPIO_133
, UP_20K
, DEEP
), /* LPSS_I2C4_SCL */
90 PAD_CFG_GPI(GPIO_134
, UP_20K
, DEEP
), /* LPSS_I2C5_SDA */
91 PAD_CFG_GPI(GPIO_135
, UP_20K
, DEEP
), /* LPSS_I2C5_SCL */
92 PAD_CFG_GPI(GPIO_136
, UP_20K
, DEEP
), /* LPSS_I2C6_SDA */
93 PAD_CFG_GPI(GPIO_137
, UP_20K
, DEEP
), /* LPSS_I2C6_SCL */
94 PAD_CFG_GPI(GPIO_138
, UP_20K
, DEEP
), /* LPSS_I2C7_SDA */
95 PAD_CFG_GPI(GPIO_139
, UP_20K
, DEEP
), /* LPSS_I2C7_SCL */
97 /* ISH_GPIO_[0:9] -- unused */
98 PAD_CFG_GPI(GPIO_146
, DN_20K
, DEEP
), /* ISH_GPIO_0 */
99 PAD_CFG_GPI(GPIO_147
, DN_20K
, DEEP
), /* ISH_GPIO_1 */
100 PAD_CFG_GPI(GPIO_148
, DN_20K
, DEEP
), /* ISH_GPIO_2 */
101 PAD_CFG_GPI(GPIO_149
, DN_20K
, DEEP
), /* ISH_GPIO_3 */
102 PAD_CFG_GPI(GPIO_150
, DN_20K
, DEEP
), /* ISH_GPIO_4 */
103 PAD_CFG_GPI(GPIO_151
, DN_20K
, DEEP
), /* ISH_GPIO_5 */
104 PAD_CFG_GPI(GPIO_152
, DN_20K
, DEEP
), /* ISH_GPIO_6 */
105 PAD_CFG_GPI(GPIO_153
, DN_20K
, DEEP
), /* ISH_GPIO_7 */
106 PAD_CFG_GPI(GPIO_154
, DN_20K
, DEEP
), /* ISH_GPIO_8 */
107 PAD_CFG_GPI(GPIO_155
, DN_20K
, DEEP
), /* ISH_GPIO_9 */
109 /* PCIE_CLKREQ[0:3]_N */
110 PAD_CFG_NF(GPIO_209
, NONE
, DEEP
, NF1
),
111 PAD_CFG_NF(GPIO_210
, NONE
, DEEP
, NF1
),
112 PAD_CFG_NF(GPIO_211
, NONE
, DEEP
, NF1
),
113 PAD_CFG_NF(GPIO_212
, NONE
, DEEP
, NF1
),
115 /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */
116 PAD_CFG_NF(OSC_CLK_OUT_0
, DN_20K
, DEEP
, NF1
),
117 /* OSC_CLK_OUT_[1:4] -- unused */
118 PAD_CFG_GPI(OSC_CLK_OUT_1
, DN_20K
, DEEP
),
119 PAD_CFG_GPI(OSC_CLK_OUT_2
, DN_20K
, DEEP
),
120 PAD_CFG_GPI(OSC_CLK_OUT_3
, DN_20K
, DEEP
),
121 PAD_CFG_GPI(OSC_CLK_OUT_4
, DN_20K
, DEEP
),
124 PAD_CFG_GPI(PMU_AC_PRESENT
, NONE
, DEEP
), /* PMU_AC_PRESENT */
125 PAD_CFG_NF(PMU_BATLOW_B
, UP_20K
, DEEP
, NF1
), /* PMU_BATLOW_N */
126 PAD_CFG_NF(PMU_PLTRST_B
, NONE
, DEEP
, NF1
), /* PMU_PLTRST_N */
127 PAD_CFG_NF(PMU_PWRBTN_B
, UP_20K
, DEEP
, NF1
), /* PMU_PWRBTN_N */
128 PAD_CFG_NF(PMU_RESETBUTTON_B
, NONE
, DEEP
, NF1
), /* PMU_RSTBTN_N */
130 PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B
, NONE
, DEEP
, NF1
, IGNORE
),
131 PAD_CFG_NF(PMU_SLP_S3_B
, NONE
, DEEP
, NF1
), /* PMU_SLP_S3_N */
132 PAD_CFG_NF(PMU_SLP_S4_B
, NONE
, DEEP
, NF1
), /* PMU_SLP_S4_N */
133 PAD_CFG_NF(PMU_SUSCLK
, NONE
, DEEP
, NF1
), /* PMU_SUSCLK */
134 PAD_CFG_TERM_GPO(PMU_WAKE_B
, 1, UP_20K
, DEEP
), /* EN_PP3300_EMMC */
135 PAD_CFG_NF(SUS_STAT_B
, NONE
, DEEP
, NF1
), /* SUS_STAT_N */
136 PAD_CFG_NF(SUSPWRDNACK
, NONE
, DEEP
, NF1
), /* SUSPWRDNACK */
138 /* Northwest Community */
140 /* DDI0 SDA and SCL -- unused */
141 PAD_CFG_GPI(GPIO_187
, DN_20K
, DEEP
), /* HV_DDI0_DDC_SDA */
142 PAD_CFG_GPI(GPIO_188
, DN_20K
, DEEP
), /* HV_DDI0_DDC_SCL */
143 /* DDI1 SDA and SCL - Display-Port */
144 PAD_CFG_NF(GPIO_189
, NONE
, DEEP
, NF1
), /* HV_DDI1_DDC_SDA */
145 PAD_CFG_NF(GPIO_190
, NONE
, DEEP
, NF1
), /* HV_DDI1_DDC_SCL */
147 /* MIPI I2C -- unused */
148 PAD_CFG_GPI(GPIO_191
, DN_20K
, DEEP
), /* MIPI_I2C_SDA */
149 PAD_CFG_GPI(GPIO_192
, DN_20K
, DEEP
), /* MIPI_I2C_SCL */
151 /* Panel 0 control -- unused */
152 PAD_CFG_TERM_GPO(GPIO_193
, 0, DN_20K
, DEEP
), /* PNL0_VDDEN */
153 PAD_CFG_TERM_GPO(GPIO_194
, 0, DN_20K
, DEEP
), /* PNL0_BKLTEN */
154 PAD_CFG_TERM_GPO(GPIO_195
, 0, DN_20K
, DEEP
), /* PNL0_BKLTCTL */
156 /* Panel 1 control -- unused */
157 PAD_CFG_GPI(GPIO_196
, DN_20K
, DEEP
), /* PNL1_VDDEN */
158 PAD_CFG_GPI(GPIO_197
, DN_20K
, DEEP
), /* PNL1_BKLTEN */
159 PAD_CFG_GPI(GPIO_198
, DN_20K
, DEEP
), /* PNL1_BKLTCTL */
161 /* DDI[0:1]_HPD -- unused */
162 PAD_CFG_GPI(GPIO_199
, NONE
, DEEP
), /* XHPD_DP */
163 PAD_CFG_GPI(GPIO_200
, DN_20K
, DEEP
), /* unused */
165 /* MDSI signals -- unused */
166 PAD_CFG_GPI(GPIO_201
, DN_20K
, DEEP
), /* MDSI_A_TE */
167 PAD_CFG_GPI(GPIO_202
, DN_20K
, DEEP
), /* MDSI_C_TE */
169 /* USB overcurrent pins. */
170 PAD_CFG_NF(GPIO_203
, NONE
, DEEP
, NF1
), /* USB_OC0_N */
171 PAD_CFG_NF(GPIO_204
, NONE
, DEEP
, NF1
), /* USB_OC1_N */
173 /* PMC SPI -- almost entirely unused. */
174 PAD_CFG_GPI(PMC_SPI_FS0
, UP_20K
, DEEP
), /* CLP_NC */
175 PAD_CFG_NF(PMC_SPI_FS1
, UP_20K
, DEEP
, NF2
), /* XHPD_EDP_APL */
176 PAD_CFG_GPI(PMC_SPI_FS2
, UP_20K
, DEEP
),
177 PAD_CFG_GPI(PMC_SPI_RXD
, DN_20K
, DEEP
),
178 PAD_CFG_GPI(PMC_SPI_TXD
, DN_20K
, DEEP
),
179 PAD_CFG_GPI(PMC_SPI_CLK
, DN_20K
, DEEP
),
181 /* PMIC Signals unused signals related to an old PMIC interface. */
182 PAD_CFG_NF(PMIC_PWRGOOD
, UP_20K
, DEEP
, NF1
), /* PMIC_PWRGOOD */
183 PAD_CFG_GPI(PMIC_RESET_B
, DN_20K
, DEEP
), /* PMIC_RESET_B */
184 PAD_CFG_TERM_GPO(GPIO_213
, 0, DN_20K
, DEEP
), /* NFC_OUT_RESERVE */
185 PAD_CFG_TERM_GPO(GPIO_214
, 0, DN_20K
, DEEP
), /* NFC_EN */
186 PAD_CFG_GPI(GPIO_215
, DN_20K
, DEEP
), /* NFC_IN_RESERVE */
188 PAD_CFG_NF(PMIC_THERMTRIP_B
, UP_20K
, DEEP
, NF1
),
189 PAD_CFG_TERM_GPO(PMIC_STDBY
, 0, DN_20K
, DEEP
), /* unused */
190 PAD_CFG_NF(PROCHOT_B
, NONE
, DEEP
, NF1
), /* PROCHOT_N */
191 PAD_CFG_NF(PMIC_I2C_SCL
, NONE
, DEEP
, NF1
), /* PMIC_I2C_SCL */
192 PAD_CFG_NF(PMIC_I2C_SDA
, NONE
, DEEP
, NF1
), /* PMIC_I2C_SDA */
195 PAD_CFG_GPI(GPIO_74
, DN_20K
, DEEP
), /* I2S1_MCLK */
196 PAD_CFG_GPI(GPIO_75
, DN_20K
, DEEP
), /* I2S1_BCLK */
197 PAD_CFG_GPI(GPIO_76
, DN_20K
, DEEP
), /* I2S1_WS_SYNC */
198 PAD_CFG_GPI(GPIO_77
, DN_20K
, DEEP
), /* I2S1_SDI */
199 PAD_CFG_GPI(GPIO_78
, DN_20K
, DEEP
), /* I2S1_SDO */
201 /* DMIC or I2S4 -- unused */
202 PAD_CFG_GPI(GPIO_79
, DN_20K
, DEEP
), /* AVS_M_CLK_A1 */
203 PAD_CFG_GPI(GPIO_80
, DN_20K
, DEEP
), /* AVS_M_CLK_B1 */
204 PAD_CFG_GPI(GPIO_81
, DN_20K
, DEEP
), /* AVS_M_DATA_1 */
205 PAD_CFG_GPI(GPIO_82
, DN_20K
, DEEP
), /* AVS_M_CLK_AB2 */
206 PAD_CFG_GPI(GPIO_83
, DN_20K
, DEEP
), /* AVS_M_DATA_2 */
209 PAD_CFG_GPI(GPIO_84
, DN_20K
, DEEP
), /* AVS_I2S2_MCLK */
210 PAD_CFG_GPI(GPIO_85
, DN_20K
, DEEP
), /* AVS_I2S2_BCLK */
211 PAD_CFG_GPI(GPIO_86
, DN_20K
, DEEP
), /* AVS_I2S2_WS_SYNC */
212 PAD_CFG_GPI(GPIO_87
, DN_20K
, DEEP
), /* AVS_I2S2_SDI */
213 PAD_CFG_GPI(GPIO_88
, DN_20K
, DEEP
), /* AVS_I2S2_SDO */
216 PAD_CFG_GPI(GPIO_89
, DN_20K
, DEEP
), /* AVS_I2S3_BCLK */
217 PAD_CFG_GPI(GPIO_90
, DN_20K
, DEEP
), /* AVS_I2S3_WS_SYNC */
218 PAD_CFG_GPI(GPIO_91
, DN_20K
, DEEP
), /* AVS_I2S3_SDI */
219 PAD_CFG_GPI(GPIO_92
, DN_20K
, DEEP
), /* AVS_I2S3_SDO */
223 PAD_CFG_NF_IOSSTATE(GPIO_97
, NATIVE
, DEEP
, NF1
, IGNORE
),
224 /* FST_SPI_CS1_B -- unused */
225 PAD_CFG_GPI(GPIO_98
, DN_20K
, DEEP
),
226 /* FST_SPI_MOSI_IO0 */
227 PAD_CFG_NF_IOSSTATE(GPIO_99
, NATIVE
, DEEP
, NF1
, IGNORE
),
228 /* FST_SPI_MISO_IO1 */
229 PAD_CFG_NF_IOSSTATE(GPIO_100
, NATIVE
, DEEP
, NF1
, IGNORE
),
230 /* FST_IO2 -- MEM_CONFIG0 */
231 PAD_CFG_NF(GPIO_101
, NATIVE
, DEEP
, NF1
),
232 /* FST_IO3 -- MEM_CONFIG1 */
233 PAD_CFG_NF(GPIO_102
, NATIVE
, DEEP
, NF1
),
235 PAD_CFG_NF_IOSSTATE(GPIO_103
, NATIVE
, DEEP
, NF1
, IGNORE
),
237 PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB
, NATIVE
, DEEP
, NF1
, IGNORE
),
239 /* SIO_SPI_0 -- unused */
240 PAD_CFG_GPI(GPIO_104
, DN_20K
, DEEP
), /* GP_SSP_0_CLK */
241 PAD_CFG_GPI(GPIO_105
, DN_20K
, DEEP
), /* GP_SSP_0_FS0 */
242 PAD_CFG_GPI(GPIO_106
, UP_20K
, DEEP
), /* GP_SSP_0_FS1 */
243 PAD_CFG_GPI(GPIO_109
, DN_20K
, DEEP
), /* GP_SSP_0_RXD */
244 PAD_CFG_GPI(GPIO_110
, DN_20K
, DEEP
), /* GP_SSP_0_TXD */
246 /* SIO_SPI_1 -- unused */
247 PAD_CFG_GPI(GPIO_111
, DN_20K
, DEEP
), /* GP_SSP_1_CLK */
248 PAD_CFG_GPI(GPIO_112
, DN_20K
, DEEP
), /* GP_SSP_1_FS0 */
249 PAD_CFG_GPI(GPIO_113
, DN_20K
, DEEP
), /* GP_SSP_1_FS1 */
250 PAD_CFG_GPI(GPIO_116
, DN_20K
, DEEP
), /* GP_SSP_1_RXD */
251 PAD_CFG_GPI(GPIO_117
, DN_20K
, DEEP
), /* GP_SSP_1_TXD */
253 /* SIO_SPI_2 -- unused */
254 PAD_CFG_GPI(GPIO_118
, DN_20K
, DEEP
), /* GP_SSP_2_CLK */
255 PAD_CFG_GPI(GPIO_119
, DN_20K
, DEEP
), /* GP_SSP_2_FS0 */
256 PAD_CFG_GPI(GPIO_120
, DN_20K
, DEEP
), /* GP_SSP_2_FS1 */
257 PAD_CFG_GPI(GPIO_121
, DN_20K
, DEEP
), /* GP_SSP_2_FS2 */
258 PAD_CFG_GPI(GPIO_122
, DN_20K
, DEEP
), /* GP_SSP_2_RXD */
259 PAD_CFG_GPI(GPIO_123
, NONE
, DEEP
), /* GP_SSP_2_TXD */
261 /* North Community */
264 PAD_CFG_GPI(GPIO_0
, DN_20K
, DEEP
), /* TRACE_0_CLK_VNN */
265 PAD_CFG_GPI(GPIO_1
, DN_20K
, DEEP
), /* TRACE_0_DATA0_VNN */
266 PAD_CFG_GPI(GPIO_2
, DN_20K
, DEEP
), /* TRACE_0_DATA1_VNN */
267 PAD_CFG_GPI(GPIO_3
, DN_20K
, DEEP
), /* TRACE_0_DATA2_VNN */
268 PAD_CFG_GPI(GPIO_4
, DN_20K
, DEEP
), /* TRACE_0_DATA3_VNN */
269 PAD_CFG_GPI(GPIO_5
, DN_20K
, DEEP
), /* TRACE_0_DATA4_VNN */
270 PAD_CFG_GPI(GPIO_6
, DN_20K
, DEEP
), /* TRACE_0_DATA5_VNN */
271 PAD_CFG_GPI(GPIO_7
, DN_20K
, DEEP
), /* TRACE_0_DATA6_VNN */
272 PAD_CFG_GPI(GPIO_8
, DN_20K
, DEEP
), /* TRACE_0_DATA7_VNN */
274 PAD_CFG_GPI(GPIO_9
, DN_20K
, DEEP
), /* TRACE_1_CLK_VNN */
275 PAD_CFG_GPI(GPIO_10
, DN_20K
, DEEP
), /* TRACE_1_DATA0_VNN */
276 PAD_CFG_GPI(GPIO_11
, DN_20K
, DEEP
), /* TRACE_1_DATA1_VNN */
277 PAD_CFG_GPI(GPIO_12
, DN_20K
, DEEP
), /* TRACE_1_DATA2_VNN */
278 PAD_CFG_GPI(GPIO_13
, DN_20K
, DEEP
), /* TRACE_1_DATA3_VNN */
279 PAD_CFG_GPI(GPIO_14
, DN_20K
, DEEP
), /* TRACE_1_DATA4_VNN */
280 PAD_CFG_GPI(GPIO_15
, DN_20K
, DEEP
), /* TRACE_1_DATA5_VNN */
281 PAD_CFG_GPI(GPIO_16
, DN_20K
, DEEP
), /* TRACE_1_DATA6_VNN */
282 PAD_CFG_GPI(GPIO_17
, DN_20K
, DEEP
), /* TRACE_1_DATA7_VNN */
284 PAD_CFG_GPI(GPIO_18
, DN_20K
, DEEP
), /* TRACE_2_CLK_VNN */
285 PAD_CFG_GPI(GPIO_19
, DN_20K
, DEEP
), /* TRACE_2_DATA0_VNN */
286 PAD_CFG_GPI(GPIO_20
, DN_20K
, DEEP
), /* TRACE_2_DATA1_VNN */
287 PAD_CFG_GPI(GPIO_21
, DN_20K
, DEEP
), /* TRACE_2_DATA2_VNN */
288 PAD_CFG_GPI(GPIO_22
, DN_20K
, DEEP
), /* TRACE_2_DATA3_VNN */
289 PAD_CFG_GPI(GPIO_23
, DN_20K
, DEEP
), /* TRACE_2_DATA4_VNN */
290 PAD_CFG_GPI(GPIO_24
, DN_20K
, DEEP
), /* TRACE_2_DATA5_VNN */
291 PAD_CFG_GPI(GPIO_25
, DN_20K
, DEEP
), /* TRACE_2_DATA6_VNN */
292 PAD_CFG_GPI(GPIO_26
, DN_20K
, DEEP
), /* TRACE_2_DATA7_VNN */
294 PAD_CFG_GPI(GPIO_27
, DN_20K
, DEEP
), /* TRIGOUT_0 */
295 PAD_CFG_GPI(GPIO_28
, DN_20K
, DEEP
), /* TRIGOUT_1 */
296 PAD_CFG_GPI(GPIO_29
, DN_20K
, DEEP
), /* TRIGIN_0 */
298 PAD_CFG_GPI(GPIO_30
, DN_20K
, DEEP
), /* ISH_GPIO_12 */
299 PAD_CFG_TERM_GPO(GPIO_31
, 1, UP_20K
, DEEP
), /* ISH_GPIO_13 */
300 PAD_CFG_GPI(GPIO_32
, UP_20K
, DEEP
), /* ISH_GPIO_14 */
301 PAD_CFG_GPI(GPIO_33
, DN_20K
, DEEP
), /* ISH_GPIO_15 */
303 /* PWM[0:3] -- unused */
304 PAD_CFG_GPI(GPIO_34
, DN_20K
, DEEP
),
305 PAD_CFG_GPI(GPIO_35
, DN_20K
, DEEP
),
306 PAD_CFG_GPI(GPIO_36
, DN_20K
, DEEP
),
307 PAD_CFG_GPI(GPIO_37
, DN_20K
, DEEP
),
310 PAD_CFG_GPI(GPIO_38
, UP_20K
, DEEP
), /* LPSS_UART0_RXD - unused */
311 PAD_CFG_GPI(GPIO_39
, DN_20K
, DEEP
), /* LPSS_UART0_TXD - unused */
312 PAD_CFG_GPI(GPIO_40
, DN_20K
, DEEP
), /* LPSS_UART0_RTS - unused */
313 PAD_CFG_GPI(GPIO_41
, UP_20K
, DEEP
), /* LPSS_UART0_CTS - unused */
314 PAD_CFG_NF(GPIO_42
, UP_20K
, DEEP
, NF1
), /* LPSS_UART1_RXD */
316 PAD_CFG_NF_IOSSTATE(GPIO_43
, NATIVE
, DEEP
, NF1
, Tx1RxDCRx0
),
317 PAD_CFG_GPI(GPIO_44
, UP_20K
, DEEP
), /* LPSS_UART1_RTS - unused */
318 PAD_CFG_GPI(GPIO_45
, UP_20K
, DEEP
), /* LPSS_UART1_CTS - unused */
319 PAD_CFG_NF(GPIO_46
, UP_20K
, DEEP
, NF1
), /* LPSS_UART2_RXD */
321 PAD_CFG_NF_IOSSTATE(GPIO_47
, NATIVE
, DEEP
, NF1
, Tx1RxDCRx0
),
322 PAD_CFG_GPI(GPIO_48
, DN_20K
, DEEP
), /* LPSS_UART2_RTS - unused */
323 PAD_CFG_GPI(GPIO_49
, UP_20K
, DEEP
), /* LPSS_UART2_CTS - unused */
325 /* Camera interface -- completely unused. */
326 PAD_CFG_GPI(GPIO_62
, DN_20K
, DEEP
), /* GP_CAMERASB00 */
327 PAD_CFG_GPI(GPIO_63
, DN_20K
, DEEP
), /* GP_CAMERASB01 */
328 PAD_CFG_GPI(GPIO_64
, DN_20K
, DEEP
), /* GP_CAMERASB02 */
329 PAD_CFG_GPI(GPIO_65
, DN_20K
, DEEP
), /* GP_CAMERASB03 */
330 PAD_CFG_GPI(GPIO_66
, DN_20K
, DEEP
), /* GP_CAMERASB04 */
331 PAD_CFG_GPI(GPIO_67
, DN_20K
, DEEP
), /* GP_CAMERASB05 */
332 PAD_CFG_GPI(GPIO_68
, DN_20K
, DEEP
), /* GP_CAMERASB06 */
333 PAD_CFG_GPI(GPIO_69
, DN_20K
, DEEP
), /* GP_CAMERASB07 */
334 PAD_CFG_GPI(GPIO_70
, UP_20K
, DEEP
), /* GP_CAMERASB08 */
335 PAD_CFG_GPI(GPIO_71
, UP_20K
, DEEP
), /* GP_CAMERASB09 */
336 PAD_CFG_GPI(GPIO_72
, UP_20K
, DEEP
), /* GP_CAMERASB10 */
337 PAD_CFG_GPI(GPIO_73
, UP_20K
, DEEP
), /* GP_CAMERASB11 */
339 /* CNV bridge described into IAFW Vol2. */
340 /* GPIO_[216:219] described into EDS Vol1. */
341 PAD_CFG_TERM_GPO(CNV_BRI_DT
, 0, DN_20K
, DEEP
), /* Reserve of FPGA */
342 PAD_CFG_TERM_GPO(CNV_BRI_RSP
, 0, DN_20K
, DEEP
), /* Reserve of FPGA */
343 PAD_CFG_TERM_GPO(CNV_RGI_DT
, 0, DN_20K
, DEEP
), /* Reserve of FPGA */
344 PAD_CFG_NF(CNV_RGI_RSP
, UP_20K
, DEEP
, NF1
), /* eMMC */
347 PAD_CFG_NF(SVID0_ALERT_B
, NONE
, DEEP
, NF1
), /* SVID0_ALERT_B */
348 PAD_CFG_NF(SVID0_DATA
, UP_20K
, DEEP
, NF1
), /* SVID0_DATA */
349 PAD_CFG_NF(SVID0_CLK
, UP_20K
, DEEP
, NF1
), /* SVID0_CLK */
352 const struct pad_config
*variant_gpio_table(size_t *num
)
354 *num
= ARRAY_SIZE(gpio_table
);
358 /* GPIOs needed prior to ramstage. */
359 static const struct pad_config early_gpio_table
[] = {
361 PAD_CFG_NF(GPIO_46
, NATIVE
, DEEP
, NF1
), /* LPSS_UART2_RXD */
362 PAD_CFG_NF_IOSSTATE(GPIO_47
, NATIVE
, DEEP
, NF1
, Tx1RxDCRx0
), /* LPSS_UART2_TXD */
365 PAD_CFG_GPI(GPIO_0
, DN_20K
, DEEP
), /* TRACE_0_CLK_VNN */
366 PAD_CFG_GPI(GPIO_1
, DN_20K
, DEEP
), /* TRACE_0_DATA0_VNN */
367 PAD_CFG_GPI(GPIO_2
, DN_20K
, DEEP
), /* TRACE_0_DATA1_VNN */
368 PAD_CFG_GPI(GPIO_3
, DN_20K
, DEEP
), /* TRACE_0_DATA2_VNN */
369 PAD_CFG_GPI(GPIO_4
, DN_20K
, DEEP
), /* TRACE_0_DATA3_VNN */
370 PAD_CFG_GPI(GPIO_5
, DN_20K
, DEEP
), /* TRACE_0_DATA4_VNN */
371 PAD_CFG_GPI(GPIO_6
, DN_20K
, DEEP
), /* TRACE_0_DATA5_VNN */
372 PAD_CFG_GPI(GPIO_7
, DN_20K
, DEEP
), /* TRACE_0_DATA6_VNN */
373 PAD_CFG_GPI(GPIO_8
, DN_20K
, DEEP
), /* TRACE_0_DATA7_VNN */
375 PAD_CFG_GPO(GPIO_13
, 0, DEEP
), /* PERST# */
376 PAD_CFG_GPO(GPIO_15
, 0, DEEP
), /* PERST# */
377 PAD_CFG_GPO(GPIO_17
, 1, DEEP
), /* PFET */
378 PAD_CFG_GPO(GPIO_19
, 1, DEEP
), /* PFET */
379 PAD_CFG_GPO(GPIO_152
, 0, DEEP
), /* PERST# */
382 PAD_CFG_NF(SMB_CLK
, NONE
, DEEP
, NF1
), /* SMB_CLK */
383 PAD_CFG_NF(SMB_DATA
, NONE
, DEEP
, NF1
), /* SMB_DATA */
386 PAD_CFG_NF(LPC_ILB_SERIRQ
, NONE
, DEEP
, NF1
), /* LPC_SERIRQ */
387 PAD_CFG_NF(LPC_CLKOUT0
, DN_20K
, DEEP
, NF1
), /* LPC_CLKOUT0 */
388 /* LPC_CLKOUT1 - unused */
389 PAD_CFG_GPI(LPC_CLKOUT1
, DN_20K
, DEEP
),
390 PAD_CFG_NF(LPC_AD0
, NONE
, DEEP
, NF1
), /* LPC_AD0 */
391 PAD_CFG_NF(LPC_AD1
, NONE
, DEEP
, NF1
), /* LPC_AD1 */
392 PAD_CFG_NF(LPC_AD2
, NONE
, DEEP
, NF1
), /* LPC_AD2 */
393 PAD_CFG_NF(LPC_AD3
, NONE
, DEEP
, NF1
), /* LPC_AD3 */
394 PAD_CFG_NF(LPC_CLKRUNB
, NONE
, DEEP
, NF1
), /* LPC_CLKRUN_N */
395 PAD_CFG_NF(LPC_FRAMEB
, NONE
, DEEP
, NF1
), /* LPC_FRAME_N */
398 const struct pad_config
*variant_early_gpio_table(size_t *num
)
400 *num
= ARRAY_SIZE(early_gpio_table
);
401 return early_gpio_table
;