1 config INTEL_LYNXPOINT_LP
3 default y if SOC_INTEL_BROADWELL
5 config PCH_SPECIFIC_OPTIONS
7 select ACPI_COMMON_MADT_LAPIC
8 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
10 select AZALIA_PLUGIN_SUPPORT
11 select BOOT_DEVICE_SUPPORTS_WRITES
12 select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
13 select HAVE_POWER_STATE_AFTER_FAILURE
14 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
15 select HAVE_SMI_HANDLER
17 select INTEL_DESCRIPTOR_MODE_CAPABLE
18 select INTEL_LYNXPOINT_LP
20 select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT
21 select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
22 select SOUTHBRIDGE_INTEL_COMMON_RESET
23 select SOUTHBRIDGE_INTEL_COMMON_RTC
24 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
25 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
27 select TCO_SPACE_NOT_YET_SPLIT
33 config SERIRQ_CONTINUOUS_MODE
37 If you set this option to y, the serial IRQ machine will be
38 operated in continuous mode.
48 config PCIEXP_COMMON_CLOCK
56 config PCIEXP_L1_SUB_STATE
60 config SERIALIO_UART_CONSOLE
63 select DRIVERS_UART_8250MEM_32
65 Selected by mainboards where SerialIO UARTs can be used to retrieve
66 coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly.
68 config CONSOLE_UART_BASE_ADDRESS
69 default 0xd6000000 if SERIALIO_UART_CONSOLE
72 bool "Disable Intel ME PCI interface (MEI1)"
75 Disable and hide the ME PCI interface during finalize stage of boot.
76 This will prevent the OS (and userspace apps) from interacting with
77 the ME via the PCI interface after boot.